BNX2X: usability fixups
[akaros.git] / kern / drivers / net / r8169.c
1 /*
2  * Copyright (c) 2008 Marty Connor <mdc@etherboot.org>
3  * Copyright (c) 2008 Entity Cyber, Inc.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License as
7  * published by the Free Software Foundation; either version 2 of the
8  * License, or any later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18  *
19  * This driver is based on rtl8169 data sheets and work by:
20  *
21  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
22  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
23  * Copyright (c) a lot of people too. Please respect their work.
24  */
25
26 #include <vfs.h>
27 #include <kfs.h>
28 #include <slab.h>
29 #include <kmalloc.h>
30 #include <kref.h>
31 #include <string.h>
32 #include <stdio.h>
33 #include <assert.h>
34 #include <error.h>
35 #include <cpio.h>
36 #include <pmap.h>
37 #include <smp.h>
38 #include <ip.h>
39 #include <mii.h>
40 #include "r8169.h"
41
42 /*** Low level hardware routines ***/
43
44 static void mdio_write(void *ioaddr, int reg_addr, int value)
45 {
46         int i;
47
48         printd("mdio_write\n");
49
50         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
51
52         for (i = 20; i > 0; i--) {
53                 /*
54                  * Check if the RTL8169 has completed writing to the specified
55                  * MII register.
56                  */
57                 if (!(RTL_R32(PHYAR) & 0x80000000))
58                         break;
59                 udelay(25);
60         }
61 }
62
63 static int mdio_read(void *ioaddr, int reg_addr)
64 {
65         int i, value = -1;
66
67         printd("mdio_read\n");
68
69         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
70
71         for (i = 20; i > 0; i--) {
72                 /*
73                  * Check if the RTL8169 has completed retrieving data from
74                  * the specified MII register.
75                  */
76                 if (RTL_R32(PHYAR) & 0x80000000) {
77                         value = RTL_R32(PHYAR) & 0xffff;
78                         break;
79                 }
80                 udelay(25);
81         }
82         return value;
83 }
84
85 static void mdio_patch(void *ioaddr, int reg_addr, int value)
86 {
87         printd("mdio_patch\n");
88
89         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
90 }
91
92 static void rtl_ephy_write(void *ioaddr, int reg_addr, int value)
93 {
94         unsigned int i;
95
96         printd("rtl_ephy_write\n");
97
98         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
99                         (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
100
101         for (i = 0; i < 100; i++) {
102                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
103                         break;
104                 udelay(10);
105         }
106 }
107
108 static uint16_t rtl_ephy_read(void *ioaddr, int reg_addr)
109 {
110         uint16_t value = 0xffff;
111         unsigned int i;
112
113         printd("rtl_ephy_read\n");
114
115         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
116
117         for (i = 0; i < 100; i++) {
118                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
119                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
120                         break;
121                 }
122                 udelay(10);
123         }
124
125         return value;
126 }
127
128 static void rtl_csi_write(void *ioaddr, int addr, int value)
129 {
130         unsigned int i;
131
132         printd("rtl_csi_write\n");
133
134         RTL_W32(CSIDR, value);
135         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
136                         CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
137
138         for (i = 0; i < 100; i++) {
139                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
140                         break;
141                 udelay(10);
142         }
143 }
144
145 static uint32_t rtl_csi_read(void *ioaddr, int addr)
146 {
147         uint32_t value = ~0x00;
148         unsigned int i;
149
150         printd("rtl_csi_read\n");
151
152         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
153                         CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
154
155         for (i = 0; i < 100; i++) {
156                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
157                         value = RTL_R32(CSIDR);
158                         break;
159                 }
160                 udelay(10);
161         }
162
163         return value;
164 }
165
166 static void rtl8169_irq_mask_and_ack(void *ioaddr)
167 {
168         printd("rtl8169_irq_mask_and_ack\n");
169
170         RTL_W16(IntrMask, 0x0000);
171
172         RTL_W16(IntrStatus, 0xffff);
173 }
174
175 static unsigned int rtl8169_tbi_reset_pending(void *ioaddr)
176 {
177         printd("rtl8169_tbi_reset_pending\n");
178
179         return RTL_R32(TBICSR) & TBIReset;
180 }
181
182 static unsigned int rtl8169_xmii_reset_pending(void *ioaddr)
183 {
184         printd("rtl8169_xmii_reset_pending\n");
185
186         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
187 }
188
189 static unsigned int rtl8169_tbi_link_ok(void *ioaddr)
190 {
191         printd("rtl8169_tbi_link_ok\n");
192
193         return RTL_R32(TBICSR) & TBILinkOk;
194 }
195
196 static unsigned int rtl8169_xmii_link_ok(void *ioaddr)
197 {
198         printd("rtl8169_xmii_link_ok\n");
199
200         return RTL_R8(PHYstatus) & LinkStatus;
201 }
202
203 static void rtl8169_tbi_reset_enable(void *ioaddr)
204 {
205         printd("rtl8169_tbi_reset_enable\n");
206
207         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
208 }
209
210 static void rtl8169_xmii_reset_enable(void *ioaddr)
211 {
212         unsigned int val;
213
214         printd("rtl8169_xmii_reset_enable\n");
215
216         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
217         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
218 }
219
220 static int rtl8169_set_speed_tbi(struct net_device *dev,
221                                                                  uint8_t autoneg,
222                                                                  uint16_t speed, uint8_t duplex)
223 {
224         struct rtl8169_private *tp = netdev_priv(dev);
225         void *ioaddr = tp->mmio_addr;
226         int ret = 0;
227         uint32_t reg;
228
229         printd("rtl8169_set_speed_tbi\n");
230
231         reg = RTL_R32(TBICSR);
232         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
233                 (duplex == DUPLEX_FULL)) {
234                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
235         } else if (autoneg == AUTONEG_ENABLE)
236                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
237         else {
238                 DBG("incorrect speed setting refused in TBI mode\n");
239                 ret = -EOPNOTSUPP;
240         }
241         return ret;
242 }
243
244 static int rtl8169_set_speed_xmii(struct net_device *dev,
245                                                                   uint8_t autoneg,
246                                                                   uint16_t speed, uint8_t duplex)
247 {
248         struct rtl8169_private *tp = netdev_priv(dev);
249         void *ioaddr = tp->mmio_addr;
250         int auto_nego, giga_ctrl;
251
252         printd("rtl8169_set_speed_xmii\n");
253
254         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
255         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
256                                    ADVERTISE_100HALF | ADVERTISE_100FULL);
257         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
258         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
259
260         if (autoneg == AUTONEG_ENABLE) {
261                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
262                                           ADVERTISE_100HALF | ADVERTISE_100FULL);
263                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
264         } else {
265                 if (speed == SPEED_10)
266                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
267                 else if (speed == SPEED_100)
268                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
269                 else if (speed == SPEED_1000)
270                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
271
272                 if (duplex == DUPLEX_HALF)
273                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
274
275                 if (duplex == DUPLEX_FULL)
276                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
277
278                 /* This tweak comes straight from Realtek's driver. */
279                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
280                         ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
281                          (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
282                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
283                 }
284         }
285
286         /* The 8100e/8101e/8102e do Fast Ethernet only. */
287         if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
288                 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
289                 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
290                 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
291                 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
292                 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
293                 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
294                 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
295                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF))) {
296                         DBG("PHY does not support 1000Mbps.\n");
297                 }
298                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
299         }
300
301         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
302
303         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
304                 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
305                 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
306                 /*
307                  * Wake up the PHY.
308                  * Vendor specific (0x1f) and reserved (0x0e) MII registers.
309                  */
310                 mdio_write(ioaddr, 0x1f, 0x0000);
311                 mdio_write(ioaddr, 0x0e, 0x0000);
312         }
313
314         tp->phy_auto_nego_reg = auto_nego;
315         tp->phy_1000_ctrl_reg = giga_ctrl;
316
317         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
318         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
319         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
320         return 0;
321 }
322
323 static int rtl8169_set_speed(struct net_device *dev,
324                                                          uint8_t autoneg, uint16_t speed, uint8_t duplex)
325 {
326         struct rtl8169_private *tp = netdev_priv(dev);
327         int ret;
328
329         printd("rtl8169_set_speed\n");
330 #warning "this should be a write to a ctl file"
331         ret = 0;        // tp->set_speed(dev, autoneg, speed, duplex);
332
333         return ret;
334 }
335
336 static void rtl8169_write_gmii_reg_bit(void *ioaddr, int reg,
337                                                                            int bitnum, int bitval)
338 {
339         int val;
340
341         printd("rtl8169_write_gmii_reg_bit\n");
342
343         val = mdio_read(ioaddr, reg);
344         val = (bitval == 1) ? val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
345         mdio_write(ioaddr, reg, val & 0xffff);
346 }
347
348 static void rtl8169_get_mac_version(struct rtl8169_private *tp, void *ioaddr)
349 {
350         /*
351          * The driver currently handles the 8168Bf and the 8168Be identically
352          * but they can be identified more specifically through the test below
353          * if needed:
354          *
355          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
356          *
357          * Same thing for the 8101Eb and the 8101Ec:
358          *
359          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
360          */
361         const struct {
362                 uint32_t mask;
363                 uint32_t val;
364                 int mac_version;
365         } mac_info[] = {
366                 /* 8168D family. */
367                 {
368                 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25},
369                         /* 8168C family. */
370                 {
371                 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24}, {
372                 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23}, {
373                 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18}, {
374                 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24}, {
375                 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19}, {
376                 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20}, {
377                 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21}, {
378                 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22}, {
379                 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22},
380                         /* 8168B family. */
381                 {
382                 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12}, {
383                 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17}, {
384                 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17}, {
385                 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11},
386                         /* 8101 family. */
387                 {
388                 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09}, {
389                 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09}, {
390                 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08}, {
391                 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08}, {
392                 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07}, {
393                 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07}, {
394                 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13}, {
395                 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10}, {
396                 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16}, {
397                 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09}, {
398                 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09}, {
399                 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16},
400                         /* FIXME: where did these entries come from ? -- FR */
401                 {
402                 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15}, {
403                 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14},
404                         /* 8110 family. */
405                 {
406                 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06}, {
407                 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05}, {
408                 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04}, {
409                 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03}, {
410                 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02}, {
411                 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01}, {
412                 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01}    /* Catch-all */
413         }, *p = mac_info;
414         uint32_t reg;
415
416         printd("rtl8169_get_mac_version\n");
417
418         reg = RTL_R32(TxConfig);
419         while ((reg & p->mask) != p->val)
420                 p++;
421         tp->mac_version = p->mac_version;
422
423         DBG("tp->mac_version = %d\n", tp->mac_version);
424
425         if (p->mask == 0x00000000) {
426                 DBG("unknown MAC (%08x)\n", reg);
427         }
428 }
429
430 struct phy_reg {
431         uint16_t reg;
432         uint16_t val;
433 };
434
435 static void rtl_phy_write(void *ioaddr, struct phy_reg *regs, int len)
436 {
437         printd("rtl_phy_write\n");
438
439         while (len-- > 0) {
440                 mdio_write(ioaddr, regs->reg, regs->val);
441                 regs++;
442         }
443 }
444
445 static void rtl8169s_hw_phy_config(void *ioaddr)
446 {
447         struct {
448                 uint16_t regs[5];               /* Beware of bit-sign propagation */
449         } phy_magic[5] = { {
450                         {
451                                 0x0000, //w 4 15 12 0
452                                         0x00a1, //w 3 15 0 00a1
453                                         0x0008, //w 2 15 0 0008
454                                         0x1020, //w 1 15 0 1020
455         0x1000}}, {     //w 0 15 0 1000
456                 {
457                         0x7000, //w 4 15 12 7
458                                 0xff41, //w 3 15 0 ff41
459                                 0xde60, //w 2 15 0 de60
460                                 0x0140, //w 1 15 0 0140
461         0x0077}}, {     //w 0 15 0 0077
462                 {
463                         0xa000, //w 4 15 12 a
464                                 0xdf01, //w 3 15 0 df01
465                                 0xdf20, //w 2 15 0 df20
466                                 0xff95, //w 1 15 0 ff95
467         0xfa00}}, {     //w 0 15 0 fa00
468                 {
469                         0xb000, //w 4 15 12 b
470                                 0xff41, //w 3 15 0 ff41
471                                 0xde20, //w 2 15 0 de20
472                                 0x0140, //w 1 15 0 0140
473         0x00bb}}, {     //w 0 15 0 00bb
474                 {
475                         0xf000, //w 4 15 12 f
476                                 0xdf01, //w 3 15 0 df01
477                                 0xdf20, //w 2 15 0 df20
478                                 0xff95, //w 1 15 0 ff95
479                 0xbf00} //w 0 15 0 bf00
480         }
481         }, *p = phy_magic;
482         unsigned int i;
483
484         printd("rtl8169s_hw_phy_config\n");
485
486         mdio_write(ioaddr, 0x1f, 0x0001);       //w 31 2 0 1
487         mdio_write(ioaddr, 0x15, 0x1000);       //w 21 15 0 1000
488         mdio_write(ioaddr, 0x18, 0x65c7);       //w 24 15 0 65c7
489         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
490
491         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
492                 int val, pos = 4;
493
494                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
495                 mdio_write(ioaddr, pos, val);
496                 while (--pos >= 0)
497                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
498                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1);   //w 4 11 11 1
499                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
500         }
501         mdio_write(ioaddr, 0x1f, 0x0000);       //w 31 2 0 0
502 }
503
504 static void rtl8169sb_hw_phy_config(void *ioaddr)
505 {
506         struct phy_reg phy_reg_init[] = {
507                 {0x1f, 0x0002},
508                 {0x01, 0x90d0},
509                 {0x1f, 0x0000}
510         };
511
512         printd("rtl8169sb_hw_phy_config\n");
513
514         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
515 }
516
517 static void rtl8168bb_hw_phy_config(void *ioaddr)
518 {
519         struct phy_reg phy_reg_init[] = {
520                 {0x10, 0xf41b},
521                 {0x1f, 0x0000}
522         };
523
524         mdio_write(ioaddr, 0x1f, 0x0001);
525         mdio_patch(ioaddr, 0x16, 1 << 0);
526
527         printd("rtl8168bb_hw_phy_config\n");
528
529         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
530 }
531
532 static void rtl8168bef_hw_phy_config(void *ioaddr)
533 {
534         struct phy_reg phy_reg_init[] = {
535                 {0x1f, 0x0001},
536                 {0x10, 0xf41b},
537                 {0x1f, 0x0000}
538         };
539
540         printd("rtl8168bef_hw_phy_config\n");
541
542         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
543 }
544
545 static void rtl8168cp_1_hw_phy_config(void *ioaddr)
546 {
547         struct phy_reg phy_reg_init[] = {
548                 {0x1f, 0x0000},
549                 {0x1d, 0x0f00},
550                 {0x1f, 0x0002},
551                 {0x0c, 0x1ec8},
552                 {0x1f, 0x0000}
553         };
554
555         printd("rtl8168cp_1_hw_phy_config\n");
556
557         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
558 }
559
560 static void rtl8168cp_2_hw_phy_config(void *ioaddr)
561 {
562         struct phy_reg phy_reg_init[] = {
563                 {0x1f, 0x0001},
564                 {0x1d, 0x3d98},
565                 {0x1f, 0x0000}
566         };
567
568         printd("rtl8168cp_2_hw_phy_config\n");
569
570         mdio_write(ioaddr, 0x1f, 0x0000);
571         mdio_patch(ioaddr, 0x14, 1 << 5);
572         mdio_patch(ioaddr, 0x0d, 1 << 5);
573
574         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
575 }
576
577 static void rtl8168c_1_hw_phy_config(void *ioaddr)
578 {
579         struct phy_reg phy_reg_init[] = {
580                 {0x1f, 0x0001},
581                 {0x12, 0x2300},
582                 {0x1f, 0x0002},
583                 {0x00, 0x88d4},
584                 {0x01, 0x82b1},
585                 {0x03, 0x7002},
586                 {0x08, 0x9e30},
587                 {0x09, 0x01f0},
588                 {0x0a, 0x5500},
589                 {0x0c, 0x00c8},
590                 {0x1f, 0x0003},
591                 {0x12, 0xc096},
592                 {0x16, 0x000a},
593                 {0x1f, 0x0000},
594                 {0x1f, 0x0000},
595                 {0x09, 0x2000},
596                 {0x09, 0x0000}
597         };
598
599         printd("rtl8168c_1_hw_phy_config\n");
600
601         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
602
603         mdio_patch(ioaddr, 0x14, 1 << 5);
604         mdio_patch(ioaddr, 0x0d, 1 << 5);
605         mdio_write(ioaddr, 0x1f, 0x0000);
606 }
607
608 static void rtl8168c_2_hw_phy_config(void *ioaddr)
609 {
610         struct phy_reg phy_reg_init[] = {
611                 {0x1f, 0x0001},
612                 {0x12, 0x2300},
613                 {0x03, 0x802f},
614                 {0x02, 0x4f02},
615                 {0x01, 0x0409},
616                 {0x00, 0xf099},
617                 {0x04, 0x9800},
618                 {0x04, 0x9000},
619                 {0x1d, 0x3d98},
620                 {0x1f, 0x0002},
621                 {0x0c, 0x7eb8},
622                 {0x06, 0x0761},
623                 {0x1f, 0x0003},
624                 {0x16, 0x0f0a},
625                 {0x1f, 0x0000}
626         };
627
628         printd("rtl8168c_2_hw_phy_config\n");
629
630         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
631
632         mdio_patch(ioaddr, 0x16, 1 << 0);
633         mdio_patch(ioaddr, 0x14, 1 << 5);
634         mdio_patch(ioaddr, 0x0d, 1 << 5);
635         mdio_write(ioaddr, 0x1f, 0x0000);
636 }
637
638 static void rtl8168c_3_hw_phy_config(void *ioaddr)
639 {
640         struct phy_reg phy_reg_init[] = {
641                 {0x1f, 0x0001},
642                 {0x12, 0x2300},
643                 {0x1d, 0x3d98},
644                 {0x1f, 0x0002},
645                 {0x0c, 0x7eb8},
646                 {0x06, 0x5461},
647                 {0x1f, 0x0003},
648                 {0x16, 0x0f0a},
649                 {0x1f, 0x0000}
650         };
651
652         printd("rtl8168c_3_hw_phy_config\n");
653
654         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
655
656         mdio_patch(ioaddr, 0x16, 1 << 0);
657         mdio_patch(ioaddr, 0x14, 1 << 5);
658         mdio_patch(ioaddr, 0x0d, 1 << 5);
659         mdio_write(ioaddr, 0x1f, 0x0000);
660 }
661
662 static void rtl8168c_4_hw_phy_config(void *ioaddr)
663 {
664         printd("rtl8168c_4_hw_phy_config\n");
665
666         rtl8168c_3_hw_phy_config(ioaddr);
667 }
668
669 static void rtl8168d_hw_phy_config(void *ioaddr)
670 {
671         struct phy_reg phy_reg_init_0[] = {
672                 {0x1f, 0x0001},
673                 {0x09, 0x2770},
674                 {0x08, 0x04d0},
675                 {0x0b, 0xad15},
676                 {0x0c, 0x5bf0},
677                 {0x1c, 0xf101},
678                 {0x1f, 0x0003},
679                 {0x14, 0x94d7},
680                 {0x12, 0xf4d6},
681                 {0x09, 0xca0f},
682                 {0x1f, 0x0002},
683                 {0x0b, 0x0b10},
684                 {0x0c, 0xd1f7},
685                 {0x1f, 0x0002},
686                 {0x06, 0x5461},
687                 {0x1f, 0x0002},
688                 {0x05, 0x6662},
689                 {0x1f, 0x0000},
690                 {0x14, 0x0060},
691                 {0x1f, 0x0000},
692                 {0x0d, 0xf8a0},
693                 {0x1f, 0x0005},
694                 {0x05, 0xffc2}
695         };
696
697         printd("rtl8168d_hw_phy_config\n");
698
699         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
700
701         if (mdio_read(ioaddr, 0x06) == 0xc400) {
702                 struct phy_reg phy_reg_init_1[] = {
703                         {0x1f, 0x0005},
704                         {0x01, 0x0300},
705                         {0x1f, 0x0000},
706                         {0x11, 0x401c},
707                         {0x16, 0x4100},
708                         {0x1f, 0x0005},
709                         {0x07, 0x0010},
710                         {0x05, 0x83dc},
711                         {0x06, 0x087d},
712                         {0x05, 0x8300},
713                         {0x06, 0x0101},
714                         {0x06, 0x05f8},
715                         {0x06, 0xf9fa},
716                         {0x06, 0xfbef},
717                         {0x06, 0x79e2},
718                         {0x06, 0x835f},
719                         {0x06, 0xe0f8},
720                         {0x06, 0x9ae1},
721                         {0x06, 0xf89b},
722                         {0x06, 0xef31},
723                         {0x06, 0x3b65},
724                         {0x06, 0xaa07},
725                         {0x06, 0x81e4},
726                         {0x06, 0xf89a},
727                         {0x06, 0xe5f8},
728                         {0x06, 0x9baf},
729                         {0x06, 0x06ae},
730                         {0x05, 0x83dc},
731                         {0x06, 0x8300},
732                 };
733
734                 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
735         }
736
737         mdio_write(ioaddr, 0x1f, 0x0000);
738 }
739
740 static void rtl8102e_hw_phy_config(void *ioaddr)
741 {
742         struct phy_reg phy_reg_init[] = {
743                 {0x1f, 0x0003},
744                 {0x08, 0x441d},
745                 {0x01, 0x9100},
746                 {0x1f, 0x0000}
747         };
748
749         printd("rtl8102e_hw_phy_config\n");
750
751         mdio_write(ioaddr, 0x1f, 0x0000);
752         mdio_patch(ioaddr, 0x11, 1 << 12);
753         mdio_patch(ioaddr, 0x19, 1 << 13);
754
755         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
756 }
757
758 static void rtl_hw_phy_config(struct net_device *dev)
759 {
760         struct rtl8169_private *tp = netdev_priv(dev);
761         void *ioaddr = tp->mmio_addr;
762
763         printd("rtl_hw_phy_config\n");
764
765         DBG("mac_version = 0x%02x\n", tp->mac_version);
766
767         switch (tp->mac_version) {
768                 case RTL_GIGA_MAC_VER_01:
769                         break;
770                 case RTL_GIGA_MAC_VER_02:
771                 case RTL_GIGA_MAC_VER_03:
772                         rtl8169s_hw_phy_config(ioaddr);
773                         break;
774                 case RTL_GIGA_MAC_VER_04:
775                         rtl8169sb_hw_phy_config(ioaddr);
776                         break;
777                 case RTL_GIGA_MAC_VER_07:
778                 case RTL_GIGA_MAC_VER_08:
779                 case RTL_GIGA_MAC_VER_09:
780                         rtl8102e_hw_phy_config(ioaddr);
781                         break;
782                 case RTL_GIGA_MAC_VER_11:
783                         rtl8168bb_hw_phy_config(ioaddr);
784                         break;
785                 case RTL_GIGA_MAC_VER_12:
786                         rtl8168bef_hw_phy_config(ioaddr);
787                         break;
788                 case RTL_GIGA_MAC_VER_17:
789                         rtl8168bef_hw_phy_config(ioaddr);
790                         break;
791                 case RTL_GIGA_MAC_VER_18:
792                         rtl8168cp_1_hw_phy_config(ioaddr);
793                         break;
794                 case RTL_GIGA_MAC_VER_19:
795                         rtl8168c_1_hw_phy_config(ioaddr);
796                         break;
797                 case RTL_GIGA_MAC_VER_20:
798                         rtl8168c_2_hw_phy_config(ioaddr);
799                         break;
800                 case RTL_GIGA_MAC_VER_21:
801                         rtl8168c_3_hw_phy_config(ioaddr);
802                         break;
803                 case RTL_GIGA_MAC_VER_22:
804                         rtl8168c_4_hw_phy_config(ioaddr);
805                         break;
806                 case RTL_GIGA_MAC_VER_23:
807                 case RTL_GIGA_MAC_VER_24:
808                         rtl8168cp_2_hw_phy_config(ioaddr);
809                         break;
810                 case RTL_GIGA_MAC_VER_25:
811                         rtl8168d_hw_phy_config(ioaddr);
812                         break;
813
814                 default:
815                         break;
816         }
817 }
818
819 /* N.B. in Ken c, you omit the parameter name, voila -- it's unused.
820  * Many others tend to come up with much harder solutions, such
821  * as tagging the declaration with another attribute like __whatever(unused)
822  * whatever. The bazaar can really be bizarre.
823  */
824 static void rtl8169_phy_reset(struct net_device *unused_dev /* __unused */ ,
825                                                           struct rtl8169_private *tp)
826 {
827         void *ioaddr = tp->mmio_addr;
828         unsigned int i;
829
830         printd("rtl8169_phy_reset\n");
831
832         tp->phy_reset_enable(ioaddr);
833         for (i = 0; i < 100; i++) {
834                 if (!tp->phy_reset_pending(ioaddr))
835                         return;
836                 mdelay(1);
837         }
838         DBG("PHY reset failed.\n");
839 }
840
841 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
842 {
843         void *ioaddr = tp->mmio_addr;
844
845         printd("rtl8169_init_phy\n");
846
847         rtl_hw_phy_config(dev);
848
849         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
850                 DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
851                 RTL_W8(0x82, 0x01);
852         }
853 #warning "fix all the pci bits; please try to do an spatch if possible."
854         //pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
855
856         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) ;   //pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
857
858         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
859                 printd("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
860                 RTL_W8(0x82, 0x01);
861                 printd("Set PHY Reg 0x0bh = 0x00h\n");
862                 mdio_write(ioaddr, 0x0b, 0x0000);       //w 0x0b 15 0 0
863         }
864
865         rtl8169_phy_reset(dev, tp);
866
867         /*
868          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
869          * only 8101. Don't panic.
870          */
871         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
872
873         if ((RTL_R8(PHYstatus) & TBI_Enable))
874                 printd("TBI auto-negotiating\n");
875 }
876
877 static const struct rtl_cfg_info {
878         //void (*hw_start)(struct net_device *);
879         unsigned int region;
880         unsigned int align;
881         uint16_t intr_event;
882         uint16_t napi_event;
883         unsigned features;
884 } rtl_cfg_infos[] = {
885         [RTL_CFG_0] = {
886 //      .hw_start   = rtl_hw_start_8169,
887         .region = 1,.align = 0,.intr_event = SYSErr | LinkChg | RxOverflow |
888                         RxFIFOOver | TxErr | TxOK | RxOK | RxErr,.napi_event =
889                         RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,.features =
890                         RTL_FEATURE_GMII},[RTL_CFG_1] = {
891 //      .hw_start   = rtl_hw_start_8168,
892         .region = 2,.align = 8,.intr_event = SYSErr | LinkChg | RxOverflow |
893                         TxErr | TxOK | RxOK | RxErr,.napi_event =
894                         TxErr | TxOK | RxOK | RxOverflow,.features =
895                         RTL_FEATURE_GMII},[RTL_CFG_2] = {
896 //      .hw_start   = rtl_hw_start_8101,
897         .region = 2,.align = 8,.intr_event =
898                         SYSErr | LinkChg | RxOverflow | PCSTimeout | RxFIFOOver | TxErr
899                         | TxOK | RxOK | RxErr,.napi_event =
900                         RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,}
901 };
902
903 static void rtl8169_hw_reset(void *ioaddr)
904 {
905         printd("rtl8169_hw_reset\n");
906
907         /* Disable interrupts */
908         rtl8169_irq_mask_and_ack(ioaddr);
909
910         /* Reset the chipset */
911         RTL_W8(ChipCmd, CmdReset);
912
913         /* PCI commit */
914         RTL_R8(ChipCmd);
915 }
916
917 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
918 {
919         void *ioaddr = tp->mmio_addr;
920         uint32_t cfg = rtl8169_rx_config;
921
922         printd("rtl_set_rx_tx_config_registers\n");
923
924         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
925         RTL_W32(RxConfig, cfg);
926
927         /* Set DMA burst size and Interframe Gap Time */
928         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
929                         (InterFrameGap << TxInterFrameGapShift));
930 }
931
932 static void rtl_soft_reset(struct net_device *dev)
933 {
934         struct rtl8169_private *tp = netdev_priv(dev);
935         void *ioaddr = tp->mmio_addr;
936         unsigned int i;
937
938         printd("rtl_hw_soft_reset\n");
939
940         /* Soft reset the chip. */
941         RTL_W8(ChipCmd, CmdReset);
942
943         /* Check that the chip has finished the reset. */
944         for (i = 0; i < 100; i++) {
945                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
946                         break;
947                 mdelay(1);
948         }
949
950         if (i == 100) {
951                 printd("Reset Failed! (> 100 iterations)\n");
952         }
953 }
954
955 static void rtl_hw_start(struct net_device *dev)
956 {
957         struct rtl8169_private *tp = netdev_priv(dev);
958
959         printd("rtl_hw_start\n");
960
961         /* Soft reset NIC */
962         rtl_soft_reset(dev);
963
964         //tp->hw_start ( dev );
965 }
966
967 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
968                                                                                  void *ioaddr)
969 {
970         printd("rtl_set_rx_tx_desc_registers\n");
971
972         /*
973          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
974          * register to be written before TxDescAddrLow to work.
975          * Switching from MMIO to I/O access fixes the issue as well.
976          */
977         RTL_W32(TxDescStartAddrHigh, 0);
978         RTL_W32(TxDescStartAddrLow, virt_to_bus(tp->tx_base));
979         RTL_W32(RxDescAddrHigh, 0);
980         RTL_W32(RxDescAddrLow, virt_to_bus(tp->rx_base));
981 }
982
983 static uint16_t rtl_rw_cpluscmd(void *ioaddr)
984 {
985         uint16_t cmd;
986
987         printd("rtl_rw_cpluscmd\n");
988
989         cmd = RTL_R16(CPlusCmd);
990         RTL_W16(CPlusCmd, cmd);
991         return cmd;
992 }
993
994 static void rtl_set_rx_max_size(void *ioaddr)
995 {
996         printd("rtl_set_rx_max_size\n");
997
998         RTL_W16(RxMaxSize, RX_BUF_SIZE);
999 }
1000
1001 static void rtl8169_set_magic_reg(void *ioaddr, unsigned mac_version)
1002 {
1003         struct {
1004                 uint32_t mac_version;
1005                 uint32_t clk;
1006                 uint32_t val;
1007         } cfg2_info[] = {
1008                 {
1009                 RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00},      // 8110SCd
1010                 {
1011                 RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff}, {
1012                 RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00},      // 8110SCe
1013                 {
1014                 RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff}
1015         }, *p = cfg2_info;
1016         unsigned int i;
1017         uint32_t clk;
1018
1019         printd("rtl8169_set_magic_reg\n");
1020
1021         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1022         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
1023                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1024                         RTL_W32(0x7c, p->val);
1025                         break;
1026                 }
1027         }
1028 }
1029
1030 static void rtl_set_rx_mode(struct net_device *netdev)
1031 {
1032         struct rtl8169_private *tp = netdev_priv(netdev);
1033         void *ioaddr = tp->mmio_addr;
1034         uint32_t tmp;
1035
1036         printd("rtl_set_rx_mode\n");
1037
1038         /* Accept all Multicast Packets */
1039
1040         RTL_W32(MAR0 + 0, 0xffffffff);
1041         RTL_W32(MAR0 + 4, 0xffffffff);
1042
1043         tmp = rtl8169_rx_config | AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1044                 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1045
1046         RTL_W32(RxConfig, tmp);
1047 }
1048
1049 static void rtl_hw_start_8169(struct net_device *dev)
1050 {
1051         struct rtl8169_private *tp = netdev_priv(dev);
1052         void *ioaddr = tp->mmio_addr;
1053 //  struct pci_device *pdev = tp->pci_dev;
1054
1055         printd("rtl_hw_start_8169\n");
1056
1057         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1058                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1059                 //pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1060         }
1061
1062         RTL_W8(Cfg9346, Cfg9346_Unlock);
1063
1064         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1065                 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1066                 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1067                 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1068                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1069
1070         RTL_W8(EarlyTxThres, EarlyTxThld);
1071
1072         rtl_set_rx_max_size(ioaddr);
1073
1074         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1075                 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1076                 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1077                 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1078                 rtl_set_rx_tx_config_registers(tp);
1079
1080         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1081
1082         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1083                 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1084                 printd("Set MAC Reg C+CR Offset 0xE0. " "Bit-3 and bit-14 MUST be 1\n");
1085                 tp->cp_cmd |= (1 << 14);
1086         }
1087
1088         RTL_W16(CPlusCmd, tp->cp_cmd);
1089
1090         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1091
1092         /*
1093          * Undocumented corner. Supposedly:
1094          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1095          */
1096         RTL_W16(IntrMitigate, 0x0000);
1097
1098         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1099
1100         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1101                 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1102                 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1103                 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1104                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1105                 rtl_set_rx_tx_config_registers(tp);
1106         }
1107
1108         RTL_W8(Cfg9346, Cfg9346_Lock);
1109
1110         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1111         RTL_R8(IntrMask);
1112
1113         RTL_W32(RxMissed, 0);
1114
1115         rtl_set_rx_mode(dev);
1116
1117         /* no early-rx interrupts */
1118         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1119
1120         //        RTL_W16(IntrMask, tp->intr_event);
1121 }
1122
1123 static void rtl_tx_performance_tweak(struct pci_device *pdev, uint16_t force)
1124 {
1125         struct net_device *dev = pci_get_drvdata(pdev);
1126         struct rtl8169_private *tp = netdev_priv(dev);
1127         int cap = tp->pcie_cap;
1128
1129         printd("rtl_tx_performance_tweak\n");
1130
1131         if (cap) {
1132                 uint16_t ctl;
1133
1134                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
1135                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
1136                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
1137         }
1138 }
1139
1140 static void rtl_csi_access_enable(void *ioaddr)
1141 {
1142         uint32_t csi;
1143
1144         printd("rtl_csi_access_enable\n");
1145
1146         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
1147         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
1148 }
1149
1150 struct ephy_info {
1151         unsigned int offset;
1152         uint16_t mask;
1153         uint16_t bits;
1154 };
1155
1156 static void rtl_ephy_init(void *ioaddr, struct ephy_info *e, int len)
1157 {
1158         uint16_t w;
1159
1160         printd("rtl_ephy_init\n");
1161
1162         while (len-- > 0) {
1163                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
1164                 rtl_ephy_write(ioaddr, e->offset, w);
1165                 e++;
1166         }
1167 }
1168
1169 static void rtl_disable_clock_request(struct pci_device *pdev)
1170 {
1171         struct net_device *dev = pci_get_drvdata(pdev);
1172         struct rtl8169_private *tp = netdev_priv(dev);
1173         int cap = tp->pcie_cap;
1174
1175         printd("rtl_disable_clock_request\n");
1176
1177         if (cap) {
1178                 uint16_t ctl;
1179
1180                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
1181                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
1182                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
1183         }
1184 }
1185
1186 #define R8168_CPCMD_QUIRK_MASK (\
1187         EnableBist | \
1188         Mac_dbgo_oe | \
1189         Force_half_dup | \
1190         Force_rxflow_en | \
1191         Force_txflow_en | \
1192         Cxpl_dbg_sel | \
1193         ASF | \
1194         PktCntrDisable | \
1195         Mac_dbgo_sel)
1196
1197 static void rtl_hw_start_8168bb(void *ioaddr, struct pci_device *pdev)
1198 {
1199         printd("rtl_hw_start_8168bb\n");
1200
1201         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
1202
1203         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
1204
1205         rtl_tx_performance_tweak(pdev,
1206                                                          (0x5 << MAX_READ_REQUEST_SHIFT) |
1207                                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
1208 }
1209
1210 static void rtl_hw_start_8168bef(void *ioaddr, struct pci_device *pdev)
1211 {
1212         printd("rtl_hw_start_8168bef\n");
1213
1214         rtl_hw_start_8168bb(ioaddr, pdev);
1215
1216         RTL_W8(EarlyTxThres, EarlyTxThld);
1217
1218         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
1219 }
1220
1221 static void __rtl_hw_start_8168cp(void *ioaddr, struct pci_device *pdev)
1222 {
1223         printd("__rtl_hw_start_8168cp\n");
1224
1225         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
1226
1227         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
1228
1229         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
1230
1231         rtl_disable_clock_request(pdev);
1232
1233         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
1234 }
1235
1236 static void rtl_hw_start_8168cp_1(void *ioaddr, struct pci_device *pdev)
1237 {
1238         static struct ephy_info e_info_8168cp[] = {
1239                 {0x01, 0, 0x0001},
1240                 {0x02, 0x0800, 0x1000},
1241                 {0x03, 0, 0x0042},
1242                 {0x06, 0x0080, 0x0000},
1243                 {0x07, 0, 0x2000}
1244         };
1245
1246         printd("rtl_hw_start_8168cp_1\n");
1247
1248         rtl_csi_access_enable(ioaddr);
1249
1250         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
1251
1252         __rtl_hw_start_8168cp(ioaddr, pdev);
1253 }
1254
1255 static void rtl_hw_start_8168cp_2(void *ioaddr, struct pci_device *pdev)
1256 {
1257         printd("rtl_hw_start_8168cp_2\n");
1258
1259         rtl_csi_access_enable(ioaddr);
1260
1261         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
1262
1263         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
1264
1265         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
1266 }
1267
1268 static void rtl_hw_start_8168cp_3(void *ioaddr, struct pci_device *pdev)
1269 {
1270         printd("rtl_hw_start_8168cp_3\n");
1271
1272         rtl_csi_access_enable(ioaddr);
1273
1274         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
1275
1276         /* Magic. */
1277         RTL_W8(DBG_REG, 0x20);
1278
1279         RTL_W8(EarlyTxThres, EarlyTxThld);
1280
1281         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
1282
1283         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
1284 }
1285
1286 static void rtl_hw_start_8168c_1(void *ioaddr, struct pci_device *pdev)
1287 {
1288         static struct ephy_info e_info_8168c_1[] = {
1289                 {0x02, 0x0800, 0x1000},
1290                 {0x03, 0, 0x0002},
1291                 {0x06, 0x0080, 0x0000}
1292         };
1293
1294         printd("rtl_hw_start_8168c_1\n");
1295
1296         rtl_csi_access_enable(ioaddr);
1297
1298         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
1299
1300         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
1301
1302         __rtl_hw_start_8168cp(ioaddr, pdev);
1303 }
1304
1305 static void rtl_hw_start_8168c_2(void *ioaddr, struct pci_device *pdev)
1306 {
1307         static struct ephy_info e_info_8168c_2[] = {
1308                 {0x01, 0, 0x0001},
1309                 {0x03, 0x0400, 0x0220}
1310         };
1311
1312         printd("rtl_hw_start_8168c_2\n");
1313
1314         rtl_csi_access_enable(ioaddr);
1315
1316         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
1317
1318         __rtl_hw_start_8168cp(ioaddr, pdev);
1319 }
1320
1321 static void rtl_hw_start_8168c_3(void *ioaddr, struct pci_device *pdev)
1322 {
1323         printd("rtl_hw_start_8168c_3\n");
1324
1325         rtl_hw_start_8168c_2(ioaddr, pdev);
1326 }
1327
1328 static void rtl_hw_start_8168c_4(void *ioaddr, struct pci_device *pdev)
1329 {
1330         printd("rtl_hw_start_8168c_4\n");
1331
1332         rtl_csi_access_enable(ioaddr);
1333
1334         __rtl_hw_start_8168cp(ioaddr, pdev);
1335 }
1336
1337 static void rtl_hw_start_8168d(void *ioaddr, struct pci_device *pdev)
1338 {
1339         printd("rtl_hw_start_8168d\n");
1340
1341         rtl_csi_access_enable(ioaddr);
1342
1343         rtl_disable_clock_request(pdev);
1344
1345         RTL_W8(EarlyTxThres, EarlyTxThld);
1346
1347         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
1348
1349         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
1350 }
1351
1352 static void rtl_hw_start_8168(void /*struct net_device *dev */ )
1353 {
1354 #if 0
1355         struct rtl8169_private *tp = netdev_priv(dev);
1356         void *ioaddr = tp->mmio_addr;
1357         struct pci_device *pdev = tp->pci_dev;
1358
1359         printd("rtl_hw_start_8168\n");
1360
1361         RTL_W8(Cfg9346, Cfg9346_Unlock);
1362
1363         RTL_W8(EarlyTxThres, EarlyTxThld);
1364
1365         rtl_set_rx_max_size(ioaddr);
1366
1367         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1368
1369         RTL_W16(CPlusCmd, tp->cp_cmd);
1370
1371         RTL_W16(IntrMitigate, 0x5151);
1372
1373         /* Work around for RxFIFO overflow. */
1374         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1375                 tp->intr_event |= RxFIFOOver | PCSTimeout;
1376                 tp->intr_event &= ~RxOverflow;
1377         }
1378
1379         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1380
1381         rtl_set_rx_mode(dev);
1382
1383         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1384                         (InterFrameGap << TxInterFrameGapShift));
1385
1386         RTL_R8(IntrMask);
1387
1388         switch (tp->mac_version) {
1389                 case RTL_GIGA_MAC_VER_11:
1390                         rtl_hw_start_8168bb(ioaddr, pdev);
1391                         break;
1392
1393                 case RTL_GIGA_MAC_VER_12:
1394                 case RTL_GIGA_MAC_VER_17:
1395                         rtl_hw_start_8168bef(ioaddr, pdev);
1396                         break;
1397
1398                 case RTL_GIGA_MAC_VER_18:
1399                         rtl_hw_start_8168cp_1(ioaddr, pdev);
1400                         break;
1401
1402                 case RTL_GIGA_MAC_VER_19:
1403                         rtl_hw_start_8168c_1(ioaddr, pdev);
1404                         break;
1405
1406                 case RTL_GIGA_MAC_VER_20:
1407                         rtl_hw_start_8168c_2(ioaddr, pdev);
1408                         break;
1409
1410                 case RTL_GIGA_MAC_VER_21:
1411                         rtl_hw_start_8168c_3(ioaddr, pdev);
1412                         break;
1413
1414                 case RTL_GIGA_MAC_VER_22:
1415                         rtl_hw_start_8168c_4(ioaddr, pdev);
1416                         break;
1417
1418                 case RTL_GIGA_MAC_VER_23:
1419                         rtl_hw_start_8168cp_2(ioaddr, pdev);
1420                         break;
1421
1422                 case RTL_GIGA_MAC_VER_24:
1423                         rtl_hw_start_8168cp_3(ioaddr, pdev);
1424                         break;
1425
1426                 case RTL_GIGA_MAC_VER_25:
1427                         rtl_hw_start_8168d(ioaddr, pdev);
1428                         break;
1429
1430                 default:
1431                         printd("Unknown chipset (mac_version = %d).\n", tp->mac_version);
1432                         break;
1433         }
1434
1435         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1436
1437         RTL_W8(Cfg9346, Cfg9346_Lock);
1438
1439         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1440
1441         //        RTL_W16(IntrMask, tp->intr_event);
1442 #endif
1443 }
1444
1445 #define R810X_CPCMD_QUIRK_MASK (\
1446         EnableBist | \
1447         Mac_dbgo_oe | \
1448         Force_half_dup | \
1449         Force_half_dup | \
1450         Force_txflow_en | \
1451         Cxpl_dbg_sel | \
1452         ASF | \
1453         PktCntrDisable | \
1454         PCIDAC | \
1455         PCIMulRW)
1456
1457 static void rtl_hw_start_8102e_1(void *ioaddr, struct pci_device *pdev)
1458 {
1459 #if 0
1460         static struct ephy_info e_info_8102e_1[] = {
1461                 {0x01, 0, 0x6e65},
1462                 {0x02, 0, 0x091f},
1463                 {0x03, 0, 0xc2f9},
1464                 {0x06, 0, 0xafb5},
1465                 {0x07, 0, 0x0e00},
1466                 {0x19, 0, 0xec80},
1467                 {0x01, 0, 0x2e65},
1468                 {0x01, 0, 0x6e65}
1469         };
1470         uint8_t cfg1;
1471
1472         printd("rtl_hw_start_8102e_1\n");
1473
1474         rtl_csi_access_enable(ioaddr);
1475
1476         RTL_W8(DBG_REG, FIX_NAK_1);
1477
1478         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
1479
1480         RTL_W8(Config1,
1481                    LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD8169 | PMEnable);
1482         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
1483
1484         cfg1 = RTL_R8(Config1);
1485         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1486                 RTL_W8(Config1, cfg1 & ~LEDS0);
1487
1488         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
1489
1490         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
1491 #endif
1492 }
1493
1494 static void rtl_hw_start_8102e_2(void *ioaddr, struct pci_device *pdev)
1495 {
1496 #if 0
1497         printd("rtl_hw_start_8102e_2\n");
1498
1499         rtl_csi_access_enable(ioaddr);
1500
1501         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
1502
1503         RTL_W8(Config1, MEMMAP | IOMAP | VPD8169 | PMEnable);
1504         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
1505
1506         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
1507 #endif
1508 }
1509
1510 static void rtl_hw_start_8102e_3(void *ioaddr, struct pci_device *pdev)
1511 {
1512 #if 0
1513         printd("rtl_hw_start_8102e_3\n");
1514
1515         rtl_hw_start_8102e_2(ioaddr, pdev);
1516
1517         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
1518 #endif
1519 }
1520
1521 static void rtl_hw_start_8101(struct net_device *dev)
1522 {
1523 #if 0
1524         struct rtl8169_private *tp = netdev_priv(dev);
1525         void *ioaddr = tp->mmio_addr;
1526         struct pci_device *pdev = tp->pci_dev;
1527
1528         printd("rtl_hw_start_8101\n");
1529
1530         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
1531                 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
1532                 int cap = tp->pcie_cap;
1533
1534                 if (cap) {
1535                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
1536                                                                   PCI_EXP_DEVCTL_NOSNOOP_EN);
1537                 }
1538         }
1539
1540         switch (tp->mac_version) {
1541                 case RTL_GIGA_MAC_VER_07:
1542                         rtl_hw_start_8102e_1(ioaddr, pdev);
1543                         break;
1544
1545                 case RTL_GIGA_MAC_VER_08:
1546                         rtl_hw_start_8102e_3(ioaddr, pdev);
1547                         break;
1548
1549                 case RTL_GIGA_MAC_VER_09:
1550                         rtl_hw_start_8102e_2(ioaddr, pdev);
1551                         break;
1552         }
1553
1554         RTL_W8(Cfg9346, Cfg9346_Unlock);
1555
1556         RTL_W8(EarlyTxThres, EarlyTxThld);
1557
1558         rtl_set_rx_max_size(ioaddr);
1559
1560         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1561
1562         RTL_W16(CPlusCmd, tp->cp_cmd);
1563
1564         RTL_W16(IntrMitigate, 0x0000);
1565
1566         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1567
1568         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1569         rtl_set_rx_tx_config_registers(tp);
1570
1571         RTL_W8(Cfg9346, Cfg9346_Lock);
1572
1573         RTL_R8(IntrMask);
1574
1575         rtl_set_rx_mode(dev);
1576
1577         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1578
1579         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1580
1581         //        RTL_W16(IntrMask, tp->intr_event);
1582 #endif
1583 }
1584
1585 #if 0
1586 /*** gPXE API Support Routines ***/
1587
1588 /**
1589  * setup_tx_resources - allocate tx resources (descriptors)
1590  *
1591  * @v tp         Driver private storage
1592  *
1593  * @ret rc       Returns 0 on success, negative on failure
1594  **/
1595 static int rtl8169_setup_tx_resources(struct rtl8169_private *tp)
1596 {
1597         printd("rtl8169_setup_tx_resources\n");
1598
1599         tp->tx_base = malloc_dma(R8169_TX_RING_BYTES, TX_RING_ALIGN);
1600
1601         if (!tp->tx_base) {
1602                 return -ENOMEM;
1603         }
1604
1605         memset(tp->tx_base, 0, R8169_TX_RING_BYTES);
1606
1607         printd("tp->tx_base      = %#08lx\n", virt_to_bus(tp->tx_base));
1608
1609         tp->tx_fill_ctr = 0;
1610         tp->tx_curr = 0;
1611         tp->tx_tail = 0;
1612
1613         return 0;
1614 }
1615
1616 static void rtl8169_process_tx_packets(struct net_device *netdev)
1617 {
1618         struct rtl8169_private *tp = netdev_priv(netdev);
1619
1620         uint32_t tx_status;
1621         struct TxDesc *tx_curr_desc;
1622
1623         printd("rtl8169_process_tx_packets\n");
1624
1625         while (tp->tx_tail != tp->tx_curr) {
1626
1627                 tx_curr_desc = tp->tx_base + tp->tx_tail;
1628
1629                 tx_status = tx_curr_desc->opts1;
1630
1631                 DBG2("Before DescOwn check tx_status: %#08x\n", tx_status);
1632
1633                 /* if the packet at tx_tail is not owned by hardware it is for us */
1634                 if (tx_status & DescOwn)
1635                         break;
1636
1637                 printd("Transmitted packet.\n");
1638                 printd("tp->tx_fill_ctr     = %d\n", tp->tx_fill_ctr);
1639                 printd("tp->tx_tail         = %d\n", tp->tx_tail);
1640                 printd("tp->tx_curr         = %d\n", tp->tx_curr);
1641                 printd("tx_status           = %d\n", tx_status);
1642                 printd("tx_curr_desc        = %#08lx\n", virt_to_bus(tx_curr_desc));
1643
1644                 /* Pass packet to core for processing */
1645                 netdev_tx_complete(netdev, tp->tx_iobuf[tp->tx_tail]);
1646
1647                 memset(tx_curr_desc, 0, sizeof(*tx_curr_desc));
1648
1649                 /* Decrement count of used descriptors */
1650                 tp->tx_fill_ctr--;
1651
1652                 /* Increment sent packets index */
1653                 tp->tx_tail = (tp->tx_tail + 1) % NUM_TX_DESC;
1654         }
1655 }
1656
1657 static void rtl8169_free_tx_resources(struct rtl8169_private *tp)
1658 {
1659         printd("rtl8169_free_tx_resources\n");
1660
1661         free_dma(tp->tx_base, R8169_TX_RING_BYTES);
1662 }
1663
1664 static void
1665 rtl8169_populate_rx_descriptor(struct rtl8169_private *tp,
1666                                                            struct RxDesc *rx_desc, uint32_t index)
1667 {
1668         printd("rtl8169_populate_rx_descriptor\n");
1669
1670         printd("Populating rx descriptor %d\n", index);
1671
1672         memset(rx_desc, 0, sizeof(*rx_desc));
1673
1674         rx_desc->addr_hi = 0;
1675         rx_desc->addr_lo = virt_to_bus(tp->rx_iobuf[index]->data);
1676         rx_desc->opts2 = 0;
1677         rx_desc->opts1 = (index == (NUM_RX_DESC - 1) ? RingEnd : 0) | RX_BUF_SIZE;
1678         rx_desc->opts1 |= DescOwn;
1679 }
1680
1681 /**
1682  * Refill descriptor ring
1683  *
1684  * @v netdev            Net device
1685  */
1686 static void rtl8169_refill_rx_ring(struct rtl8169_private *tp)
1687 {
1688         struct RxDesc *rx_curr_desc;
1689         int i;
1690
1691         printd("rtl8169_refill_rx_ring\n");
1692
1693         for (i = 0; i < NUM_RX_DESC; i++) {
1694
1695                 rx_curr_desc = (tp->rx_base) + i;
1696
1697                 /* Don't touch descriptors owned by the NIC */
1698                 if (rx_curr_desc->opts1 & DescOwn)
1699                         continue;
1700
1701                 /* Don't touch descriptors with iobufs, they still need to be
1702                    processed by the poll routine */
1703                 if (tp->rx_iobuf[tp->rx_curr] != NULL)
1704                         continue;
1705
1706                 /** If we can't get an iobuf for this descriptor
1707                     try again later (next poll).
1708                  */
1709                 if (!(tp->rx_iobuf[i] = alloc_iob(RX_BUF_SIZE))) {
1710                         printd("Refill rx ring failed!!\n");
1711                         break;
1712                 }
1713
1714                 rtl8169_populate_rx_descriptor(tp, rx_curr_desc, i);
1715         }
1716 }
1717
1718 /**
1719  * setup_rx_resources - allocate Rx resources (Descriptors)
1720  *
1721  * @v tp:        Driver private structure
1722  *
1723  * @ret rc       Returns 0 on success, negative on failure
1724  *
1725  **/
1726 static int rtl8169_setup_rx_resources(struct rtl8169_private *tp)
1727 {
1728         printd("rtl8169_setup_rx_resources\n");
1729
1730         tp->rx_base = malloc_dma(R8169_RX_RING_BYTES, RX_RING_ALIGN);
1731
1732         printd("tp->rx_base      = %#08lx\n", virt_to_bus(tp->rx_base));
1733
1734         if (!tp->rx_base) {
1735                 return -ENOMEM;
1736         }
1737         memset(tp->rx_base, 0, R8169_RX_RING_BYTES);
1738
1739         rtl8169_refill_rx_ring(tp);
1740
1741         tp->rx_curr = 0;
1742
1743         return 0;
1744 }
1745
1746 static void rtl8169_process_rx_packets(struct net_device *netdev)
1747 {
1748         struct rtl8169_private *tp = netdev_priv(netdev);
1749         uint32_t rx_status;
1750         uint16_t rx_len;
1751         struct RxDesc *rx_curr_desc;
1752         int i;
1753
1754         printd("rtl8169_process_rx_packets\n");
1755
1756         for (i = 0; i < NUM_RX_DESC; i++) {
1757
1758                 rx_curr_desc = tp->rx_base + tp->rx_curr;
1759
1760                 rx_status = rx_curr_desc->opts1;
1761
1762                 DBG2("Before DescOwn check rx_status: %#08x\n", rx_status);
1763
1764                 /* Hardware still owns the descriptor */
1765                 if (rx_status & DescOwn)
1766                         break;
1767
1768                 /* We own the descriptor, but it has not been refilled yet */
1769                 if (tp->rx_iobuf[tp->rx_curr] == NULL)
1770                         break;
1771
1772                 rx_len = rx_status & 0x3fff;
1773
1774                 printd("Received packet.\n");
1775                 printd("tp->rx_curr         = %d\n", tp->rx_curr);
1776                 printd("rx_len              = %d\n", rx_len);
1777                 printd("rx_status           = %#08x\n", rx_status);
1778                 printd("rx_curr_desc        = %#08lx\n", virt_to_bus(rx_curr_desc));
1779
1780                 if (rx_status & RxRES) {
1781
1782                         netdev_rx_err(netdev, tp->rx_iobuf[tp->rx_curr], -EINVAL);
1783
1784                         printd("rtl8169_poll: Corrupted packet received!\n"
1785                                    " rx_status: %#08x\n", rx_status);
1786
1787                 } else {
1788
1789                         /* Adjust size of the iobuf to reflect received data */
1790                         iob_put(tp->rx_iobuf[tp->rx_curr], rx_len);
1791
1792                         /* Add this packet to the receive queue.  */
1793                         netdev_rx(netdev, tp->rx_iobuf[tp->rx_curr]);
1794                 }
1795
1796                 /* Invalidate this iobuf and descriptor */
1797                 tp->rx_iobuf[tp->rx_curr] = NULL;
1798                 memset(rx_curr_desc, 0, sizeof(*rx_curr_desc));
1799
1800                 /* Update pointer to next available rx descriptor */
1801                 tp->rx_curr = (tp->rx_curr + 1) % NUM_RX_DESC;
1802         }
1803         rtl8169_refill_rx_ring(tp);
1804 }
1805
1806 static void rtl8169_free_rx_resources(struct rtl8169_private *tp)
1807 {
1808         int i;
1809
1810         printd("rtl8169_free_rx_resources\n");
1811
1812         free_dma(tp->rx_base, R8169_RX_RING_BYTES);
1813
1814         for (i = 0; i < NUM_RX_DESC; i++) {
1815                 free_iob(tp->rx_iobuf[i]);
1816                 tp->rx_iobuf[i] = NULL;
1817         }
1818 }
1819
1820 static void rtl8169_irq_enable(struct rtl8169_private *tp)
1821 {
1822         void *ioaddr = tp->mmio_addr;
1823
1824         printd("rtl8169_irq_enable\n");
1825
1826         RTL_W16(IntrMask, tp->intr_event);
1827 }
1828
1829 static void rtl8169_irq_disable(struct rtl8169_private *tp)
1830 {
1831         void *ioaddr = tp->mmio_addr;
1832
1833         printd("rtl8169_irq_disable\n");
1834
1835         rtl8169_irq_mask_and_ack(ioaddr);
1836 }
1837
1838 /*** gPXE Core API Routines ***/
1839
1840 /**
1841  * open - Called when a network interface is made active
1842  *
1843  * @v netdev    network interface device structure
1844  * @ret rc      Return status code, 0 on success, negative value on failure
1845  *
1846  **/
1847 static int rtl8169_open(struct net_device *netdev)
1848 {
1849         struct rtl8169_private *tp = netdev_priv(netdev);
1850         void *ioaddr = tp->mmio_addr;
1851         int rc;
1852
1853         printd("rtl8169_open\n");
1854
1855         /* allocate transmit descriptors */
1856         rc = rtl8169_setup_tx_resources(tp);
1857         if (rc) {
1858                 printd("Error setting up TX resources!\n");
1859                 goto err_setup_tx;
1860         }
1861
1862         /* allocate receive descriptors */
1863         rc = rtl8169_setup_rx_resources(tp);
1864         if (rc) {
1865                 printd("Error setting up RX resources!\n");
1866                 goto err_setup_rx;
1867         }
1868
1869         rtl_hw_start(netdev);
1870
1871         printd("TxDescStartAddrHigh   = %#08lx\n", RTL_R32(TxDescStartAddrHigh));
1872         printd("TxDescStartAddrLow    = %#08lx\n", RTL_R32(TxDescStartAddrLow));
1873         printd("RxDescAddrHigh        = %#08lx\n", RTL_R32(RxDescAddrHigh));
1874         printd("RxDescAddrLow         = %#08lx\n", RTL_R32(RxDescAddrLow));
1875
1876         return 0;
1877
1878 err_setup_rx:
1879         rtl8169_free_tx_resources(tp);
1880 err_setup_tx:
1881         rtl8169_hw_reset(ioaddr);
1882
1883         return rc;
1884 }
1885
1886 /**
1887  * transmit - Transmit a packet
1888  *
1889  * @v netdev    Network device
1890  * @v iobuf     I/O buffer
1891  *
1892  * @ret rc       Returns 0 on success, negative on failure
1893  */
1894 static int rtl8169_transmit(struct net_device *netdev, struct io_buffer *iobuf)
1895 {
1896         struct rtl8169_private *tp = netdev_priv(netdev);
1897         void *ioaddr = tp->mmio_addr;
1898         uint32_t tx_len = iob_len(iobuf);
1899
1900         struct TxDesc *tx_curr_desc;
1901
1902         printd("rtl8169_transmit\n");
1903
1904         if (tp->tx_fill_ctr == NUM_TX_DESC) {
1905                 printd("TX overflow\n");
1906                 return -ENOBUFS;
1907         }
1908
1909         /**
1910          *  The rtl8169 family automatically pads short packets to a
1911          *  minimum size, but if it did not, like some older cards,
1912          *  we could do:
1913          *  iob_pad ( iobuf, ETH_ZLEN );
1914          */
1915
1916         /* Save pointer to this iobuf we have been given to transmit so
1917            we can pass it to netdev_tx_complete() later */
1918         tp->tx_iobuf[tp->tx_curr] = iobuf;
1919
1920         tx_curr_desc = tp->tx_base + tp->tx_curr;
1921
1922         printd("tp->tx_fill_ctr = %d\n", tp->tx_fill_ctr);
1923         printd("tp->tx_curr     = %d\n", tp->tx_curr);
1924         printd("tx_curr_desc    = %#08lx\n", virt_to_bus(tx_curr_desc));
1925         printd("iobuf->data     = %#08lx\n", virt_to_bus(iobuf->data));
1926         printd("tx_len          = %d\n", tx_len);
1927
1928         /* Configure current descriptor to transmit supplied packet */
1929         tx_curr_desc->addr_hi = 0;
1930         tx_curr_desc->addr_lo = virt_to_bus(iobuf->data);
1931         tx_curr_desc->opts2 = 0;
1932         tx_curr_desc->opts1 = FirstFrag | LastFrag |
1933                 (tp->tx_curr == (NUM_TX_DESC - 1) ? RingEnd : 0) | tx_len;
1934
1935         /* Mark descriptor as owned by NIC */
1936         tx_curr_desc->opts1 |= DescOwn;
1937
1938         printd("tx_curr_desc->opts1   = %#08x\n", tx_curr_desc->opts1);
1939         printd("tx_curr_desc->opts2   = %#08x\n", tx_curr_desc->opts2);
1940         printd("tx_curr_desc->addr_hi = %#08x\n", tx_curr_desc->addr_hi);
1941         printd("tx_curr_desc->addr_lo = %#08x\n", tx_curr_desc->addr_lo);
1942
1943         RTL_W8(TxPoll, NPQ);    /* set polling bit */
1944
1945         /* Point to next free descriptor */
1946         tp->tx_curr = (tp->tx_curr + 1) % NUM_TX_DESC;
1947
1948         /* Increment number of tx descriptors in use */
1949         tp->tx_fill_ctr++;
1950
1951         return 0;
1952 }
1953
1954 /**
1955  * poll - Poll for received packets
1956  *
1957  * @v netdev    Network device
1958  */
1959 static void rtl8169_poll(struct net_device *netdev)
1960 {
1961         struct rtl8169_private *tp = netdev_priv(netdev);
1962         void *ioaddr = tp->mmio_addr;
1963
1964         uint16_t intr_status;
1965         uint16_t intr_mask;
1966
1967         printd("rtl8169_poll\n");
1968
1969         intr_status = RTL_R16(IntrStatus);
1970         intr_mask = RTL_R16(IntrMask);
1971
1972         DBG2("rtl8169_poll (before): intr_mask = %#04x  intr_status = %#04x\n",
1973                  intr_mask, intr_status);
1974
1975         RTL_W16(IntrStatus, 0xffff);
1976
1977         /* hotplug / major error / no more work / shared irq */
1978         if (intr_status == 0xffff)
1979                 return;
1980
1981         /* Process transmitted packets */
1982         rtl8169_process_tx_packets(netdev);
1983
1984         /* Process received packets  */
1985         rtl8169_process_rx_packets(netdev);
1986 }
1987
1988 /**
1989  * close - Disable network interface
1990  *
1991  * @v netdev    network interface device structure
1992  *
1993  **/
1994 static void rtl8169_close(struct net_device *netdev)
1995 {
1996         struct rtl8169_private *tp = netdev_priv(netdev);
1997         void *ioaddr = tp->mmio_addr;
1998
1999         printd("r8169_close\n");
2000
2001         rtl8169_hw_reset(ioaddr);
2002
2003         rtl8169_free_tx_resources(tp);
2004         rtl8169_free_rx_resources(tp);
2005 }
2006
2007 /**
2008  * irq - enable or Disable interrupts
2009  *
2010  * @v netdev    network adapter
2011  * @v action    requested interrupt action
2012  *
2013  **/
2014 static void rtl8169_irq(struct net_device *netdev, int action)
2015 {
2016         struct rtl8169_private *tp = netdev_priv(netdev);
2017
2018         printd("rtl8169_irq\n");
2019
2020         switch (action) {
2021                 case 0:
2022                         rtl8169_irq_disable(tp);
2023                         break;
2024                 default:
2025                         rtl8169_irq_enable(tp);
2026                         break;
2027         }
2028 }
2029
2030 static struct net_device_operations rtl8169_operations = {
2031         .open = rtl8169_open,
2032         .transmit = rtl8169_transmit,
2033         .poll = rtl8169_poll,
2034         .close = rtl8169_close,
2035         .irq = rtl8169_irq,
2036 };
2037
2038 /**
2039  * probe - Initial configuration of NIC
2040  *
2041  * @v pci       PCI device
2042  * @v id        PCI IDs
2043  *
2044  * @ret rc      Return status code
2045  **/
2046 static int
2047 rtl8169_probe(struct pci_device *pdev, const struct pci_device_id *ent)
2048 {
2049         int i, rc;
2050         struct net_device *netdev;
2051         struct rtl8169_private *tp;
2052         void *ioaddr;
2053
2054         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2055
2056         printd("rtl8169_probe\n");
2057
2058         printd("ent->vendor = %#04x, ent->device = %#04x\n", ent->vendor,
2059                    ent->device);
2060
2061         printd("cfg->intr_event = %#04x\n", cfg->intr_event);
2062
2063         rc = -ENOMEM;
2064
2065         /* Allocate net device ( also allocates memory for netdev->priv
2066            and makes netdev-priv point to it )
2067          */
2068         netdev = alloc_etherdev(sizeof(*tp));
2069
2070         if (!netdev)
2071                 goto err_alloc_etherdev;
2072
2073         /* Associate driver-specific network operations with
2074            generic network device layer
2075          */
2076         netdev_init(netdev, &rtl8169_operations);
2077
2078         /* Associate this network device with the given PCI device */
2079         pci_set_drvdata(pdev, netdev);
2080         netdev->dev = &pdev->dev;
2081
2082         /* Initialize driver private storage */
2083         tp = netdev_priv(netdev);
2084         memset(tp, 0, (sizeof(*tp)));
2085
2086         tp->pci_dev = pdev;
2087         tp->irqno = pdev->irq;
2088         tp->netdev = netdev;
2089         tp->intr_event = cfg->intr_event;
2090         tp->cp_cmd = PCIMulRW;
2091
2092         tp->hw_start = cfg->hw_start;
2093
2094         rc = -EIO;
2095
2096         adjust_pci_device(pdev);
2097
2098         /* ioremap MMIO region */
2099         ioaddr = ioremap(pdev->membase, R8169_REGS_SIZE);
2100
2101         if (!ioaddr) {
2102                 printd("cannot remap MMIO\n");
2103                 rc = -EIO;
2104                 goto err_ioremap;
2105         }
2106
2107         tp->mmio_addr = ioaddr;
2108
2109         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2110         if (tp->pcie_cap) {
2111                 printd("PCI Express capability\n");
2112         } else {
2113                 printd("No PCI Express capability\n");
2114         }
2115
2116         /* Mask interrupts just in case */
2117         rtl8169_irq_mask_and_ack(ioaddr);
2118
2119         /* Soft reset NIC */
2120         rtl_soft_reset(netdev);
2121
2122         /* Identify chip attached to board */
2123         rtl8169_get_mac_version(tp, ioaddr);
2124
2125         for (i = 0; (uint32_t) i < ARRAY_SIZE(rtl_chip_info); i++) {
2126                 if (tp->mac_version == rtl_chip_info[i].mac_version)
2127                         break;
2128         }
2129         if (i == ARRAY_SIZE(rtl_chip_info)) {
2130                 /* Unknown chip: assume array element #0, original RTL-8169 */
2131                 printd("Unknown chip version, assuming %s\n", rtl_chip_info[0].name);
2132                 i = 0;
2133         }
2134         tp->chipset = i;
2135
2136         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2137                 (RTL_R8(PHYstatus) & TBI_Enable)) {
2138                 tp->set_speed = rtl8169_set_speed_tbi;
2139                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2140                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2141                 tp->link_ok = rtl8169_tbi_link_ok;
2142
2143                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL;     /* Implied by TBI */
2144         } else {
2145                 tp->set_speed = rtl8169_set_speed_xmii;
2146                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2147                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2148                 tp->link_ok = rtl8169_xmii_link_ok;
2149         }
2150
2151         /* Get MAC address */
2152         for (i = 0; i < MAC_ADDR_LEN; i++)
2153                 netdev->hw_addr[i] = RTL_R8(MAC0 + i);
2154
2155         printd("%s\n", eth_ntoa(netdev->hw_addr));
2156
2157         rtl8169_init_phy(netdev, tp);
2158
2159         if ((rc = register_netdev(netdev)) != 0)
2160                 goto err_register;
2161
2162         /* Mark as link up; we don't yet handle link state */
2163         netdev_link_up(netdev);
2164
2165         printd("rtl8169_probe succeeded!\n");
2166
2167         /* No errors, return success */
2168         return 0;
2169
2170 /* Error return paths */
2171 err_register:
2172 err_ioremap:
2173         netdev_put(netdev);
2174 err_alloc_etherdev:
2175         return rc;
2176 }
2177
2178 /**
2179  * remove - Device Removal Routine
2180  *
2181  * @v pdev PCI device information struct
2182  *
2183  **/
2184 static void rtl8169_remove(struct pci_device *pdev)
2185 {
2186         struct net_device *netdev = pci_get_drvdata(pdev);
2187         struct rtl8169_private *tp = netdev_priv(netdev);
2188         void *ioaddr = tp->mmio_addr;
2189
2190         printd("rtl8169_remove\n");
2191
2192         rtl8169_hw_reset(ioaddr);
2193
2194         unregister_netdev(netdev);
2195         netdev_nullify(netdev);
2196         netdev_put(netdev);
2197 }
2198
2199 static struct pci_device_id rtl8169_nics[] = {
2200         PCI_ROM(0x10ec, 0x8129, "rtl8169-0x8129", "rtl8169-0x8129", RTL_CFG_0),
2201         PCI_ROM(0x10ec, 0x8136, "rtl8169-0x8136", "rtl8169-0x8136", RTL_CFG_2),
2202         PCI_ROM(0x10ec, 0x8167, "rtl8169-0x8167", "rtl8169-0x8167", RTL_CFG_0),
2203         PCI_ROM(0x10ec, 0x8168, "rtl8169-0x8168", "rtl8169-0x8168", RTL_CFG_1),
2204         PCI_ROM(0x10ec, 0x8169, "rtl8169-0x8169", "rtl8169-0x8169", RTL_CFG_0),
2205         PCI_ROM(0x1186, 0x4300, "rtl8169-0x4300", "rtl8169-0x4300", RTL_CFG_0),
2206         PCI_ROM(0x1259, 0xc107, "rtl8169-0xc107", "rtl8169-0xc107", RTL_CFG_0),
2207         PCI_ROM(0x16ec, 0x0116, "rtl8169-0x0116", "rtl8169-0x0116", RTL_CFG_0),
2208         PCI_ROM(0x1737, 0x1032, "rtl8169-0x1032", "rtl8169-0x1032", RTL_CFG_0),
2209         PCI_ROM(0x0001, 0x8168, "rtl8169-0x8168", "rtl8169-0x8168", RTL_CFG_2),
2210 };
2211
2212 struct pci_driver rtl8169_driver __pci_driver = {
2213         .ids = rtl8169_nics,
2214         .id_count = (sizeof(rtl8169_nics) / sizeof(rtl8169_nics[0])),
2215         .probe = rtl8169_probe,
2216         .remove = rtl8169_remove,
2217 };
2218 #endif
2219
2220 linker_func_3(ether8169link)
2221 {
2222         //addethercard("rtl8169", rtl8169pnp);
2223 }
2224
2225 /*
2226  * Local variables:
2227  *  c-basic-offset: 8
2228  *  c-indent-level: 8
2229  *  tab-width: 8
2230  * End:
2231  */