Return real vendor/part id in query_device
[akaros.git] / kern / drivers / net / mlx4u / qp.c
1 /*
2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33
34 #if 0   /* AKAROS */
35 #include <linux/log2.h>
36 #include <linux/slab.h>
37 #include <linux/netdevice.h>
38
39 #include <rdma/ib_cache.h>
40 #include <rdma/ib_pack.h>
41 #include <rdma/ib_addr.h>
42 #include <rdma/ib_mad.h>
43 #endif  /* AKAROS */
44
45 #include <linux/mlx4/driver.h>
46 #include <linux/mlx4/qp.h>
47
48 #include "mlx4_ib.h"
49 #include "user.h"
50
51 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
52                              struct mlx4_ib_cq *recv_cq);
53 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
54                                struct mlx4_ib_cq *recv_cq);
55
56 enum {
57         MLX4_IB_ACK_REQ_FREQ    = 8,
58 };
59
60 enum {
61         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
62         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
63         MLX4_IB_LINK_TYPE_IB            = 0,
64         MLX4_IB_LINK_TYPE_ETH           = 1
65 };
66
67 enum {
68         /*
69          * Largest possible UD header: send with GRH and immediate
70          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
71          * tag.  (LRH would only use 8 bytes, so Ethernet is the
72          * biggest case)
73          */
74         MLX4_IB_UD_HEADER_SIZE          = 82,
75         MLX4_IB_LSO_HEADER_SPARE        = 128,
76 };
77
78 enum {
79         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
80 };
81
82 struct mlx4_ib_sqp {
83         struct mlx4_ib_qp       qp;
84         int                     pkey_index;
85         u32                     qkey;
86         u32                     send_psn;
87         struct ib_ud_header     ud_header;
88         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
89 };
90
91 enum {
92         MLX4_IB_MIN_SQ_STRIDE   = 6,
93         MLX4_IB_CACHE_LINE_SIZE = 64,
94 };
95
96 enum {
97         MLX4_RAW_QP_MTU         = 7,
98         MLX4_RAW_QP_MSGMAX      = 31,
99 };
100
101 #ifndef ETH_ALEN
102 #define ETH_ALEN        6
103 #endif
104
105 static const __be32 mlx4_ib_opcode[] = {
106         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
107         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
108         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
109         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
110         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
111         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
112         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
113         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
114         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
115         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
116         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
117         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
118         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
119         [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
120 };
121
122 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
123 {
124         return container_of(mqp, struct mlx4_ib_sqp, qp);
125 }
126
127 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
128 {
129         if (!mlx4_is_master(dev->dev))
130                 return 0;
131
132         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
133                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
134                 8 * MLX4_MFUNC_MAX;
135 }
136
137 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
138 {
139         int proxy_sqp = 0;
140         int real_sqp = 0;
141         int i;
142         /* PPF or Native -- real SQP */
143         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
144                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
145                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
146         if (real_sqp)
147                 return 1;
148         /* VF or PF -- proxy SQP */
149         if (mlx4_is_mfunc(dev->dev)) {
150                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
151                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
152                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
153                                 proxy_sqp = 1;
154                                 break;
155                         }
156                 }
157         }
158         return proxy_sqp;
159 }
160
161 /* used for INIT/CLOSE port logic */
162 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
163 {
164         int proxy_qp0 = 0;
165         int real_qp0 = 0;
166         int i;
167         /* PPF or Native -- real QP0 */
168         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
169                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
170                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
171         if (real_qp0)
172                 return 1;
173         /* VF or PF -- proxy QP0 */
174         if (mlx4_is_mfunc(dev->dev)) {
175                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
176                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
177                                 proxy_qp0 = 1;
178                                 break;
179                         }
180                 }
181         }
182         return proxy_qp0;
183 }
184
185 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
186 {
187         return mlx4_buf_offset(&qp->buf, offset);
188 }
189
190 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
191 {
192         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
193 }
194
195 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
196 {
197         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
198 }
199
200 /*
201  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
202  * first four bytes of every 64 byte chunk with
203  *     0x7FFFFFF | (invalid_ownership_value << 31).
204  *
205  * When the max work request size is less than or equal to the WQE
206  * basic block size, as an optimization, we can stamp all WQEs with
207  * 0xffffffff, and skip the very first chunk of each WQE.
208  */
209 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
210 {
211         __be32 *wqe;
212         int i;
213         int s;
214         int ind;
215         void *buf;
216         __be32 stamp;
217         struct mlx4_wqe_ctrl_seg *ctrl;
218
219         if (qp->sq_max_wqes_per_wr > 1) {
220                 s = roundup(size, 1U << qp->sq.wqe_shift);
221                 for (i = 0; i < s; i += 64) {
222                         ind = (i >> qp->sq.wqe_shift) + n;
223                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
224                                                        cpu_to_be32(0xffffffff);
225                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
226                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
227                         *wqe = stamp;
228                 }
229         } else {
230                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
231                 s = (ctrl->fence_size & 0x3f) << 4;
232                 for (i = 64; i < s; i += 64) {
233                         wqe = buf + i;
234                         *wqe = cpu_to_be32(0xffffffff);
235                 }
236         }
237 }
238
239 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
240 {
241         struct mlx4_wqe_ctrl_seg *ctrl;
242         struct mlx4_wqe_inline_seg *inl;
243         void *wqe;
244         int s;
245
246         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
247         s = sizeof(struct mlx4_wqe_ctrl_seg);
248
249         if (qp->ibqp.qp_type == IB_QPT_UD) {
250                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
251                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
252                 memset(dgram, 0, sizeof *dgram);
253                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
254                 s += sizeof(struct mlx4_wqe_datagram_seg);
255         }
256
257         /* Pad the remainder of the WQE with an inline data segment. */
258         if (size > s) {
259                 inl = wqe + s;
260                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
261         }
262         ctrl->srcrb_flags = 0;
263         ctrl->fence_size = size / 16;
264         /*
265          * Make sure descriptor is fully written before setting ownership bit
266          * (because HW can start executing as soon as we do).
267          */
268         wmb();
269
270         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
271                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
272
273         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
274 }
275
276 /* Post NOP WQE to prevent wrap-around in the middle of WR */
277 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
278 {
279         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
280         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
281                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
282                 ind += s;
283         }
284         return ind;
285 }
286
287 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
288 {
289         struct ib_event event;
290         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
291
292         if (type == MLX4_EVENT_TYPE_PATH_MIG)
293                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
294
295         if (ibqp->event_handler) {
296                 event.device     = ibqp->device;
297                 event.element.qp = ibqp;
298                 switch (type) {
299                 case MLX4_EVENT_TYPE_PATH_MIG:
300                         event.event = IB_EVENT_PATH_MIG;
301                         break;
302                 case MLX4_EVENT_TYPE_COMM_EST:
303                         event.event = IB_EVENT_COMM_EST;
304                         break;
305                 case MLX4_EVENT_TYPE_SQ_DRAINED:
306                         event.event = IB_EVENT_SQ_DRAINED;
307                         break;
308                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
309                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
310                         break;
311                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
312                         event.event = IB_EVENT_QP_FATAL;
313                         break;
314                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
315                         event.event = IB_EVENT_PATH_MIG_ERR;
316                         break;
317                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
318                         event.event = IB_EVENT_QP_REQ_ERR;
319                         break;
320                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
321                         event.event = IB_EVENT_QP_ACCESS_ERR;
322                         break;
323                 default:
324                         pr_warn("Unexpected event type %d "
325                                "on QP %06x\n", type, qp->qpn);
326                         return;
327                 }
328
329                 ibqp->event_handler(&event, ibqp->qp_context);
330         }
331 }
332
333 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
334 {
335         /*
336          * UD WQEs must have a datagram segment.
337          * RC and UC WQEs might have a remote address segment.
338          * MLX WQEs need two extra inline data segments (for the UD
339          * header and space for the ICRC).
340          */
341         switch (type) {
342         case MLX4_IB_QPT_UD:
343                 return sizeof (struct mlx4_wqe_ctrl_seg) +
344                         sizeof (struct mlx4_wqe_datagram_seg) +
345                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
346         case MLX4_IB_QPT_PROXY_SMI_OWNER:
347         case MLX4_IB_QPT_PROXY_SMI:
348         case MLX4_IB_QPT_PROXY_GSI:
349                 return sizeof (struct mlx4_wqe_ctrl_seg) +
350                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
351         case MLX4_IB_QPT_TUN_SMI_OWNER:
352         case MLX4_IB_QPT_TUN_GSI:
353                 return sizeof (struct mlx4_wqe_ctrl_seg) +
354                         sizeof (struct mlx4_wqe_datagram_seg);
355
356         case MLX4_IB_QPT_UC:
357                 return sizeof (struct mlx4_wqe_ctrl_seg) +
358                         sizeof (struct mlx4_wqe_raddr_seg);
359         case MLX4_IB_QPT_RC:
360                 return sizeof (struct mlx4_wqe_ctrl_seg) +
361                         sizeof (struct mlx4_wqe_atomic_seg) +
362                         sizeof (struct mlx4_wqe_raddr_seg);
363         case MLX4_IB_QPT_SMI:
364         case MLX4_IB_QPT_GSI:
365                 return sizeof (struct mlx4_wqe_ctrl_seg) +
366                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
367                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
368                                            MLX4_INLINE_ALIGN) *
369                               sizeof (struct mlx4_wqe_inline_seg),
370                               sizeof (struct mlx4_wqe_data_seg)) +
371                         ALIGN(4 +
372                               sizeof (struct mlx4_wqe_inline_seg),
373                               sizeof (struct mlx4_wqe_data_seg));
374         default:
375                 return sizeof (struct mlx4_wqe_ctrl_seg);
376         }
377 }
378
379 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
380                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
381 {
382         /* Sanity check RQ size before proceeding */
383         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
384             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
385                 return -EINVAL;
386
387         if (!has_rq) {
388                 if (cap->max_recv_wr)
389                         return -EINVAL;
390
391                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
392         } else {
393                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
394                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
395                         return -EINVAL;
396
397                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
398                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
399                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
400         }
401
402         /* leave userspace return values as they were, so as not to break ABI */
403         if (is_user) {
404                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
405                 cap->max_recv_sge = qp->rq.max_gs;
406         } else {
407                 cap->max_recv_wr  = qp->rq.max_post =
408                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
409                 cap->max_recv_sge = min(qp->rq.max_gs,
410                                         min(dev->dev->caps.max_sq_sg,
411                                             dev->dev->caps.max_rq_sg));
412         }
413
414         return 0;
415 }
416
417 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
418                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
419 {
420         int s;
421
422         /* Sanity check SQ size before proceeding */
423         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
424             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
425             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
426             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
427                 return -EINVAL;
428
429         /*
430          * For MLX transport we need 2 extra S/G entries:
431          * one for the header and one for the checksum at the end
432          */
433         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
434              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
435             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
436                 return -EINVAL;
437
438         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
439                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
440                 send_wqe_overhead(type, qp->flags);
441
442         if (s > dev->dev->caps.max_sq_desc_sz)
443                 return -EINVAL;
444
445         /*
446          * Hermon supports shrinking WQEs, such that a single work
447          * request can include multiple units of 1 << wqe_shift.  This
448          * way, work requests can differ in size, and do not have to
449          * be a power of 2 in size, saving memory and speeding up send
450          * WR posting.  Unfortunately, if we do this then the
451          * wqe_index field in CQEs can't be used to look up the WR ID
452          * anymore, so we do this only if selective signaling is off.
453          *
454          * Further, on 32-bit platforms, we can't use vmap() to make
455          * the QP buffer virtually contiguous.  Thus we have to use
456          * constant-sized WRs to make sure a WR is always fully within
457          * a single page-sized chunk.
458          *
459          * Finally, we use NOP work requests to pad the end of the
460          * work queue, to avoid wrap-around in the middle of WR.  We
461          * set NEC bit to avoid getting completions with error for
462          * these NOP WRs, but since NEC is only supported starting
463          * with firmware 2.2.232, we use constant-sized WRs for older
464          * firmware.
465          *
466          * And, since MLX QPs only support SEND, we use constant-sized
467          * WRs in this case.
468          *
469          * We look for the smallest value of wqe_shift such that the
470          * resulting number of wqes does not exceed device
471          * capabilities.
472          *
473          * We set WQE size to at least 64 bytes, this way stamping
474          * invalidates each WQE.
475          */
476         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
477             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
478             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
479             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
480                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
481                 qp->sq.wqe_shift = ilog2(64);
482         else
483                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
484
485         for (;;) {
486                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
487
488                 /*
489                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
490                  * allow HW to prefetch.
491                  */
492                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
493                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
494                                                     qp->sq_max_wqes_per_wr +
495                                                     qp->sq_spare_wqes);
496
497                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
498                         break;
499
500                 if (qp->sq_max_wqes_per_wr <= 1)
501                         return -EINVAL;
502
503                 ++qp->sq.wqe_shift;
504         }
505
506         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
507                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
508                          send_wqe_overhead(type, qp->flags)) /
509                 sizeof (struct mlx4_wqe_data_seg);
510
511         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
512                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
513         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
514                 qp->rq.offset = 0;
515                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
516         } else {
517                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
518                 qp->sq.offset = 0;
519         }
520
521         cap->max_send_wr  = qp->sq.max_post =
522                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
523         cap->max_send_sge = min(qp->sq.max_gs,
524                                 min(dev->dev->caps.max_sq_sg,
525                                     dev->dev->caps.max_rq_sg));
526         /* We don't support inline sends for kernel QPs (yet) */
527         cap->max_inline_data = 0;
528
529         return 0;
530 }
531
532 static int set_user_sq_size(struct mlx4_ib_dev *dev,
533                             struct mlx4_ib_qp *qp,
534                             struct mlx4_ib_create_qp *ucmd)
535 {
536         /* Sanity check SQ size before proceeding */
537         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
538             ucmd->log_sq_stride >
539                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
540             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
541                 return -EINVAL;
542
543         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
544         qp->sq.wqe_shift = ucmd->log_sq_stride;
545
546         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
547                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
548
549         return 0;
550 }
551
552 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
553 {
554         int i;
555
556         qp->sqp_proxy_rcv =
557                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
558                         GFP_KERNEL);
559         if (!qp->sqp_proxy_rcv)
560                 return -ENOMEM;
561         for (i = 0; i < qp->rq.wqe_cnt; i++) {
562                 qp->sqp_proxy_rcv[i].addr =
563                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
564                                 GFP_KERNEL);
565                 if (!qp->sqp_proxy_rcv[i].addr)
566                         goto err;
567                 qp->sqp_proxy_rcv[i].map =
568                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
569                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
570                                           DMA_FROM_DEVICE);
571                 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
572                         kfree(qp->sqp_proxy_rcv[i].addr);
573                         goto err;
574                 }
575         }
576         return 0;
577
578 err:
579         while (i > 0) {
580                 --i;
581                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
582                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
583                                     DMA_FROM_DEVICE);
584                 kfree(qp->sqp_proxy_rcv[i].addr);
585         }
586         kfree(qp->sqp_proxy_rcv);
587         qp->sqp_proxy_rcv = NULL;
588         return -ENOMEM;
589 }
590
591 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
592 {
593         int i;
594
595         for (i = 0; i < qp->rq.wqe_cnt; i++) {
596                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
597                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
598                                     DMA_FROM_DEVICE);
599                 kfree(qp->sqp_proxy_rcv[i].addr);
600         }
601         kfree(qp->sqp_proxy_rcv);
602 }
603
604 static int qp_has_rq(struct ib_qp_init_attr *attr)
605 {
606         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
607                 return 0;
608
609         return !attr->srq;
610 }
611
612 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
613 {
614         int i;
615         for (i = 0; i < dev->caps.num_ports; i++) {
616                 if (qpn == dev->caps.qp0_proxy[i])
617                         return !!dev->caps.qp0_qkey[i];
618         }
619         return 0;
620 }
621
622 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
623                             struct ib_qp_init_attr *init_attr,
624                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
625                             gfp_t gfp)
626 {
627         int qpn;
628         int err;
629         struct mlx4_ib_sqp *sqp;
630         struct mlx4_ib_qp *qp;
631         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
632         struct mlx4_ib_cq *mcq;
633         unsigned long flags;
634
635         /* When tunneling special qps, we use a plain UD qp */
636         if (sqpn) {
637                 if (mlx4_is_mfunc(dev->dev) &&
638                     (!mlx4_is_master(dev->dev) ||
639                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
640                         if (init_attr->qp_type == IB_QPT_GSI)
641                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
642                         else {
643                                 if (mlx4_is_master(dev->dev) ||
644                                     qp0_enabled_vf(dev->dev, sqpn))
645                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
646                                 else
647                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
648                         }
649                 }
650                 qpn = sqpn;
651                 /* add extra sg entry for tunneling */
652                 init_attr->cap.max_recv_sge++;
653         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
654                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
655                         container_of(init_attr,
656                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
657                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
658                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
659                     !mlx4_is_master(dev->dev))
660                         return -EINVAL;
661                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
662                         qp_type = MLX4_IB_QPT_TUN_GSI;
663                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
664                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
665                                              tnl_init->port))
666                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
667                 else
668                         qp_type = MLX4_IB_QPT_TUN_SMI;
669                 /* we are definitely in the PPF here, since we are creating
670                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
671                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
672                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
673                 sqpn = qpn;
674         }
675
676         if (!*caller_qp) {
677                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
678                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
679                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
680                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
681                         if (!sqp)
682                                 return -ENOMEM;
683                         qp = &sqp->qp;
684                         qp->pri.vid = 0xFFFF;
685                         qp->alt.vid = 0xFFFF;
686                 } else {
687                         qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
688                         if (!qp)
689                                 return -ENOMEM;
690                         qp->pri.vid = 0xFFFF;
691                         qp->alt.vid = 0xFFFF;
692                 }
693         } else
694                 qp = *caller_qp;
695
696         qp->mlx4_ib_qp_type = qp_type;
697
698         mutex_init(&qp->mutex);
699         spin_lock_init(&qp->sq.lock);
700         spin_lock_init(&qp->rq.lock);
701         INIT_LIST_HEAD(&qp->gid_list);
702         INIT_LIST_HEAD(&qp->steering_rules);
703
704         qp->state        = IB_QPS_RESET;
705         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
706                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
707
708         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
709         if (err)
710                 goto err;
711
712         if (pd->uobject) {
713                 struct mlx4_ib_create_qp ucmd;
714
715                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
716                         err = -EFAULT;
717                         goto err;
718                 }
719
720                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
721
722                 err = set_user_sq_size(dev, qp, &ucmd);
723                 if (err)
724                         goto err;
725
726                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
727                                        qp->buf_size, 0, 0);
728                 if (IS_ERR(qp->umem)) {
729                         err = PTR_ERR(qp->umem);
730                         goto err;
731                 }
732
733                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
734                                     ilog2(qp->umem->page_size), &qp->mtt);
735                 if (err)
736                         goto err_buf;
737
738                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
739                 if (err)
740                         goto err_mtt;
741
742                 if (qp_has_rq(init_attr)) {
743                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
744                                                   ucmd.db_addr, &qp->db);
745                         if (err)
746                                 goto err_mtt;
747                 }
748         } else {
749                 qp->sq_no_prefetch = 0;
750
751                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
752                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
753
754                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
755                         qp->flags |= MLX4_IB_QP_LSO;
756
757                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
758                         if (dev->steering_support ==
759                             MLX4_STEERING_MODE_DEVICE_MANAGED)
760                                 qp->flags |= MLX4_IB_QP_NETIF;
761                         else
762                                 goto err;
763                 }
764
765                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
766                 if (err)
767                         goto err;
768
769                 if (qp_has_rq(init_attr)) {
770                         err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
771                         if (err)
772                                 goto err;
773
774                         *qp->db.db = 0;
775                 }
776
777                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
778                         err = -ENOMEM;
779                         goto err_db;
780                 }
781
782                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
783                                     &qp->mtt);
784                 if (err)
785                         goto err_buf;
786
787                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
788                 if (err)
789                         goto err_mtt;
790
791                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
792                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
793                 if (!qp->sq.wrid || !qp->rq.wrid) {
794                         err = -ENOMEM;
795                         goto err_wrid;
796                 }
797         }
798
799         if (sqpn) {
800                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
801                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
802                         if (alloc_proxy_bufs(pd->device, qp)) {
803                                 err = -ENOMEM;
804                                 goto err_wrid;
805                         }
806                 }
807         } else {
808                 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
809                  * otherwise, the WQE BlueFlame setup flow wrongly causes
810                  * VLAN insertion. */
811                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
812                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
813                                                     (init_attr->cap.max_send_wr ?
814                                                      MLX4_RESERVE_ETH_BF_QP : 0) |
815                                                     (init_attr->cap.max_recv_wr ?
816                                                      MLX4_RESERVE_A0_QP : 0));
817                 else
818                         if (qp->flags & MLX4_IB_QP_NETIF)
819                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
820                         else
821                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
822                                                             &qpn, 0);
823                 if (err)
824                         goto err_proxy;
825         }
826
827         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
828         if (err)
829                 goto err_qpn;
830
831         if (init_attr->qp_type == IB_QPT_XRC_TGT)
832                 qp->mqp.qpn |= (1 << 23);
833
834         /*
835          * Hardware wants QPN written in big-endian order (after
836          * shifting) for send doorbell.  Precompute this value to save
837          * a little bit when posting sends.
838          */
839         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
840
841         qp->mqp.event = mlx4_ib_qp_event;
842         if (!*caller_qp)
843                 *caller_qp = qp;
844
845         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
846         mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
847                          to_mcq(init_attr->recv_cq));
848         /* Maintain device to QPs access, needed for further handling
849          * via reset flow
850          */
851         list_add_tail(&qp->qps_list, &dev->qp_list);
852         /* Maintain CQ to QPs access, needed for further handling
853          * via reset flow
854          */
855         mcq = to_mcq(init_attr->send_cq);
856         list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
857         mcq = to_mcq(init_attr->recv_cq);
858         list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
859         mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
860                            to_mcq(init_attr->recv_cq));
861         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
862         return 0;
863
864 err_qpn:
865         if (!sqpn) {
866                 if (qp->flags & MLX4_IB_QP_NETIF)
867                         mlx4_ib_steer_qp_free(dev, qpn, 1);
868                 else
869                         mlx4_qp_release_range(dev->dev, qpn, 1);
870         }
871 err_proxy:
872         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
873                 free_proxy_bufs(pd->device, qp);
874 err_wrid:
875         if (pd->uobject) {
876                 if (qp_has_rq(init_attr))
877                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
878         } else {
879                 kfree(qp->sq.wrid);
880                 kfree(qp->rq.wrid);
881         }
882
883 err_mtt:
884         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
885
886 err_buf:
887         if (pd->uobject)
888                 ib_umem_release(qp->umem);
889         else
890                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
891
892 err_db:
893         if (!pd->uobject && qp_has_rq(init_attr))
894                 mlx4_db_free(dev->dev, &qp->db);
895
896 err:
897         if (!*caller_qp)
898                 kfree(qp);
899         return err;
900 }
901
902 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
903 {
904         switch (state) {
905         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
906         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
907         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
908         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
909         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
910         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
911         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
912         default:                return -1;
913         }
914 }
915
916 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
917         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
918 {
919         if (send_cq == recv_cq) {
920                 spin_lock(&send_cq->lock);
921                 __acquire(&recv_cq->lock);
922         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
923                 spin_lock(&send_cq->lock);
924                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
925         } else {
926                 spin_lock(&recv_cq->lock);
927                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
928         }
929 }
930
931 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
932         __releases(&send_cq->lock) __releases(&recv_cq->lock)
933 {
934         if (send_cq == recv_cq) {
935                 __release(&recv_cq->lock);
936                 spin_unlock(&send_cq->lock);
937         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
938                 spin_unlock(&recv_cq->lock);
939                 spin_unlock(&send_cq->lock);
940         } else {
941                 spin_unlock(&send_cq->lock);
942                 spin_unlock(&recv_cq->lock);
943         }
944 }
945
946 static void del_gid_entries(struct mlx4_ib_qp *qp)
947 {
948         struct mlx4_ib_gid_entry *ge, *tmp;
949
950         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
951                 list_del(&ge->list);
952                 kfree(ge);
953         }
954 }
955
956 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
957 {
958         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
959                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
960         else
961                 return to_mpd(qp->ibqp.pd);
962 }
963
964 static void get_cqs(struct mlx4_ib_qp *qp,
965                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
966 {
967         switch (qp->ibqp.qp_type) {
968         case IB_QPT_XRC_TGT:
969                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
970                 *recv_cq = *send_cq;
971                 break;
972         case IB_QPT_XRC_INI:
973                 *send_cq = to_mcq(qp->ibqp.send_cq);
974                 *recv_cq = *send_cq;
975                 break;
976         default:
977                 *send_cq = to_mcq(qp->ibqp.send_cq);
978                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
979                 break;
980         }
981 }
982
983 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
984                               int is_user)
985 {
986         struct mlx4_ib_cq *send_cq, *recv_cq;
987         unsigned long flags;
988
989         if (qp->state != IB_QPS_RESET) {
990                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
991                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
992                         pr_warn("modify QP %06x to RESET failed.\n",
993                                qp->mqp.qpn);
994                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
995                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
996                         qp->pri.smac = 0;
997                         qp->pri.smac_port = 0;
998                 }
999                 if (qp->alt.smac) {
1000                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1001                         qp->alt.smac = 0;
1002                 }
1003                 if (qp->pri.vid < 0x1000) {
1004                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1005                         qp->pri.vid = 0xFFFF;
1006                         qp->pri.candidate_vid = 0xFFFF;
1007                         qp->pri.update_vid = 0;
1008                 }
1009                 if (qp->alt.vid < 0x1000) {
1010                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1011                         qp->alt.vid = 0xFFFF;
1012                         qp->alt.candidate_vid = 0xFFFF;
1013                         qp->alt.update_vid = 0;
1014                 }
1015         }
1016
1017         get_cqs(qp, &send_cq, &recv_cq);
1018
1019         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1020         mlx4_ib_lock_cqs(send_cq, recv_cq);
1021
1022         /* del from lists under both locks above to protect reset flow paths */
1023         list_del(&qp->qps_list);
1024         list_del(&qp->cq_send_list);
1025         list_del(&qp->cq_recv_list);
1026         if (!is_user) {
1027                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1028                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1029                 if (send_cq != recv_cq)
1030                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1031         }
1032
1033         mlx4_qp_remove(dev->dev, &qp->mqp);
1034
1035         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1036         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1037
1038         mlx4_qp_free(dev->dev, &qp->mqp);
1039
1040         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1041                 if (qp->flags & MLX4_IB_QP_NETIF)
1042                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1043                 else
1044                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1045         }
1046
1047         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1048
1049         if (is_user) {
1050                 if (qp->rq.wqe_cnt)
1051                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1052                                               &qp->db);
1053                 ib_umem_release(qp->umem);
1054         } else {
1055                 kfree(qp->sq.wrid);
1056                 kfree(qp->rq.wrid);
1057                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1058                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1059                         free_proxy_bufs(&dev->ib_dev, qp);
1060                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1061                 if (qp->rq.wqe_cnt)
1062                         mlx4_db_free(dev->dev, &qp->db);
1063         }
1064
1065         del_gid_entries(qp);
1066 }
1067
1068 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1069 {
1070         /* Native or PPF */
1071         if (!mlx4_is_mfunc(dev->dev) ||
1072             (mlx4_is_master(dev->dev) &&
1073              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1074                 return  dev->dev->phys_caps.base_sqpn +
1075                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1076                         attr->port_num - 1;
1077         }
1078         /* PF or VF -- creating proxies */
1079         if (attr->qp_type == IB_QPT_SMI)
1080                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1081         else
1082                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1083 }
1084
1085 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1086                                 struct ib_qp_init_attr *init_attr,
1087                                 struct ib_udata *udata)
1088 {
1089         struct mlx4_ib_qp *qp = NULL;
1090         int err;
1091         u16 xrcdn = 0;
1092         gfp_t gfp;
1093
1094         gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1095                 GFP_NOIO : GFP_KERNEL;
1096         /*
1097          * We only support LSO, vendor flag1, and multicast loopback blocking,
1098          * and only for kernel UD QPs.
1099          */
1100         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1101                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1102                                         MLX4_IB_SRIOV_TUNNEL_QP |
1103                                         MLX4_IB_SRIOV_SQP |
1104                                         MLX4_IB_QP_NETIF |
1105                                         MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1106                 return ERR_PTR(-EINVAL);
1107
1108         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1109                 if (init_attr->qp_type != IB_QPT_UD)
1110                         return ERR_PTR(-EINVAL);
1111         }
1112
1113         if (init_attr->create_flags &&
1114             (udata ||
1115              ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | MLX4_IB_QP_CREATE_USE_GFP_NOIO)) &&
1116               init_attr->qp_type != IB_QPT_UD) ||
1117              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1118               init_attr->qp_type > IB_QPT_GSI)))
1119                 return ERR_PTR(-EINVAL);
1120
1121         switch (init_attr->qp_type) {
1122         case IB_QPT_XRC_TGT:
1123                 pd = to_mxrcd(init_attr->xrcd)->pd;
1124                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1125                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1126                 /* fall through */
1127         case IB_QPT_XRC_INI:
1128                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1129                         return ERR_PTR(-ENOSYS);
1130                 init_attr->recv_cq = init_attr->send_cq;
1131                 /* fall through */
1132         case IB_QPT_RC:
1133         case IB_QPT_UC:
1134         case IB_QPT_RAW_PACKET:
1135                 qp = kzalloc(sizeof *qp, gfp);
1136                 if (!qp)
1137                         return ERR_PTR(-ENOMEM);
1138                 qp->pri.vid = 0xFFFF;
1139                 qp->alt.vid = 0xFFFF;
1140                 /* fall through */
1141         case IB_QPT_UD:
1142         {
1143                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1144                                        udata, 0, &qp, gfp);
1145                 if (err)
1146                         return ERR_PTR(err);
1147
1148                 qp->ibqp.qp_num = qp->mqp.qpn;
1149                 qp->xrcdn = xrcdn;
1150
1151                 break;
1152         }
1153         case IB_QPT_SMI:
1154         case IB_QPT_GSI:
1155         {
1156                 /* Userspace is not allowed to create special QPs: */
1157                 if (udata)
1158                         return ERR_PTR(-EINVAL);
1159
1160                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1161                                        get_sqp_num(to_mdev(pd->device), init_attr),
1162                                        &qp, gfp);
1163                 if (err)
1164                         return ERR_PTR(err);
1165
1166                 qp->port        = init_attr->port_num;
1167                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1168
1169                 break;
1170         }
1171         default:
1172                 /* Don't support raw QPs */
1173                 return ERR_PTR(-EINVAL);
1174         }
1175
1176         return &qp->ibqp;
1177 }
1178
1179 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1180 {
1181         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1182         struct mlx4_ib_qp *mqp = to_mqp(qp);
1183         struct mlx4_ib_pd *pd;
1184
1185         if (is_qp0(dev, mqp))
1186                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1187
1188         if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1189                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1190                 dev->qp1_proxy[mqp->port - 1] = NULL;
1191                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1192         }
1193
1194         pd = get_pd(mqp);
1195         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1196
1197         if (is_sqp(dev, mqp))
1198                 kfree(to_msqp(mqp));
1199         else
1200                 kfree(mqp);
1201
1202         return 0;
1203 }
1204
1205 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1206 {
1207         switch (type) {
1208         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1209         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1210         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1211         case MLX4_IB_QPT_XRC_INI:
1212         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1213         case MLX4_IB_QPT_SMI:
1214         case MLX4_IB_QPT_GSI:
1215         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1216
1217         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1218         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1219                                                 MLX4_QP_ST_MLX : -1);
1220         case MLX4_IB_QPT_PROXY_SMI:
1221         case MLX4_IB_QPT_TUN_SMI:
1222         case MLX4_IB_QPT_PROXY_GSI:
1223         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1224                                                 MLX4_QP_ST_UD : -1);
1225         default:                        return -1;
1226         }
1227 }
1228
1229 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1230                                    int attr_mask)
1231 {
1232         u8 dest_rd_atomic;
1233         u32 access_flags;
1234         u32 hw_access_flags = 0;
1235
1236         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1237                 dest_rd_atomic = attr->max_dest_rd_atomic;
1238         else
1239                 dest_rd_atomic = qp->resp_depth;
1240
1241         if (attr_mask & IB_QP_ACCESS_FLAGS)
1242                 access_flags = attr->qp_access_flags;
1243         else
1244                 access_flags = qp->atomic_rd_en;
1245
1246         if (!dest_rd_atomic)
1247                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1248
1249         if (access_flags & IB_ACCESS_REMOTE_READ)
1250                 hw_access_flags |= MLX4_QP_BIT_RRE;
1251         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1252                 hw_access_flags |= MLX4_QP_BIT_RAE;
1253         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1254                 hw_access_flags |= MLX4_QP_BIT_RWE;
1255
1256         return cpu_to_be32(hw_access_flags);
1257 }
1258
1259 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1260                             int attr_mask)
1261 {
1262         if (attr_mask & IB_QP_PKEY_INDEX)
1263                 sqp->pkey_index = attr->pkey_index;
1264         if (attr_mask & IB_QP_QKEY)
1265                 sqp->qkey = attr->qkey;
1266         if (attr_mask & IB_QP_SQ_PSN)
1267                 sqp->send_psn = attr->sq_psn;
1268 }
1269
1270 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1271 {
1272         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1273 }
1274
1275 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1276                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1277                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1278 {
1279         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1280                 IB_LINK_LAYER_ETHERNET;
1281         int vidx;
1282         int smac_index;
1283         int err;
1284
1285
1286         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1287         path->rlid          = cpu_to_be16(ah->dlid);
1288         if (ah->static_rate) {
1289                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1290                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1291                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1292                         --path->static_rate;
1293         } else
1294                 path->static_rate = 0;
1295
1296         if (ah->ah_flags & IB_AH_GRH) {
1297                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
1298                         pr_err("sgid_index (%u) too large. max is %d\n",
1299                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1300                         return -1;
1301                 }
1302
1303                 path->grh_mylmc |= 1 << 7;
1304                 path->mgid_index = ah->grh.sgid_index;
1305                 path->hop_limit  = ah->grh.hop_limit;
1306                 path->tclass_flowlabel =
1307                         cpu_to_be32((ah->grh.traffic_class << 20) |
1308                                     (ah->grh.flow_label));
1309                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1310         }
1311
1312         if (is_eth) {
1313                 if (!(ah->ah_flags & IB_AH_GRH))
1314                         return -1;
1315
1316                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1317                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1318
1319                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1320                 if (vlan_tag < 0x1000) {
1321                         if (smac_info->vid < 0x1000) {
1322                                 /* both valid vlan ids */
1323                                 if (smac_info->vid != vlan_tag) {
1324                                         /* different VIDs.  unreg old and reg new */
1325                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1326                                         if (err)
1327                                                 return err;
1328                                         smac_info->candidate_vid = vlan_tag;
1329                                         smac_info->candidate_vlan_index = vidx;
1330                                         smac_info->candidate_vlan_port = port;
1331                                         smac_info->update_vid = 1;
1332                                         path->vlan_index = vidx;
1333                                 } else {
1334                                         path->vlan_index = smac_info->vlan_index;
1335                                 }
1336                         } else {
1337                                 /* no current vlan tag in qp */
1338                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1339                                 if (err)
1340                                         return err;
1341                                 smac_info->candidate_vid = vlan_tag;
1342                                 smac_info->candidate_vlan_index = vidx;
1343                                 smac_info->candidate_vlan_port = port;
1344                                 smac_info->update_vid = 1;
1345                                 path->vlan_index = vidx;
1346                         }
1347                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1348                         path->fl = 1 << 6;
1349                 } else {
1350                         /* have current vlan tag. unregister it at modify-qp success */
1351                         if (smac_info->vid < 0x1000) {
1352                                 smac_info->candidate_vid = 0xFFFF;
1353                                 smac_info->update_vid = 1;
1354                         }
1355                 }
1356
1357                 /* get smac_index for RoCE use.
1358                  * If no smac was yet assigned, register one.
1359                  * If one was already assigned, but the new mac differs,
1360                  * unregister the old one and register the new one.
1361                 */
1362                 if ((!smac_info->smac && !smac_info->smac_port) ||
1363                     smac_info->smac != smac) {
1364                         /* register candidate now, unreg if needed, after success */
1365                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1366                         if (smac_index >= 0) {
1367                                 smac_info->candidate_smac_index = smac_index;
1368                                 smac_info->candidate_smac = smac;
1369                                 smac_info->candidate_smac_port = port;
1370                         } else {
1371                                 return -EINVAL;
1372                         }
1373                 } else {
1374                         smac_index = smac_info->smac_index;
1375                 }
1376
1377                 memcpy(path->dmac, ah->dmac, 6);
1378                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1379                 /* put MAC table smac index for IBoE */
1380                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1381         } else {
1382                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1383                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1384         }
1385
1386         return 0;
1387 }
1388
1389 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1390                          enum ib_qp_attr_mask qp_attr_mask,
1391                          struct mlx4_ib_qp *mqp,
1392                          struct mlx4_qp_path *path, u8 port)
1393 {
1394         return _mlx4_set_path(dev, &qp->ah_attr,
1395                               mlx4_mac_to_u64((u8 *)qp->smac),
1396                               (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
1397                               path, &mqp->pri, port);
1398 }
1399
1400 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1401                              const struct ib_qp_attr *qp,
1402                              enum ib_qp_attr_mask qp_attr_mask,
1403                              struct mlx4_ib_qp *mqp,
1404                              struct mlx4_qp_path *path, u8 port)
1405 {
1406         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1407                               mlx4_mac_to_u64((u8 *)qp->alt_smac),
1408                               (qp_attr_mask & IB_QP_ALT_VID) ?
1409                               qp->alt_vlan_id : 0xffff,
1410                               path, &mqp->alt, port);
1411 }
1412
1413 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1414 {
1415         struct mlx4_ib_gid_entry *ge, *tmp;
1416
1417         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1418                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1419                         ge->added = 1;
1420                         ge->port = qp->port;
1421                 }
1422         }
1423 }
1424
1425 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1426                                     struct mlx4_qp_context *context)
1427 {
1428         u64 u64_mac;
1429         int smac_index;
1430
1431         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1432
1433         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1434         if (!qp->pri.smac && !qp->pri.smac_port) {
1435                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1436                 if (smac_index >= 0) {
1437                         qp->pri.candidate_smac_index = smac_index;
1438                         qp->pri.candidate_smac = u64_mac;
1439                         qp->pri.candidate_smac_port = qp->port;
1440                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1441                 } else {
1442                         return -ENOENT;
1443                 }
1444         }
1445         return 0;
1446 }
1447
1448 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1449                                const struct ib_qp_attr *attr, int attr_mask,
1450                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1451 {
1452         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1453         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1454         struct mlx4_ib_pd *pd;
1455         struct mlx4_ib_cq *send_cq, *recv_cq;
1456         struct mlx4_qp_context *context;
1457         enum mlx4_qp_optpar optpar = 0;
1458         int sqd_event;
1459         int steer_qp = 0;
1460         int err = -EINVAL;
1461
1462         /* APM is not supported under RoCE */
1463         if (attr_mask & IB_QP_ALT_PATH &&
1464             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1465             IB_LINK_LAYER_ETHERNET)
1466                 return -ENOTSUPP;
1467
1468         context = kzalloc(sizeof *context, GFP_KERNEL);
1469         if (!context)
1470                 return -ENOMEM;
1471
1472         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1473                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1474
1475         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1476                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1477         else {
1478                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1479                 switch (attr->path_mig_state) {
1480                 case IB_MIG_MIGRATED:
1481                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1482                         break;
1483                 case IB_MIG_REARM:
1484                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1485                         break;
1486                 case IB_MIG_ARMED:
1487                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1488                         break;
1489                 }
1490         }
1491
1492         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1493                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1494         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1495                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1496         else if (ibqp->qp_type == IB_QPT_UD) {
1497                 if (qp->flags & MLX4_IB_QP_LSO)
1498                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1499                                               ilog2(dev->dev->caps.max_gso_sz);
1500                 else
1501                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1502         } else if (attr_mask & IB_QP_PATH_MTU) {
1503                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1504                         pr_err("path MTU (%u) is invalid\n",
1505                                attr->path_mtu);
1506                         goto out;
1507                 }
1508                 context->mtu_msgmax = (attr->path_mtu << 5) |
1509                         ilog2(dev->dev->caps.max_msg_sz);
1510         }
1511
1512         if (qp->rq.wqe_cnt)
1513                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1514         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1515
1516         if (qp->sq.wqe_cnt)
1517                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1518         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1519
1520         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1521                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1522                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1523                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1524                         context->param3 |= cpu_to_be32(1 << 30);
1525         }
1526
1527         if (qp->ibqp.uobject)
1528                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1529         else
1530                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1531
1532         if (attr_mask & IB_QP_DEST_QPN)
1533                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1534
1535         if (attr_mask & IB_QP_PORT) {
1536                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1537                     !(attr_mask & IB_QP_AV)) {
1538                         mlx4_set_sched(&context->pri_path, attr->port_num);
1539                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1540                 }
1541         }
1542
1543         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1544                 if (dev->counters[qp->port - 1] != -1) {
1545                         context->pri_path.counter_index =
1546                                                 dev->counters[qp->port - 1];
1547                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1548                 } else
1549                         context->pri_path.counter_index = 0xff;
1550
1551                 if (qp->flags & MLX4_IB_QP_NETIF) {
1552                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1553                         steer_qp = 1;
1554                 }
1555         }
1556
1557         if (attr_mask & IB_QP_PKEY_INDEX) {
1558                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1559                         context->pri_path.disable_pkey_check = 0x40;
1560                 context->pri_path.pkey_index = attr->pkey_index;
1561                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1562         }
1563
1564         if (attr_mask & IB_QP_AV) {
1565                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1566                                   attr_mask & IB_QP_PORT ?
1567                                   attr->port_num : qp->port))
1568                         goto out;
1569
1570                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1571                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1572         }
1573
1574         if (attr_mask & IB_QP_TIMEOUT) {
1575                 context->pri_path.ackto |= attr->timeout << 3;
1576                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1577         }
1578
1579         if (attr_mask & IB_QP_ALT_PATH) {
1580                 if (attr->alt_port_num == 0 ||
1581                     attr->alt_port_num > dev->dev->caps.num_ports)
1582                         goto out;
1583
1584                 if (attr->alt_pkey_index >=
1585                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1586                         goto out;
1587
1588                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1589                                       &context->alt_path,
1590                                       attr->alt_port_num))
1591                         goto out;
1592
1593                 context->alt_path.pkey_index = attr->alt_pkey_index;
1594                 context->alt_path.ackto = attr->alt_timeout << 3;
1595                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1596         }
1597
1598         pd = get_pd(qp);
1599         get_cqs(qp, &send_cq, &recv_cq);
1600         context->pd       = cpu_to_be32(pd->pdn);
1601         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1602         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1603         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1604
1605         /* Set "fast registration enabled" for all kernel QPs */
1606         if (!qp->ibqp.uobject)
1607                 context->params1 |= cpu_to_be32(1 << 11);
1608
1609         if (attr_mask & IB_QP_RNR_RETRY) {
1610                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1611                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1612         }
1613
1614         if (attr_mask & IB_QP_RETRY_CNT) {
1615                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1616                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1617         }
1618
1619         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1620                 if (attr->max_rd_atomic)
1621                         context->params1 |=
1622                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1623                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1624         }
1625
1626         if (attr_mask & IB_QP_SQ_PSN)
1627                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1628
1629         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1630                 if (attr->max_dest_rd_atomic)
1631                         context->params2 |=
1632                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1633                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1634         }
1635
1636         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1637                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1638                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1639         }
1640
1641         if (ibqp->srq)
1642                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1643
1644         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1645                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1646                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1647         }
1648         if (attr_mask & IB_QP_RQ_PSN)
1649                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1650
1651         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1652         if (attr_mask & IB_QP_QKEY) {
1653                 if (qp->mlx4_ib_qp_type &
1654                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1655                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1656                 else {
1657                         if (mlx4_is_mfunc(dev->dev) &&
1658                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1659                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1660                             MLX4_RESERVED_QKEY_BASE) {
1661                                 pr_err("Cannot use reserved QKEY"
1662                                        " 0x%x (range 0xffff0000..0xffffffff"
1663                                        " is reserved)\n", attr->qkey);
1664                                 err = -EINVAL;
1665                                 goto out;
1666                         }
1667                         context->qkey = cpu_to_be32(attr->qkey);
1668                 }
1669                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1670         }
1671
1672         if (ibqp->srq)
1673                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1674
1675         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1676                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1677
1678         if (cur_state == IB_QPS_INIT &&
1679             new_state == IB_QPS_RTR  &&
1680             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1681              ibqp->qp_type == IB_QPT_UD ||
1682              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1683                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1684                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1685                     qp->mlx4_ib_qp_type &
1686                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1687                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1688                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1689                                 context->pri_path.fl = 0x80;
1690                 } else {
1691                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1692                                 context->pri_path.fl = 0x80;
1693                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1694                 }
1695                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1696                     IB_LINK_LAYER_ETHERNET) {
1697                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1698                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1699                                 context->pri_path.feup = 1 << 7; /* don't fsm */
1700                         /* handle smac_index */
1701                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1702                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1703                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1704                                 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
1705                                 if (err) {
1706                                         err = -EINVAL;
1707                                         goto out;
1708                                 }
1709                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1710                                         dev->qp1_proxy[qp->port - 1] = qp;
1711                         }
1712                 }
1713         }
1714
1715         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1716                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1717                                         MLX4_IB_LINK_TYPE_ETH;
1718                 if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1719                         /* set QP to receive both tunneled & non-tunneled packets */
1720                         if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1721                                 context->srqn = cpu_to_be32(7 << 28);
1722                 }
1723         }
1724
1725         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1726                 int is_eth = rdma_port_get_link_layer(
1727                                 &dev->ib_dev, qp->port) ==
1728                                 IB_LINK_LAYER_ETHERNET;
1729                 if (is_eth) {
1730                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1731                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1732                 }
1733         }
1734
1735
1736         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1737             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1738                 sqd_event = 1;
1739         else
1740                 sqd_event = 0;
1741
1742         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1743                 context->rlkey |= (1 << 4);
1744
1745         /*
1746          * Before passing a kernel QP to the HW, make sure that the
1747          * ownership bits of the send queue are set and the SQ
1748          * headroom is stamped so that the hardware doesn't start
1749          * processing stale work requests.
1750          */
1751         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1752                 struct mlx4_wqe_ctrl_seg *ctrl;
1753                 int i;
1754
1755                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1756                         ctrl = get_send_wqe(qp, i);
1757                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1758                         if (qp->sq_max_wqes_per_wr == 1)
1759                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1760
1761                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1762                 }
1763         }
1764
1765         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1766                              to_mlx4_state(new_state), context, optpar,
1767                              sqd_event, &qp->mqp);
1768         if (err)
1769                 goto out;
1770
1771         qp->state = new_state;
1772
1773         if (attr_mask & IB_QP_ACCESS_FLAGS)
1774                 qp->atomic_rd_en = attr->qp_access_flags;
1775         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1776                 qp->resp_depth = attr->max_dest_rd_atomic;
1777         if (attr_mask & IB_QP_PORT) {
1778                 qp->port = attr->port_num;
1779                 update_mcg_macs(dev, qp);
1780         }
1781         if (attr_mask & IB_QP_ALT_PATH)
1782                 qp->alt_port = attr->alt_port_num;
1783
1784         if (is_sqp(dev, qp))
1785                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1786
1787         /*
1788          * If we moved QP0 to RTR, bring the IB link up; if we moved
1789          * QP0 to RESET or ERROR, bring the link back down.
1790          */
1791         if (is_qp0(dev, qp)) {
1792                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1793                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1794                                 pr_warn("INIT_PORT failed for port %d\n",
1795                                        qp->port);
1796
1797                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1798                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1799                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1800         }
1801
1802         /*
1803          * If we moved a kernel QP to RESET, clean up all old CQ
1804          * entries and reinitialize the QP.
1805          */
1806         if (new_state == IB_QPS_RESET) {
1807                 if (!ibqp->uobject) {
1808                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1809                                          ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1810                         if (send_cq != recv_cq)
1811                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1812
1813                         qp->rq.head = 0;
1814                         qp->rq.tail = 0;
1815                         qp->sq.head = 0;
1816                         qp->sq.tail = 0;
1817                         qp->sq_next_wqe = 0;
1818                         if (qp->rq.wqe_cnt)
1819                                 *qp->db.db  = 0;
1820
1821                         if (qp->flags & MLX4_IB_QP_NETIF)
1822                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1823                 }
1824                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1825                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1826                         qp->pri.smac = 0;
1827                         qp->pri.smac_port = 0;
1828                 }
1829                 if (qp->alt.smac) {
1830                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1831                         qp->alt.smac = 0;
1832                 }
1833                 if (qp->pri.vid < 0x1000) {
1834                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1835                         qp->pri.vid = 0xFFFF;
1836                         qp->pri.candidate_vid = 0xFFFF;
1837                         qp->pri.update_vid = 0;
1838                 }
1839
1840                 if (qp->alt.vid < 0x1000) {
1841                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1842                         qp->alt.vid = 0xFFFF;
1843                         qp->alt.candidate_vid = 0xFFFF;
1844                         qp->alt.update_vid = 0;
1845                 }
1846         }
1847 out:
1848         if (err && steer_qp)
1849                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1850         kfree(context);
1851         if (qp->pri.candidate_smac ||
1852             (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
1853                 if (err) {
1854                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1855                 } else {
1856                         if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
1857                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1858                         qp->pri.smac = qp->pri.candidate_smac;
1859                         qp->pri.smac_index = qp->pri.candidate_smac_index;
1860                         qp->pri.smac_port = qp->pri.candidate_smac_port;
1861                 }
1862                 qp->pri.candidate_smac = 0;
1863                 qp->pri.candidate_smac_index = 0;
1864                 qp->pri.candidate_smac_port = 0;
1865         }
1866         if (qp->alt.candidate_smac) {
1867                 if (err) {
1868                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1869                 } else {
1870                         if (qp->alt.smac)
1871                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1872                         qp->alt.smac = qp->alt.candidate_smac;
1873                         qp->alt.smac_index = qp->alt.candidate_smac_index;
1874                         qp->alt.smac_port = qp->alt.candidate_smac_port;
1875                 }
1876                 qp->alt.candidate_smac = 0;
1877                 qp->alt.candidate_smac_index = 0;
1878                 qp->alt.candidate_smac_port = 0;
1879         }
1880
1881         if (qp->pri.update_vid) {
1882                 if (err) {
1883                         if (qp->pri.candidate_vid < 0x1000)
1884                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1885                                                      qp->pri.candidate_vid);
1886                 } else {
1887                         if (qp->pri.vid < 0x1000)
1888                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1889                                                      qp->pri.vid);
1890                         qp->pri.vid = qp->pri.candidate_vid;
1891                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1892                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
1893                 }
1894                 qp->pri.candidate_vid = 0xFFFF;
1895                 qp->pri.update_vid = 0;
1896         }
1897
1898         if (qp->alt.update_vid) {
1899                 if (err) {
1900                         if (qp->alt.candidate_vid < 0x1000)
1901                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1902                                                      qp->alt.candidate_vid);
1903                 } else {
1904                         if (qp->alt.vid < 0x1000)
1905                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1906                                                      qp->alt.vid);
1907                         qp->alt.vid = qp->alt.candidate_vid;
1908                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1909                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
1910                 }
1911                 qp->alt.candidate_vid = 0xFFFF;
1912                 qp->alt.update_vid = 0;
1913         }
1914
1915         return err;
1916 }
1917
1918 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1919                       int attr_mask, struct ib_udata *udata)
1920 {
1921         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1922         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1923         enum ib_qp_state cur_state, new_state;
1924         int err = -EINVAL;
1925         int ll;
1926         mutex_lock(&qp->mutex);
1927
1928         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1929         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1930
1931         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1932                 ll = IB_LINK_LAYER_UNSPECIFIED;
1933         } else {
1934                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1935                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1936         }
1937
1938         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1939                                 attr_mask, ll)) {
1940                 pr_debug("qpn 0x%x: invalid attribute mask specified "
1941                          "for transition %d to %d. qp_type %d,"
1942                          " attr_mask 0x%x\n",
1943                          ibqp->qp_num, cur_state, new_state,
1944                          ibqp->qp_type, attr_mask);
1945                 goto out;
1946         }
1947
1948         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
1949                 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
1950                         if ((ibqp->qp_type == IB_QPT_RC) ||
1951                             (ibqp->qp_type == IB_QPT_UD) ||
1952                             (ibqp->qp_type == IB_QPT_UC) ||
1953                             (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
1954                             (ibqp->qp_type == IB_QPT_XRC_INI)) {
1955                                 attr->port_num = mlx4_ib_bond_next_port(dev);
1956                         }
1957                 } else {
1958                         /* no sense in changing port_num
1959                          * when ports are bonded */
1960                         attr_mask &= ~IB_QP_PORT;
1961                 }
1962         }
1963
1964         if ((attr_mask & IB_QP_PORT) &&
1965             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
1966                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1967                          "for transition %d to %d. qp_type %d\n",
1968                          ibqp->qp_num, attr->port_num, cur_state,
1969                          new_state, ibqp->qp_type);
1970                 goto out;
1971         }
1972
1973         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1974             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1975              IB_LINK_LAYER_ETHERNET))
1976                 goto out;
1977
1978         if (attr_mask & IB_QP_PKEY_INDEX) {
1979                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1980                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1981                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1982                                  "for transition %d to %d. qp_type %d\n",
1983                                  ibqp->qp_num, attr->pkey_index, cur_state,
1984                                  new_state, ibqp->qp_type);
1985                         goto out;
1986                 }
1987         }
1988
1989         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1990             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1991                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1992                          "Transition %d to %d. qp_type %d\n",
1993                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
1994                          new_state, ibqp->qp_type);
1995                 goto out;
1996         }
1997
1998         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1999             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2000                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2001                          "Transition %d to %d. qp_type %d\n",
2002                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2003                          new_state, ibqp->qp_type);
2004                 goto out;
2005         }
2006
2007         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2008                 err = 0;
2009                 goto out;
2010         }
2011
2012         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2013
2014         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2015                 attr->port_num = 1;
2016
2017 out:
2018         mutex_unlock(&qp->mutex);
2019         return err;
2020 }
2021
2022 #if 0   /* AKAROS */
2023 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2024 {
2025         int i;
2026         for (i = 0; i < dev->caps.num_ports; i++) {
2027                 if (qpn == dev->caps.qp0_proxy[i] ||
2028                     qpn == dev->caps.qp0_tunnel[i]) {
2029                         *qkey = dev->caps.qp0_qkey[i];
2030                         return 0;
2031                 }
2032         }
2033         return -EINVAL;
2034 }
2035
2036 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2037                                   struct ib_send_wr *wr,
2038                                   void *wqe, unsigned *mlx_seg_len)
2039 {
2040         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2041         struct ib_device *ib_dev = &mdev->ib_dev;
2042         struct mlx4_wqe_mlx_seg *mlx = wqe;
2043         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2044         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2045         u16 pkey;
2046         u32 qkey;
2047         int send_size;
2048         int header_size;
2049         int spc;
2050         int i;
2051
2052         if (wr->opcode != IB_WR_SEND)
2053                 return -EINVAL;
2054
2055         send_size = 0;
2056
2057         for (i = 0; i < wr->num_sge; ++i)
2058                 send_size += wr->sg_list[i].length;
2059
2060         /* for proxy-qp0 sends, need to add in size of tunnel header */
2061         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2062         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2063                 send_size += sizeof (struct mlx4_ib_tunnel_header);
2064
2065         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2066
2067         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2068                 sqp->ud_header.lrh.service_level =
2069                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2070                 sqp->ud_header.lrh.destination_lid =
2071                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2072                 sqp->ud_header.lrh.source_lid =
2073                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2074         }
2075
2076         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2077
2078         /* force loopback */
2079         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2080         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2081
2082         sqp->ud_header.lrh.virtual_lane    = 0;
2083         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2084         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2085         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2086         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2087                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2088         else
2089                 sqp->ud_header.bth.destination_qpn =
2090                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2091
2092         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2093         if (mlx4_is_master(mdev->dev)) {
2094                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2095                         return -EINVAL;
2096         } else {
2097                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2098                         return -EINVAL;
2099         }
2100         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2101         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2102
2103         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2104         sqp->ud_header.immediate_present = 0;
2105
2106         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2107
2108         /*
2109          * Inline data segments may not cross a 64 byte boundary.  If
2110          * our UD header is bigger than the space available up to the
2111          * next 64 byte boundary in the WQE, use two inline data
2112          * segments to hold the UD header.
2113          */
2114         spc = MLX4_INLINE_ALIGN -
2115               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2116         if (header_size <= spc) {
2117                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2118                 memcpy(inl + 1, sqp->header_buf, header_size);
2119                 i = 1;
2120         } else {
2121                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2122                 memcpy(inl + 1, sqp->header_buf, spc);
2123
2124                 inl = (void *) (inl + 1) + spc;
2125                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2126                 /*
2127                  * Need a barrier here to make sure all the data is
2128                  * visible before the byte_count field is set.
2129                  * Otherwise the HCA prefetcher could grab the 64-byte
2130                  * chunk with this inline segment and get a valid (!=
2131                  * 0xffffffff) byte count but stale data, and end up
2132                  * generating a packet with bad headers.
2133                  *
2134                  * The first inline segment's byte_count field doesn't
2135                  * need a barrier, because it comes after a
2136                  * control/MLX segment and therefore is at an offset
2137                  * of 16 mod 64.
2138                  */
2139                 wmb();
2140                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2141                 i = 2;
2142         }
2143
2144         *mlx_seg_len =
2145         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2146         return 0;
2147 }
2148
2149 static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2150 {
2151         int i;
2152
2153         for (i = ETH_ALEN; i; i--) {
2154                 dst_mac[i - 1] = src_mac & 0xff;
2155                 src_mac >>= 8;
2156         }
2157 }
2158
2159 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
2160                             void *wqe, unsigned *mlx_seg_len)
2161 {
2162         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2163         struct mlx4_wqe_mlx_seg *mlx = wqe;
2164         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2165         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2166         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2167         union ib_gid sgid;
2168         u16 pkey;
2169         int send_size;
2170         int header_size;
2171         int spc;
2172         int i;
2173         int err = 0;
2174         u16 vlan = 0xffff;
2175         bool is_eth;
2176         bool is_vlan = false;
2177         bool is_grh;
2178
2179         send_size = 0;
2180         for (i = 0; i < wr->num_sge; ++i)
2181                 send_size += wr->sg_list[i].length;
2182
2183         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2184         is_grh = mlx4_ib_ah_grh_present(ah);
2185         if (is_eth) {
2186                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2187                         /* When multi-function is enabled, the ib_core gid
2188                          * indexes don't necessarily match the hw ones, so
2189                          * we must use our own cache */
2190                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2191                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2192                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2193                         if (err)
2194                                 return err;
2195                 } else  {
2196                         err = ib_get_cached_gid(ib_dev,
2197                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2198                                                 ah->av.ib.gid_index, &sgid);
2199                         if (err)
2200                                 return err;
2201                 }
2202
2203                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2204                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2205                         is_vlan = 1;
2206                 }
2207         }
2208         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2209
2210         if (!is_eth) {
2211                 sqp->ud_header.lrh.service_level =
2212                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2213                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2214                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2215         }
2216
2217         if (is_grh) {
2218                 sqp->ud_header.grh.traffic_class =
2219                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2220                 sqp->ud_header.grh.flow_label    =
2221                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2222                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2223                 if (is_eth)
2224                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2225                 else {
2226                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2227                         /* When multi-function is enabled, the ib_core gid
2228                          * indexes don't necessarily match the hw ones, so
2229                          * we must use our own cache */
2230                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
2231                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2232                                                        subnet_prefix;
2233                         sqp->ud_header.grh.source_gid.global.interface_id =
2234                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2235                                                guid_cache[ah->av.ib.gid_index];
2236                 } else
2237                         ib_get_cached_gid(ib_dev,
2238                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
2239                                           ah->av.ib.gid_index,
2240                                           &sqp->ud_header.grh.source_gid);
2241                 }
2242                 memcpy(sqp->ud_header.grh.destination_gid.raw,
2243                        ah->av.ib.dgid, 16);
2244         }
2245
2246         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2247
2248         if (!is_eth) {
2249                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2250                                           (sqp->ud_header.lrh.destination_lid ==
2251                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2252                                           (sqp->ud_header.lrh.service_level << 8));
2253                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2254                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2255                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2256         }
2257
2258         switch (wr->opcode) {
2259         case IB_WR_SEND:
2260                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2261                 sqp->ud_header.immediate_present = 0;
2262                 break;
2263         case IB_WR_SEND_WITH_IMM:
2264                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2265                 sqp->ud_header.immediate_present = 1;
2266                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
2267                 break;
2268         default:
2269                 return -EINVAL;
2270         }
2271
2272         if (is_eth) {
2273                 struct in6_addr in6;
2274
2275                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2276
2277                 mlx->sched_prio = cpu_to_be16(pcp);
2278
2279                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2280                 /* FIXME: cache smac value? */
2281                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2282                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2283                 memcpy(&in6, sgid.raw, sizeof(in6));
2284
2285                 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2286                         u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2287                         u8 smac[ETH_ALEN];
2288
2289                         mlx4_u64_to_smac(smac, mac);
2290                         memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2291                 } else {
2292                         /* use the src mac of the tunnel */
2293                         memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2294                 }
2295
2296                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2297                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2298                 if (!is_vlan) {
2299                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2300                 } else {
2301                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2302                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2303                 }
2304         } else {
2305                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
2306                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2307                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2308         }
2309         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2310         if (!sqp->qp.ibqp.qp_num)
2311                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2312         else
2313                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2314         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2315         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2316         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2317         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2318                                                sqp->qkey : wr->wr.ud.remote_qkey);
2319         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2320
2321         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2322
2323         if (0) {
2324                 pr_err("built UD header of size %d:\n", header_size);
2325                 for (i = 0; i < header_size / 4; ++i) {
2326                         if (i % 8 == 0)
2327                                 pr_err("  [%02x] ", i * 4);
2328                         pr_cont(" %08x",
2329                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2330                         if ((i + 1) % 8 == 0)
2331                                 pr_cont("\n");
2332                 }
2333                 pr_err("\n");
2334         }
2335
2336         /*
2337          * Inline data segments may not cross a 64 byte boundary.  If
2338          * our UD header is bigger than the space available up to the
2339          * next 64 byte boundary in the WQE, use two inline data
2340          * segments to hold the UD header.
2341          */
2342         spc = MLX4_INLINE_ALIGN -
2343                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2344         if (header_size <= spc) {
2345                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2346                 memcpy(inl + 1, sqp->header_buf, header_size);
2347                 i = 1;
2348         } else {
2349                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2350                 memcpy(inl + 1, sqp->header_buf, spc);
2351
2352                 inl = (void *) (inl + 1) + spc;
2353                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2354                 /*
2355                  * Need a barrier here to make sure all the data is
2356                  * visible before the byte_count field is set.
2357                  * Otherwise the HCA prefetcher could grab the 64-byte
2358                  * chunk with this inline segment and get a valid (!=
2359                  * 0xffffffff) byte count but stale data, and end up
2360                  * generating a packet with bad headers.
2361                  *
2362                  * The first inline segment's byte_count field doesn't
2363                  * need a barrier, because it comes after a
2364                  * control/MLX segment and therefore is at an offset
2365                  * of 16 mod 64.
2366                  */
2367                 wmb();
2368                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2369                 i = 2;
2370         }
2371
2372         *mlx_seg_len =
2373                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2374         return 0;
2375 }
2376
2377 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2378 {
2379         unsigned cur;
2380         struct mlx4_ib_cq *cq;
2381
2382         cur = wq->head - wq->tail;
2383         if (likely(cur + nreq < wq->max_post))
2384                 return 0;
2385
2386         cq = to_mcq(ib_cq);
2387         spin_lock(&cq->lock);
2388         cur = wq->head - wq->tail;
2389         spin_unlock(&cq->lock);
2390
2391         return cur + nreq >= wq->max_post;
2392 }
2393
2394 static __be32 convert_access(int acc)
2395 {
2396         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2397                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2398                (acc & IB_ACCESS_REMOTE_WRITE  ?
2399                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2400                (acc & IB_ACCESS_REMOTE_READ   ?
2401                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2402                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2403                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2404 }
2405
2406 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2407 {
2408         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
2409         int i;
2410
2411         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2412                 mfrpl->mapped_page_list[i] =
2413                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2414                                     MLX4_MTT_FLAG_PRESENT);
2415
2416         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
2417         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
2418         fseg->buf_list          = cpu_to_be64(mfrpl->map);
2419         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
2420         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
2421         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2422         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
2423         fseg->reserved[0]       = 0;
2424         fseg->reserved[1]       = 0;
2425 }
2426
2427 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2428 {
2429         bseg->flags1 =
2430                 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2431                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2432                             MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2433                             MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2434         bseg->flags2 = 0;
2435         if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2436                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2437         if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2438                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2439         bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2440         bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2441         bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2442         bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2443 }
2444
2445 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2446 {
2447         memset(iseg, 0, sizeof(*iseg));
2448         iseg->mem_key = cpu_to_be32(rkey);
2449 }
2450
2451 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2452                                           u64 remote_addr, u32 rkey)
2453 {
2454         rseg->raddr    = cpu_to_be64(remote_addr);
2455         rseg->rkey     = cpu_to_be32(rkey);
2456         rseg->reserved = 0;
2457 }
2458
2459 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2460 {
2461         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2462                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2463                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
2464         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2465                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2466                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2467         } else {
2468                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2469                 aseg->compare  = 0;
2470         }
2471
2472 }
2473
2474 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2475                                   struct ib_send_wr *wr)
2476 {
2477         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
2478         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
2479         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
2480         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2481 }
2482
2483 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2484                              struct ib_send_wr *wr)
2485 {
2486         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2487         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2488         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2489         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2490         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
2491 }
2492
2493 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2494                                     struct mlx4_wqe_datagram_seg *dseg,
2495                                     struct ib_send_wr *wr,
2496                                     enum mlx4_ib_qp_type qpt)
2497 {
2498         union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2499         struct mlx4_av sqp_av = {0};
2500         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2501
2502         /* force loopback */
2503         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2504         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2505         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2506                         cpu_to_be32(0xf0000000);
2507
2508         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2509         if (qpt == MLX4_IB_QPT_PROXY_GSI)
2510                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2511         else
2512                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2513         /* Use QKEY from the QP context, which is set by master */
2514         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2515 }
2516
2517 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2518 {
2519         struct mlx4_wqe_inline_seg *inl = wqe;
2520         struct mlx4_ib_tunnel_header hdr;
2521         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2522         int spc;
2523         int i;
2524
2525         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2526         hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2527         hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2528         hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2529         memcpy(hdr.mac, ah->av.eth.mac, 6);
2530         hdr.vlan = ah->av.eth.vlan;
2531
2532         spc = MLX4_INLINE_ALIGN -
2533                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2534         if (sizeof (hdr) <= spc) {
2535                 memcpy(inl + 1, &hdr, sizeof (hdr));
2536                 wmb();
2537                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2538                 i = 1;
2539         } else {
2540                 memcpy(inl + 1, &hdr, spc);
2541                 wmb();
2542                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2543
2544                 inl = (void *) (inl + 1) + spc;
2545                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2546                 wmb();
2547                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2548                 i = 2;
2549         }
2550
2551         *mlx_seg_len =
2552                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2553 }
2554
2555 static void set_mlx_icrc_seg(void *dseg)
2556 {
2557         u32 *t = dseg;
2558         struct mlx4_wqe_inline_seg *iseg = dseg;
2559
2560         t[1] = 0;
2561
2562         /*
2563          * Need a barrier here before writing the byte_count field to
2564          * make sure that all the data is visible before the
2565          * byte_count field is set.  Otherwise, if the segment begins
2566          * a new cacheline, the HCA prefetcher could grab the 64-byte
2567          * chunk and get a valid (!= * 0xffffffff) byte count but
2568          * stale data, and end up sending the wrong data.
2569          */
2570         wmb();
2571
2572         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2573 }
2574
2575 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2576 {
2577         dseg->lkey       = cpu_to_be32(sg->lkey);
2578         dseg->addr       = cpu_to_be64(sg->addr);
2579
2580         /*
2581          * Need a barrier here before writing the byte_count field to
2582          * make sure that all the data is visible before the
2583          * byte_count field is set.  Otherwise, if the segment begins
2584          * a new cacheline, the HCA prefetcher could grab the 64-byte
2585          * chunk and get a valid (!= * 0xffffffff) byte count but
2586          * stale data, and end up sending the wrong data.
2587          */
2588         wmb();
2589
2590         dseg->byte_count = cpu_to_be32(sg->length);
2591 }
2592
2593 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2594 {
2595         dseg->byte_count = cpu_to_be32(sg->length);
2596         dseg->lkey       = cpu_to_be32(sg->lkey);
2597         dseg->addr       = cpu_to_be64(sg->addr);
2598 }
2599
2600 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
2601                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2602                          __be32 *lso_hdr_sz, __be32 *blh)
2603 {
2604         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2605
2606         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2607                 *blh = cpu_to_be32(1 << 6);
2608
2609         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2610                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2611                 return -EINVAL;
2612
2613         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2614
2615         *lso_hdr_sz  = cpu_to_be32(wr->wr.ud.mss << 16 | wr->wr.ud.hlen);
2616         *lso_seg_len = halign;
2617         return 0;
2618 }
2619
2620 static __be32 send_ieth(struct ib_send_wr *wr)
2621 {
2622         switch (wr->opcode) {
2623         case IB_WR_SEND_WITH_IMM:
2624         case IB_WR_RDMA_WRITE_WITH_IMM:
2625                 return wr->ex.imm_data;
2626
2627         case IB_WR_SEND_WITH_INV:
2628                 return cpu_to_be32(wr->ex.invalidate_rkey);
2629
2630         default:
2631                 return 0;
2632         }
2633 }
2634
2635 static void add_zero_len_inline(void *wqe)
2636 {
2637         struct mlx4_wqe_inline_seg *inl = wqe;
2638         memset(wqe, 0, 16);
2639         inl->byte_count = cpu_to_be32(1 << 31);
2640 }
2641
2642 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2643                       struct ib_send_wr **bad_wr)
2644 {
2645         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2646         void *wqe;
2647         struct mlx4_wqe_ctrl_seg *ctrl;
2648         struct mlx4_wqe_data_seg *dseg;
2649         unsigned long flags;
2650         int nreq;
2651         int err = 0;
2652         unsigned ind;
2653         int uninitialized_var(stamp);
2654         int uninitialized_var(size);
2655         unsigned uninitialized_var(seglen);
2656         __be32 dummy;
2657         __be32 *lso_wqe;
2658         __be32 uninitialized_var(lso_hdr_sz);
2659         __be32 blh;
2660         int i;
2661         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2662
2663         spin_lock_irqsave(&qp->sq.lock, flags);
2664         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2665                 err = -EIO;
2666                 *bad_wr = wr;
2667                 nreq = 0;
2668                 goto out;
2669         }
2670
2671         ind = qp->sq_next_wqe;
2672
2673         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2674                 lso_wqe = &dummy;
2675                 blh = 0;
2676
2677                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2678                         err = -ENOMEM;
2679                         *bad_wr = wr;
2680                         goto out;
2681                 }
2682
2683                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2684                         err = -EINVAL;
2685                         *bad_wr = wr;
2686                         goto out;
2687                 }
2688
2689                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2690                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2691
2692                 ctrl->srcrb_flags =
2693                         (wr->send_flags & IB_SEND_SIGNALED ?
2694                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2695                         (wr->send_flags & IB_SEND_SOLICITED ?
2696                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2697                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2698                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2699                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2700                         qp->sq_signal_bits;
2701
2702                 ctrl->imm = send_ieth(wr);
2703
2704                 wqe += sizeof *ctrl;
2705                 size = sizeof *ctrl / 16;
2706
2707                 switch (qp->mlx4_ib_qp_type) {
2708                 case MLX4_IB_QPT_RC:
2709                 case MLX4_IB_QPT_UC:
2710                         switch (wr->opcode) {
2711                         case IB_WR_ATOMIC_CMP_AND_SWP:
2712                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2713                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2714                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2715                                               wr->wr.atomic.rkey);
2716                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2717
2718                                 set_atomic_seg(wqe, wr);
2719                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2720
2721                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2722                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2723
2724                                 break;
2725
2726                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2727                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2728                                               wr->wr.atomic.rkey);
2729                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2730
2731                                 set_masked_atomic_seg(wqe, wr);
2732                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2733
2734                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2735                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2736
2737                                 break;
2738
2739                         case IB_WR_RDMA_READ:
2740                         case IB_WR_RDMA_WRITE:
2741                         case IB_WR_RDMA_WRITE_WITH_IMM:
2742                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2743                                               wr->wr.rdma.rkey);
2744                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2745                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2746                                 break;
2747
2748                         case IB_WR_LOCAL_INV:
2749                                 ctrl->srcrb_flags |=
2750                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2751                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2752                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2753                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2754                                 break;
2755
2756                         case IB_WR_FAST_REG_MR:
2757                                 ctrl->srcrb_flags |=
2758                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2759                                 set_fmr_seg(wqe, wr);
2760                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2761                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2762                                 break;
2763
2764                         case IB_WR_BIND_MW:
2765                                 ctrl->srcrb_flags |=
2766                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2767                                 set_bind_seg(wqe, wr);
2768                                 wqe  += sizeof(struct mlx4_wqe_bind_seg);
2769                                 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2770                                 break;
2771                         default:
2772                                 /* No extra segments required for sends */
2773                                 break;
2774                         }
2775                         break;
2776
2777                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2778                         err =  build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2779                         if (unlikely(err)) {
2780                                 *bad_wr = wr;
2781                                 goto out;
2782                         }
2783                         wqe  += seglen;
2784                         size += seglen / 16;
2785                         break;
2786                 case MLX4_IB_QPT_TUN_SMI:
2787                 case MLX4_IB_QPT_TUN_GSI:
2788                         /* this is a UD qp used in MAD responses to slaves. */
2789                         set_datagram_seg(wqe, wr);
2790                         /* set the forced-loopback bit in the data seg av */
2791                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2792                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2793                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2794                         break;
2795                 case MLX4_IB_QPT_UD:
2796                         set_datagram_seg(wqe, wr);
2797                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2798                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2799
2800                         if (wr->opcode == IB_WR_LSO) {
2801                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
2802                                 if (unlikely(err)) {
2803                                         *bad_wr = wr;
2804                                         goto out;
2805                                 }
2806                                 lso_wqe = (__be32 *) wqe;
2807                                 wqe  += seglen;
2808                                 size += seglen / 16;
2809                         }
2810                         break;
2811
2812                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2813                         err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2814                         if (unlikely(err)) {
2815                                 *bad_wr = wr;
2816                                 goto out;
2817                         }
2818                         wqe  += seglen;
2819                         size += seglen / 16;
2820                         /* to start tunnel header on a cache-line boundary */
2821                         add_zero_len_inline(wqe);
2822                         wqe += 16;
2823                         size++;
2824                         build_tunnel_header(wr, wqe, &seglen);
2825                         wqe  += seglen;
2826                         size += seglen / 16;
2827                         break;
2828                 case MLX4_IB_QPT_PROXY_SMI:
2829                 case MLX4_IB_QPT_PROXY_GSI:
2830                         /* If we are tunneling special qps, this is a UD qp.
2831                          * In this case we first add a UD segment targeting
2832                          * the tunnel qp, and then add a header with address
2833                          * information */
2834                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr,
2835                                                 qp->mlx4_ib_qp_type);
2836                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2837                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2838                         build_tunnel_header(wr, wqe, &seglen);
2839                         wqe  += seglen;
2840                         size += seglen / 16;
2841                         break;
2842
2843                 case MLX4_IB_QPT_SMI:
2844                 case MLX4_IB_QPT_GSI:
2845                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2846                         if (unlikely(err)) {
2847                                 *bad_wr = wr;
2848                                 goto out;
2849                         }
2850                         wqe  += seglen;
2851                         size += seglen / 16;
2852                         break;
2853
2854                 default:
2855                         break;
2856                 }
2857
2858                 /*
2859                  * Write data segments in reverse order, so as to
2860                  * overwrite cacheline stamp last within each
2861                  * cacheline.  This avoids issues with WQE
2862                  * prefetching.
2863                  */
2864
2865                 dseg = wqe;
2866                 dseg += wr->num_sge - 1;
2867                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2868
2869                 /* Add one more inline data segment for ICRC for MLX sends */
2870                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2871                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2872                              qp->mlx4_ib_qp_type &
2873                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2874                         set_mlx_icrc_seg(dseg + 1);
2875                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
2876                 }
2877
2878                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2879                         set_data_seg(dseg, wr->sg_list + i);
2880
2881                 /*
2882                  * Possibly overwrite stamping in cacheline with LSO
2883                  * segment only after making sure all data segments
2884                  * are written.
2885                  */
2886                 wmb();
2887                 *lso_wqe = lso_hdr_sz;
2888
2889                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2890                                     MLX4_WQE_CTRL_FENCE : 0) | size;
2891
2892                 /*
2893                  * Make sure descriptor is fully written before
2894                  * setting ownership bit (because HW can start
2895                  * executing as soon as we do).
2896                  */
2897                 wmb();
2898
2899                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
2900                         *bad_wr = wr;
2901                         err = -EINVAL;
2902                         goto out;
2903                 }
2904
2905                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
2906                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
2907
2908                 stamp = ind + qp->sq_spare_wqes;
2909                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2910
2911                 /*
2912                  * We can improve latency by not stamping the last
2913                  * send queue WQE until after ringing the doorbell, so
2914                  * only stamp here if there are still more WQEs to post.
2915                  *
2916                  * Same optimization applies to padding with NOP wqe
2917                  * in case of WQE shrinking (used to prevent wrap-around
2918                  * in the middle of WR).
2919                  */
2920                 if (wr->next) {
2921                         stamp_send_wqe(qp, stamp, size * 16);
2922                         ind = pad_wraparound(qp, ind);
2923                 }
2924         }
2925
2926 out:
2927         if (likely(nreq)) {
2928                 qp->sq.head += nreq;
2929
2930                 /*
2931                  * Make sure that descriptors are written before
2932                  * doorbell record.
2933                  */
2934                 wmb();
2935
2936                 writel(qp->doorbell_qpn,
2937                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2938
2939                 /*
2940                  * Make sure doorbells don't leak out of SQ spinlock
2941                  * and reach the HCA out of order.
2942                  */
2943                 mmiowb();
2944
2945                 stamp_send_wqe(qp, stamp, size * 16);
2946
2947                 ind = pad_wraparound(qp, ind);
2948                 qp->sq_next_wqe = ind;
2949         }
2950
2951         spin_unlock_irqrestore(&qp->sq.lock, flags);
2952
2953         return err;
2954 }
2955
2956 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2957                       struct ib_recv_wr **bad_wr)
2958 {
2959         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2960         struct mlx4_wqe_data_seg *scat;
2961         unsigned long flags;
2962         int err = 0;
2963         int nreq;
2964         int ind;
2965         int max_gs;
2966         int i;
2967         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2968
2969         max_gs = qp->rq.max_gs;
2970         spin_lock_irqsave(&qp->rq.lock, flags);
2971
2972         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2973                 err = -EIO;
2974                 *bad_wr = wr;
2975                 nreq = 0;
2976                 goto out;
2977         }
2978
2979         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2980
2981         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2982                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2983                         err = -ENOMEM;
2984                         *bad_wr = wr;
2985                         goto out;
2986                 }
2987
2988                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2989                         err = -EINVAL;
2990                         *bad_wr = wr;
2991                         goto out;
2992                 }
2993
2994                 scat = get_recv_wqe(qp, ind);
2995
2996                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2997                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2998                         ib_dma_sync_single_for_device(ibqp->device,
2999                                                       qp->sqp_proxy_rcv[ind].map,
3000                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
3001                                                       DMA_FROM_DEVICE);
3002                         scat->byte_count =
3003                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3004                         /* use dma lkey from upper layer entry */
3005                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3006                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3007                         scat++;
3008                         max_gs--;
3009                 }
3010
3011                 for (i = 0; i < wr->num_sge; ++i)
3012                         __set_data_seg(scat + i, wr->sg_list + i);
3013
3014                 if (i < max_gs) {
3015                         scat[i].byte_count = 0;
3016                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3017                         scat[i].addr       = 0;
3018                 }
3019
3020                 qp->rq.wrid[ind] = wr->wr_id;
3021
3022                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3023         }
3024
3025 out:
3026         if (likely(nreq)) {
3027                 qp->rq.head += nreq;
3028
3029                 /*
3030                  * Make sure that descriptors are written before
3031                  * doorbell record.
3032                  */
3033                 wmb();
3034
3035                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3036         }
3037
3038         spin_unlock_irqrestore(&qp->rq.lock, flags);
3039
3040         return err;
3041 }
3042
3043 #else   /* AKAROS */
3044
3045 /*
3046  * Stub for now: mlx4_ib_post_send() is used by mr.c, but enabling the
3047  * actual mlx4_ib_post_send() code will drag in quite a few more header
3048  * files. Also, all these interfaces are mandatory as checked by
3049  * ib_device_check_mandatory()
3050  */
3051 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3052                       struct ib_send_wr **bad_wr)
3053 {
3054         BUG();
3055         return -1;
3056 }
3057
3058 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,