mlx4: /dev/ -> /dev_vfs/
[akaros.git] / kern / drivers / net / mlx4 / profile.c
1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34
35 #include "mlx4.h"
36 #include "fw.h"
37
38 enum {
39         MLX4_RES_QP,
40         MLX4_RES_RDMARC,
41         MLX4_RES_ALTC,
42         MLX4_RES_AUXC,
43         MLX4_RES_SRQ,
44         MLX4_RES_CQ,
45         MLX4_RES_EQ,
46         MLX4_RES_DMPT,
47         MLX4_RES_CMPT,
48         MLX4_RES_MTT,
49         MLX4_RES_MCG,
50         MLX4_RES_NUM
51 };
52
53 static const char *res_name[] = {
54         [MLX4_RES_QP]           = "QP",
55         [MLX4_RES_RDMARC]       = "RDMARC",
56         [MLX4_RES_ALTC]         = "ALTC",
57         [MLX4_RES_AUXC]         = "AUXC",
58         [MLX4_RES_SRQ]          = "SRQ",
59         [MLX4_RES_CQ]           = "CQ",
60         [MLX4_RES_EQ]           = "EQ",
61         [MLX4_RES_DMPT]         = "DMPT",
62         [MLX4_RES_CMPT]         = "CMPT",
63         [MLX4_RES_MTT]          = "MTT",
64         [MLX4_RES_MCG]          = "MCG",
65 };
66
67 uint64_t mlx4_make_profile(struct mlx4_dev *dev,
68                       struct mlx4_profile *request,
69                       struct mlx4_dev_cap *dev_cap,
70                       struct mlx4_init_hca_param *init_hca)
71 {
72         struct mlx4_priv *priv = mlx4_priv(dev);
73         struct mlx4_resource {
74                 uint64_t size;
75                 uint64_t start;
76                 int type;
77                 uint32_t num;
78                 int log_num;
79         };
80
81         uint64_t total_size = 0;
82         struct mlx4_resource *profile;
83         struct mlx4_resource tmp;
84 #if 0 // AKAROS_PORT
85         struct sysinfo si;
86 #endif
87         int i, j;
88
89         profile = kzmalloc((MLX4_RES_NUM) * (sizeof(*profile)), MEM_WAIT);
90         if (!profile)
91                 return -ENOMEM;
92
93         /*
94          * We want to scale the number of MTTs with the size of the
95          * system memory, since it makes sense to register a lot of
96          * memory on a system with a lot of memory.  As a heuristic,
97          * make sure we have enough MTTs to cover twice the system
98          * memory (with PAGE_SIZE entries).
99          *
100          * This number has to be a power of two and fit into 32 bits
101          * due to device limitations, so cap this at 2^31 as well.
102          * That limits us to 8TB of memory registration per HCA with
103          * 4KB pages, which is probably OK for the next few months.
104          */
105 #if 0 // AKAROS_PORT
106         si_meminfo(&si);
107         request->num_mtt =
108                 ROUNDUPPWR2(MAX_T(unsigned, request->num_mtt, MIN(1UL << (31 - log_mtts_per_seg), si.totalram >> (log_mtts_per_seg - 1))));
109 #else
110         request->num_mtt =
111                 ROUNDUPPWR2(MAX_T(unsigned, request->num_mtt, 1UL << (31 - log_mtts_per_seg)));
112 #endif
113
114         profile[MLX4_RES_QP].size     = dev_cap->qpc_entry_sz;
115         profile[MLX4_RES_RDMARC].size = dev_cap->rdmarc_entry_sz;
116         profile[MLX4_RES_ALTC].size   = dev_cap->altc_entry_sz;
117         profile[MLX4_RES_AUXC].size   = dev_cap->aux_entry_sz;
118         profile[MLX4_RES_SRQ].size    = dev_cap->srq_entry_sz;
119         profile[MLX4_RES_CQ].size     = dev_cap->cqc_entry_sz;
120         profile[MLX4_RES_EQ].size     = dev_cap->eqc_entry_sz;
121         profile[MLX4_RES_DMPT].size   = dev_cap->dmpt_entry_sz;
122         profile[MLX4_RES_CMPT].size   = dev_cap->cmpt_entry_sz;
123         profile[MLX4_RES_MTT].size    = dev_cap->mtt_entry_sz;
124         profile[MLX4_RES_MCG].size    = mlx4_get_mgm_entry_size(dev);
125
126         profile[MLX4_RES_QP].num      = request->num_qp;
127         profile[MLX4_RES_RDMARC].num  = request->num_qp * request->rdmarc_per_qp;
128         profile[MLX4_RES_ALTC].num    = request->num_qp;
129         profile[MLX4_RES_AUXC].num    = request->num_qp;
130         profile[MLX4_RES_SRQ].num     = request->num_srq;
131         profile[MLX4_RES_CQ].num      = request->num_cq;
132         profile[MLX4_RES_EQ].num = mlx4_is_mfunc(dev) ? dev->phys_caps.num_phys_eqs :
133                                         MIN_T(unsigned, dev_cap->max_eqs,
134                                               MAX_MSIX);
135         profile[MLX4_RES_DMPT].num    = request->num_mpt;
136         profile[MLX4_RES_CMPT].num    = MLX4_NUM_CMPTS;
137         profile[MLX4_RES_MTT].num     = request->num_mtt * (1 << log_mtts_per_seg);
138         profile[MLX4_RES_MCG].num     = request->num_mcg;
139
140         for (i = 0; i < MLX4_RES_NUM; ++i) {
141                 profile[i].type     = i;
142                 profile[i].num      = ROUNDUPPWR2(profile[i].num);
143                 profile[i].log_num  = LOG2_UP(profile[i].num);
144                 profile[i].size    *= profile[i].num;
145                 profile[i].size     = MAX(profile[i].size,
146                                           (uint64_t)PAGE_SIZE);
147         }
148
149         /*
150          * Sort the resources in decreasing order of size.  Since they
151          * all have sizes that are powers of 2, we'll be able to keep
152          * resources aligned to their size and pack them without gaps
153          * using the sorted order.
154          */
155         for (i = MLX4_RES_NUM; i > 0; --i)
156                 for (j = 1; j < i; ++j) {
157                         if (profile[j].size > profile[j - 1].size) {
158                                 tmp            = profile[j];
159                                 profile[j]     = profile[j - 1];
160                                 profile[j - 1] = tmp;
161                         }
162                 }
163
164         for (i = 0; i < MLX4_RES_NUM; ++i) {
165                 if (profile[i].size) {
166                         profile[i].start = total_size;
167                         total_size      += profile[i].size;
168                 }
169
170                 if (total_size > dev_cap->max_icm_sz) {
171                         mlx4_err(dev, "Profile requires 0x%llx bytes; won't fit in 0x%llx bytes of context memory\n",
172                                  (unsigned long long) total_size,
173                                  (unsigned long long) dev_cap->max_icm_sz);
174                         kfree(profile);
175                         return -ENOMEM;
176                 }
177
178                 if (profile[i].size)
179                         mlx4_dbg(dev, "  profile[%2d] (%6s): 2^%02d entries @ 0x%10llx, size 0x%10llx\n",
180                                  i, res_name[profile[i].type],
181                                  profile[i].log_num,
182                                  (unsigned long long) profile[i].start,
183                                  (unsigned long long) profile[i].size);
184         }
185
186         mlx4_dbg(dev, "HCA context memory: reserving %d KB\n",
187                  (int) (total_size >> 10));
188
189         for (i = 0; i < MLX4_RES_NUM; ++i) {
190                 switch (profile[i].type) {
191                 case MLX4_RES_QP:
192                         dev->caps.num_qps     = profile[i].num;
193                         init_hca->qpc_base    = profile[i].start;
194                         init_hca->log_num_qps = profile[i].log_num;
195                         break;
196                 case MLX4_RES_RDMARC:
197                         for (priv->qp_table.rdmarc_shift = 0;
198                              request->num_qp << priv->qp_table.rdmarc_shift < profile[i].num;
199                              ++priv->qp_table.rdmarc_shift)
200                                 ; /* nothing */
201                         dev->caps.max_qp_dest_rdma = 1 << priv->qp_table.rdmarc_shift;
202                         priv->qp_table.rdmarc_base   = (uint32_t) profile[i].start;
203                         init_hca->rdmarc_base        = profile[i].start;
204                         init_hca->log_rd_per_qp      = priv->qp_table.rdmarc_shift;
205                         break;
206                 case MLX4_RES_ALTC:
207                         init_hca->altc_base = profile[i].start;
208                         break;
209                 case MLX4_RES_AUXC:
210                         init_hca->auxc_base = profile[i].start;
211                         break;
212                 case MLX4_RES_SRQ:
213                         dev->caps.num_srqs     = profile[i].num;
214                         init_hca->srqc_base    = profile[i].start;
215                         init_hca->log_num_srqs = profile[i].log_num;
216                         break;
217                 case MLX4_RES_CQ:
218                         dev->caps.num_cqs     = profile[i].num;
219                         init_hca->cqc_base    = profile[i].start;
220                         init_hca->log_num_cqs = profile[i].log_num;
221                         break;
222                 case MLX4_RES_EQ:
223                         if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
224                                 init_hca->log_num_eqs = 0x1f;
225                                 init_hca->eqc_base    = profile[i].start;
226                                 init_hca->num_sys_eqs = dev_cap->num_sys_eqs;
227                         } else {
228                                 dev->caps.num_eqs     = ROUNDUPPWR2(MIN_T(unsigned, dev_cap->max_eqs, MAX_MSIX));
229                                 init_hca->eqc_base    = profile[i].start;
230                                 init_hca->log_num_eqs = LOG2_UP(dev->caps.num_eqs);
231                         }
232                         break;
233                 case MLX4_RES_DMPT:
234                         dev->caps.num_mpts      = profile[i].num;
235                         priv->mr_table.mpt_base = profile[i].start;
236                         init_hca->dmpt_base     = profile[i].start;
237                         init_hca->log_mpt_sz    = profile[i].log_num;
238                         break;
239                 case MLX4_RES_CMPT:
240                         init_hca->cmpt_base      = profile[i].start;
241                         break;
242                 case MLX4_RES_MTT:
243                         dev->caps.num_mtts       = profile[i].num;
244                         priv->mr_table.mtt_base  = profile[i].start;
245                         init_hca->mtt_base       = profile[i].start;
246                         break;
247                 case MLX4_RES_MCG:
248                         init_hca->mc_base         = profile[i].start;
249                         init_hca->log_mc_entry_sz =
250                                         LOG2_UP(mlx4_get_mgm_entry_size(dev));
251                         init_hca->log_mc_table_sz = profile[i].log_num;
252                         if (dev->caps.steering_mode ==
253                             MLX4_STEERING_MODE_DEVICE_MANAGED) {
254                                 dev->caps.num_mgms = profile[i].num;
255                         } else {
256                                 init_hca->log_mc_hash_sz =
257                                                 profile[i].log_num - 1;
258                                 dev->caps.num_mgms = profile[i].num >> 1;
259                                 dev->caps.num_amgms = profile[i].num >> 1;
260                         }
261                         break;
262                 default:
263                         break;
264                 }
265         }
266
267         /*
268          * PDs don't take any HCA memory, but we assign them as part
269          * of the HCA profile anyway.
270          */
271         dev->caps.num_pds = MLX4_NUM_PDS;
272
273         kfree(profile);
274         return total_size;
275 }