0f450f9b60c16b01addaa31b82f39905f834f036
[akaros.git] / kern / drivers / net / mlx4 / main.c
1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * OpenIB.org BSD license below:
12  *
13  *     Redistribution and use in source and binary forms, with or
14  *     without modification, are permitted provided that the following
15  *     conditions are met:
16  *
17  *      - Redistributions of source code must retain the above
18  *        copyright notice, this list of conditions and the following
19  *        disclaimer.
20  *
21  *      - Redistributions in binary form must reproduce the above
22  *        copyright notice, this list of conditions and the following
23  *        disclaimer in the documentation and/or other materials
24  *        provided with the distribution.
25  *
26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33  * SOFTWARE.
34  */
35
36 #include <linux_compat.h>
37 #include <linux/mlx4/device.h>
38 #include <linux/mlx4/doorbell.h>
39
40 #include "mlx4.h"
41 #include "fw.h"
42 #include "icm.h"
43
44 MODULE_AUTHOR("Roland Dreier");
45 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
46 MODULE_LICENSE("Dual BSD/GPL");
47 MODULE_VERSION(DRV_VERSION);
48
49 struct workqueue_struct *mlx4_wq;
50
51 #ifdef CONFIG_MLX4_DEBUG
52
53 int mlx4_debug_level = 0;
54 module_param_named(debug_level, mlx4_debug_level, int, 0644);
55 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
56
57 #endif /* CONFIG_MLX4_DEBUG */
58
59 #ifdef CONFIG_PCI_MSI
60
61 static int msi_x = 1;
62 module_param(msi_x, int, 0444);
63 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
64
65 #else /* CONFIG_PCI_MSI */
66
67 #define msi_x (0)
68
69 #endif /* CONFIG_PCI_MSI */
70
71 static uint8_t num_vfs[3] = {0, 0, 0};
72 static int num_vfs_argc;
73 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
74 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
75                           "num_vfs=port1,port2,port1+2");
76
77 static uint8_t probe_vf[3] = {0, 0, 0};
78 static int probe_vfs_argc;
79 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
80 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
81                            "probe_vf=port1,port2,port1+2");
82
83 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
84 module_param_named(log_num_mgm_entry_size,
85                         mlx4_log_num_mgm_entry_size, int, 0444);
86 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
87                                          " of qp per mcg, for example:"
88                                          " 10 gives 248.range: 7 <="
89                                          " log_num_mgm_entry_size <= 12."
90                                          " To activate device managed"
91                                          " flow steering when available, set to -1");
92
93 static bool enable_64b_cqe_eqe = true;
94 module_param(enable_64b_cqe_eqe, bool, 0444);
95 MODULE_PARM_DESC(enable_64b_cqe_eqe,
96                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
97
98 #define PF_CONTEXT_BEHAVIOUR_MASK       (MLX4_FUNC_CAP_64B_EQE_CQE | \
99                                          MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
100                                          MLX4_FUNC_CAP_DMFS_A0_STATIC)
101
102 #define RESET_PERSIST_MASK_FLAGS        (MLX4_FLAG_SRIOV)
103
104 static char mlx4_version[] =
105         DRV_NAME ": Mellanox ConnectX core driver v"
106         DRV_VERSION " (" DRV_RELDATE ")\n";
107
108 static struct mlx4_profile default_profile = {
109         .num_qp         = 1 << 18,
110         .num_srq        = 1 << 16,
111         .rdmarc_per_qp  = 1 << 4,
112         .num_cq         = 1 << 16,
113         .num_mcg        = 1 << 13,
114         .num_mpt        = 1 << 19,
115         .num_mtt        = 1 << 20, /* It is really num mtt segements */
116 };
117
118 static struct mlx4_profile low_mem_profile = {
119         .num_qp         = 1 << 17,
120         .num_srq        = 1 << 6,
121         .rdmarc_per_qp  = 1 << 4,
122         .num_cq         = 1 << 8,
123         .num_mcg        = 1 << 8,
124         .num_mpt        = 1 << 9,
125         .num_mtt        = 1 << 7,
126 };
127
128 static int log_num_mac = 7;
129 module_param_named(log_num_mac, log_num_mac, int, 0444);
130 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
131
132 static int log_num_vlan;
133 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
134 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
135 /* Log2 max number of VLANs per ETH port (0-7) */
136 #define MLX4_LOG_NUM_VLANS 7
137 #define MLX4_MIN_LOG_NUM_VLANS 0
138 #define MLX4_MIN_LOG_NUM_MAC 1
139
140 static bool use_prio;
141 module_param_named(use_prio, use_prio, bool, 0444);
142 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
143
144 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
145 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
146 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
147
148 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
149 static int arr_argc = 2;
150 module_param_array(port_type_array, int, &arr_argc, 0444);
151 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
152                                 "1 for IB, 2 for Ethernet");
153
154 struct mlx4_port_config {
155         struct list_head list;
156         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
157         struct pci_device *pdev;
158 };
159
160 static atomic_t pf_loading = ATOMIC_INIT(0);
161
162 int mlx4_check_port_params(struct mlx4_dev *dev,
163                            enum mlx4_port_type *port_type)
164 {
165         int i;
166
167         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
168                 for (i = 0; i < dev->caps.num_ports - 1; i++) {
169                         if (port_type[i] != port_type[i + 1]) {
170                                 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
171                                 return -EINVAL;
172                         }
173                 }
174         }
175
176         for (i = 0; i < dev->caps.num_ports; i++) {
177                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
178                         mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
179                                  i + 1);
180                         return -EINVAL;
181                 }
182         }
183         return 0;
184 }
185
186 static void mlx4_set_port_mask(struct mlx4_dev *dev)
187 {
188         int i;
189
190         for (i = 1; i <= dev->caps.num_ports; ++i)
191                 dev->caps.port_mask[i] = dev->caps.port_type[i];
192 }
193
194 enum {
195         MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
196 };
197
198 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
199 {
200         int err = 0;
201         struct mlx4_func func;
202
203         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
204                 err = mlx4_QUERY_FUNC(dev, &func, 0);
205                 if (err) {
206                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
207                         return err;
208                 }
209                 dev_cap->max_eqs = func.max_eq;
210                 dev_cap->reserved_eqs = func.rsvd_eqs;
211                 dev_cap->reserved_uars = func.rsvd_uars;
212                 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
213         }
214         return err;
215 }
216
217 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
218 {
219         struct mlx4_caps *dev_cap = &dev->caps;
220
221         /* FW not supporting or cancelled by user */
222         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
223             !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
224                 return;
225
226         /* Must have 64B CQE_EQE enabled by FW to use bigger stride
227          * When FW has NCSI it may decide not to report 64B CQE/EQEs
228          */
229         if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
230             !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
231                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
232                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
233                 return;
234         }
235
236         if (cache_line_size() == 128 || cache_line_size() == 256) {
237                 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
238                 /* Changing the real data inside CQE size to 32B */
239                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
240                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
241
242                 if (mlx4_is_master(dev))
243                         dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
244         } else {
245                 if (cache_line_size() != 32  && cache_line_size() != 64)
246                         mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
247                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
248                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
249         }
250 }
251
252 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
253                           struct mlx4_port_cap *port_cap)
254 {
255         dev->caps.vl_cap[port]      = port_cap->max_vl;
256         dev->caps.ib_mtu_cap[port]          = port_cap->ib_mtu;
257         dev->phys_caps.gid_phys_table_len[port]  = port_cap->max_gids;
258         dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
259         /* set gid and pkey table operating lengths by default
260          * to non-sriov values
261          */
262         dev->caps.gid_table_len[port]  = port_cap->max_gids;
263         dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
264         dev->caps.port_width_cap[port] = port_cap->max_port_width;
265         dev->caps.eth_mtu_cap[port]    = port_cap->eth_mtu;
266         dev->caps.def_mac[port]        = port_cap->def_mac;
267         dev->caps.supported_type[port] = port_cap->supported_port_types;
268         dev->caps.suggested_type[port] = port_cap->suggested_type;
269         dev->caps.default_sense[port] = port_cap->default_sense;
270         dev->caps.trans_type[port]          = port_cap->trans_type;
271         dev->caps.vendor_oui[port]     = port_cap->vendor_oui;
272         dev->caps.wavelength[port]     = port_cap->wavelength;
273         dev->caps.trans_code[port]     = port_cap->trans_code;
274
275         return 0;
276 }
277
278 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
279                          struct mlx4_port_cap *port_cap)
280 {
281         int err = 0;
282
283         err = mlx4_QUERY_PORT(dev, port, port_cap);
284
285         if (err)
286                 mlx4_err(dev, "QUERY_PORT command failed.\n");
287
288         return err;
289 }
290
291 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
292 {
293         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
294                 return;
295
296         if (mlx4_is_mfunc(dev)) {
297                 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
298                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
299                 return;
300         }
301
302         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
303                 mlx4_dbg(dev,
304                          "Keep FCS is not supported - Disabling Ignore FCS");
305                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
306                 return;
307         }
308 }
309
310 #define MLX4_A0_STEERING_TABLE_SIZE     256
311 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
312 {
313         int err;
314         int i;
315
316         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
317         if (err) {
318                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
319                 return err;
320         }
321         mlx4_dev_cap_dump(dev, dev_cap);
322
323         if (dev_cap->min_page_sz > PAGE_SIZE) {
324                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
325                          dev_cap->min_page_sz, PAGE_SIZE);
326                 return -ENODEV;
327         }
328         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
329                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
330                          dev_cap->num_ports, MLX4_MAX_PORTS);
331                 return -ENODEV;
332         }
333
334         if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
335                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
336                          dev_cap->uar_size,
337                          (unsigned long long)
338                          pci_resource_len(dev->persist->pdev, 2));
339                 return -ENODEV;
340         }
341
342         dev->caps.num_ports          = dev_cap->num_ports;
343         dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
344         dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
345                                       dev->caps.num_sys_eqs :
346                                       MLX4_MAX_EQ_NUM;
347         for (i = 1; i <= dev->caps.num_ports; ++i) {
348                 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
349                 if (err) {
350                         mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
351                         return err;
352                 }
353         }
354
355         dev->caps.uar_page_size      = PAGE_SIZE;
356         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
357         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
358         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
359         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
360         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
361         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
362         dev->caps.max_wqes           = dev_cap->max_qp_sz;
363         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
364         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
365         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
366         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
367         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
368         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
369         /*
370          * Subtract 1 from the limit because we need to allocate a
371          * spare CQE so the HCA HW can tell the difference between an
372          * empty CQ and a full CQ.
373          */
374         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
375         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
376         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
377         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
378         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
379
380         /* The first 128 UARs are used for EQ doorbells */
381         dev->caps.reserved_uars      = MAX_T(int, 128,
382                                                     dev_cap->reserved_uars);
383         dev->caps.reserved_pds       = dev_cap->reserved_pds;
384         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
385                                         dev_cap->reserved_xrcds : 0;
386         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
387                                         dev_cap->max_xrcds : 0;
388         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
389
390         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
391         dev->caps.page_size_cap      = ~(uint32_t) (dev_cap->min_page_sz - 1);
392         dev->caps.flags              = dev_cap->flags;
393         dev->caps.flags2             = dev_cap->flags2;
394         dev->caps.bmme_flags         = dev_cap->bmme_flags;
395         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
396         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
397         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
398         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
399
400         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
401         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
402                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
403         /* Don't do sense port on multifunction devices (for now at least) */
404         if (mlx4_is_mfunc(dev))
405                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
406
407         if (mlx4_low_memory_profile()) {
408                 dev->caps.log_num_macs  = MLX4_MIN_LOG_NUM_MAC;
409                 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
410         } else {
411                 dev->caps.log_num_macs  = log_num_mac;
412                 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
413         }
414
415         for (i = 1; i <= dev->caps.num_ports; ++i) {
416                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
417                 if (dev->caps.supported_type[i]) {
418                         /* if only ETH is supported - assign ETH */
419                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
420                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
421                         /* if only IB is supported, assign IB */
422                         else if (dev->caps.supported_type[i] ==
423                                  MLX4_PORT_TYPE_IB)
424                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
425                         else {
426                                 /* if IB and ETH are supported, we set the port
427                                  * type according to user selection of port type;
428                                  * if user selected none, take the FW hint */
429                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
430                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
431                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
432                                 else
433                                         dev->caps.port_type[i] = port_type_array[i - 1];
434                         }
435                 }
436                 /*
437                  * Link sensing is allowed on the port if 3 conditions are true:
438                  * 1. Both protocols are supported on the port.
439                  * 2. Different types are supported on the port
440                  * 3. FW declared that it supports link sensing
441                  */
442                 mlx4_priv(dev)->sense.sense_allowed[i] =
443                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
444                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
445                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
446
447                 /*
448                  * If "default_sense" bit is set, we move the port to "AUTO" mode
449                  * and perform sense_port FW command to try and set the correct
450                  * port type from beginning
451                  */
452                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
453                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
454                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
455                         mlx4_SENSE_PORT(dev, i, &sensed_port);
456                         if (sensed_port != MLX4_PORT_TYPE_NONE)
457                                 dev->caps.port_type[i] = sensed_port;
458                 } else {
459                         dev->caps.possible_type[i] = dev->caps.port_type[i];
460                 }
461
462                 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
463                         dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
464                         mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
465                                   i, 1 << dev->caps.log_num_macs);
466                 }
467                 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
468                         dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
469                         mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
470                                   i, 1 << dev->caps.log_num_vlans);
471                 }
472         }
473
474         dev->caps.max_counters = 1 << LOG2_UP(dev_cap->max_counters);
475
476         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
477         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
478                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
479                 (1 << dev->caps.log_num_macs) *
480                 (1 << dev->caps.log_num_vlans) *
481                 dev->caps.num_ports;
482         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
483
484         if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
485             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
486                 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
487         else
488                 dev->caps.dmfs_high_rate_qpn_base =
489                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
490
491         if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
492             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
493                 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
494                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
495                 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
496         } else {
497                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
498                 dev->caps.dmfs_high_rate_qpn_base =
499                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
500                 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
501         }
502
503         dev->caps.rl_caps = dev_cap->rl_caps;
504
505         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
506                 dev->caps.dmfs_high_rate_qpn_range;
507
508         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
509                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
510                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
511                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
512
513         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
514
515         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
516                 if (dev_cap->flags &
517                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
518                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
519                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
520                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
521                 }
522
523                 if (dev_cap->flags2 &
524                     (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
525                      MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
526                         mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
527                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
528                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
529                 }
530         }
531
532         if ((dev->caps.flags &
533             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
534             mlx4_is_master(dev))
535                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
536
537         if (!mlx4_is_slave(dev)) {
538                 mlx4_enable_cqe_eqe_stride(dev);
539                 dev->caps.alloc_res_qp_mask =
540                         (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
541                         MLX4_RESERVE_A0_QP;
542
543                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
544                     dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
545                         mlx4_warn(dev, "Old device ETS support detected\n");
546                         mlx4_warn(dev, "Consider upgrading device FW.\n");
547                         dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
548                 }
549
550         } else {
551                 dev->caps.alloc_res_qp_mask = 0;
552         }
553
554         mlx4_enable_ignore_fcs(dev);
555
556         return 0;
557 }
558
559 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
560                                        enum pci_bus_speed *speed,
561                                        enum pcie_link_width *width)
562 {
563         uint32_t lnkcap1, lnkcap2;
564         int err1, err2;
565
566 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
567
568         *speed = PCI_SPEED_UNKNOWN;
569         *width = PCIE_LNK_WIDTH_UNKNOWN;
570
571         err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
572                                           &lnkcap1);
573         err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
574                                           &lnkcap2);
575         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
576                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
577                         *speed = PCIE_SPEED_8_0GT;
578                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
579                         *speed = PCIE_SPEED_5_0GT;
580                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
581                         *speed = PCIE_SPEED_2_5GT;
582         }
583         if (!err1) {
584                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
585                 if (!lnkcap2) { /* pre-r3.0 */
586                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
587                                 *speed = PCIE_SPEED_5_0GT;
588                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
589                                 *speed = PCIE_SPEED_2_5GT;
590                 }
591         }
592
593         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
594                 return err1 ? err1 :
595                         err2 ? err2 : -EINVAL;
596         }
597         return 0;
598 }
599
600 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
601 {
602         enum pcie_link_width width, width_cap;
603         enum pci_bus_speed speed, speed_cap;
604         int err;
605
606 #define PCIE_SPEED_STR(speed) \
607         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
608          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
609          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
610          "Unknown")
611
612         err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
613         if (err) {
614                 mlx4_warn(dev,
615                           "Unable to determine PCIe device BW capabilities\n");
616                 return;
617         }
618
619         err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
620         if (err || speed == PCI_SPEED_UNKNOWN ||
621             width == PCIE_LNK_WIDTH_UNKNOWN) {
622                 mlx4_warn(dev,
623                           "Unable to determine PCI device chain minimum BW\n");
624                 return;
625         }
626
627         if (width != width_cap || speed != speed_cap)
628                 mlx4_warn(dev,
629                           "PCIe BW is different than device's capability\n");
630
631         mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
632                   PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
633         mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
634                   width, width_cap);
635         return;
636 }
637
638 /*The function checks if there are live vf, return the num of them*/
639 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
640 {
641         struct mlx4_priv *priv = mlx4_priv(dev);
642         struct mlx4_slave_state *s_state;
643         int i;
644         int ret = 0;
645
646         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
647                 s_state = &priv->mfunc.master.slave_state[i];
648                 if (s_state->active && s_state->last_cmd !=
649                     MLX4_COMM_CMD_RESET) {
650                         mlx4_warn(dev, "%s: slave: %d is still active\n",
651                                   __func__, i);
652                         ret++;
653                 }
654         }
655         return ret;
656 }
657
658 int mlx4_get_parav_qkey(struct mlx4_dev *dev, uint32_t qpn, uint32_t *qkey)
659 {
660         uint32_t qk = MLX4_RESERVED_QKEY_BASE;
661
662         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
663             qpn < dev->phys_caps.base_proxy_sqpn)
664                 return -EINVAL;
665
666         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
667                 /* tunnel qp */
668                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
669         else
670                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
671         *qkey = qk;
672         return 0;
673 }
674 EXPORT_SYMBOL(mlx4_get_parav_qkey);
675
676 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
677 {
678         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
679
680         if (!mlx4_is_master(dev))
681                 return;
682
683         priv->virt2phys_pkey[slave][port - 1][i] = val;
684 }
685 EXPORT_SYMBOL(mlx4_sync_pkey_table);
686
687 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
688 {
689         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
690
691         if (!mlx4_is_master(dev))
692                 return;
693
694         priv->slave_node_guids[slave] = guid;
695 }
696 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
697
698 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
699 {
700         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
701
702         if (!mlx4_is_master(dev))
703                 return 0;
704
705         return priv->slave_node_guids[slave];
706 }
707 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
708
709 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
710 {
711         struct mlx4_priv *priv = mlx4_priv(dev);
712         struct mlx4_slave_state *s_slave;
713
714         if (!mlx4_is_master(dev))
715                 return 0;
716
717         s_slave = &priv->mfunc.master.slave_state[slave];
718         return !!s_slave->active;
719 }
720 EXPORT_SYMBOL(mlx4_is_slave_active);
721
722 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
723                                        struct mlx4_dev_cap *dev_cap,
724                                        struct mlx4_init_hca_param *hca_param)
725 {
726         dev->caps.steering_mode = hca_param->steering_mode;
727         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
728                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
729                 dev->caps.fs_log_max_ucast_qp_range_size =
730                         dev_cap->fs_log_max_ucast_qp_range_size;
731         } else
732                 dev->caps.num_qp_per_mgm =
733                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
734
735         mlx4_dbg(dev, "Steering mode is: %s\n",
736                  mlx4_steering_mode_str(dev->caps.steering_mode));
737 }
738
739 static int mlx4_slave_cap(struct mlx4_dev *dev)
740 {
741         int                        err;
742         uint32_t                           page_size;
743         struct mlx4_dev_cap        dev_cap;
744         struct mlx4_func_cap       func_cap;
745         struct mlx4_init_hca_param hca_param;
746         uint8_t                    i;
747
748         memset(&hca_param, 0, sizeof(hca_param));
749         err = mlx4_QUERY_HCA(dev, &hca_param);
750         if (err) {
751                 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
752                 return err;
753         }
754
755         /* fail if the hca has an unknown global capability
756          * at this time global_caps should be always zeroed
757          */
758         if (hca_param.global_caps) {
759                 mlx4_err(dev, "Unknown hca global capabilities\n");
760                 return -ENOSYS;
761         }
762
763         mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
764
765         dev->caps.hca_core_clock = hca_param.hca_core_clock;
766
767         memset(&dev_cap, 0, sizeof(dev_cap));
768         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
769         err = mlx4_dev_cap(dev, &dev_cap);
770         if (err) {
771                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
772                 return err;
773         }
774
775         err = mlx4_QUERY_FW(dev);
776         if (err)
777                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
778
779         page_size = ~dev->caps.page_size_cap + 1;
780         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
781         if (page_size > PAGE_SIZE) {
782                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
783                          page_size, PAGE_SIZE);
784                 return -ENODEV;
785         }
786
787         /* slave gets uar page size from QUERY_HCA fw command */
788         dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
789
790         /* TODO: relax this assumption */
791         if (dev->caps.uar_page_size != PAGE_SIZE) {
792                 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
793                          dev->caps.uar_page_size, PAGE_SIZE);
794                 return -ENODEV;
795         }
796
797         memset(&func_cap, 0, sizeof(func_cap));
798         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
799         if (err) {
800                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
801                          err);
802                 return err;
803         }
804
805         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
806             PF_CONTEXT_BEHAVIOUR_MASK) {
807                 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
808                          func_cap.pf_context_behaviour, PF_CONTEXT_BEHAVIOUR_MASK);
809                 return -ENOSYS;
810         }
811
812         dev->caps.num_ports             = func_cap.num_ports;
813         dev->quotas.qp                  = func_cap.qp_quota;
814         dev->quotas.srq                 = func_cap.srq_quota;
815         dev->quotas.cq                  = func_cap.cq_quota;
816         dev->quotas.mpt                 = func_cap.mpt_quota;
817         dev->quotas.mtt                 = func_cap.mtt_quota;
818         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
819         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
820         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
821         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
822         dev->caps.num_eqs               = func_cap.max_eq;
823         dev->caps.reserved_eqs          = func_cap.reserved_eq;
824         dev->caps.reserved_lkey         = func_cap.reserved_lkey;
825         dev->caps.num_pds               = MLX4_NUM_PDS;
826         dev->caps.num_mgms              = 0;
827         dev->caps.num_amgms             = 0;
828
829         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
830                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
831                          dev->caps.num_ports, MLX4_MAX_PORTS);
832                 return -ENODEV;
833         }
834
835         dev->caps.qp0_qkey = kzmalloc((dev->caps.num_ports) * (sizeof(uint32_t)),
836                                       KMALLOC_WAIT);
837         dev->caps.qp0_tunnel = kzmalloc((dev->caps.num_ports) * (sizeof(uint32_t)),
838                                         KMALLOC_WAIT);
839         dev->caps.qp0_proxy = kzmalloc((dev->caps.num_ports) * (sizeof(uint32_t)),
840                                        KMALLOC_WAIT);
841         dev->caps.qp1_tunnel = kzmalloc((dev->caps.num_ports) * (sizeof(uint32_t)),
842                                         KMALLOC_WAIT);
843         dev->caps.qp1_proxy = kzmalloc((dev->caps.num_ports) * (sizeof(uint32_t)),
844                                        KMALLOC_WAIT);
845
846         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
847             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy ||
848             !dev->caps.qp0_qkey) {
849                 err = -ENOMEM;
850                 goto err_mem;
851         }
852
853         for (i = 1; i <= dev->caps.num_ports; ++i) {
854                 err = mlx4_QUERY_FUNC_CAP(dev, i, &func_cap);
855                 if (err) {
856                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
857                                  i, err);
858                         goto err_mem;
859                 }
860                 dev->caps.qp0_qkey[i - 1] = func_cap.qp0_qkey;
861                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
862                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
863                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
864                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
865                 dev->caps.port_mask[i] = dev->caps.port_type[i];
866                 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
867                 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
868                                                     &dev->caps.gid_table_len[i],
869                                                     &dev->caps.pkey_table_len[i]))
870                         goto err_mem;
871         }
872
873         if (dev->caps.uar_page_size * (dev->caps.num_uars -
874                                        dev->caps.reserved_uars) >
875                                        pci_resource_len(dev->persist->pdev,
876                                                         2)) {
877                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
878                          dev->caps.uar_page_size * dev->caps.num_uars,
879                          (unsigned long long)
880                          pci_resource_len(dev->persist->pdev, 2));
881                 goto err_mem;
882         }
883
884         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
885                 dev->caps.eqe_size   = 64;
886                 dev->caps.eqe_factor = 1;
887         } else {
888                 dev->caps.eqe_size   = 32;
889                 dev->caps.eqe_factor = 0;
890         }
891
892         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
893                 dev->caps.cqe_size   = 64;
894                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
895         } else {
896                 dev->caps.cqe_size   = 32;
897         }
898
899         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
900                 dev->caps.eqe_size = hca_param.eqe_size;
901                 dev->caps.eqe_factor = 0;
902         }
903
904         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
905                 dev->caps.cqe_size = hca_param.cqe_size;
906                 /* User still need to know when CQE > 32B */
907                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
908         }
909
910         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
911         mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
912
913         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
914         mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
915                  hca_param.rss_ip_frags ? "on" : "off");
916
917         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
918             dev->caps.bf_reg_size)
919                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
920
921         if (func_cap.extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
922                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
923
924         return 0;
925
926 err_mem:
927         kfree(dev->caps.qp0_qkey);
928         kfree(dev->caps.qp0_tunnel);
929         kfree(dev->caps.qp0_proxy);
930         kfree(dev->caps.qp1_tunnel);
931         kfree(dev->caps.qp1_proxy);
932         dev->caps.qp0_qkey = NULL;
933         dev->caps.qp0_tunnel = NULL;
934         dev->caps.qp0_proxy = NULL;
935         dev->caps.qp1_tunnel = NULL;
936         dev->caps.qp1_proxy = NULL;
937
938         return err;
939 }
940
941 static void mlx4_request_modules(struct mlx4_dev *dev)
942 {
943         int port;
944         int has_ib_port = false;
945         int has_eth_port = false;
946 #define EN_DRV_NAME     "mlx4_en"
947 #define IB_DRV_NAME     "mlx4_ib"
948
949         for (port = 1; port <= dev->caps.num_ports; port++) {
950                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
951                         has_ib_port = true;
952                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
953                         has_eth_port = true;
954         }
955
956 #if 0 // AKAROS_PORT
957         if (has_eth_port)
958                 request_module_nowait(EN_DRV_NAME);
959         if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
960                 request_module_nowait(IB_DRV_NAME);
961 #endif
962 }
963
964 /*
965  * Change the port configuration of the device.
966  * Every user of this function must hold the port mutex.
967  */
968 int mlx4_change_port_types(struct mlx4_dev *dev,
969                            enum mlx4_port_type *port_types)
970 {
971         int err = 0;
972         int change = 0;
973         int port;
974
975         for (port = 0; port <  dev->caps.num_ports; port++) {
976                 /* Change the port type only if the new type is different
977                  * from the current, and not set to Auto */
978                 if (port_types[port] != dev->caps.port_type[port + 1])
979                         change = 1;
980         }
981         if (change) {
982                 mlx4_unregister_device(dev);
983                 for (port = 1; port <= dev->caps.num_ports; port++) {
984                         mlx4_CLOSE_PORT(dev, port);
985                         dev->caps.port_type[port] = port_types[port - 1];
986                         err = mlx4_SET_PORT(dev, port, -1);
987                         if (err) {
988                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
989                                          port);
990                                 goto out;
991                         }
992                 }
993                 mlx4_set_port_mask(dev);
994                 err = mlx4_register_device(dev);
995                 if (err) {
996                         mlx4_err(dev, "Failed to register device\n");
997                         goto out;
998                 }
999                 mlx4_request_modules(dev);
1000         }
1001
1002 out:
1003         return err;
1004 }
1005
1006 static ssize_t show_port_type(struct device *dev,
1007                               struct device_attribute *attr,
1008                               char *buf)
1009 {
1010         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1011                                                    port_attr);
1012         struct mlx4_dev *mdev = info->dev;
1013         char type[8];
1014
1015         sprintf(type, "%s",
1016                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1017                 "ib" : "eth");
1018         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1019                 sprintf(buf, "auto (%s)\n", type);
1020         else
1021                 sprintf(buf, "%s\n", type);
1022
1023         return strlen(buf);
1024 }
1025
1026 static ssize_t set_port_type(struct device *dev,
1027                              struct device_attribute *attr,
1028                              const char *buf, size_t count)
1029 {
1030         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1031                                                    port_attr);
1032         struct mlx4_dev *mdev = info->dev;
1033         struct mlx4_priv *priv = mlx4_priv(mdev);
1034         enum mlx4_port_type types[MLX4_MAX_PORTS];
1035         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1036         static DEFINE_MUTEX(set_port_type_mutex);
1037         int i;
1038         int err = 0;
1039
1040         qlock(&set_port_type_mutex);
1041
1042         if (!strcmp(buf, "ib\n"))
1043                 info->tmp_type = MLX4_PORT_TYPE_IB;
1044         else if (!strcmp(buf, "eth\n"))
1045                 info->tmp_type = MLX4_PORT_TYPE_ETH;
1046         else if (!strcmp(buf, "auto\n"))
1047                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
1048         else {
1049                 mlx4_err(mdev, "%s is not supported port type\n", buf);
1050                 err = -EINVAL;
1051                 goto err_out;
1052         }
1053
1054         mlx4_stop_sense(mdev);
1055         qlock(&priv->port_mutex);
1056         /* Possible type is always the one that was delivered */
1057         mdev->caps.possible_type[info->port] = info->tmp_type;
1058
1059         for (i = 0; i < mdev->caps.num_ports; i++) {
1060                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1061                                         mdev->caps.possible_type[i+1];
1062                 if (types[i] == MLX4_PORT_TYPE_AUTO)
1063                         types[i] = mdev->caps.port_type[i+1];
1064         }
1065
1066         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1067             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1068                 for (i = 1; i <= mdev->caps.num_ports; i++) {
1069                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1070                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1071                                 err = -EINVAL;
1072                         }
1073                 }
1074         }
1075         if (err) {
1076                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1077                 goto out;
1078         }
1079
1080         mlx4_do_sense_ports(mdev, new_types, types);
1081
1082         err = mlx4_check_port_params(mdev, new_types);
1083         if (err)
1084                 goto out;
1085
1086         /* We are about to apply the changes after the configuration
1087          * was verified, no need to remember the temporary types
1088          * any more */
1089         for (i = 0; i < mdev->caps.num_ports; i++)
1090                 priv->port[i + 1].tmp_type = 0;
1091
1092         err = mlx4_change_port_types(mdev, new_types);
1093
1094 out:
1095         mlx4_start_sense(mdev);
1096         qunlock(&priv->port_mutex);
1097 err_out:
1098         qunlock(&set_port_type_mutex);
1099
1100         return err ? err : count;
1101 }
1102
1103 enum ibta_mtu {
1104         IB_MTU_256  = 1,
1105         IB_MTU_512  = 2,
1106         IB_MTU_1024 = 3,
1107         IB_MTU_2048 = 4,
1108         IB_MTU_4096 = 5
1109 };
1110
1111 static inline int int_to_ibta_mtu(int mtu)
1112 {
1113         switch (mtu) {
1114         case 256:  return IB_MTU_256;
1115         case 512:  return IB_MTU_512;
1116         case 1024: return IB_MTU_1024;
1117         case 2048: return IB_MTU_2048;
1118         case 4096: return IB_MTU_4096;
1119         default: return -1;
1120         }
1121 }
1122
1123 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1124 {
1125         switch (mtu) {
1126         case IB_MTU_256:  return  256;
1127         case IB_MTU_512:  return  512;
1128         case IB_MTU_1024: return 1024;
1129         case IB_MTU_2048: return 2048;
1130         case IB_MTU_4096: return 4096;
1131         default: return -1;
1132         }
1133 }
1134
1135 static ssize_t show_port_ib_mtu(struct device *dev,
1136                              struct device_attribute *attr,
1137                              char *buf)
1138 {
1139         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1140                                                    port_mtu_attr);
1141         struct mlx4_dev *mdev = info->dev;
1142
1143         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1144                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1145
1146         sprintf(buf, "%d\n",
1147                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1148         return strlen(buf);
1149 }
1150
1151 static ssize_t set_port_ib_mtu(struct device *dev,
1152                              struct device_attribute *attr,
1153                              const char *buf, size_t count)
1154 {
1155         panic("Disabled");
1156 #if 0 // AKAROS_PORT
1157         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1158                                                    port_mtu_attr);
1159         struct mlx4_dev *mdev = info->dev;
1160         struct mlx4_priv *priv = mlx4_priv(mdev);
1161         int err, port, mtu, ibta_mtu = -1;
1162
1163         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1164                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1165                 return -EINVAL;
1166         }
1167
1168         err = kstrtoint(buf, 0, &mtu);
1169         if (!err)
1170                 ibta_mtu = int_to_ibta_mtu(mtu);
1171
1172         if (err || ibta_mtu < 0) {
1173                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1174                 return -EINVAL;
1175         }
1176
1177         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1178
1179         mlx4_stop_sense(mdev);
1180         qlock(&priv->port_mutex);
1181         mlx4_unregister_device(mdev);
1182         for (port = 1; port <= mdev->caps.num_ports; port++) {
1183                 mlx4_CLOSE_PORT(mdev, port);
1184                 err = mlx4_SET_PORT(mdev, port, -1);
1185                 if (err) {
1186                         mlx4_err(mdev, "Failed to set port %d, aborting\n",
1187                                  port);
1188                         goto err_set_port;
1189                 }
1190         }
1191         err = mlx4_register_device(mdev);
1192 err_set_port:
1193         qunlock(&priv->port_mutex);
1194         mlx4_start_sense(mdev);
1195         return err ? err : count;
1196 #endif
1197 }
1198
1199 int mlx4_bond(struct mlx4_dev *dev)
1200 {
1201         int ret = 0;
1202         struct mlx4_priv *priv = mlx4_priv(dev);
1203
1204         qlock(&priv->bond_mutex);
1205
1206         if (!mlx4_is_bonded(dev))
1207                 ret = mlx4_do_bond(dev, true);
1208         else
1209                 ret = 0;
1210
1211         qunlock(&priv->bond_mutex);
1212         if (ret)
1213                 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1214         else
1215                 mlx4_dbg(dev, "Device is bonded\n");
1216         return ret;
1217 }
1218 EXPORT_SYMBOL_GPL(mlx4_bond);
1219
1220 int mlx4_unbond(struct mlx4_dev *dev)
1221 {
1222         int ret = 0;
1223         struct mlx4_priv *priv = mlx4_priv(dev);
1224
1225         qlock(&priv->bond_mutex);
1226
1227         if (mlx4_is_bonded(dev))
1228                 ret = mlx4_do_bond(dev, false);
1229
1230         qunlock(&priv->bond_mutex);
1231         if (ret)
1232                 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1233         else
1234                 mlx4_dbg(dev, "Device is unbonded\n");
1235         return ret;
1236 }
1237 EXPORT_SYMBOL_GPL(mlx4_unbond);
1238
1239
1240 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1241 {
1242         uint8_t port1 = v2p->port1;
1243         uint8_t port2 = v2p->port2;
1244         struct mlx4_priv *priv = mlx4_priv(dev);
1245         int err;
1246
1247         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1248                 return -ENOTSUPP;
1249
1250         qlock(&priv->bond_mutex);
1251
1252         /* zero means keep current mapping for this port */
1253         if (port1 == 0)
1254                 port1 = priv->v2p.port1;
1255         if (port2 == 0)
1256                 port2 = priv->v2p.port2;
1257
1258         if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1259             (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1260             (port1 == 2 && port2 == 1)) {
1261                 /* besides boundary checks cross mapping makes
1262                  * no sense and therefore not allowed */
1263                 err = -EINVAL;
1264         } else if ((port1 == priv->v2p.port1) &&
1265                  (port2 == priv->v2p.port2)) {
1266                 err = 0;
1267         } else {
1268                 err = mlx4_virt2phy_port_map(dev, port1, port2);
1269                 if (!err) {
1270                         mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1271                                  port1, port2);
1272                         priv->v2p.port1 = port1;
1273                         priv->v2p.port2 = port2;
1274                 } else {
1275                         mlx4_err(dev, "Failed to change port mape: %d\n", err);
1276                 }
1277         }
1278
1279         qunlock(&priv->bond_mutex);
1280         return err;
1281 }
1282 EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1283
1284 static int mlx4_load_fw(struct mlx4_dev *dev)
1285 {
1286         struct mlx4_priv *priv = mlx4_priv(dev);
1287         int err;
1288
1289         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1290                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
1291         if (!priv->fw.fw_icm) {
1292                 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1293                 return -ENOMEM;
1294         }
1295
1296         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1297         if (err) {
1298                 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1299                 goto err_free;
1300         }
1301
1302         err = mlx4_RUN_FW(dev);
1303         if (err) {
1304                 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1305                 goto err_unmap_fa;
1306         }
1307
1308         return 0;
1309
1310 err_unmap_fa:
1311         mlx4_UNMAP_FA(dev);
1312
1313 err_free:
1314         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1315         return err;
1316 }
1317
1318 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, uint64_t cmpt_base,
1319                                 int cmpt_entry_sz)
1320 {
1321         struct mlx4_priv *priv = mlx4_priv(dev);
1322         int err;
1323         int num_eqs;
1324
1325         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1326                                   cmpt_base +
1327                                   ((uint64_t) (MLX4_CMPT_TYPE_QP *
1328                                                cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1329                                   cmpt_entry_sz, dev->caps.num_qps,
1330                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1331                                   0, 0);
1332         if (err)
1333                 goto err;
1334
1335         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1336                                   cmpt_base +
1337                                   ((uint64_t) (MLX4_CMPT_TYPE_SRQ *
1338                                                cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1339                                   cmpt_entry_sz, dev->caps.num_srqs,
1340                                   dev->caps.reserved_srqs, 0, 0);
1341         if (err)
1342                 goto err_qp;
1343
1344         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1345                                   cmpt_base +
1346                                   ((uint64_t) (MLX4_CMPT_TYPE_CQ *
1347                                                cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1348                                   cmpt_entry_sz, dev->caps.num_cqs,
1349                                   dev->caps.reserved_cqs, 0, 0);
1350         if (err)
1351                 goto err_srq;
1352
1353         num_eqs = dev->phys_caps.num_phys_eqs;
1354         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1355                                   cmpt_base +
1356                                   ((uint64_t) (MLX4_CMPT_TYPE_EQ *
1357                                                cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1358                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1359         if (err)
1360                 goto err_cq;
1361
1362         return 0;
1363
1364 err_cq:
1365         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1366
1367 err_srq:
1368         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1369
1370 err_qp:
1371         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1372
1373 err:
1374         return err;
1375 }
1376
1377 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1378                          struct mlx4_init_hca_param *init_hca,
1379                          uint64_t icm_size)
1380 {
1381         struct mlx4_priv *priv = mlx4_priv(dev);
1382         uint64_t aux_pages;
1383         int num_eqs;
1384         int err;
1385
1386         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1387         if (err) {
1388                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1389                 return err;
1390         }
1391
1392         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1393                  (unsigned long long) icm_size >> 10,
1394                  (unsigned long long) aux_pages << 2);
1395
1396         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1397                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1398         if (!priv->fw.aux_icm) {
1399                 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1400                 return -ENOMEM;
1401         }
1402
1403         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1404         if (err) {
1405                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1406                 goto err_free_aux;
1407         }
1408
1409         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1410         if (err) {
1411                 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1412                 goto err_unmap_aux;
1413         }
1414
1415
1416         num_eqs = dev->phys_caps.num_phys_eqs;
1417         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1418                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1419                                   num_eqs, num_eqs, 0, 0);
1420         if (err) {
1421                 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1422                 goto err_unmap_cmpt;
1423         }
1424
1425         /*
1426          * Reserved MTT entries must be aligned up to a cacheline
1427          * boundary, since the FW will write to them, while the driver
1428          * writes to all other MTT entries. (The variable
1429          * dev->caps.mtt_entry_sz below is really the MTT segment
1430          * size, not the raw entry size)
1431          */
1432         dev->caps.reserved_mtts =
1433                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1434                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1435
1436         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1437                                   init_hca->mtt_base,
1438                                   dev->caps.mtt_entry_sz,
1439                                   dev->caps.num_mtts,
1440                                   dev->caps.reserved_mtts, 1, 0);
1441         if (err) {
1442                 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1443                 goto err_unmap_eq;
1444         }
1445
1446         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1447                                   init_hca->dmpt_base,
1448                                   dev_cap->dmpt_entry_sz,
1449                                   dev->caps.num_mpts,
1450                                   dev->caps.reserved_mrws, 1, 1);
1451         if (err) {
1452                 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1453                 goto err_unmap_mtt;
1454         }
1455
1456         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1457                                   init_hca->qpc_base,
1458                                   dev_cap->qpc_entry_sz,
1459                                   dev->caps.num_qps,
1460                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1461                                   0, 0);
1462         if (err) {
1463                 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1464                 goto err_unmap_dmpt;
1465         }
1466
1467         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1468                                   init_hca->auxc_base,
1469                                   dev_cap->aux_entry_sz,
1470                                   dev->caps.num_qps,
1471                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1472                                   0, 0);
1473         if (err) {
1474                 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1475                 goto err_unmap_qp;
1476         }
1477
1478         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1479                                   init_hca->altc_base,
1480                                   dev_cap->altc_entry_sz,
1481                                   dev->caps.num_qps,
1482                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1483                                   0, 0);
1484         if (err) {
1485                 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1486                 goto err_unmap_auxc;
1487         }
1488
1489         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1490                                   init_hca->rdmarc_base,
1491                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1492                                   dev->caps.num_qps,
1493                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1494                                   0, 0);
1495         if (err) {
1496                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1497                 goto err_unmap_altc;
1498         }
1499
1500         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1501                                   init_hca->cqc_base,
1502                                   dev_cap->cqc_entry_sz,
1503                                   dev->caps.num_cqs,
1504                                   dev->caps.reserved_cqs, 0, 0);
1505         if (err) {
1506                 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1507                 goto err_unmap_rdmarc;
1508         }
1509
1510         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1511                                   init_hca->srqc_base,
1512                                   dev_cap->srq_entry_sz,
1513                                   dev->caps.num_srqs,
1514                                   dev->caps.reserved_srqs, 0, 0);
1515         if (err) {
1516                 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1517                 goto err_unmap_cq;
1518         }
1519
1520         /*
1521          * For flow steering device managed mode it is required to use
1522          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1523          * required, but for simplicity just map the whole multicast
1524          * group table now.  The table isn't very big and it's a lot
1525          * easier than trying to track ref counts.
1526          */
1527         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1528                                   init_hca->mc_base,
1529                                   mlx4_get_mgm_entry_size(dev),
1530                                   dev->caps.num_mgms + dev->caps.num_amgms,
1531                                   dev->caps.num_mgms + dev->caps.num_amgms,
1532                                   0, 0);
1533         if (err) {
1534                 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1535                 goto err_unmap_srq;
1536         }
1537
1538         return 0;
1539
1540 err_unmap_srq:
1541         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1542
1543 err_unmap_cq:
1544         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1545
1546 err_unmap_rdmarc:
1547         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1548
1549 err_unmap_altc:
1550         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1551
1552 err_unmap_auxc:
1553         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1554
1555 err_unmap_qp:
1556         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1557
1558 err_unmap_dmpt:
1559         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1560
1561 err_unmap_mtt:
1562         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1563
1564 err_unmap_eq:
1565         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1566
1567 err_unmap_cmpt:
1568         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1569         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1570         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1571         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1572
1573 err_unmap_aux:
1574         mlx4_UNMAP_ICM_AUX(dev);
1575
1576 err_free_aux:
1577         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1578
1579         return err;
1580 }
1581
1582 static void mlx4_free_icms(struct mlx4_dev *dev)
1583 {
1584         struct mlx4_priv *priv = mlx4_priv(dev);
1585
1586         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1587         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1588         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1589         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1590         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1591         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1592         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1593         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1594         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1595         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1596         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1597         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1598         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1599         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1600
1601         mlx4_UNMAP_ICM_AUX(dev);
1602         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1603 }
1604
1605 static void mlx4_slave_exit(struct mlx4_dev *dev)
1606 {
1607         struct mlx4_priv *priv = mlx4_priv(dev);
1608
1609         qlock(&priv->cmd.slave_cmd_mutex);
1610         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1611                           MLX4_COMM_TIME))
1612                 mlx4_warn(dev, "Failed to close slave function\n");
1613         qunlock(&priv->cmd.slave_cmd_mutex);
1614 }
1615
1616 static int map_bf_area(struct mlx4_dev *dev)
1617 {
1618         panic("Disabled");
1619 #if 0 // AKAROS_PORT
1620         struct mlx4_priv *priv = mlx4_priv(dev);
1621         resource_size_t bf_start;
1622         resource_size_t bf_len;
1623         int err = 0;
1624
1625         if (!dev->caps.bf_reg_size)
1626                 return -ENXIO;
1627
1628         bf_start = pci_resource_start(dev->persist->pdev, 2) +
1629                         (dev->caps.num_uars << PAGE_SHIFT);
1630         bf_len = pci_resource_len(dev->persist->pdev, 2) -
1631                         (dev->caps.num_uars << PAGE_SHIFT);
1632         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1633         if (!priv->bf_mapping)
1634                 err = -ENOMEM;
1635
1636         return err;
1637 #endif
1638 }
1639
1640 static void unmap_bf_area(struct mlx4_dev *dev)
1641 {
1642         panic("Disabled");
1643 #if 0 // AKAROS_PORT
1644         if (mlx4_priv(dev)->bf_mapping)
1645                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1646 #endif
1647 }
1648
1649 uint64_t mlx4_read_clock(struct mlx4_dev *dev)
1650 {
1651         uint32_t clockhi, clocklo, clockhi1;
1652         uint64_t cycles;
1653         int i;
1654         struct mlx4_priv *priv = mlx4_priv(dev);
1655
1656         for (i = 0; i < 10; i++) {
1657                 clockhi = swab32(read32(priv->clock_mapping));
1658                 clocklo = swab32(read32(priv->clock_mapping + 4));
1659                 clockhi1 = swab32(read32(priv->clock_mapping));
1660                 if (clockhi == clockhi1)
1661                         break;
1662         }
1663
1664         cycles = (uint64_t) clockhi << 32 | (uint64_t) clocklo;
1665
1666         return cycles;
1667 }
1668 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1669
1670
1671 static int map_internal_clock(struct mlx4_dev *dev)
1672 {
1673         struct mlx4_priv *priv = mlx4_priv(dev);
1674
1675         priv->clock_mapping =
1676                 ioremap(pci_resource_start(dev->persist->pdev,
1677                                            priv->fw.clock_bar) +
1678                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1679
1680         if (!priv->clock_mapping)
1681                 return -ENOMEM;
1682
1683         return 0;
1684 }
1685
1686 static void unmap_internal_clock(struct mlx4_dev *dev)
1687 {
1688         struct mlx4_priv *priv = mlx4_priv(dev);
1689
1690         if (priv->clock_mapping)
1691                 iounmap(priv->clock_mapping);
1692 }
1693
1694 static void mlx4_close_hca(struct mlx4_dev *dev)
1695 {
1696         unmap_internal_clock(dev);
1697         unmap_bf_area(dev);
1698         if (mlx4_is_slave(dev))
1699                 mlx4_slave_exit(dev);
1700         else {
1701                 mlx4_CLOSE_HCA(dev, 0);
1702                 mlx4_free_icms(dev);
1703         }
1704 }
1705
1706 static void mlx4_close_fw(struct mlx4_dev *dev)
1707 {
1708         if (!mlx4_is_slave(dev)) {
1709                 mlx4_UNMAP_FA(dev);
1710                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1711         }
1712 }
1713
1714 static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1715 {
1716         panic("Disabled");
1717 #if 0 // AKAROS_PORT
1718 #define COMM_CHAN_OFFLINE_OFFSET 0x09
1719
1720         uint32_t comm_flags;
1721         uint32_t offline_bit;
1722         unsigned long end;
1723         struct mlx4_priv *priv = mlx4_priv(dev);
1724
1725         end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1726         while (time_before(jiffies, end)) {
1727                 comm_flags = swab32(read32((__iomem char *)priv->mfunc.comm +
1728                                            MLX4_COMM_CHAN_FLAGS));
1729                 offline_bit = (comm_flags &
1730                                (uint32_t)(1 << COMM_CHAN_OFFLINE_OFFSET));
1731                 if (!offline_bit)
1732                         return 0;
1733                 /* There are cases as part of AER/Reset flow that PF needs
1734                  * around 100 msec to load. We therefore sleep for 100 msec
1735                  * to allow other tasks to make use of that CPU during this
1736                  * time interval.
1737                  */
1738                 kthread_usleep(1000 * 100);
1739         }
1740         mlx4_err(dev, "Communication channel is offline.\n");
1741         return -EIO;
1742 #endif
1743 }
1744
1745 static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1746 {
1747 #define COMM_CHAN_RST_OFFSET 0x1e
1748
1749         struct mlx4_priv *priv = mlx4_priv(dev);
1750         uint32_t comm_rst;
1751         uint32_t comm_caps;
1752
1753         comm_caps = swab32(read32((__iomem char *)priv->mfunc.comm +
1754                                   MLX4_COMM_CHAN_CAPS));
1755         comm_rst = (comm_caps & (uint32_t)(1 << COMM_CHAN_RST_OFFSET));
1756
1757         if (comm_rst)
1758                 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1759 }
1760
1761 static int mlx4_init_slave(struct mlx4_dev *dev)
1762 {
1763         struct mlx4_priv *priv = mlx4_priv(dev);
1764         uint64_t dma = (uint64_t) priv->mfunc.vhcr_dma;
1765         int ret_from_reset = 0;
1766         uint32_t slave_read;
1767         uint32_t cmd_channel_ver;
1768
1769         if (atomic_read(&pf_loading)) {
1770                 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1771                 return -EPROBE_DEFER;
1772         }
1773
1774         qlock(&priv->cmd.slave_cmd_mutex);
1775         priv->cmd.max_cmds = 1;
1776         if (mlx4_comm_check_offline(dev)) {
1777                 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1778                 goto err_offline;
1779         }
1780
1781         mlx4_reset_vf_support(dev);
1782         mlx4_warn(dev, "Sending reset\n");
1783         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1784                                        MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
1785         /* if we are in the middle of flr the slave will try
1786          * NUM_OF_RESET_RETRIES times before leaving.*/
1787         if (ret_from_reset) {
1788                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1789                         mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1790                         qunlock(&priv->cmd.slave_cmd_mutex);
1791                         return -EPROBE_DEFER;
1792                 } else
1793                         goto err;
1794         }
1795
1796         /* check the driver version - the slave I/F revision
1797          * must match the master's */
1798         slave_read = swab32(read32(&priv->mfunc.comm->slave_read));
1799         cmd_channel_ver = mlx4_comm_get_version();
1800
1801         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1802                 MLX4_COMM_GET_IF_REV(slave_read)) {
1803                 mlx4_err(dev, "slave driver version is not supported by the master\n");
1804                 goto err;
1805         }
1806
1807         mlx4_warn(dev, "Sending vhcr0\n");
1808         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1809                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1810                 goto err;
1811         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1812                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1813                 goto err;
1814         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1815                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1816                 goto err;
1817         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1818                           MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1819                 goto err;
1820
1821         qunlock(&priv->cmd.slave_cmd_mutex);
1822         return 0;
1823
1824 err:
1825         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
1826 err_offline:
1827         qunlock(&priv->cmd.slave_cmd_mutex);
1828         return -EIO;
1829 }
1830
1831 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1832 {
1833         int i;
1834
1835         for (i = 1; i <= dev->caps.num_ports; i++) {
1836                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1837                         dev->caps.gid_table_len[i] =
1838                                 mlx4_get_slave_num_gids(dev, 0, i);
1839                 else
1840                         dev->caps.gid_table_len[i] = 1;
1841                 dev->caps.pkey_table_len[i] =
1842                         dev->phys_caps.pkey_phys_table_len[i] - 1;
1843         }
1844 }
1845
1846 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1847 {
1848         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1849
1850         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1851               i++) {
1852                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1853                         break;
1854         }
1855
1856         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1857 }
1858
1859 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
1860 {
1861         switch (dmfs_high_steer_mode) {
1862         case MLX4_STEERING_DMFS_A0_DEFAULT:
1863                 return "default performance";
1864
1865         case MLX4_STEERING_DMFS_A0_DYNAMIC:
1866                 return "dynamic hybrid mode";
1867
1868         case MLX4_STEERING_DMFS_A0_STATIC:
1869                 return "performance optimized for limited rule configuration (static)";
1870
1871         case MLX4_STEERING_DMFS_A0_DISABLE:
1872                 return "disabled performance optimized steering";
1873
1874         case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
1875                 return "performance optimized steering not supported";
1876
1877         default:
1878                 return "Unrecognized mode";
1879         }
1880 }
1881
1882 #define MLX4_DMFS_A0_STEERING                   (1UL << 2)
1883
1884 static void choose_steering_mode(struct mlx4_dev *dev,
1885                                  struct mlx4_dev_cap *dev_cap)
1886 {
1887         if (mlx4_log_num_mgm_entry_size <= 0) {
1888                 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
1889                         if (dev->caps.dmfs_high_steer_mode ==
1890                             MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1891                                 mlx4_err(dev, "DMFS high rate mode not supported\n");
1892                         else
1893                                 dev->caps.dmfs_high_steer_mode =
1894                                         MLX4_STEERING_DMFS_A0_STATIC;
1895                 }
1896         }
1897
1898         if (mlx4_log_num_mgm_entry_size <= 0 &&
1899             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1900             (!mlx4_is_mfunc(dev) ||
1901              (dev_cap->fs_max_num_qp_per_entry >=
1902              (dev->persist->num_vfs + 1))) &&
1903             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1904                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1905                 dev->oper_log_mgm_entry_size =
1906                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1907                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1908                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1909                 dev->caps.fs_log_max_ucast_qp_range_size =
1910                         dev_cap->fs_log_max_ucast_qp_range_size;
1911         } else {
1912                 if (dev->caps.dmfs_high_steer_mode !=
1913                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1914                         dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
1915                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1916                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1917                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1918                 else {
1919                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1920
1921                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1922                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1923                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
1924                 }
1925                 dev->oper_log_mgm_entry_size =
1926                         mlx4_log_num_mgm_entry_size > 0 ?
1927                         mlx4_log_num_mgm_entry_size :
1928                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1929                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1930         }
1931         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
1932                  mlx4_steering_mode_str(dev->caps.steering_mode),
1933                  dev->oper_log_mgm_entry_size,
1934                  mlx4_log_num_mgm_entry_size);
1935 }
1936
1937 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1938                                        struct mlx4_dev_cap *dev_cap)
1939 {
1940         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1941             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1942                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1943         else
1944                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1945
1946         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
1947                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1948 }
1949
1950 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
1951 {
1952         int i;
1953         struct mlx4_port_cap port_cap;
1954
1955         if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1956                 return -EINVAL;
1957
1958         for (i = 1; i <= dev->caps.num_ports; i++) {
1959                 if (mlx4_dev_port(dev, i, &port_cap)) {
1960                         mlx4_err(dev,
1961                                  "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
1962                 } else if ((dev->caps.dmfs_high_steer_mode !=
1963                             MLX4_STEERING_DMFS_A0_DEFAULT) &&
1964                            (port_cap.dmfs_optimized_state ==
1965                             !!(dev->caps.dmfs_high_steer_mode ==
1966                             MLX4_STEERING_DMFS_A0_DISABLE))) {
1967                         mlx4_err(dev,
1968                                  "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
1969                                  dmfs_high_rate_steering_mode_str(
1970                                         dev->caps.dmfs_high_steer_mode),
1971                                  (port_cap.dmfs_optimized_state ?
1972                                         "enabled" : "disabled"));
1973                 }
1974         }
1975
1976         return 0;
1977 }
1978
1979 static int mlx4_init_fw(struct mlx4_dev *dev)
1980 {
1981         struct mlx4_mod_stat_cfg   mlx4_cfg;
1982         int err = 0;
1983
1984         if (!mlx4_is_slave(dev)) {
1985                 err = mlx4_QUERY_FW(dev);
1986                 if (err) {
1987                         if (err == -EACCES)
1988                                 mlx4_info(dev, "non-primary physical function, skipping\n");
1989                         else
1990                                 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
1991                         return err;
1992                 }
1993
1994                 err = mlx4_load_fw(dev);
1995                 if (err) {
1996                         mlx4_err(dev, "Failed to start FW, aborting\n");
1997                         return err;
1998                 }
1999
2000                 mlx4_cfg.log_pg_sz_m = 1;
2001                 mlx4_cfg.log_pg_sz = 0;
2002                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2003                 if (err)
2004                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2005         }
2006
2007         return err;
2008 }
2009
2010 static int mlx4_init_hca(struct mlx4_dev *dev)
2011 {
2012         struct mlx4_priv          *priv = mlx4_priv(dev);
2013         struct mlx4_adapter        adapter;
2014         struct mlx4_dev_cap        dev_cap;
2015         struct mlx4_profile        profile;
2016         struct mlx4_init_hca_param init_hca;
2017         uint64_t icm_size;
2018         struct mlx4_config_dev_params params;
2019         int err;
2020
2021         if (!mlx4_is_slave(dev)) {
2022                 err = mlx4_dev_cap(dev, &dev_cap);
2023                 if (err) {
2024                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2025                         return err;
2026                 }
2027
2028                 choose_steering_mode(dev, &dev_cap);
2029                 choose_tunnel_offload_mode(dev, &dev_cap);
2030
2031                 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2032                     mlx4_is_master(dev))
2033                         dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2034
2035                 err = mlx4_get_phys_port_id(dev);
2036                 if (err)
2037                         mlx4_err(dev, "Fail to get physical port id\n");
2038
2039                 if (mlx4_is_master(dev))
2040                         mlx4_parav_master_pf_caps(dev);
2041
2042                 if (mlx4_low_memory_profile()) {
2043                         mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2044                         profile = low_mem_profile;
2045                 } else {
2046                         profile = default_profile;
2047                 }
2048                 if (dev->caps.steering_mode ==
2049                     MLX4_STEERING_MODE_DEVICE_MANAGED)
2050                         profile.num_mcg = MLX4_FS_NUM_MCG;
2051
2052                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2053                                              &init_hca);
2054                 if ((long long) icm_size < 0) {
2055                         err = icm_size;
2056                         return err;
2057                 }
2058
2059                 dev->caps.max_fmr_maps = (1 << (32 - LOG2_UP(dev->caps.num_mpts))) - 1;
2060
2061                 init_hca.log_uar_sz = LOG2_UP(dev->caps.num_uars);
2062                 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2063                 init_hca.mw_enabled = 0;
2064                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2065                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2066                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2067
2068                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2069                 if (err)
2070                         return err;
2071
2072                 err = mlx4_INIT_HCA(dev, &init_hca);
2073                 if (err) {
2074                         mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2075                         goto err_free_icm;
2076                 }
2077
2078                 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2079                         err = mlx4_query_func(dev, &dev_cap);
2080                         if (err < 0) {
2081                                 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2082                                 goto err_close;
2083                         } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2084                                 dev->caps.num_eqs = dev_cap.max_eqs;
2085                                 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2086                                 dev->caps.reserved_uars = dev_cap.reserved_uars;
2087                         }
2088                 }
2089
2090                 /*
2091                  * If TS is supported by FW
2092                  * read HCA frequency by QUERY_HCA command
2093                  */
2094                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2095                         memset(&init_hca, 0, sizeof(init_hca));
2096                         err = mlx4_QUERY_HCA(dev, &init_hca);
2097                         if (err) {
2098                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2099                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2100                         } else {
2101                                 dev->caps.hca_core_clock =
2102                                         init_hca.hca_core_clock;
2103                         }
2104
2105                         /* In case we got HCA frequency 0 - disable timestamping
2106                          * to avoid dividing by zero
2107                          */
2108                         if (!dev->caps.hca_core_clock) {
2109                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2110                                 mlx4_err(dev,
2111                                          "HCA frequency is 0 - timestamping is not supported\n");
2112                         } else if (map_internal_clock(dev)) {
2113                                 /*
2114                                  * Map internal clock,
2115                                  * in case of failure disable timestamping
2116                                  */
2117                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2118                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2119                         }
2120                 }
2121
2122                 if (dev->caps.dmfs_high_steer_mode !=
2123                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2124                         if (mlx4_validate_optimized_steering(dev))
2125                                 mlx4_warn(dev, "Optimized steering validation failed\n");
2126
2127                         if (dev->caps.dmfs_high_steer_mode ==
2128                             MLX4_STEERING_DMFS_A0_DISABLE) {
2129                                 dev->caps.dmfs_high_rate_qpn_base =
2130                                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2131                                 dev->caps.dmfs_high_rate_qpn_range =
2132                                         MLX4_A0_STEERING_TABLE_SIZE;
2133                         }
2134
2135                         mlx4_dbg(dev, "DMFS high rate steer mode is: %s\n",
2136                                  dmfs_high_rate_steering_mode_str(
2137                                         dev->caps.dmfs_high_steer_mode));
2138                 }
2139         } else {
2140                 err = mlx4_init_slave(dev);
2141                 if (err) {
2142                         if (err != -EPROBE_DEFER)
2143                                 mlx4_err(dev, "Failed to initialize slave\n");
2144                         return err;
2145                 }
2146
2147                 err = mlx4_slave_cap(dev);
2148                 if (err) {
2149                         mlx4_err(dev, "Failed to obtain slave caps\n");
2150                         goto err_close;
2151                 }
2152         }
2153
2154 #if 0 // AKAROS_PORT
2155         if (map_bf_area(dev))
2156                 mlx4_dbg(dev, "Failed to map blue flame area\n");
2157 #endif
2158
2159         /*Only the master set the ports, all the rest got it from it.*/
2160         if (!mlx4_is_slave(dev))
2161                 mlx4_set_port_mask(dev);
2162
2163         err = mlx4_QUERY_ADAPTER(dev, &adapter);
2164         if (err) {
2165                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2166                 goto unmap_bf;
2167         }
2168
2169         /* Query CONFIG_DEV parameters */
2170         err = mlx4_config_dev_retrieval(dev, &params);
2171         if (err && err != -ENOTSUPP) {
2172                 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2173         } else if (!err) {
2174                 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2175                 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2176         }
2177         priv->eq_table.inta_pin = adapter.inta_pin;
2178         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
2179
2180         return 0;
2181
2182 unmap_bf:
2183         unmap_internal_clock(dev);
2184         unmap_bf_area(dev);
2185
2186         if (mlx4_is_slave(dev)) {
2187                 kfree(dev->caps.qp0_qkey);
2188                 kfree(dev->caps.qp0_tunnel);
2189                 kfree(dev->caps.qp0_proxy);
2190                 kfree(dev->caps.qp1_tunnel);
2191                 kfree(dev->caps.qp1_proxy);
2192         }
2193
2194 err_close:
2195         if (mlx4_is_slave(dev))
2196                 mlx4_slave_exit(dev);
2197         else
2198                 mlx4_CLOSE_HCA(dev, 0);
2199
2200 err_free_icm:
2201         if (!mlx4_is_slave(dev))
2202                 mlx4_free_icms(dev);
2203
2204         return err;
2205 }
2206
2207 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2208 {
2209         struct mlx4_priv *priv = mlx4_priv(dev);
2210         int nent;
2211
2212         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2213                 return -ENOENT;
2214
2215         nent = dev->caps.max_counters;
2216         return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
2217 }
2218
2219 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2220 {
2221         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2222 }
2223
2224 int __mlx4_counter_alloc(struct mlx4_dev *dev, uint32_t *idx)
2225 {
2226         struct mlx4_priv *priv = mlx4_priv(dev);
2227
2228         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2229                 return -ENOENT;
2230
2231         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2232         if (*idx == -1)
2233                 return -ENOMEM;
2234
2235         return 0;
2236 }
2237
2238 int mlx4_counter_alloc(struct mlx4_dev *dev, uint32_t *idx)
2239 {
2240         uint64_t out_param;
2241         int err;
2242
2243         if (mlx4_is_mfunc(dev)) {
2244                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2245                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2246                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2247                 if (!err)
2248                         *idx = get_param_l(&out_param);
2249
2250                 return err;
2251         }
2252         return __mlx4_counter_alloc(dev, idx);
2253 }
2254 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2255
2256 void __mlx4_counter_free(struct mlx4_dev *dev, uint32_t idx)
2257 {
2258         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2259         return;
2260 }
2261
2262 void mlx4_counter_free(struct mlx4_dev *dev, uint32_t idx)
2263 {
2264         uint64_t in_param = 0;
2265
2266         if (mlx4_is_mfunc(dev)) {
2267                 set_param_l(&in_param, idx);
2268                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2269                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2270                          MLX4_CMD_WRAPPED);
2271                 return;
2272         }
2273         __mlx4_counter_free(dev, idx);
2274 }
2275 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2276
2277 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2278 {
2279         struct mlx4_priv *priv = mlx4_priv(dev);
2280
2281         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2282 }
2283 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2284
2285 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2286 {
2287         struct mlx4_priv *priv = mlx4_priv(dev);
2288
2289         return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2290 }
2291 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2292
2293 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2294 {
2295         struct mlx4_priv *priv = mlx4_priv(dev);
2296         __be64 guid;
2297
2298         /* hw GUID */
2299         if (entry == 0)
2300                 return;
2301
2302         get_random_bytes((char *)&guid, sizeof(guid));
2303         guid &= ~(cpu_to_be64(1ULL << 56));
2304         guid |= cpu_to_be64(1ULL << 57);
2305         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2306 }
2307
2308 static int mlx4_setup_hca(struct mlx4_dev *dev)
2309 {
2310         struct mlx4_priv *priv = mlx4_priv(dev);
2311         int err;
2312         int port;
2313         __be32 ib_port_default_caps;
2314
2315         err = mlx4_init_uar_table(dev);
2316         if (err) {
2317                 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2318                  return err;
2319         }
2320
2321         err = mlx4_uar_alloc(dev, &priv->driver_uar);
2322         if (err) {
2323                 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2324                 goto err_uar_table_free;
2325         }
2326
2327         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2328         if (!priv->kar) {
2329                 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2330                 err = -ENOMEM;
2331                 goto err_uar_free;
2332         }
2333
2334         err = mlx4_init_pd_table(dev);
2335         if (err) {
2336                 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2337                 goto err_kar_unmap;
2338         }
2339
2340         err = mlx4_init_xrcd_table(dev);
2341         if (err) {
2342                 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2343                 goto err_pd_table_free;
2344         }
2345
2346         err = mlx4_init_mr_table(dev);
2347         if (err) {
2348                 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2349                 goto err_xrcd_table_free;
2350         }
2351
2352         if (!mlx4_is_slave(dev)) {
2353                 err = mlx4_init_mcg_table(dev);
2354                 if (err) {
2355                         mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2356                         goto err_mr_table_free;
2357                 }
2358                 err = mlx4_config_mad_demux(dev);
2359                 if (err) {
2360                         mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2361                         goto err_mcg_table_free;
2362                 }
2363         }
2364
2365         err = mlx4_init_eq_table(dev);
2366         if (err) {
2367                 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2368                 goto err_mcg_table_free;
2369         }
2370
2371         err = mlx4_cmd_use_events(dev);
2372         if (err) {
2373                 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2374                 goto err_eq_table_free;
2375         }
2376
2377         err = mlx4_NOP(dev);
2378         if (err) {
2379                 if (dev->flags & MLX4_FLAG_MSI_X) {
2380                         mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2381                                   priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2382                         mlx4_warn(dev, "Trying again without MSI-X\n");
2383                 } else {
2384                         mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2385                                  priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2386                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2387                 }
2388
2389                 goto err_cmd_poll;
2390         }
2391
2392         mlx4_dbg(dev, "NOP command IRQ test passed\n");
2393
2394         err = mlx4_init_cq_table(dev);
2395         if (err) {
2396                 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2397                 goto err_cmd_poll;
2398         }
2399
2400         err = mlx4_init_srq_table(dev);
2401         if (err) {
2402                 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2403                 goto err_cq_table_free;
2404         }
2405
2406         err = mlx4_init_qp_table(dev);
2407         if (err) {
2408                 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2409                 goto err_srq_table_free;
2410         }
2411
2412         err = mlx4_init_counters_table(dev);
2413         if (err && err != -ENOENT) {
2414                 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2415                 goto err_qp_table_free;
2416         }
2417
2418         if (!mlx4_is_slave(dev)) {
2419                 for (port = 1; port <= dev->caps.num_ports; port++) {
2420                         ib_port_default_caps = 0;
2421                         err = mlx4_get_port_ib_caps(dev, port,
2422                                                     &ib_port_default_caps);
2423                         if (err)
2424                                 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2425                                           port, err);
2426                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2427
2428                         /* initialize per-slave default ib port capabilities */
2429                         if (mlx4_is_master(dev)) {
2430                                 int i;
2431                                 for (i = 0; i < dev->num_slaves; i++) {
2432                                         if (i == mlx4_master_func_num(dev))
2433                                                 continue;
2434                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2435                                                 ib_port_default_caps;
2436                                 }
2437                         }
2438
2439                         if (mlx4_is_mfunc(dev))
2440                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2441                         else
2442                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2443
2444                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2445                                             dev->caps.pkey_table_len[port] : -1);
2446                         if (err) {
2447                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
2448                                          port);
2449                                 goto err_counters_table_free;
2450                         }
2451                 }
2452         }
2453
2454         return 0;
2455
2456 err_counters_table_free:
2457         mlx4_cleanup_counters_table(dev);
2458
2459 err_qp_table_free:
2460         mlx4_cleanup_qp_table(dev);
2461
2462 err_srq_table_free:
2463         mlx4_cleanup_srq_table(dev);
2464
2465 err_cq_table_free:
2466         mlx4_cleanup_cq_table(dev);
2467
2468 err_cmd_poll:
2469         mlx4_cmd_use_polling(dev);
2470
2471 err_eq_table_free:
2472         mlx4_cleanup_eq_table(dev);
2473
2474 err_mcg_table_free:
2475         if (!mlx4_is_slave(dev))
2476                 mlx4_cleanup_mcg_table(dev);
2477
2478 err_mr_table_free:
2479         mlx4_cleanup_mr_table(dev);
2480
2481 err_xrcd_table_free:
2482         mlx4_cleanup_xrcd_table(dev);
2483
2484 err_pd_table_free:
2485         mlx4_cleanup_pd_table(dev);
2486
2487 err_kar_unmap:
2488         iounmap(priv->kar);
2489
2490 err_uar_free:
2491         mlx4_uar_free(dev, &priv->driver_uar);
2492
2493 err_uar_table_free:
2494         mlx4_cleanup_uar_table(dev);
2495         return err;
2496 }
2497
2498 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2499 {
2500 #if 0 // AKAROS_PORT
2501         struct mlx4_priv *priv = mlx4_priv(dev);
2502         struct msix_entry *entries;
2503         int i;
2504
2505         if (msi_x) {
2506                 int nreq = dev->caps.num_ports * num_online_cpus() + MSIX_LEGACY_SZ;
2507
2508                 nreq = MIN_T(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2509                              nreq);
2510
2511                 entries = kzmalloc((nreq) * (sizeof *entries), KMALLOC_WAIT);
2512                 if (!entries)
2513                         goto no_msi;
2514
2515                 for (i = 0; i < nreq; ++i)
2516                         entries[i].entry = i;
2517
2518                 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2519                                              nreq);
2520
2521                 if (nreq < 0) {
2522                         kfree(entries);
2523                         goto no_msi;
2524                 } else if (nreq < MSIX_LEGACY_SZ +
2525                            dev->caps.num_ports * MIN_MSIX_P_PORT) {
2526                         /*Working in legacy mode , all EQ's shared*/
2527                         dev->caps.comp_pool           = 0;
2528                         dev->caps.num_comp_vectors = nreq - 1;
2529                 } else {
2530                         dev->caps.comp_pool           = nreq - MSIX_LEGACY_SZ;
2531                         dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2532                 }
2533                 for (i = 0; i < nreq; ++i)
2534                         priv->eq_table.eq[i].irq = entries[i].vector;
2535
2536                 dev->flags |= MLX4_FLAG_MSI_X;
2537
2538                 kfree(entries);
2539                 return;
2540         }
2541
2542 no_msi:
2543         dev->caps.num_comp_vectors = 1;
2544         dev->caps.comp_pool        = 0;
2545
2546         for (i = 0; i < 2; ++i)
2547                 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2548 #endif
2549 }
2550
2551 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2552 {
2553         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2554         int err = 0;
2555
2556         info->dev = dev;
2557         info->port = port;
2558         if (!mlx4_is_slave(dev)) {
2559                 mlx4_init_mac_table(dev, &info->mac_table);
2560                 mlx4_init_vlan_table(dev, &info->vlan_table);
2561                 mlx4_init_roce_gid_table(dev, &info->gid_table);
2562                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2563         }
2564
2565         sprintf(info->dev_name, "mlx4_port%d", port);
2566 #if 0 // AKAROS_PORT
2567         info->port_attr.attr.name = info->dev_name;
2568         if (mlx4_is_mfunc(dev))
2569                 info->port_attr.attr.mode = S_IRUGO;
2570         else {
2571                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2572                 info->port_attr.store     = set_port_type;
2573         }
2574         info->port_attr.show      = show_port_type;
2575         sysfs_attr_init(&info->port_attr.attr);
2576
2577         err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2578         if (err) {
2579                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2580                 info->port = -1;
2581         }
2582 #endif
2583
2584         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2585 #if 0 // AKAROS_PORT
2586         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2587         if (mlx4_is_mfunc(dev))
2588                 info->port_mtu_attr.attr.mode = S_IRUGO;
2589         else {
2590                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2591                 info->port_mtu_attr.store     = set_port_ib_mtu;
2592         }
2593         info->port_mtu_attr.show      = show_port_ib_mtu;
2594         sysfs_attr_init(&info->port_mtu_attr.attr);
2595
2596         err = device_create_file(&dev->persist->pdev->dev,
2597                                  &info->port_mtu_attr);
2598         if (err) {
2599                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2600                 device_remove_file(&info->dev->persist->pdev->dev,
2601                                    &info->port_attr);
2602                 info->port = -1;
2603         }
2604 #endif
2605
2606         return err;
2607 }
2608
2609 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2610 {
2611         panic("Disabled");
2612 #if 0 // AKAROS_PORT
2613         if (info->port < 0)
2614                 return;
2615
2616         device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2617         device_remove_file(&info->dev->persist->pdev->dev,
2618                            &info->port_mtu_attr);
2619 #endif
2620 }
2621
2622 static int mlx4_init_steering(struct mlx4_dev *dev)
2623 {
2624         struct mlx4_priv *priv = mlx4_priv(dev);
2625         int num_entries = dev->caps.num_ports;
2626         int i, j;
2627
2628         priv->steer = kzmalloc(sizeof(struct mlx4_steer) * num_entries,
2629                                KMALLOC_WAIT);
2630         if (!priv->steer)
2631                 return -ENOMEM;
2632
2633         for (i = 0; i < num_entries; i++)
2634                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2635                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2636                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2637                 }
2638         return 0;
2639 }
2640
2641 static void mlx4_clear_steering(struct mlx4_dev *dev)
2642 {
2643         struct mlx4_priv *priv = mlx4_priv(dev);
2644         struct mlx4_steer_index *entry, *tmp_entry;
2645         struct mlx4_promisc_qp *pqp, *tmp_pqp;
2646         int num_entries = dev->caps.num_ports;
2647         int i, j;
2648
2649         for (i = 0; i < num_entries; i++) {
2650                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2651                         list_for_each_entry_safe(pqp, tmp_pqp,
2652                                                  &priv->steer[i].promisc_qps[j],
2653                                                  list) {
2654                                 list_del(&pqp->list);
2655                                 kfree(pqp);
2656                         }
2657                         list_for_each_entry_safe(entry, tmp_entry,
2658                                                  &priv->steer[i].steer_entries[j],
2659                                                  list) {
2660                                 list_del(&entry->list);
2661                                 list_for_each_entry_safe(pqp, tmp_pqp,
2662                                                          &entry->duplicates,
2663                                                          list) {
2664                                         list_del(&pqp->list);
2665                                         kfree(pqp);
2666                                 }
2667                                 kfree(entry);
2668                         }
2669                 }
2670         }
2671         kfree(priv->steer);
2672 }
2673
2674 #if 0 // AKAROS_PORT
2675 static int extended_func_num(struct pci_device *pdev)
2676 {
2677         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2678 }
2679 #endif
2680
2681 #define MLX4_OWNER_BASE 0x8069c
2682 #define MLX4_OWNER_SIZE 4
2683
2684 static int mlx4_get_ownership(struct mlx4_dev *dev)
2685 {
2686         void __iomem *owner;
2687         uint32_t ret;
2688
2689         if (pci_channel_offline(dev->persist->pdev))
2690                 return -EIO;
2691
2692         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2693                         MLX4_OWNER_BASE,
2694                         MLX4_OWNER_SIZE);
2695         if (!owner) {
2696                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2697                 return -ENOMEM;
2698         }
2699
2700         ret = read32(owner);
2701         iounmap(owner);
2702         return (int) !!ret;
2703 }
2704
2705 static void mlx4_free_ownership(struct mlx4_dev *dev)
2706 {
2707         void __iomem *owner;
2708
2709         if (pci_channel_offline(dev->persist->pdev))
2710                 return;
2711
2712         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
2713                         MLX4_OWNER_BASE,
2714                         MLX4_OWNER_SIZE);
2715         if (!owner) {
2716                 mlx4_err(dev, "Failed to obtain ownership bit\n");
2717                 return;
2718         }
2719         write32(0, owner);
2720         kthread_usleep(1000 * 1000);
2721         iounmap(owner);
2722 }
2723
2724 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2725                                   !!((flags) & MLX4_FLAG_MASTER))
2726
2727 static uint64_t mlx4_enable_sriov(struct mlx4_dev *dev,
2728                                   struct pci_device *pdev,
2729                                   uint8_t total_vfs, int existing_vfs,
2730                                   int reset_flow)
2731 {
2732         panic("Disabled");
2733 #if 0 // AKAROS_PORT
2734         uint64_t dev_flags = dev->flags;
2735         int err = 0;
2736
2737         if (reset_flow) {
2738                 dev->dev_vfs = kzmalloc((total_vfs) * (sizeof(*dev->dev_vfs)),
2739                                         KMALLOC_WAIT);
2740                 if (!dev->dev_vfs)
2741                         goto free_mem;
2742                 return dev_flags;
2743         }
2744
2745         atomic_inc(&pf_loading);
2746         if (dev->flags &  MLX4_FLAG_SRIOV) {
2747                 if (existing_vfs != total_vfs) {
2748                         mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2749                                  existing_vfs, total_vfs);
2750                         total_vfs = existing_vfs;
2751                 }
2752         }
2753
2754         dev->dev_vfs = kzmalloc(total_vfs * sizeof(*dev->dev_vfs),
2755                                 KMALLOC_WAIT);
2756         if (NULL == dev->dev_vfs) {
2757                 mlx4_err(dev, "Failed to allocate memory for VFs\n");
2758                 goto disable_sriov;
2759         }
2760
2761         if (!(dev->flags &  MLX4_FLAG_SRIOV)) {
2762                 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
2763                 err = pci_enable_sriov(pdev, total_vfs);
2764         }
2765         if (err) {
2766                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2767                          err);
2768                 goto disable_sriov;
2769         } else {
2770                 mlx4_warn(dev, "Running in master mode\n");
2771                 dev_flags |= MLX4_FLAG_SRIOV |
2772                         MLX4_FLAG_MASTER;
2773                 dev_flags &= ~MLX4_FLAG_SLAVE;
2774                 dev->persist->num_vfs = total_vfs;
2775         }
2776         return dev_flags;
2777
2778 disable_sriov:
2779         atomic_dec(&pf_loading);
2780 free_mem:
2781         dev->persist->num_vfs = 0;
2782         kfree(dev->dev_vfs);
2783         return dev_flags & ~MLX4_FLAG_MASTER;
2784 #endif
2785 }
2786
2787 enum {
2788         MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
2789 };
2790
2791 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
2792                               int *nvfs)
2793 {
2794         int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
2795         /* Checking for 64 VFs as a limitation of CX2 */
2796         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
2797             requested_vfs >= 64) {
2798                 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
2799                          requested_vfs);
2800                 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
2801         }
2802         return 0;
2803 }
2804
2805 static int mlx4_load_one(struct pci_device *pdev, int pci_dev_data,
2806                          int total_vfs, int *nvfs, struct mlx4_priv *priv,
2807                          int reset_flow)
2808 {
2809         struct mlx4_dev *dev;
2810         unsigned sum = 0;
2811         int err;
2812         int port;
2813         int i;
2814         struct mlx4_dev_cap *dev_cap = NULL;
2815         int existing_vfs = 0;
2816
2817         dev = &priv->dev;
2818
2819         INIT_LIST_HEAD(&priv->ctx_list);
2820         spinlock_init_irqsave(&priv->ctx_lock);
2821
2822         qlock_init(&priv->port_mutex);
2823         qlock_init(&priv->bond_mutex);
2824
2825         INIT_LIST_HEAD(&priv->pgdir_list);
2826         qlock_init(&priv->pgdir_mutex);
2827
2828         INIT_LIST_HEAD(&priv->bf_list);
2829         qlock_init(&priv->bf_mutex);
2830
2831 #if 0 // AKAROS_PORT
2832         dev->rev_id = pdev->revision;
2833 #endif
2834         dev->numa_node = dev_to_node(&pdev->dev);
2835
2836         /* Detect if this device is a virtual function */
2837         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
2838                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2839                 dev->flags |= MLX4_FLAG_SLAVE;
2840         } else {
2841                 /* We reset the device and enable SRIOV only for physical
2842                  * devices.  Try to claim ownership on the device;
2843                  * if already taken, skip -- do not allow multiple PFs */
2844                 err = mlx4_get_ownership(dev);
2845                 if (err) {
2846                         if (err < 0)
2847                                 return err;
2848                         else {
2849                                 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
2850                                 return -EINVAL;
2851                         }
2852                 }
2853
2854                 atomic_set(&priv->opreq_count, 0);
2855                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2856
2857                 /*
2858                  * Now reset the HCA before we touch the PCI capabilities or
2859                  * attempt a firmware command, since a boot ROM may have left
2860                  * the HCA in an undefined state.
2861                  */
2862                 err = mlx4_reset(dev);
2863                 if (err) {
2864                         mlx4_err(dev, "Failed to reset HCA, aborting\n");
2865                         goto err_sriov;
2866                 }
2867
2868 #if 0 // AKAROS_PORT
2869                 if (total_vfs) {
2870                         dev->flags = MLX4_FLAG_MASTER;
2871                         existing_vfs = pci_num_vf(pdev);
2872                         if (existing_vfs)
2873                                 dev->flags |= MLX4_FLAG_SRIOV;
2874                         dev->persist->num_vfs = total_vfs;
2875                 }
2876 #endif
2877         }
2878
2879         /* on load remove any previous indication of internal error,
2880          * device is up.
2881          */
2882         dev->persist->state = MLX4_DEVICE_STATE_UP;
2883
2884 slave_start:
2885         err = mlx4_cmd_init(dev);
2886         if (err) {
2887                 mlx4_err(dev, "Failed to init command interface, aborting\n");
2888                 goto err_sriov;
2889         }
2890
2891         /* In slave functions, the communication channel must be initialized
2892          * before posting commands. Also, init num_slaves before calling
2893          * mlx4_init_hca */
2894         if (mlx4_is_mfunc(dev)) {
2895                 if (mlx4_is_master(dev)) {
2896                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2897
2898                 } else {
2899                         dev->num_slaves = 0;
2900                         err = mlx4_multi_func_init(dev);
2901                         if (err) {
2902                                 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
2903                                 goto err_cmd;
2904                         }
2905                 }
2906         }
2907
2908         err = mlx4_init_fw(dev);
2909         if (err) {
2910                 mlx4_err(dev, "Failed to init fw, aborting.\n");
2911                 goto err_mfunc;
2912         }
2913
2914         if (mlx4_is_master(dev)) {
2915                 /* when we hit the goto slave_start below, dev_cap already initialized */
2916                 if (!dev_cap) {
2917                         dev_cap = kzmalloc(sizeof(*dev_cap), KMALLOC_WAIT);
2918
2919                         if (!dev_cap) {
2920                                 err = -ENOMEM;
2921                                 goto err_fw;
2922                         }
2923
2924                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2925                         if (err) {
2926                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2927                                 goto err_fw;
2928                         }
2929
2930                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2931                                 goto err_fw;
2932
2933                         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2934                                 uint64_t dev_flags = mlx4_enable_sriov(dev, pdev,
2935                                                                   total_vfs,
2936                                                                   existing_vfs,
2937                                                                   reset_flow);
2938
2939                                 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2940                                 dev->flags = dev_flags;
2941                                 if (!SRIOV_VALID_STATE(dev->flags)) {
2942                                         mlx4_err(dev, "Invalid SRIOV state\n");
2943                                         goto err_sriov;
2944                                 }
2945                                 err = mlx4_reset(dev);
2946                                 if (err) {
2947                                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2948                                         goto err_sriov;
2949                                 }
2950                                 goto slave_start;
2951                         }
2952                 } else {
2953                         /* Legacy mode FW requires SRIOV to be enabled before
2954                          * doing QUERY_DEV_CAP, since max_eq's value is different if
2955                          * SRIOV is enabled.
2956                          */
2957                         memset(dev_cap, 0, sizeof(*dev_cap));
2958                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
2959                         if (err) {
2960                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2961                                 goto err_fw;
2962                         }
2963
2964                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
2965                                 goto err_fw;
2966                 }
2967         }
2968
2969         err = mlx4_init_hca(dev);
2970         if (err) {
2971                 if (err == -EACCES) {
2972                         /* Not primary Physical function
2973                          * Running in slave mode */
2974                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
2975                         /* We're not a PF */
2976 #if 0 // AKAROS_PORT
2977                         if (dev->flags & MLX4_FLAG_SRIOV) {
2978                                 if (!existing_vfs)
2979                                         pci_disable_sriov(pdev);
2980                                 if (mlx4_is_master(dev) && !reset_flow)
2981                                         atomic_dec(&pf_loading);
2982                                 dev->flags &= ~MLX4_FLAG_SRIOV;
2983                         }
2984 #endif
2985                         if (!mlx4_is_slave(dev))
2986                                 mlx4_free_ownership(dev);
2987                         dev->flags |= MLX4_FLAG_SLAVE;
2988                         dev->flags &= ~MLX4_FLAG_MASTER;
2989                         goto slave_start;
2990                 } else
2991                         goto err_fw;
2992         }
2993
2994         if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
2995                 uint64_t dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
2996                                                   existing_vfs, reset_flow);
2997
2998                 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
2999                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3000                         dev->flags = dev_flags;
3001                         err = mlx4_cmd_init(dev);
3002                         if (err) {
3003                                 /* Only VHCR is cleaned up, so could still
3004                                  * send FW commands
3005                                  */
3006                                 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3007                                 goto err_close;
3008                         }
3009                 } else {
3010                         dev->flags = dev_flags;
3011                 }
3012
3013                 if (!SRIOV_VALID_STATE(dev->flags)) {
3014                         mlx4_err(dev, "Invalid SRIOV state\n");
3015                         goto err_close;
3016                 }
3017         }
3018
3019         /* check if the device is functioning at its maximum possible speed.
3020          * No return code for this call, just warn the user in case of PCI
3021          * express device capabilities are under-satisfied by the bus.
3022          */
3023         if (!mlx4_is_slave(dev))
3024                 mlx4_check_pcie_caps(dev);
3025
3026         /* In master functions, the communication channel must be initialized
3027          * after obtaining its address from fw */
3028         if (mlx4_is_master(dev)) {
3029                 int ib_ports = 0;
3030
3031                 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3032                         ib_ports++;
3033
3034                 if (ib_ports &&
3035                     (num_vfs_argc > 1 || probe_vfs_argc > 1)) {
3036                         mlx4_err(dev,
3037                                  "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
3038                         err = -EINVAL;
3039                         goto err_close;
3040                 }
3041                 if (dev->caps.num_ports < 2 &&
3042                     num_vfs_argc > 1) {
3043                         err = -EINVAL;
3044                         mlx4_err(dev,
3045                                  "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3046                                  dev->caps.num_ports);
3047                         goto err_close;
3048                 }
3049                 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
3050
3051                 for (i = 0;
3052                      i < sizeof(dev->persist->nvfs)/
3053                      sizeof(dev->persist->nvfs[0]); i++) {
3054                         unsigned j;
3055
3056                         for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
3057                                 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3058                                 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3059                                         dev->caps.num_ports;
3060                         }
3061                 }
3062
3063                 /* In master functions, the communication channel
3064                  * must be initialized after obtaining its address from fw
3065                  */
3066                 err = mlx4_multi_func_init(dev);
3067                 if (err) {
3068                         mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3069                         goto err_close;
3070                 }
3071         }
3072
3073         err = mlx4_alloc_eq_table(dev);
3074         if (err)
3075                 goto err_master_mfunc;
3076
3077         priv->msix_ctl.pool_bm = 0;
3078         qlock_init(&priv->msix_ctl.pool_lock);
3079
3080         mlx4_enable_msi_x(dev);
3081         if ((mlx4_is_mfunc(dev)) &&
3082             !(dev->flags & MLX4_FLAG_MSI_X)) {
3083                 err = -ENOSYS;
3084                 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
3085                 goto err_free_eq;
3086         }
3087
3088         if (!mlx4_is_slave(dev)) {
3089                 err = mlx4_init_steering(dev);
3090                 if (err)
3091                         goto err_disable_msix;
3092         }
3093
3094         err = mlx4_setup_hca(dev);
3095 #if 0 // AKAROS_PORT
3096         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3097             !mlx4_is_mfunc(dev)) {
3098                 dev->flags &= ~MLX4_FLAG_MSI_X;
3099                 dev->caps.num_comp_vectors = 1;
3100                 dev->caps.comp_pool        = 0;
3101                 pci_disable_msix(pdev);
3102                 err = mlx4_setup_hca(dev);
3103         }
3104 #endif
3105
3106         if (err)
3107                 goto err_steer;
3108
3109         mlx4_init_quotas(dev);
3110         /* When PF resources are ready arm its comm channel to enable
3111          * getting commands
3112          */
3113         if (mlx4_is_master(dev)) {
3114                 err = mlx4_ARM_COMM_CHANNEL(dev);
3115                 if (err) {
3116                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3117                                  err);
3118                         goto err_steer;
3119                 }
3120         }
3121
3122         for (port = 1; port <= dev->caps.num_ports; port++) {
3123                 err = mlx4_init_port_info(dev, port);
3124                 if (err)
3125                         goto err_port;
3126         }
3127
3128         priv->v2p.port1 = 1;
3129         priv->v2p.port2 = 2;
3130
3131         err = mlx4_register_device(dev);
3132         if (err)
3133                 goto err_port;
3134
3135         mlx4_request_modules(dev);
3136
3137         mlx4_sense_init(dev);
3138         mlx4_start_sense(dev);
3139
3140         priv->removed = 0;
3141
3142         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3143                 atomic_dec(&pf_loading);
3144
3145         kfree(dev_cap);
3146         return 0;
3147
3148 err_port:
3149         for (--port; port >= 1; --port)
3150                 mlx4_cleanup_port_info(&priv->port[port]);
3151
3152         mlx4_cleanup_counters_table(dev);
3153         mlx4_cleanup_qp_table(dev);
3154         mlx4_cleanup_srq_table(dev);
3155         mlx4_cleanup_cq_table(dev);
3156         mlx4_cmd_use_polling(dev);
3157         mlx4_cleanup_eq_table(dev);
3158         mlx4_cleanup_mcg_table(dev);
3159         mlx4_cleanup_mr_table(dev);
3160         mlx4_cleanup_xrcd_table(dev);
3161         mlx4_cleanup_pd_table(dev);
3162         mlx4_cleanup_uar_table(dev);
3163
3164 err_steer:
3165         if (!mlx4_is_slave(dev))
3166                 mlx4_clear_steering(dev);
3167
3168 err_disable_msix:
3169 #if 0 // AKAROS_PORT
3170         if (dev->flags & MLX4_FLAG_MSI_X)
3171                 pci_disable_msix(pdev);
3172 #endif
3173
3174 err_free_eq:
3175         mlx4_free_eq_table(dev);
3176
3177 err_master_mfunc:
3178         if (mlx4_is_master(dev)) {
3179                 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3180                 mlx4_multi_func_cleanup(dev);
3181         }
3182
3183         if (mlx4_is_slave(dev)) {
3184                 kfree(dev->caps.qp0_qkey);
3185                 kfree(dev->caps.qp0_tunnel);
3186                 kfree(dev->caps.qp0_proxy);
3187                 kfree(dev->caps.qp1_tunnel);
3188                 kfree(dev->caps.qp1_proxy);
3189         }
3190
3191 err_close:
3192         mlx4_close_hca(dev);
3193
3194 err_fw:
3195         mlx4_close_fw(dev);
3196
3197 err_mfunc:
3198         if (mlx4_is_slave(dev))
3199                 mlx4_multi_func_cleanup(dev);
3200
3201 err_cmd:
3202         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3203
3204 err_sriov:
3205 #if 0 // AKAROS_PORT
3206         if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
3207                 pci_disable_sriov(pdev);
3208                 dev->flags &= ~MLX4_FLAG_SRIOV;
3209         }
3210 #endif
3211
3212         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3213                 atomic_dec(&pf_loading);
3214
3215         kfree(priv->dev.dev_vfs);
3216
3217         if (!mlx4_is_slave(dev))
3218                 mlx4_free_ownership(dev);
3219
3220         kfree(dev_cap);
3221         return err;
3222 }
3223
3224 static int __mlx4_init_one(struct pci_device *pdev, int pci_dev_data,
3225                            struct mlx4_priv *priv)
3226 {
3227         int err;
3228         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3229         int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3230         const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3231                 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3232         unsigned total_vfs = 0;
3233         unsigned int i;
3234
3235         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3236
3237         err = pci_enable_device(pdev);
3238         if (err) {
3239                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3240                 return err;
3241         }
3242
3243         /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3244          * per port, we must limit the number of VFs to 63 (since their are
3245          * 128 MACs)
3246          */
3247         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3248              total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3249                 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3250                 if (nvfs[i] < 0) {
3251                         dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3252                         err = -EINVAL;
3253                         goto err_disable_pdev;
3254                 }
3255         }
3256         for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3257              i++) {
3258                 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3259                 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3260                         dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3261                         err = -EINVAL;
3262                         goto err_disable_pdev;
3263                 }
3264         }
3265         if (total_vfs >= MLX4_MAX_NUM_VF) {
3266                 dev_err(&pdev->dev,
3267                         "Requested more VF's (%d) than allowed (%d)\n",
3268                         total_vfs, MLX4_MAX_NUM_VF - 1);
3269                 err = -EINVAL;
3270                 goto err_disable_pdev;
3271         }
3272
3273         for (i = 0; i < MLX4_MAX_PORTS; i++) {
3274                 if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) {
3275                         dev_err(&pdev->dev,
3276                                 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
3277                                 nvfs[i] + nvfs[2], i + 1,
3278                                 MLX4_MAX_NUM_VF_P_PORT - 1);
3279                         err = -EINVAL;
3280                         goto err_disable_pdev;
3281                 }
3282         }
3283
3284         /* Check for BARs. */
3285         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3286 #if 0 // AKAROS_PORT
3287             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3288 #else
3289             !pci_get_membar(pdev, 0)) {
3290 #endif
3291                 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3292 #if 0 // AKAROS_PORT
3293                         pci_dev_data, pci_resource_flags(pdev, 0));
3294 #else
3295                         pci_dev_data, pci_get_membar(pdev, 0));
3296 #endif
3297                 err = -ENODEV;
3298                 goto err_disable_pdev;
3299         }
3300 #if 0 // AKAROS_PORT
3301         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3302 #else
3303         if (!pci_get_membar(pdev, 2)) {
3304 #endif
3305                 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3306                 err = -ENODEV;
3307                 goto err_disable_pdev;
3308         }
3309
3310         err = pci_request_regions(pdev, DRV_NAME);
3311         if (err) {
3312                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3313                 goto err_disable_pdev;
3314         }
3315
3316         pci_set_master(pdev);
3317
3318         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3319         if (err) {
3320                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3321                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3322                 if (err) {
3323                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3324                         goto err_release_regions;
3325                 }
3326         }
3327         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3328         if (err) {
3329                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3330                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3331                 if (err) {
3332                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3333                         goto err_release_regions;
3334                 }
3335         }
3336
3337         /* Allow large DMA segments, up to the firmware limit of 1 GB */
3338         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3339 #if 0 // AKAROS_PORT
3340         /* Detect if this device is a virtual function */
3341         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3342                 /* When acting as pf, we normally skip vfs unless explicitly
3343                  * requested to probe them.
3344                  */
3345                 if (total_vfs) {
3346                         unsigned vfs_offset = 0;
3347
3348                         for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3349                              vfs_offset + nvfs[i] < extended_func_num(pdev);
3350                              vfs_offset += nvfs[i], i++)
3351                                 ;
3352                         if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3353                                 err = -ENODEV;
3354                                 goto err_release_regions;
3355                         }
3356                         if ((extended_func_num(pdev) - vfs_offset)
3357                             > prb_vf[i]) {
3358                                 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3359                                          extended_func_num(pdev));
3360                                 err = -ENODEV;
3361                                 goto err_release_regions;
3362                         }
3363                 }
3364         }
3365 #endif
3366
3367         err = mlx4_catas_init(&priv->dev);
3368         if (err)
3369                 goto err_release_regions;
3370
3371         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
3372         if (err)
3373                 goto err_catas;
3374
3375         return 0;
3376
3377 err_catas:
3378         mlx4_catas_end(&priv->dev);
3379
3380 err_release_regions:
3381 #if 0 // AKAROS_PORT
3382         pci_release_regions(pdev);
3383 #endif
3384
3385 err_disable_pdev:
3386         pci_disable_device(pdev);
3387         pci_set_drvdata(pdev, NULL);
3388         return err;
3389 }
3390
3391 static int mlx4_init_one(struct pci_device *pdev,
3392                          const struct pci_device_id *id)
3393 {
3394         struct mlx4_priv *priv;
3395         struct mlx4_dev *dev;
3396         int ret;
3397
3398         printk_once(KERN_INFO "%s", mlx4_version);
3399
3400         priv = kzmalloc(sizeof(*priv), KMALLOC_WAIT);
3401         if (!priv)
3402                 return -ENOMEM;
3403
3404         dev       = &priv->dev;
3405         dev->persist = kzmalloc(sizeof(*dev->persist), KMALLOC_WAIT);
3406         if (!dev->persist) {
3407                 kfree(priv);
3408                 return -ENOMEM;
3409         }
3410         dev->persist->pdev = pdev;
3411         dev->persist->dev = dev;
3412         pci_set_drvdata(pdev, dev->persist);
3413         priv->pci_dev_data = id->driver_data;
3414         qlock_init(&dev->persist->device_state_mutex);
3415         qlock_init(&dev->persist->interface_state_mutex);
3416
3417         ret =  __mlx4_init_one(pdev, id->driver_data, priv);
3418         if (ret) {
3419                 kfree(dev->persist);
3420                 kfree(priv);
3421         } else {
3422                 pci_save_state(pdev);
3423         }
3424
3425         return ret;
3426 }
3427
3428 static void mlx4_clean_dev(struct mlx4_dev *dev)
3429 {
3430         struct mlx4_dev_persistent *persist = dev->persist;
3431         struct mlx4_priv *priv = mlx4_priv(dev);
3432         unsigned long   flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
3433
3434         memset(priv, 0, sizeof(*priv));
3435         priv->dev.persist = persist;
3436         priv->dev.flags = flags;
3437 }
3438
3439 static void mlx4_unload_one(struct pci_device *pdev)
3440 {
3441         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3442         struct mlx4_dev  *dev  = persist->dev;
3443         struct mlx4_priv *priv = mlx4_priv(dev);
3444         int               pci_dev_data;
3445         int p, i;
3446
3447         if (priv->removed)
3448                 return;
3449
3450         /* saving current ports type for further use */
3451         for (i = 0; i < dev->caps.num_ports; i++) {
3452                 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3453                 dev->persist->curr_port_poss_type[i] = dev->caps.
3454                                                        possible_type[i + 1];
3455         }
3456
3457         pci_dev_data = priv->pci_dev_data;
3458
3459         mlx4_stop_sense(dev);
3460         mlx4_unregister_device(dev);
3461
3462         for (p = 1; p <= dev->caps.num_ports; p++) {
3463                 mlx4_cleanup_port_info(&priv->port[p]);
3464                 mlx4_CLOSE_PORT(dev, p);
3465         }
3466
3467         if (mlx4_is_master(dev))
3468                 mlx4_free_resource_tracker(dev,
3469                                            RES_TR_FREE_SLAVES_ONLY);
3470
3471         mlx4_cleanup_counters_table(dev);
3472         mlx4_cleanup_qp_table(dev);
3473         mlx4_cleanup_srq_table(dev);
3474         mlx4_cleanup_cq_table(dev);
3475         mlx4_cmd_use_polling(dev);
3476         mlx4_cleanup_eq_table(dev);
3477         mlx4_cleanup_mcg_table(dev);
3478         mlx4_cleanup_mr_table(dev);
3479         mlx4_cleanup_xrcd_table(dev);
3480         mlx4_cleanup_pd_table(dev);
3481
3482         if (mlx4_is_master(dev))
3483                 mlx4_free_resource_tracker(dev,
3484                                            RES_TR_FREE_STRUCTS_ONLY);
3485
3486         iounmap(priv->kar);
3487         mlx4_uar_free(dev, &priv->driver_uar);
3488         mlx4_cleanup_uar_table(dev);
3489         if (!mlx4_is_slave(dev))
3490                 mlx4_clear_steering(dev);
3491         mlx4_free_eq_table(dev);
3492         if (mlx4_is_master(dev))
3493                 mlx4_multi_func_cleanup(dev);
3494         mlx4_close_hca(dev);
3495         mlx4_close_fw(dev);
3496         if (mlx4_is_slave(dev))
3497                 mlx4_multi_func_cleanup(dev);
3498         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3499
3500 #if 0 // AKAROS_PORT
3501         if (dev->flags & MLX4_FLAG_MSI_X)
3502                 pci_disable_msix(pdev);
3503 #endif
3504
3505         if (!mlx4_is_slave(dev))
3506                 mlx4_free_ownership(dev);
3507
3508         kfree(dev->caps.qp0_qkey);
3509         kfree(dev->caps.qp0_tunnel);
3510         kfree(dev->caps.qp0_proxy);
3511         kfree(dev->caps.qp1_tunnel);
3512         kfree(dev->caps.qp1_proxy);
3513         kfree(dev->dev_vfs);
3514
3515         mlx4_clean_dev(dev);
3516         priv->pci_dev_data = pci_dev_data;
3517         priv->removed = 1;
3518 }
3519
3520 static void mlx4_remove_one(struct pci_device *pdev)
3521 {
3522         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3523         struct mlx4_dev  *dev  = persist->dev;
3524         struct mlx4_priv *priv = mlx4_priv(dev);
3525         int active_vfs = 0;
3526
3527         qlock(&persist->interface_state_mutex);
3528         persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3529         qunlock(&persist->interface_state_mutex);
3530
3531         /* Disabling SR-IOV is not allowed while there are active vf's */
3532         if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3533                 active_vfs = mlx4_how_many_lives_vf(dev);
3534                 if (active_vfs) {
3535                         pr_warn("Removing PF when there are active VF's !!\n");
3536                         pr_warn("Will not disable SR-IOV.\n");
3537                 }
3538         }
3539
3540         /* device marked to be under deletion running now without the lock
3541          * letting other tasks to be terminated
3542          */
3543         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3544                 mlx4_unload_one(pdev);
3545         else
3546                 mlx4_info(dev, "%s: interface is down\n", __func__);
3547         mlx4_catas_end(dev);
3548 #if 0 // AKAROS_PORT
3549         if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3550                 mlx4_warn(dev, "Disabling SR-IOV\n");
3551                 pci_disable_sriov(pdev);
3552         }
3553
3554         pci_release_regions(pdev);
3555 #endif
3556         pci_disable_device(pdev);
3557         kfree(dev->persist);
3558         kfree(priv);
3559         pci_set_drvdata(pdev, NULL);
3560 }
3561
3562 static int restore_current_port_types(struct mlx4_dev *dev,
3563                                       enum mlx4_port_type *types,
3564                                       enum mlx4_port_type *poss_types)
3565 {
3566         struct mlx4_priv *priv = mlx4_priv(dev);
3567         int err, i;
3568
3569         mlx4_stop_sense(dev);
3570
3571         qlock(&priv->port_mutex);
3572         for (i = 0; i < dev->caps.num_ports; i++)
3573                 dev->caps.possible_type[i + 1] = poss_types[i];
3574         err = mlx4_change_port_types(dev, types);
3575         mlx4_start_sense(dev);
3576         qunlock(&priv->port_mutex);
3577
3578         return err;
3579 }
3580
3581 int mlx4_restart_one(struct pci_device *pdev)
3582 {
3583         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3584         struct mlx4_dev  *dev  = persist->dev;
3585         struct mlx4_priv *priv = mlx4_priv(dev);
3586         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3587         int pci_dev_data, err, total_vfs;
3588
3589         pci_dev_data = priv->pci_dev_data;
3590         total_vfs = dev->persist->num_vfs;
3591         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3592
3593         mlx4_unload_one(pdev);
3594         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
3595         if (err) {
3596                 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3597                          __func__, pci_name(pdev), err);
3598                 return err;
3599         }
3600
3601         err = restore_current_port_types(dev, dev->persist->curr_port_type,
3602                                          dev->persist->curr_port_poss_type);
3603         if (err)
3604                 mlx4_err(dev, "could not restore original port types (%d)\n",
3605                          err);
3606
3607         return err;
3608 }
3609
3610 static const struct pci_device_id mlx4_pci_table[] = {
3611         /* MT25408 "Hermon" SDR */
3612         { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3613         /* MT25408 "Hermon" DDR */
3614         { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3615         /* MT25408 "Hermon" QDR */
3616         { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3617         /* MT25408 "Hermon" DDR PCIe gen2 */
3618         { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3619         /* MT25408 "Hermon" QDR PCIe gen2 */
3620         { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3621         /* MT25408 "Hermon" EN 10GigE */
3622         { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3623         /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
3624         { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3625         /* MT25458 ConnectX EN 10GBASE-T 10GigE */
3626         { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3627         /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
3628         { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3629         /* MT26468 ConnectX EN 10GigE PCIe gen2*/
3630         { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3631         /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
3632         { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3633         /* MT26478 ConnectX2 40GigE PCIe gen2 */
3634         { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3635         /* MT25400 Family [ConnectX-2 Virtual Function] */
3636         { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
3637         /* MT27500 Family [ConnectX-3] */
3638         { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3639         /* MT27500 Family [ConnectX-3 Virtual Function] */
3640         { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
3641         { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3642         { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3643         { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3644         { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3645         { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3646         { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3647         { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3648         { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3649         { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3650         { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3651         { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3652         { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
3653         { 0, }
3654 };
3655
3656 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3657
3658 static pci_ers_result_t mlx4_pci_err_detected(struct pci_device *pdev,
3659                                               pci_channel_state_t state)
3660 {
3661         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3662
3663         mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
3664         mlx4_enter_error_state(persist);
3665
3666         qlock(&persist->interface_state_mutex);
3667         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3668                 mlx4_unload_one(pdev);
3669
3670         qunlock(&persist->interface_state_mutex);
3671         if (state == pci_channel_io_perm_failure)
3672                 return PCI_ERS_RESULT_DISCONNECT;
3673
3674         pci_disable_device(pdev);
3675         return PCI_ERS_RESULT_NEED_RESET;
3676 }
3677
3678 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_device *pdev)
3679 {
3680         panic("Disabled");
3681 #if 0 // AKAROS_PORT
3682         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3683         struct mlx4_dev  *dev  = persist->dev;
3684         struct mlx4_priv *priv = mlx4_priv(dev);
3685         int               ret;
3686         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3687         int total_vfs;
3688
3689         mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
3690         ret = pci_enable_device(pdev);
3691         if (ret) {
3692                 mlx4_err(dev, "Can not re-enable device, ret=%d\n", ret);
3693                 return PCI_ERS_RESULT_DISCONNECT;
3694         }
3695
3696         pci_set_master(pdev);
3697         pci_restore_state(pdev);
3698         pci_save_state(pdev);
3699
3700         total_vfs = dev-