mlx4: TX path
[akaros.git] / kern / drivers / net / mlx4 / en_tx.c
1 /*
2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33
34 #include <linux/mlx4/cq.h>
35 #include <linux/mlx4/qp.h>
36 #include "mlx4_en.h"
37
38 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
39                            struct mlx4_en_tx_ring **pring, uint32_t size,
40                            uint16_t stride, int node, int queue_index)
41 {
42         struct mlx4_en_dev *mdev = priv->mdev;
43         struct mlx4_en_tx_ring *ring;
44         int tmp;
45         int err;
46
47         ring = kzalloc_node(sizeof(*ring), KMALLOC_WAIT, node);
48         if (!ring) {
49                 ring = kzmalloc(sizeof(*ring), KMALLOC_WAIT);
50                 if (!ring) {
51                         en_err(priv, "Failed allocating TX ring\n");
52                         return -ENOMEM;
53                 }
54         }
55
56         ring->size = size;
57         ring->size_mask = size - 1;
58         ring->stride = stride;
59
60         tmp = size * sizeof(struct mlx4_en_tx_info);
61         ring->tx_info = kmalloc_node(tmp, KMALLOC_WAIT | __GFP_NOWARN, node);
62         if (!ring->tx_info) {
63                 ring->tx_info = vmalloc(tmp);
64                 if (!ring->tx_info) {
65                         err = -ENOMEM;
66                         goto err_ring;
67                 }
68         }
69
70         en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
71                  ring->tx_info, tmp);
72
73         ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, KMALLOC_WAIT, node);
74         if (!ring->bounce_buf) {
75                 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, KMALLOC_WAIT);
76                 if (!ring->bounce_buf) {
77                         err = -ENOMEM;
78                         goto err_info;
79                 }
80         }
81         ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
82
83         /* Allocate HW buffers on provided NUMA node */
84         set_dev_node(&mdev->dev->persist->pdev->dev, node);
85         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
86                                  2 * PAGE_SIZE);
87         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
88         if (err) {
89                 en_err(priv, "Failed allocating hwq resources\n");
90                 goto err_bounce;
91         }
92
93         err = mlx4_en_map_buffer(&ring->wqres.buf);
94         if (err) {
95                 en_err(priv, "Failed to map TX buffer\n");
96                 goto err_hwq_res;
97         }
98
99         ring->buf = ring->wqres.buf.direct.buf;
100
101         en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
102                ring, ring->buf, ring->size, ring->buf_size,
103                (unsigned long long) ring->wqres.buf.direct.map);
104
105         err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
106                                     MLX4_RESERVE_ETH_BF_QP);
107         if (err) {
108                 en_err(priv, "failed reserving qp for TX ring\n");
109                 goto err_map;
110         }
111
112         err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, KMALLOC_WAIT);
113         if (err) {
114                 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
115                 goto err_reserve;
116         }
117         ring->qp.event = mlx4_en_sqp_event;
118
119 #if 0 // AKAROS_PORT
120         err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
121         if (err) {
122 #else
123         if (true) {
124 #endif
125                 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
126                 ring->bf.uar = &mdev->priv_uar;
127                 ring->bf.uar->map = mdev->uar_map;
128                 ring->bf_enabled = false;
129                 ring->bf_alloced = false;
130                 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
131         } else {
132                 ring->bf_alloced = true;
133                 ring->bf_enabled = !!(priv->pflags &
134                                       MLX4_EN_PRIV_FLAGS_BLUEFLAME);
135         }
136
137         ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
138         ring->queue_index = queue_index;
139
140         if (queue_index < priv->num_tx_rings_p_up)
141                 cpumask_set_cpu(cpumask_local_spread(queue_index,
142                                                      priv->mdev->dev->numa_node),
143                                 &ring->affinity_mask);
144
145         *pring = ring;
146         return 0;
147
148 err_reserve:
149         mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
150 err_map:
151         mlx4_en_unmap_buffer(&ring->wqres.buf);
152 err_hwq_res:
153         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
154 err_bounce:
155         kfree(ring->bounce_buf);
156         ring->bounce_buf = NULL;
157 err_info:
158 #if 0 // AKAROS_PORT
159         kvfree(ring->tx_info);
160 #endif
161         ring->tx_info = NULL;
162 err_ring:
163         kfree(ring);
164         *pring = NULL;
165         return err;
166 }
167
168 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
169                              struct mlx4_en_tx_ring **pring)
170 {
171         panic("Disabled");
172 #if 0 // AKAROS_PORT
173         struct mlx4_en_dev *mdev = priv->mdev;
174         struct mlx4_en_tx_ring *ring = *pring;
175         en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
176
177         if (ring->bf_alloced)
178                 mlx4_bf_free(mdev->dev, &ring->bf);
179         mlx4_qp_remove(mdev->dev, &ring->qp);
180         mlx4_qp_free(mdev->dev, &ring->qp);
181         mlx4_en_unmap_buffer(&ring->wqres.buf);
182         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
183         kfree(ring->bounce_buf);
184         ring->bounce_buf = NULL;
185         kvfree(ring->tx_info);
186         ring->tx_info = NULL;
187         kfree(ring);
188         *pring = NULL;
189 #endif
190 }
191
192 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
193                              struct mlx4_en_tx_ring *ring,
194                              int cq, int user_prio)
195 {
196         struct mlx4_en_dev *mdev = priv->mdev;
197         int err;
198
199         ring->cqn = cq;
200         ring->prod = 0;
201         ring->cons = 0xffffffff;
202         ring->last_nr_txbb = 1;
203         memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
204         memset(ring->buf, 0, ring->buf_size);
205
206         ring->qp_state = MLX4_QP_STATE_RST;
207         ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8);
208         ring->mr_key = cpu_to_be32(mdev->mr.key);
209
210         mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
211                                 ring->cqn, user_prio, &ring->context);
212         if (ring->bf_alloced)
213                 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
214
215         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
216                                &ring->qp, &ring->qp_state);
217 #if 0 // AKAROS_PORT
218         if (!cpumask_empty(&ring->affinity_mask))
219                 netif_set_xps_queue(priv->dev, &ring->affinity_mask,
220                                     ring->queue_index);
221 #endif
222
223         return err;
224 }
225
226 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
227                                 struct mlx4_en_tx_ring *ring)
228 {
229         struct mlx4_en_dev *mdev = priv->mdev;
230
231         mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
232                        MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
233 }
234
235 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
236                               struct mlx4_en_tx_ring *ring, int index,
237                               uint8_t owner)
238 {
239         __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
240         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
241         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
242         void *end = ring->buf + ring->buf_size;
243         __be32 *ptr = (__be32 *)tx_desc;
244         int i;
245
246         /* Optimize the common case when there are no wraparounds */
247         if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
248                 /* Stamp the freed descriptor */
249                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
250                      i += STAMP_STRIDE) {
251                         *ptr = stamp;
252                         ptr += STAMP_DWORDS;
253                 }
254         } else {
255                 /* Stamp the freed descriptor */
256                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
257                      i += STAMP_STRIDE) {
258                         *ptr = stamp;
259                         ptr += STAMP_DWORDS;
260                         if ((void *)ptr >= end) {
261                                 ptr = ring->buf;
262                                 stamp ^= cpu_to_be32(0x80000000);
263                         }
264                 }
265         }
266 }
267
268
269 static uint32_t mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
270                                 struct mlx4_en_tx_ring *ring,
271                                 int index, uint8_t owner, uint64_t timestamp)
272 {
273         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
274         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
275         struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
276         void *end = ring->buf + ring->buf_size;
277         struct block *block = tx_info->block;
278         int nr_maps = tx_info->nr_maps;
279         int i;
280
281 #if 0 // AKAROS_PORT
282         /* We do not touch skb here, so prefetch skb->users location
283          * to speedup consume_skb()
284          */
285         prefetchw(&skb->users);
286
287         if (unlikely(timestamp)) {
288                 struct skb_shared_hwtstamps hwts;
289
290                 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
291                 skb_tstamp_tx(skb, &hwts);
292         }
293 #endif
294
295         /* Optimize the common case when there are no wraparounds */
296         if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
297                 if (!tx_info->inl) {
298                         if (tx_info->linear)
299                                 dma_unmap_single(priv->ddev,
300                                                 tx_info->map0_dma,
301                                                 tx_info->map0_byte_count,
302                                                 PCI_DMA_TODEVICE);
303                         else
304                                 dma_unmap_page(priv->ddev,
305                                                tx_info->map0_dma,
306                                                tx_info->map0_byte_count,
307                                                PCI_DMA_TODEVICE);
308                         for (i = 1; i < nr_maps; i++) {
309                                 data++;
310                                 dma_unmap_page(priv->ddev,
311                                         (dma_addr_t)be64_to_cpu(data->addr),
312                                         be32_to_cpu(data->byte_count),
313                                         PCI_DMA_TODEVICE);
314                         }
315                 }
316         } else {
317                 if (!tx_info->inl) {
318                         if ((void *) data >= end) {
319                                 data = ring->buf + ((void *)data - end);
320                         }
321
322                         if (tx_info->linear)
323                                 dma_unmap_single(priv->ddev,
324                                                 tx_info->map0_dma,
325                                                 tx_info->map0_byte_count,
326                                                 PCI_DMA_TODEVICE);
327                         else
328                                 dma_unmap_page(priv->ddev,
329                                                tx_info->map0_dma,
330                                                tx_info->map0_byte_count,
331                                                PCI_DMA_TODEVICE);
332                         for (i = 1; i < nr_maps; i++) {
333                                 data++;
334                                 /* Check for wraparound before unmapping */
335                                 if ((void *) data >= end)
336                                         data = ring->buf;
337                                 dma_unmap_page(priv->ddev,
338                                         (dma_addr_t)be64_to_cpu(data->addr),
339                                         be32_to_cpu(data->byte_count),
340                                         PCI_DMA_TODEVICE);
341                         }
342                 }
343         }
344         freeb(block);
345         return tx_info->nr_txbb;
346 }
347
348
349 int mlx4_en_free_tx_buf(struct ether *dev, struct mlx4_en_tx_ring *ring)
350 {
351         panic("Disabled");
352 #if 0 // AKAROS_PORT
353         struct mlx4_en_priv *priv = netdev_priv(dev);
354         int cnt = 0;
355
356         /* Skip last polled descriptor */
357         ring->cons += ring->last_nr_txbb;
358         en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
359                  ring->cons, ring->prod);
360
361         if ((uint32_t) (ring->prod - ring->cons) > ring->size) {
362                 if (netif_msg_tx_err(priv))
363                         en_warn(priv, "Tx consumer passed producer!\n");
364                 return 0;
365         }
366
367         while (ring->cons != ring->prod) {
368                 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
369                                                 ring->cons & ring->size_mask,
370                                                 !!(ring->cons & ring->size), 0);
371                 ring->cons += ring->last_nr_txbb;
372                 cnt++;
373         }
374
375         netdev_tx_reset_queue(ring->tx_queue);
376
377         if (cnt)
378                 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
379
380         return cnt;
381 #endif
382 }
383
384 static bool mlx4_en_process_tx_cq(struct ether *dev,
385                                   struct mlx4_en_cq *cq)
386 {
387         struct mlx4_en_priv *priv = netdev_priv(dev);
388         struct mlx4_cq *mcq = &cq->mcq;
389         struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
390         struct mlx4_cqe *cqe;
391         uint16_t index;
392         uint16_t new_index, ring_index, stamp_index;
393         uint32_t txbbs_skipped = 0;
394         uint32_t txbbs_stamp = 0;
395         uint32_t cons_index = mcq->cons_index;
396         int size = cq->size;
397         uint32_t size_mask = ring->size_mask;
398         struct mlx4_cqe *buf = cq->buf;
399         uint32_t packets = 0;
400         uint32_t bytes = 0;
401         int factor = priv->cqe_factor;
402         uint64_t timestamp = 0;
403         int done = 0;
404         int budget = priv->tx_work_limit;
405         uint32_t last_nr_txbb;
406         uint32_t ring_cons;
407
408         if (!priv->port_up)
409                 return true;
410
411 #if 0 // AKAROS_PORT
412         netdev_txq_bql_complete_prefetchw(ring->tx_queue);
413 #endif
414
415         index = cons_index & size_mask;
416         cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
417         last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb);
418         ring_cons = ACCESS_ONCE(ring->cons);
419         ring_index = ring_cons & size_mask;
420         stamp_index = ring_index;
421
422         /* Process all completed CQEs */
423         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
424                         cons_index & size) && (done < budget)) {
425                 /*
426                  * make sure we read the CQE after we read the
427                  * ownership bit
428                  */
429                 bus_rmb();
430
431                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
432                              MLX4_CQE_OPCODE_ERROR)) {
433                         struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe;
434
435                         en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
436                                cqe_err->vendor_err_syndrome,
437                                cqe_err->syndrome);
438                 }
439
440                 /* Skip over last polled CQE */
441                 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
442
443                 do {
444                         txbbs_skipped += last_nr_txbb;
445                         ring_index = (ring_index + last_nr_txbb) & size_mask;
446                         if (ring->tx_info[ring_index].ts_requested)
447                                 timestamp = mlx4_en_get_cqe_ts(cqe);
448
449                         /* free next descriptor */
450                         last_nr_txbb = mlx4_en_free_tx_desc(
451                                         priv, ring, ring_index,
452                                         !!((ring_cons + txbbs_skipped) &
453                                         ring->size), timestamp);
454
455                         mlx4_en_stamp_wqe(priv, ring, stamp_index,
456                                           !!((ring_cons + txbbs_stamp) &
457                                                 ring->size));
458                         stamp_index = ring_index;
459                         txbbs_stamp = txbbs_skipped;
460                         packets++;
461                         bytes += ring->tx_info[ring_index].nr_bytes;
462                 } while ((++done < budget) && (ring_index != new_index));
463
464                 ++cons_index;
465                 index = cons_index & size_mask;
466                 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
467         }
468
469
470         /*
471          * To prevent CQ overflow we first update CQ consumer and only then
472          * the ring consumer.
473          */
474         mcq->cons_index = cons_index;
475         mlx4_cq_set_ci(mcq);
476         wmb();
477
478         /* we want to dirty this cache line once */
479         ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb;
480         ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped;
481
482 #if 0 // AKAROS_PORT
483         netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
484
485         /*
486          * Wakeup Tx queue if this stopped, and at least 1 packet
487          * was completed
488          */
489         if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) {
490                 netif_tx_wake_queue(ring->tx_queue);
491                 ring->wake_queue++;
492         }
493 #endif
494         return done < budget;
495 }
496
497 static void mlx4_en_poll_tx_cq(uint32_t srcid, long a0, long a1, long a2);
498
499 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
500 {
501         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
502         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
503
504         if (likely(priv->port_up))
505 #if 0 // AKAROS_PORT
506                 napi_schedule_irqoff(&cq->napi);
507 #else
508                 send_kernel_message(core_id(), mlx4_en_poll_tx_cq, (long)cq,
509                                     0, 0, KMSG_ROUTINE);
510 #endif
511         else
512                 mlx4_en_arm_cq(priv, cq);
513 }
514
515 /* TX CQ polling - called by NAPI */
516 static void mlx4_en_poll_tx_cq(uint32_t srcid, long a0, long a1, long a2)
517 {
518         struct mlx4_en_cq *cq = (struct mlx4_en_cq *)a0;
519         struct ether *dev = cq->dev;
520         struct mlx4_en_priv *priv = netdev_priv(dev);
521         int clean_complete;
522
523         clean_complete = mlx4_en_process_tx_cq(dev, cq);
524         if (!clean_complete)
525                 return;
526
527         mlx4_en_arm_cq(priv, cq);
528 }
529
530 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
531                                                       struct mlx4_en_tx_ring *ring,
532                                                       uint32_t index,
533                                                       unsigned int desc_size)
534 {
535         uint32_t copy = (ring->size - index) * TXBB_SIZE;
536         int i;
537
538         for (i = desc_size - copy - 4; i >= 0; i -= 4) {
539                 if ((i & (TXBB_SIZE - 1)) == 0)
540                         wmb();
541
542                 *((uint32_t *) (ring->buf + i)) =
543                         *((uint32_t *) (ring->bounce_buf + copy + i));
544         }
545
546         for (i = copy - 4; i >= 4 ; i -= 4) {
547                 if ((i & (TXBB_SIZE - 1)) == 0)
548                         wmb();
549
550                 *((uint32_t *) (ring->buf + index * TXBB_SIZE + i)) =
551                         *((uint32_t *) (ring->bounce_buf + i));
552         }
553
554         /* Return real descriptor location */
555         return ring->buf + index * TXBB_SIZE;
556 }
557
558 #if 0 // AKAROS_PORT
559 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
560  *
561  * It seems strange we do not simply use skb_copy_bits().
562  * This would allow to inline all skbs iff skb->len <= inline_thold
563  *
564  * Note that caller already checked skb was not a gso packet
565  */
566 static bool is_inline(int inline_thold, const struct sk_buff *skb,
567                       const struct skb_shared_info *shinfo,
568                       void **pfrag)
569 {
570         void *ptr;
571
572         if (skb->len > inline_thold || !inline_thold)
573                 return false;
574
575         if (shinfo->nr_frags == 1) {
576                 ptr = skb_frag_address_safe(&shinfo->frags[0]);
577                 if (unlikely(!ptr))
578                         return false;
579                 *pfrag = ptr;
580                 return true;
581         }
582         if (shinfo->nr_frags)
583                 return false;
584         return true;
585 }
586
587 static int inline_size(const struct sk_buff *skb)
588 {
589         if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
590             <= MLX4_INLINE_ALIGN)
591                 return ALIGN(skb->len + CTRL_SIZE +
592                              sizeof(struct mlx4_wqe_inline_seg), 16);
593         else
594                 return ALIGN(skb->len + CTRL_SIZE + 2 *
595                              sizeof(struct mlx4_wqe_inline_seg), 16);
596 }
597
598 static int get_real_size(const struct sk_buff *skb,
599                          const struct skb_shared_info *shinfo,
600                          struct ether *dev,
601                          int *lso_header_size,
602                          bool *inline_ok,
603                          void **pfrag)
604 {
605         struct mlx4_en_priv *priv = netdev_priv(dev);
606         int real_size;
607
608         if (shinfo->gso_size) {
609                 *inline_ok = false;
610                 if (skb->encapsulation)
611                         *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
612                 else
613                         *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
614                 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
615                         ALIGN(*lso_header_size + 4, DS_SIZE);
616                 if (unlikely(*lso_header_size != skb_headlen(skb))) {
617                         /* We add a segment for the skb linear buffer only if
618                          * it contains data */
619                         if (*lso_header_size < skb_headlen(skb))
620                                 real_size += DS_SIZE;
621                         else {
622                                 if (netif_msg_tx_err(priv))
623                                         en_warn(priv, "Non-linear headers\n");
624                                 return 0;
625                         }
626                 }
627         } else {
628                 *lso_header_size = 0;
629                 *inline_ok = is_inline(priv->prof->inline_thold, skb,
630                                        shinfo, pfrag);
631
632                 if (*inline_ok)
633                         real_size = inline_size(skb);
634                 else
635                         real_size = CTRL_SIZE +
636                                     (shinfo->nr_frags + 1) * DS_SIZE;
637         }
638
639         return real_size;
640 }
641
642 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
643                              const struct sk_buff *skb,
644                              const struct skb_shared_info *shinfo,
645                              int real_size, uint16_t *vlan_tag,
646                              int tx_ind, void *fragptr)
647 {
648         struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
649         int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
650         unsigned int hlen = skb_headlen(skb);
651
652         if (skb->len <= spc) {
653                 if (likely(skb->len >= MIN_PKT_LEN)) {
654                         inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
655                 } else {
656                         inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
657                         memset(((void *)(inl + 1)) + skb->len, 0,
658                                MIN_PKT_LEN - skb->len);
659                 }
660                 skb_copy_from_linear_data(skb, inl + 1, hlen);
661                 if (shinfo->nr_frags)
662                         memcpy(((void *)(inl + 1)) + hlen, fragptr,
663                                skb_frag_size(&shinfo->frags[0]));
664
665         } else {
666                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
667                 if (hlen <= spc) {
668                         skb_copy_from_linear_data(skb, inl + 1, hlen);
669                         if (hlen < spc) {
670                                 memcpy(((void *)(inl + 1)) + hlen,
671                                        fragptr, spc - hlen);
672                                 fragptr +=  spc - hlen;
673                         }
674                         inl = (void *) (inl + 1) + spc;
675                         memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
676                 } else {
677                         skb_copy_from_linear_data(skb, inl + 1, spc);
678                         inl = (void *) (inl + 1) + spc;
679                         skb_copy_from_linear_data_offset(skb, spc, inl + 1,
680                                                          hlen - spc);
681                         if (shinfo->nr_frags)
682                                 memcpy(((void *)(inl + 1)) + hlen - spc,
683                                        fragptr,
684                                        skb_frag_size(&shinfo->frags[0]));
685                 }
686
687                 bus_wmb();
688                 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
689         }
690 }
691 #endif
692
693 uint16_t mlx4_en_select_queue(struct ether *dev, struct sk_buff *skb,
694                               void *accel_priv,
695                               select_queue_fallback_t fallback)
696 {
697         panic("Disabled");
698 #if 0 // AKAROS_PORT
699         struct mlx4_en_priv *priv = netdev_priv(dev);
700         uint16_t rings_p_up = priv->num_tx_rings_p_up;
701         uint8_t up = 0;
702
703         if (dev->num_tc)
704                 return skb_tx_hash(dev, skb);
705
706         if (skb_vlan_tag_present(skb))
707                 up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT;
708
709         return fallback(dev, skb) % rings_p_up + up * rings_p_up;
710 #endif
711 }
712
713 #if 0 // AKAROS_PORT
714 static void mlx4_bf_copy(void __iomem *dst, const void *src,
715                          unsigned int bytecnt)
716 {
717         __iowrite64_copy(dst, src, bytecnt / 8);
718 }
719 #endif
720
721 netdev_tx_t mlx4_send_packet(struct block *block, struct ether *dev)
722 {
723         struct mlx4_en_priv *priv = netdev_priv(dev);
724         struct mlx4_en_tx_ring *ring;
725         struct mlx4_en_tx_desc *tx_desc;
726         struct mlx4_wqe_data_seg *data;
727         struct mlx4_en_tx_info *tx_info;
728         int nr_txbb;
729         int desc_size;
730         int real_size;
731         uint32_t index;
732         __be32 op_own;
733         bool bounce = false;
734         dma_addr_t dma = 0;
735         uint32_t byte_count = 0;
736
737         if (!priv->port_up)
738                 goto tx_drop;
739
740         ring = priv->tx_ring[0]; /* TODO multi-queue support */
741
742         real_size = CTRL_SIZE + DS_SIZE;
743         if (unlikely(!real_size))
744                 goto tx_drop;
745
746         /* Align descriptor to TXBB size */
747         desc_size = ALIGN(real_size, TXBB_SIZE);
748         nr_txbb = desc_size / TXBB_SIZE;
749         if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
750                 en_warn(priv, "Oversized header or SG list\n");
751                 goto tx_drop;
752         }
753
754         index = ring->prod & ring->size_mask;
755
756         /* See if we have enough space for whole descriptor TXBB for setting
757          * SW ownership on next descriptor; if not, use a bounce buffer. */
758         if (likely(index + nr_txbb <= ring->size))
759                 tx_desc = ring->buf + index * TXBB_SIZE;
760         else {
761                 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
762                 bounce = true;
763         }
764
765         /* Save skb in tx_info ring */
766         tx_info = &ring->tx_info[index];
767         tx_info->block = block;
768         tx_info->nr_txbb = nr_txbb;
769
770         data = &tx_desc->data;
771
772         /* valid only for none inline segments */
773         tx_info->data_offset = (void *)data - (void *)tx_desc;
774         tx_info->inl = 0;
775         tx_info->linear = 1;
776         tx_info->nr_maps = 1;
777
778         byte_count = BLEN(block);
779
780         dma = dma_map_single(0, block->rp, BLEN(block), DMA_TO_DEVICE);
781         if (unlikely(dma_mapping_error(0, dma)))
782                 goto tx_drop_unmap;
783
784         data->addr = cpu_to_be64(dma);
785         data->lkey = ring->mr_key;
786         bus_wmb();
787         data->byte_count = cpu_to_be32(byte_count);
788
789         /* tx completion can avoid cache line miss for common cases */
790         tx_info->map0_dma = dma;
791         tx_info->map0_byte_count = byte_count;
792
793         /*
794          * For timestamping add flag to skb_shinfo and
795          * set flag for further reference
796          */
797         tx_info->ts_requested = 0;
798
799         /* Prepare ctrl segement apart opcode+ownership */
800         tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
801
802         if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
803                 struct ethhdr *ethh;
804
805                 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
806                  * so that VFs and PF can communicate with each other
807                  */
808                 ethh = (struct ethhdr *)block->rp;
809                 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
810                 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
811         }
812
813         /* Normal (Non LSO) packet */
814         op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
815                 ((ring->prod & ring->size) ?
816                  cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
817         tx_info->nr_bytes = MAX_T(unsigned int, BLEN(block), ETH_ZLEN);
818         ring->packets++;
819         ring->bytes += tx_info->nr_bytes;
820         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, BLEN(block));
821
822         ring->prod += nr_txbb;
823
824         /* If we used a bounce buffer then copy descriptor back into place */
825         if (unlikely(bounce))
826                 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
827
828         real_size = (real_size / 16) & 0x3f; /* Clear fence bit. */
829
830         tx_desc->ctrl.vlan_tag = 0;
831         tx_desc->ctrl.ins_vlan = 0;
832         tx_desc->ctrl.fence_size = real_size;
833
834         /* Ensure new descriptor hits memory
835          * before setting ownership of this descriptor to HW
836          */
837         bus_wmb();
838         tx_desc->ctrl.owner_opcode = op_own;
839         wmb();
840         /* Since there is no iowrite*_native() that writes the
841          * value as is, without byteswapping - using the one
842          * the doesn't do byteswapping in the relevant arch
843          * endianness.
844          */
845 #if defined(__LITTLE_ENDIAN)
846         write32(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL);
847 #else
848         iowrite32be(ring->doorbell_qpn,
849                     ring->bf.uar->map + MLX4_SEND_DOORBELL);
850 #endif
851
852         return NETDEV_TX_OK;
853
854 tx_drop_unmap:
855         en_err(priv, "DMA mapping error\n");
856
857 tx_drop:
858         priv->stats.tx_dropped++;
859         return NETDEV_TX_OK;
860 }
861
862 #if 0 // AKAROS_PORT
863 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct ether *dev)
864 {
865         struct skb_shared_info *shinfo = skb_shinfo(skb);
866         struct mlx4_en_priv *priv = netdev_priv(dev);
867         struct device *ddev = priv->ddev;
868         struct mlx4_en_tx_ring *ring;
869         struct mlx4_en_tx_desc *tx_desc;
870         struct mlx4_wqe_data_seg *data;
871         struct mlx4_en_tx_info *tx_info;
872         int tx_ind = 0;
873         int nr_txbb;
874         int desc_size;
875         int real_size;
876         uint32_t index, bf_index;
877         __be32 op_own;
878         uint16_t vlan_tag = 0;
879         int i_frag;
880         int lso_header_size;
881         void *fragptr = NULL;
882         bool bounce = false;
883         bool send_doorbell;
884         bool stop_queue;
885         bool inline_ok;
886         uint32_t ring_cons;
887
888         if (!priv->port_up)
889                 goto tx_drop;
890
891         tx_ind = skb_get_queue_mapping(skb);
892         ring = priv->tx_ring[tx_ind];
893
894         /* fetch ring->cons far ahead before needing it to avoid stall */
895         ring_cons = ACCESS_ONCE(ring->cons);
896
897         real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
898                                   &inline_ok, &fragptr);
899         if (unlikely(!real_size))
900                 goto tx_drop;
901
902         /* Align descriptor to TXBB size */
903         desc_size = ALIGN(real_size, TXBB_SIZE);
904         nr_txbb = desc_size / TXBB_SIZE;
905         if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
906                 if (netif_msg_tx_err(priv))
907                         en_warn(priv, "Oversized header or SG list\n");
908                 goto tx_drop;
909         }
910
911         if (skb_vlan_tag_present(skb))
912                 vlan_tag = skb_vlan_tag_get(skb);
913
914
915         netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
916
917         /* Track current inflight packets for performance analysis */
918         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
919                          (uint32_t)(ring->prod - ring_cons - 1));
920
921         /* Packet is good - grab an index and transmit it */
922         index = ring->prod & ring->size_mask;
923         bf_index = ring->prod;
924
925         /* See if we have enough space for whole descriptor TXBB for setting
926          * SW ownership on next descriptor; if not, use a bounce buffer. */
927         if (likely(index + nr_txbb <= ring->size))
928                 tx_desc = ring->buf + index * TXBB_SIZE;
929         else {
930                 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
931                 bounce = true;
932         }
933
934         /* Save skb in tx_info ring */
935         tx_info = &ring->tx_info[index];
936         tx_info->skb = skb;
937         tx_info->nr_txbb = nr_txbb;
938
939         data = &tx_desc->data;
940         if (lso_header_size)
941                 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4,
942                                                       DS_SIZE));
943
944         /* valid only for none inline segments */
945         tx_info->data_offset = (void *)data - (void *)tx_desc;
946
947         tx_info->inl = inline_ok;
948
949         tx_info->linear = (lso_header_size < skb_headlen(skb) &&
950                            !inline_ok) ? 1 : 0;
951
952         tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
953         data += tx_info->nr_maps - 1;
954
955         if (!tx_info->inl) {
956                 dma_addr_t dma = 0;
957                 uint32_t byte_count = 0;
958
959                 /* Map fragments if any */
960                 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
961                         const struct skb_frag_struct *frag;
962
963                         frag = &shinfo->frags[i_frag];
964                         byte_count = skb_frag_size(frag);
965                         dma = skb_frag_dma_map(ddev, frag,
966                                                0, byte_count,
967                                                DMA_TO_DEVICE);
968                         if (dma_mapping_error(ddev, dma))
969                                 goto tx_drop_unmap;
970
971                         data->addr = cpu_to_be64(dma);
972                         data->lkey = ring->mr_key;
973                         bus_wmb();
974                         data->byte_count = cpu_to_be32(byte_count);
975                         --data;
976                 }
977
978                 /* Map linear part if needed */
979                 if (tx_info->linear) {
980                         byte_count = skb_headlen(skb) - lso_header_size;
981
982                         dma = dma_map_single(ddev, skb->data +
983                                              lso_header_size, byte_count,
984                                              PCI_DMA_TODEVICE);
985                         if (dma_mapping_error(ddev, dma))
986                                 goto tx_drop_unmap;
987
988                         data->addr = cpu_to_be64(dma);
989                         data->lkey = ring->mr_key;
990                         bus_wmb();
991                         data->byte_count = cpu_to_be32(byte_count);
992                 }
993                 /* tx completion can avoid cache line miss for common cases */
994                 tx_info->map0_dma = dma;
995                 tx_info->map0_byte_count = byte_count;
996         }
997
998         /*
999          * For timestamping add flag to skb_shinfo and
1000          * set flag for further reference
1001          */
1002         tx_info->ts_requested = 0;
1003         if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
1004                      shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
1005                 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
1006                 tx_info->ts_requested = 1;
1007         }
1008
1009         /* Prepare ctrl segement apart opcode+ownership, which depends on
1010          * whether LSO is used */
1011         tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
1012         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1013                 if (!skb->encapsulation)
1014                         tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1015                                                                  MLX4_WQE_CTRL_TCP_UDP_CSUM);
1016                 else
1017                         tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
1018                 ring->tx_csum++;
1019         }
1020
1021         if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
1022                 struct ethhdr *ethh;
1023
1024                 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
1025                  * so that VFs and PF can communicate with each other
1026                  */
1027                 ethh = (struct ethhdr *)skb->data;
1028                 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
1029                 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
1030         }
1031
1032         /* Handle LSO (TSO) packets */
1033         if (lso_header_size) {
1034                 int i;
1035
1036                 /* Mark opcode as LSO */
1037                 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
1038                         ((ring->prod & ring->size) ?
1039                                 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1040
1041                 /* Fill in the LSO prefix */
1042                 tx_desc->lso.mss_hdr_size = cpu_to_be32(
1043                         shinfo->gso_size << 16 | lso_header_size);
1044
1045                 /* Copy headers;
1046                  * note that we already verified that it is linear */
1047                 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
1048
1049                 ring->tso_packets++;
1050
1051                 i = ((skb->len - lso_header_size) / shinfo->gso_size) +
1052                         !!((skb->len - lso_header_size) % shinfo->gso_size);
1053                 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
1054                 ring->packets += i;
1055         } else {
1056                 /* Normal (Non LSO) packet */
1057                 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1058                         ((ring->prod & ring->size) ?
1059                          cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1060                 tx_info->nr_bytes = MAX_T(unsigned int, skb->len, ETH_ZLEN);
1061                 ring->packets++;
1062         }
1063         ring->bytes += tx_info->nr_bytes;
1064         netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
1065         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
1066
1067         if (tx_info->inl)
1068                 build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag,
1069                                  tx_ind, fragptr);
1070
1071         if (skb->encapsulation) {
1072                 struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb);
1073                 if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP)
1074                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
1075                 else
1076                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
1077         }
1078
1079         ring->prod += nr_txbb;
1080
1081         /* If we used a bounce buffer then copy descriptor back into place */
1082         if (unlikely(bounce))
1083                 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
1084
1085         skb_tx_timestamp(skb);
1086
1087         /* Check available TXBBs And 2K spare for prefetch */
1088         stop_queue = (int)(ring->prod - ring_cons) >
1089                       ring->size - HEADROOM - MAX_DESC_TXBBS;
1090         if (unlikely(stop_queue)) {
1091                 netif_tx_stop_queue(ring->tx_queue);
1092                 ring->queue_stopped++;
1093         }
1094         send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
1095
1096         real_size = (real_size / 16) & 0x3f;
1097
1098         if (ring->bf_enabled && desc_size <= MAX_BF && !bounce &&
1099             !skb_vlan_tag_present(skb) && send_doorbell) {
1100                 tx_desc->ctrl.bf_qpn = ring->doorbell_qpn |
1101                                        cpu_to_be32(real_size);
1102
1103                 op_own |= cpu_to_be32((bf_index & 0xffff) << 8);
1104                 /* Ensure new descriptor hits memory
1105                  * before setting ownership of this descriptor to HW
1106                  */
1107                 bus_wmb();
1108                 tx_desc->ctrl.owner_opcode = op_own;
1109
1110                 wmb();
1111
1112                 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
1113                              desc_size);
1114
1115                 wmb();
1116
1117                 ring->bf.offset ^= ring->bf.buf_size;
1118         } else {
1119                 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
1120                 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
1121                         !!skb_vlan_tag_present(skb);
1122                 tx_desc->ctrl.fence_size = real_size;
1123
1124                 /* Ensure new descriptor hits memory
1125                  * before setting ownership of this descriptor to HW
1126                  */
1127                 bus_wmb();
1128                 tx_desc->ctrl.owner_opcode = op_own;
1129                 if (send_doorbell) {
1130                         wmb();
1131                         /* Since there is no iowrite*_native() that writes the
1132                          * value as is, without byteswapping - using the one
1133                          * the doesn't do byteswapping in the relevant arch
1134                          * endianness.
1135                          */
1136 #if defined(__LITTLE_ENDIAN)
1137                         iowrite32(
1138 #else
1139                         iowrite32be(
1140 #endif
1141                                   ring->doorbell_qpn,
1142                                   ring->bf.uar->map + MLX4_SEND_DOORBELL);
1143                 } else {
1144                         ring->xmit_more++;
1145                 }
1146         }
1147
1148         if (unlikely(stop_queue)) {
1149                 /* If queue was emptied after the if (stop_queue) , and before
1150                  * the netif_tx_stop_queue() - need to wake the queue,
1151                  * or else it will remain stopped forever.
1152                  * Need a memory barrier to make sure ring->cons was not
1153                  * updated before queue was stopped.
1154                  */
1155                 rmb();
1156
1157                 ring_cons = ACCESS_ONCE(ring->cons);
1158                 if (unlikely(((int)(ring->prod - ring_cons)) <=
1159                              ring->size - HEADROOM - MAX_DESC_TXBBS)) {
1160                         netif_tx_wake_queue(ring->tx_queue);
1161                         ring->wake_queue++;
1162                 }
1163         }
1164         return NETDEV_TX_OK;
1165
1166 tx_drop_unmap:
1167         en_err(priv, "DMA mapping error\n");
1168
1169         while (++i_frag < shinfo->nr_frags) {
1170                 ++data;
1171                 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr),
1172                                be32_to_cpu(data->byte_count),
1173                                PCI_DMA_TODEVICE);
1174         }
1175
1176 tx_drop:
1177         dev_kfree_skb_any(skb);
1178         priv->stats.tx_dropped++;
1179         return NETDEV_TX_OK;
1180 }
1181 #endif
1182