mlx4: /dev/ -> /dev_vfs/
[akaros.git] / kern / drivers / net / mlx4 / en_rx.c
1 /*
2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33
34 #include <linux_compat.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/mlx4/qp.h>
37 #include "mlx4_en.h"
38
39 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
40                             struct mlx4_en_rx_alloc *page_alloc,
41                             const struct mlx4_en_frag_info *frag_info,
42                             gfp_t _gfp)
43 {
44         int order;
45         struct page *page;
46         dma_addr_t dma;
47
48         for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
49                 gfp_t gfp = _gfp;
50
51                 if (order)
52                         gfp |= __GFP_COMP | __GFP_NOWARN;
53                 page = kva2page(get_cont_pages(order, gfp));
54                 if (likely(page))
55                         break;
56                 if (--order < 0 ||
57                     ((PAGE_SIZE << order) < frag_info->frag_size))
58                         return -ENOMEM;
59         }
60         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
61                            PCI_DMA_FROMDEVICE);
62         if (dma_mapping_error(priv->ddev, dma)) {
63                 page_decref(page);
64                 return -ENOMEM;
65         }
66         page_alloc->page_size = PAGE_SIZE << order;
67         page_alloc->page = page;
68         page_alloc->dma = dma;
69         page_alloc->page_offset = 0;
70         /* Not doing get_page() for each frag is a big win
71          * on asymetric workloads. Note we can not use atomic_set().
72          */
73         atomic_add(&page->pg_kref.refcount,
74                    page_alloc->page_size / frag_info->frag_stride - 1);
75         return 0;
76 }
77
78 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
79                                struct mlx4_en_rx_desc *rx_desc,
80                                struct mlx4_en_rx_alloc *frags,
81                                struct mlx4_en_rx_alloc *ring_alloc,
82                                gfp_t gfp)
83 {
84         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
85         const struct mlx4_en_frag_info *frag_info;
86         struct page *page;
87         dma_addr_t dma;
88         int i;
89
90         for (i = 0; i < priv->num_frags; i++) {
91                 frag_info = &priv->frag_info[i];
92                 page_alloc[i] = ring_alloc[i];
93                 page_alloc[i].page_offset += frag_info->frag_stride;
94
95                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
96                     ring_alloc[i].page_size)
97                         continue;
98
99                 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
100                         goto out;
101         }
102
103         for (i = 0; i < priv->num_frags; i++) {
104                 frags[i] = ring_alloc[i];
105                 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
106                 ring_alloc[i] = page_alloc[i];
107                 rx_desc->data[i].addr = cpu_to_be64(dma);
108         }
109
110         return 0;
111
112 out:
113         while (i--) {
114                 if (page_alloc[i].page != ring_alloc[i].page) {
115                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
116                                 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
117                         page = page_alloc[i].page;
118                         atomic_set(&page->pg_kref.refcount, 1);
119                         page_decref(page);
120                 }
121         }
122         return -ENOMEM;
123 }
124
125 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
126                               struct mlx4_en_rx_alloc *frags,
127                               int i)
128 {
129         const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
130         uint32_t next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
131
132
133         if (next_frag_end > frags[i].page_size)
134                 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
135                                PCI_DMA_FROMDEVICE);
136
137         if (frags[i].page)
138                 page_decref(frags[i].page);
139 }
140
141 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
142                                   struct mlx4_en_rx_ring *ring)
143 {
144         int i;
145         struct mlx4_en_rx_alloc *page_alloc;
146
147         for (i = 0; i < priv->num_frags; i++) {
148                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
149
150                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
151                                      frag_info, MEM_WAIT | __GFP_COLD))
152                         goto out;
153
154                 en_dbg(DRV, priv, "  frag %d allocator: - size:%d frags:%d\n",
155                        i, ring->page_alloc[i].page_size,
156                        atomic_read(&ring->page_alloc[i].page->pg_kref.refcount));
157         }
158         return 0;
159
160 out:
161         while (i--) {
162                 struct page *page;
163
164                 page_alloc = &ring->page_alloc[i];
165                 dma_unmap_page(priv->ddev, page_alloc->dma,
166                                page_alloc->page_size, PCI_DMA_FROMDEVICE);
167                 page = page_alloc->page;
168                 atomic_set(&page->pg_kref.refcount, 1);
169                 page_decref(page);
170                 page_alloc->page = NULL;
171         }
172         return -ENOMEM;
173 }
174
175 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
176                                       struct mlx4_en_rx_ring *ring)
177 {
178         panic("Disabled");
179 #if 0 // AKAROS_PORT
180         struct mlx4_en_rx_alloc *page_alloc;
181         int i;
182
183         for (i = 0; i < priv->num_frags; i++) {
184                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
185
186                 page_alloc = &ring->page_alloc[i];
187                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
188                        i, page_count(page_alloc->page));
189
190                 dma_unmap_page(priv->ddev, page_alloc->dma,
191                                 page_alloc->page_size, PCI_DMA_FROMDEVICE);
192                 while (page_alloc->page_offset + frag_info->frag_stride <
193                        page_alloc->page_size) {
194                         page_decref(page_alloc->page);
195                         page_alloc->page_offset += frag_info->frag_stride;
196                 }
197                 page_alloc->page = NULL;
198         }
199 #endif
200 }
201
202 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
203                                  struct mlx4_en_rx_ring *ring, int index)
204 {
205         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
206         int possible_frags;
207         int i;
208
209         /* Set size and memtype fields */
210         for (i = 0; i < priv->num_frags; i++) {
211                 rx_desc->data[i].byte_count =
212                         cpu_to_be32(priv->frag_info[i].frag_size);
213                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
214         }
215
216         /* If the number of used fragments does not fill up the ring stride,
217          * remaining (unused) fragments must be padded with null address/size
218          * and a special memory key */
219         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
220         for (i = priv->num_frags; i < possible_frags; i++) {
221                 rx_desc->data[i].byte_count = 0;
222                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
223                 rx_desc->data[i].addr = 0;
224         }
225 }
226
227 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
228                                    struct mlx4_en_rx_ring *ring, int index,
229                                    gfp_t gfp)
230 {
231         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
232         struct mlx4_en_rx_alloc *frags = ring->rx_info +
233                                         (index << priv->log_rx_info);
234
235         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
236 }
237
238 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
239 {
240         assert(!((uint32_t)(ring->prod - ring->cons) > ring->actual_size));
241         return ring->prod == ring->cons;
242 }
243
244 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
245 {
246         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
247 }
248
249 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
250                                  struct mlx4_en_rx_ring *ring,
251                                  int index)
252 {
253         struct mlx4_en_rx_alloc *frags;
254         int nr;
255
256         frags = ring->rx_info + (index << priv->log_rx_info);
257         for (nr = 0; nr < priv->num_frags; nr++) {
258                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
259                 mlx4_en_free_frag(priv, frags, nr);
260         }
261 }
262
263 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
264 {
265         struct mlx4_en_rx_ring *ring;
266         int ring_ind;
267         int buf_ind;
268         int new_size;
269
270         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
271                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
272                         ring = priv->rx_ring[ring_ind];
273
274                         if (mlx4_en_prepare_rx_desc(priv, ring,
275                                                     ring->actual_size,
276                                                     MEM_WAIT | __GFP_COLD)) {
277                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
278                                         en_err(priv, "Failed to allocate enough rx buffers\n");
279                                         return -ENOMEM;
280                                 } else {
281                                         new_size = ROUNDDOWNPWR2(ring->actual_size);
282                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
283                                                 ring->actual_size, new_size);
284                                         goto reduce_rings;
285                                 }
286                         }
287                         ring->actual_size++;
288                         ring->prod++;
289                 }
290         }
291         return 0;
292
293 reduce_rings:
294         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
295                 ring = priv->rx_ring[ring_ind];
296                 while (ring->actual_size > new_size) {
297                         ring->actual_size--;
298                         ring->prod--;
299                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
300                 }
301         }
302
303         return 0;
304 }
305
306 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
307                                 struct mlx4_en_rx_ring *ring)
308 {
309         int index;
310
311         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
312                ring->cons, ring->prod);
313
314         /* Unmap and free Rx buffers */
315         while (!mlx4_en_is_ring_empty(ring)) {
316                 index = ring->cons & ring->size_mask;
317                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
318                 mlx4_en_free_rx_desc(priv, ring, index);
319                 ++ring->cons;
320         }
321 }
322
323 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
324 {
325         int i;
326         int num_of_eqs;
327         int num_rx_rings;
328         struct mlx4_dev *dev = mdev->dev;
329
330         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
331                 if (!dev->caps.comp_pool)
332                         num_of_eqs = MAX_T(int, MIN_RX_RINGS,
333                                            MIN_T(int, dev->caps.num_comp_vectors, DEF_RX_RINGS));
334                 else
335                         num_of_eqs = MIN_T(int, MAX_MSIX_P_PORT,
336                                            dev->caps.comp_pool / dev->caps.num_ports) - 1;
337
338                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
339                         MIN_T(int, num_of_eqs,
340                               netif_get_num_default_rss_queues());
341                 mdev->profile.prof[i].rx_ring_num =
342                         ROUNDDOWNPWR2(num_rx_rings);
343         }
344 }
345
346 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
347                            struct mlx4_en_rx_ring **pring,
348                            uint32_t size, uint16_t stride, int node)
349 {
350         struct mlx4_en_dev *mdev = priv->mdev;
351         struct mlx4_en_rx_ring *ring;
352         int err = -ENOMEM;
353         int tmp;
354
355         ring = kzalloc_node(sizeof(*ring), MEM_WAIT, node);
356         if (!ring) {
357                 ring = kzmalloc(sizeof(*ring), MEM_WAIT);
358                 if (!ring) {
359                         en_err(priv, "Failed to allocate RX ring structure\n");
360                         return -ENOMEM;
361                 }
362         }
363
364         ring->prod = 0;
365         ring->cons = 0;
366         ring->size = size;
367         ring->size_mask = size - 1;
368         ring->stride = stride;
369         ring->log_stride = ffs(ring->stride) - 1;
370         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
371
372         tmp = size * ROUNDUPPWR2(MLX4_EN_MAX_RX_FRAGS * sizeof(struct mlx4_en_rx_alloc));
373         ring->rx_info = vmalloc_node(tmp, node);
374         if (!ring->rx_info) {
375                 ring->rx_info = vmalloc(tmp);
376                 if (!ring->rx_info) {
377                         err = -ENOMEM;
378                         goto err_ring;
379                 }
380         }
381
382         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
383                  ring->rx_info, tmp);
384
385         /* Allocate HW buffers on provided NUMA node */
386         set_dev_node(&mdev->dev->persist->pdev->dev, node);
387         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
388                                  ring->buf_size, 2 * PAGE_SIZE);
389         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
390         if (err)
391                 goto err_info;
392
393         err = mlx4_en_map_buffer(&ring->wqres.buf);
394         if (err) {
395                 en_err(priv, "Failed to map RX buffer\n");
396                 goto err_hwq;
397         }
398         ring->buf = ring->wqres.buf.direct.buf;
399
400         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
401
402         *pring = ring;
403         return 0;
404
405 err_hwq:
406         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
407 err_info:
408         panic("Not implemented");
409 #if 0 // AKAROS_PORT
410         vfree(ring->rx_info);
411 #endif
412         ring->rx_info = NULL;
413 err_ring:
414         kfree(ring);
415         *pring = NULL;
416
417         return err;
418 }
419
420 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
421 {
422         struct mlx4_en_rx_ring *ring;
423         int i;
424         int ring_ind;
425         int err;
426         int stride = ROUNDUPPWR2(sizeof(struct mlx4_en_rx_desc) + DS_SIZE * priv->num_frags);
427
428         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
429                 ring = priv->rx_ring[ring_ind];
430
431                 ring->prod = 0;
432                 ring->cons = 0;
433                 ring->actual_size = 0;
434                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
435
436                 ring->stride = stride;
437                 if (ring->stride <= TXBB_SIZE)
438                         ring->buf += TXBB_SIZE;
439
440                 ring->log_stride = ffs(ring->stride) - 1;
441                 ring->buf_size = ring->size * ring->stride;
442
443                 memset(ring->buf, 0, ring->buf_size);
444                 mlx4_en_update_rx_prod_db(ring);
445
446                 /* Initialize all descriptors */
447                 for (i = 0; i < ring->size; i++)
448                         mlx4_en_init_rx_desc(priv, ring, i);
449
450                 /* Initialize page allocators */
451                 err = mlx4_en_init_allocator(priv, ring);
452                 if (err) {
453                         en_err(priv, "Failed initializing ring allocator\n");
454                         if (ring->stride <= TXBB_SIZE)
455                                 ring->buf -= TXBB_SIZE;
456                         ring_ind--;
457                         goto err_allocator;
458                 }
459         }
460         err = mlx4_en_fill_rx_buffers(priv);
461         if (err)
462                 goto err_buffers;
463
464         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
465                 ring = priv->rx_ring[ring_ind];
466
467                 ring->size_mask = ring->actual_size - 1;
468                 mlx4_en_update_rx_prod_db(ring);
469         }
470
471         return 0;
472
473 err_buffers:
474         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
475                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
476
477         ring_ind = priv->rx_ring_num - 1;
478 err_allocator:
479         while (ring_ind >= 0) {
480                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
481                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
482                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
483                 ring_ind--;
484         }
485         return err;
486 }
487
488 /* We recover from out of memory by scheduling our napi poll
489  * function (mlx4_en_process_cq), which tries to allocate
490  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
491  */
492 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
493 {
494         int ring;
495
496         if (!priv->port_up)
497                 return;
498
499         for (ring = 0; ring < priv->rx_ring_num; ring++) {
500                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring]))
501                         panic("Not implemented");
502 #if 0 // AKAROS_PORT
503                         napi_reschedule(&priv->rx_cq[ring]->napi);
504 #endif
505         }
506 }
507
508 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
509                              struct mlx4_en_rx_ring **pring,
510                              uint32_t size, uint16_t stride)
511 {
512         panic("Disabled");
513 #if 0 // AKAROS_PORT
514         struct mlx4_en_dev *mdev = priv->mdev;
515         struct mlx4_en_rx_ring *ring = *pring;
516
517         mlx4_en_unmap_buffer(&ring->wqres.buf);
518         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
519         vfree(ring->rx_info);
520         ring->rx_info = NULL;
521         kfree(ring);
522         *pring = NULL;
523 #ifdef CONFIG_RFS_ACCEL
524         mlx4_en_cleanup_filters(priv);
525 #endif
526 #endif
527 }
528
529 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
530                                 struct mlx4_en_rx_ring *ring)
531 {
532         mlx4_en_free_rx_buf(priv, ring);
533         if (ring->stride <= TXBB_SIZE)
534                 ring->buf -= TXBB_SIZE;
535         mlx4_en_destroy_allocator(priv, ring);
536 }
537
538
539 #if 0 // AKAROS_PORT
540 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
541                                     struct mlx4_en_rx_desc *rx_desc,
542                                     struct mlx4_en_rx_alloc *frags,
543                                     struct sk_buff *skb,
544                                     int length)
545 {
546         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
547         struct mlx4_en_frag_info *frag_info;
548         int nr;
549         dma_addr_t dma;
550
551         /* Collect used fragments while replacing them in the HW descriptors */
552         for (nr = 0; nr < priv->num_frags; nr++) {
553                 frag_info = &priv->frag_info[nr];
554                 if (length <= frag_info->frag_prefix_size)
555                         break;
556                 if (!frags[nr].page)
557                         goto fail;
558
559                 dma = be64_to_cpu(rx_desc->data[nr].addr);
560                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
561                                         DMA_FROM_DEVICE);
562
563                 /* Save page reference in skb */
564                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
565                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
566                 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
567                 skb->truesize += frag_info->frag_stride;
568                 frags[nr].page = NULL;
569         }
570         /* Adjust size of last fragment to match actual length */
571         if (nr > 0)
572                 skb_frag_size_set(&skb_frags_rx[nr - 1],
573                         length - priv->frag_info[nr - 1].frag_prefix_size);
574         return nr;
575
576 fail:
577         while (nr > 0) {
578                 nr--;
579                 __skb_frag_unref(&skb_frags_rx[nr]);
580         }
581         return 0;
582 }
583 #endif
584
585 static void dump_packet(struct mlx4_en_priv *priv,
586                         struct mlx4_en_rx_desc *rx_desc,
587                         struct mlx4_en_rx_alloc *frags,
588                         unsigned int length)
589 {
590         void *va;
591
592         va = page_address(frags[0].page) + frags[0].page_offset;
593
594         if (length <= SMALL_PACKET_SIZE) {
595                 hexdump(va, length);
596         } else {
597                 printk("priv %p num_frags %d\n", priv, priv->num_frags);
598                 hexdump(va, SMALL_PACKET_SIZE);
599         }
600 }
601
602 static void recv_packet(struct mlx4_en_priv *priv,
603                         struct mlx4_en_rx_desc *rx_desc,
604                         struct mlx4_en_rx_alloc *frags,
605                         unsigned int length)
606 {
607         struct block *block;
608         void *va;
609
610         assert(priv->num_frags == 1);
611
612         block = block_alloc(length, MEM_ATOMIC);
613         if (!block) {
614                 en_dbg(RX_ERR, priv, "Failed allocating block\n");
615                 priv->stats.rx_dropped++;
616                 return;
617         }
618
619         va = page_address(frags[0].page) + frags[0].page_offset;
620         memcpy(block->wp, va, length);
621         block->wp += length;
622
623         etheriq(priv->dev, block, 1 /* fromwire */);
624 }
625
626 #if 0 // AKAROS_PORT
627 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
628                                       struct mlx4_en_rx_desc *rx_desc,
629                                       struct mlx4_en_rx_alloc *frags,
630                                       unsigned int length)
631 {
632         struct sk_buff *skb;
633         void *va;
634         int used_frags;
635         dma_addr_t dma;
636
637         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
638         if (!skb) {
639                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
640                 return NULL;
641         }
642         skb_reserve(skb, NET_IP_ALIGN);
643         skb->len = length;
644
645         /* Get pointer to first fragment so we could copy the headers into the
646          * (linear part of the) skb */
647         va = page_address(frags[0].page) + frags[0].page_offset;
648
649         if (length <= SMALL_PACKET_SIZE) {
650                 /* We are copying all relevant data to the skb - temporarily
651                  * sync buffers for the copy */
652                 dma = be64_to_cpu(rx_desc->data[0].addr);
653                 dma_sync_single_for_cpu(priv->ddev, dma, length,
654                                         DMA_FROM_DEVICE);
655                 skb_copy_to_linear_data(skb, va, length);
656                 skb->tail += length;
657         } else {
658                 unsigned int pull_len;
659
660                 /* Move relevant fragments to skb */
661                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
662                                                         skb, length);
663                 if (unlikely(!used_frags)) {
664                         kfree_skb(skb);
665                         return NULL;
666                 }
667                 skb_shinfo(skb)->nr_frags = used_frags;
668
669                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
670                 /* Copy headers into the skb linear buffer */
671                 memcpy(skb->data, va, pull_len);
672                 skb->tail += pull_len;
673
674                 /* Skip headers in first fragment */
675                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
676
677                 /* Adjust size of first fragment */
678                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
679                 skb->data_len = length - pull_len;
680         }
681         return skb;
682 }
683
684 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
685 {
686         int i;
687         int offset = ETHERHDRSIZE;
688
689         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
690                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
691                         goto out_loopback;
692         }
693         /* Loopback found */
694         priv->loopback_ok = 1;
695
696 out_loopback:
697         dev_kfree_skb_any(skb);
698 }
699 #endif
700
701 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
702                                      struct mlx4_en_rx_ring *ring)
703 {
704         int index = ring->prod & ring->size_mask;
705
706         while ((uint32_t) (ring->prod - ring->cons) < ring->actual_size) {
707                 if (mlx4_en_prepare_rx_desc(priv, ring, index,
708                                             0 | __GFP_COLD))
709                         break;
710                 ring->prod++;
711                 index = ring->prod & ring->size_mask;
712         }
713 }
714
715 #if 0 // AKAROS_PORT
716 /* When hardware doesn't strip the vlan, we need to calculate the checksum
717  * over it and add it to the hardware's checksum calculation
718  */
719 static inline uint32_t get_fixed_vlan_csum(uint32_t hw_checksum,
720                                            struct vlan_hdr *vlanh)
721 {
722         return csum_add(hw_checksum, *(uint32_t *)vlanh);
723 }
724
725 /* Although the stack expects checksum which doesn't include the pseudo
726  * header, the HW adds it. To address that, we are subtracting the pseudo
727  * header checksum from the checksum value provided by the HW.
728  */
729 static void get_fixed_ipv4_csum(uint32_t hw_checksum, struct sk_buff *skb,
730                                 struct iphdr *iph)
731 {
732         uint16_t length_for_csum = 0;
733         uint32_t csum_pseudo_header = 0;
734
735         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
736         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
737                                                 length_for_csum, iph->protocol, 0);
738         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
739 }
740
741 #if IS_ENABLED(CONFIG_IPV6)
742 /* In IPv6 packets, besides subtracting the pseudo header checksum,
743  * we also compute/add the IP header checksum which
744  * is not added by the HW.
745  */
746 static int get_fixed_ipv6_csum(uint32_t hw_checksum, struct sk_buff *skb,
747                                struct ipv6hdr *ipv6h)
748 {
749         uint32_t csum_pseudo_hdr = 0;
750
751         if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS)
752                 return -1;
753         hw_checksum = csum_add(hw_checksum,
754                                (__force uint32_t)(ipv6h->nexthdr << 8));
755
756         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
757                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
758         csum_pseudo_hdr = csum_add(csum_pseudo_hdr,
759                                    (__force uint32_t)ipv6h->payload_len);
760         csum_pseudo_hdr = csum_add(csum_pseudo_hdr,
761                                    (__force uint32_t)be16_to_cpu(ipv6h->nexthdr));
762
763         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
764         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
765         return 0;
766 }
767 #endif
768 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
769                       int hwtstamp_rx_filter)
770 {
771         uint32_t hw_checksum = 0;
772
773         void *hdr = (uint8_t *)va + sizeof(struct ethhdr);
774
775         hw_checksum = csum_unfold((__force uint16_t)cqe->checksum);
776
777         if (((struct ethhdr *)va)->h_proto == cpu_to_be16(ETH_P_8021Q) &&
778             hwtstamp_rx_filter != HWTSTAMP_FILTER_NONE) {
779                 /* next protocol non IPv4 or IPv6 */
780                 if (((struct vlan_hdr *)hdr)->h_vlan_encapsulated_proto
781                     != cpu_to_be16(ETH_P_IP) &&
782                     ((struct vlan_hdr *)hdr)->h_vlan_encapsulated_proto
783                     != cpu_to_be16(ETH_P_IPV6))
784                         return -1;
785                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
786                 hdr += sizeof(struct vlan_hdr);
787         }
788
789         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
790                 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
791 #if IS_ENABLED(CONFIG_IPV6)
792         else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
793                 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr))
794                         return -1;
795 #endif
796         return 0;
797 }
798 #endif
799
800 int mlx4_en_process_rx_cq(struct ether *dev, struct mlx4_en_cq *cq,
801                           int budget)
802 {
803         struct mlx4_en_priv *priv = netdev_priv(dev);
804         struct mlx4_en_dev *mdev = priv->mdev;
805         struct mlx4_cqe *cqe;
806         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
807         struct mlx4_en_rx_alloc *frags;
808         struct mlx4_en_rx_desc *rx_desc;
809         struct sk_buff *skb;
810         int index;
811         int nr;
812         unsigned int length;
813         int polled = 0;
814         int ip_summed;
815         int factor = priv->cqe_factor;
816         uint64_t timestamp;
817         bool l2_tunnel;
818
819         if (!priv->port_up)
820                 return 0;
821
822         if (budget <= 0)
823                 return polled;
824
825         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
826          * descriptor offset can be deduced from the CQE index instead of
827          * reading 'cqe->index' */
828         index = cq->mcq.cons_index & ring->size_mask;
829         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
830
831         /* Process all completed CQEs */
832         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
833                     cq->mcq.cons_index & cq->size)) {
834
835                 frags = ring->rx_info + (index << priv->log_rx_info);
836                 rx_desc = ring->buf + (index << ring->log_stride);
837
838                 /*
839                  * make sure we read the CQE after we read the ownership bit
840                  */
841                 bus_rmb();
842
843                 /* Drop packet on bad receive or bad checksum */
844                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
845                                                 MLX4_CQE_OPCODE_ERROR)) {
846                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
847                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
848                                ((struct mlx4_err_cqe *)cqe)->syndrome);
849                         goto next;
850                 }
851                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
852                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
853                         goto next;
854                 }
855
856 #if 0 // AKAROS_PORT
857                 /* Check if we need to drop the packet if SRIOV is not enabled
858                  * and not performing the selftest or flb disabled
859                  */
860                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
861                         struct ethhdr *ethh;
862                         dma_addr_t dma;
863                         /* Get pointer to first fragment since we haven't
864                          * skb yet and cast it to ethhdr struct
865                          */
866                         dma = be64_to_cpu(rx_desc->data[0].addr);
867                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
868                                                 DMA_FROM_DEVICE);
869                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
870                                                  frags[0].page_offset);
871
872                         if (is_multicast_ether_addr(ethh->h_dest)) {
873                                 struct mlx4_mac_entry *entry;
874                                 struct hlist_head *bucket;
875                                 unsigned int mac_hash;
876
877                                 /* Drop the packet, since HW loopback-ed it */
878                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
879                                 bucket = &priv->mac_hash[mac_hash];
880                                 rcu_read_lock();
881                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
882                                         if (ether_addr_equal_64bits(entry->mac,
883                                                                     ethh->h_source)) {
884                                                 rcu_read_unlock();
885                                                 goto next;
886                                         }
887                                 }
888                                 rcu_read_unlock();
889                         }
890                 }
891 #endif
892
893                 /*
894                  * Packet is OK - process it.
895                  */
896                 length = be32_to_cpu(cqe->byte_cnt);
897                 length -= ring->fcs_del;
898                 ring->bytes += length;
899                 ring->packets++;
900 #if 0 // AKAROS_PORT
901                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
902                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
903 #else
904                 l2_tunnel = 0;
905 #endif
906
907                 if (likely(dev->feat & NETIF_F_RXCSUM)) {
908                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
909                                                       MLX4_CQE_STATUS_UDP)) {
910                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
911                                     cqe->checksum == cpu_to_be16(0xffff)) {
912                                         ip_summed = CHECKSUM_UNNECESSARY;
913                                         ring->csum_ok++;
914                                 } else {
915                                         ip_summed = CHECKSUM_NONE;
916                                         ring->csum_none++;
917                                 }
918                         } else {
919                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
920                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
921                                                                MLX4_CQE_STATUS_IPV6))) {
922                                         ip_summed = CHECKSUM_COMPLETE;
923                                         ring->csum_complete++;
924                                 } else {
925                                         ip_summed = CHECKSUM_NONE;
926                                         ring->csum_none++;
927                                 }
928                         }
929                 } else {
930                         ip_summed = CHECKSUM_NONE;
931                         ring->csum_none++;
932                 }
933
934                 printd("length %d ring %p bytes %d packets %d ip_summed %d\n",
935                        length, ring, ring->bytes, ring->packets, ip_summed);
936                 //dump_packet(priv, rx_desc, frags, length);
937                 recv_packet(priv, rx_desc, frags, length);
938                 goto next;
939
940 #if 0 // AKAROS_PORT
941                 /* This packet is eligible for GRO if it is:
942                  * - DIX Ethernet (type interpretation)
943                  * - TCP/IP (v4)
944                  * - without IP options
945                  * - not an IP fragment
946                  * - no LLS polling in progress
947                  */
948                 if (!mlx4_en_cq_busy_polling(cq) &&
949                     (dev->feat & NETIF_F_GRO)) {
950                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
951                         if (!gro_skb)
952                                 goto next;
953
954                         nr = mlx4_en_complete_rx_desc(priv,
955                                 rx_desc, frags, gro_skb,
956                                 length);
957                         if (!nr)
958                                 goto next;
959
960                         if (ip_summed == CHECKSUM_COMPLETE) {
961                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
962                                 if (check_csum(cqe, gro_skb, va, ring->hwtstamp_rx_filter)) {
963                                         ip_summed = CHECKSUM_NONE;
964                                         ring->csum_none++;
965                                         ring->csum_complete--;
966                                 }
967                         }
968
969                         skb_shinfo(gro_skb)->nr_frags = nr;
970                         gro_skb->len = length;
971                         gro_skb->data_len = length;
972                         gro_skb->ip_summed = ip_summed;
973
974                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
975                                 gro_skb->csum_level = 1;
976
977                         if ((cqe->vlan_my_qpn &
978                             cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) &&
979                             (dev->feat & NETIF_F_HW_VLAN_CTAG_RX)) {
980                                 uint16_t vid = be16_to_cpu(cqe->sl_vid);
981
982                                 __vlan_hwaccel_put_tag(gro_skb,
983                                                        cpu_to_be16(ETH_P_8021Q),
984                                                        vid);
985                         }
986
987                         if (dev->feat & NETIF_F_RXHASH)
988                                 skb_set_hash(gro_skb,
989                                              be32_to_cpu(cqe->immed_rss_invalid),
990                                              PKT_HASH_TYPE_L3);
991
992                         skb_record_rx_queue(gro_skb, cq->ring);
993                         skb_mark_napi_id(gro_skb, &cq->napi);
994
995                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
996                                 timestamp = mlx4_en_get_cqe_ts(cqe);
997                                 mlx4_en_fill_hwtstamps(mdev,
998                                                        skb_hwtstamps(gro_skb),
999                                                        timestamp);
1000                         }
1001
1002                         napi_gro_frags(&cq->napi);
1003                         goto next;
1004                 }
1005
1006                 /* GRO not possible, complete processing here */
1007                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
1008                 if (!skb) {
1009                         priv->stats.rx_dropped++;
1010                         goto next;
1011                 }
1012
1013                 if (unlikely(priv->validate_loopback)) {
1014                         validate_loopback(priv, skb);
1015                         goto next;
1016                 }
1017
1018                 if (ip_summed == CHECKSUM_COMPLETE) {
1019                         if (check_csum(cqe, skb, skb->data, ring->hwtstamp_rx_filter)) {
1020                                 ip_summed = CHECKSUM_NONE;
1021                                 ring->csum_complete--;
1022                                 ring->csum_none++;
1023                         }
1024                 }
1025
1026                 skb->ip_summed = ip_summed;
1027                 skb->protocol = eth_type_trans(skb, dev);
1028                 skb_record_rx_queue(skb, cq->ring);
1029
1030                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1031                         skb->csum_level = 1;
1032
1033                 if (dev->feat & NETIF_F_RXHASH)
1034                         skb_set_hash(skb,
1035                                      be32_to_cpu(cqe->immed_rss_invalid),
1036                                      PKT_HASH_TYPE_L3);
1037
1038                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
1039                     MLX4_CQE_VLAN_PRESENT_MASK) &&
1040                     (dev->feat & NETIF_F_HW_VLAN_CTAG_RX))
1041                         __vlan_hwaccel_put_tag(skb, cpu_to_be16(ETH_P_8021Q),
1042                                                be16_to_cpu(cqe->sl_vid));
1043
1044                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1045                         timestamp = mlx4_en_get_cqe_ts(cqe);
1046                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
1047                                                timestamp);
1048                 }
1049
1050                 skb_mark_napi_id(skb, &cq->napi);
1051
1052                 if (!mlx4_en_cq_busy_polling(cq))
1053                         napi_gro_receive(&cq->napi, skb);
1054                 else
1055                         netif_receive_skb(skb);
1056 #endif
1057
1058 next:
1059                 for (nr = 0; nr < priv->num_frags; nr++)
1060                         mlx4_en_free_frag(priv, frags, nr);
1061
1062                 ++cq->mcq.cons_index;
1063                 index = (cq->mcq.cons_index) & ring->size_mask;
1064                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1065                 if (++polled == budget)
1066                         goto out;
1067         }
1068
1069 out:
1070         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1071         mlx4_cq_set_ci(&cq->mcq);
1072         wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1073         ring->cons = cq->mcq.cons_index;
1074         mlx4_en_refill_rx_buffers(priv, ring);
1075         mlx4_en_update_rx_prod_db(ring);
1076         return polled;
1077 }
1078
1079 static void mlx4_en_poll_rx_cq(uint32_t srcid, long a0, long a1, long a2);
1080
1081 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1082 {
1083         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1084         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1085
1086         if (likely(priv->port_up))
1087 #if 0 // AKAROS_PORT
1088                 napi_schedule_irqoff(&cq->napi);
1089 #else
1090                 send_kernel_message(core_id(), mlx4_en_poll_rx_cq, (long)cq,
1091                                     0, 0, KMSG_ROUTINE);
1092 #endif
1093         else
1094                 mlx4_en_arm_cq(priv, cq);
1095 }
1096
1097 /* Rx CQ polling - called by NAPI */
1098 static void mlx4_en_poll_rx_cq(uint32_t srcid, long a0, long a1, long a2)
1099 {
1100         struct mlx4_en_cq *cq = (struct mlx4_en_cq *)a0;
1101         struct ether *dev = cq->dev;
1102         struct mlx4_en_priv *priv = netdev_priv(dev);
1103         int done, budget = INT32_MAX;
1104
1105         if (!mlx4_en_cq_lock_napi(cq))
1106                 return;
1107
1108         done = mlx4_en_process_rx_cq(dev, cq, budget);
1109
1110         mlx4_en_cq_unlock_napi(cq);
1111
1112 #if 0 // AKAROS_PORT
1113         /* If we used up all the quota - we're probably not done yet... */
1114         if (done == budget) {
1115                 int cpu_curr;
1116                 const struct cpumask *aff;
1117
1118                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1119
1120                 cpu_curr = core_id();
1121                 aff = irq_desc_get_irq_data(cq->irq_desc)->affinity;
1122
1123                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1124                         return;
1125
1126                 /* Current cpu is not according to smp_irq_affinity -
1127                  * probably affinity changed. need to stop this NAPI
1128                  * poll, and restart it on the right CPU
1129                  */
1130                 done = 0;
1131         }
1132         /* Done for now */
1133         napi_complete_done(napi, done);
1134 #endif
1135         mlx4_en_arm_cq(priv, cq);
1136 }
1137
1138 static const int frag_sizes[] = {
1139         FRAG_SZ0,
1140         FRAG_SZ1,
1141         FRAG_SZ2,
1142         FRAG_SZ3
1143 };
1144
1145 void mlx4_en_calc_rx_buf(struct ether *dev)
1146 {
1147         struct mlx4_en_priv *priv = netdev_priv(dev);
1148         int eff_mtu = dev->maxmtu + ETHERHDRSIZE + VLAN_HLEN;
1149         int buf_size = 0;
1150         int i = 0;
1151
1152         while (buf_size < eff_mtu) {
1153                 priv->frag_info[i].frag_size =
1154                         (eff_mtu > buf_size + frag_sizes[i]) ?
1155                                 frag_sizes[i] : eff_mtu - buf_size;
1156                 priv->frag_info[i].frag_prefix_size = buf_size;
1157                 priv->frag_info[i].frag_stride =
1158                                 ALIGN(priv->frag_info[i].frag_size,
1159                                       SMP_CACHE_BYTES);
1160                 buf_size += priv->frag_info[i].frag_size;
1161                 i++;
1162         }
1163
1164         priv->num_frags = i;
1165         priv->rx_skb_size = eff_mtu;
1166         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1167
1168         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1169                eff_mtu, priv->num_frags);
1170         for (i = 0; i < priv->num_frags; i++) {
1171                 en_err(priv,
1172                        "  frag:%d - size:%d prefix:%d stride:%d\n",
1173                        i,
1174                        priv->frag_info[i].frag_size,
1175                        priv->frag_info[i].frag_prefix_size,
1176                        priv->frag_info[i].frag_stride);
1177         }
1178 }
1179
1180 /* RSS related functions */
1181
1182 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1183                                  struct mlx4_en_rx_ring *ring,
1184                                  enum mlx4_qp_state *state,
1185                                  struct mlx4_qp *qp)
1186 {
1187         struct mlx4_en_dev *mdev = priv->mdev;
1188         struct mlx4_qp_context *context;
1189         int err = 0;
1190
1191         context = kmalloc(sizeof(*context), MEM_WAIT);
1192         if (!context)
1193                 return -ENOMEM;
1194
1195         err = mlx4_qp_alloc(mdev->dev, qpn, qp, MEM_WAIT);
1196         if (err) {
1197                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1198                 goto out;
1199         }
1200         qp->event = mlx4_en_sqp_event;
1201
1202         memset(context, 0, sizeof *context);
1203         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1204                                 qpn, ring->cqn, -1, context);
1205         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1206
1207         /* Cancel FCS removal if FW allows */
1208         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1209                 context->param3 |= cpu_to_be32(1 << 29);
1210                 if (priv->dev->feat & NETIF_F_RXFCS)
1211                         ring->fcs_del = 0;
1212                 else
1213                         ring->fcs_del = ETH_FCS_LEN;
1214         } else
1215                 ring->fcs_del = 0;
1216
1217         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1218         if (err) {
1219                 mlx4_qp_remove(mdev->dev, qp);
1220                 mlx4_qp_free(mdev->dev, qp);
1221         }
1222         mlx4_en_update_rx_prod_db(ring);
1223 out:
1224         kfree(context);
1225         return err;
1226 }
1227
1228 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1229 {
1230         int err;
1231         uint32_t qpn;
1232
1233         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, (int *)&qpn,
1234                                     MLX4_RESERVE_A0_QP);
1235         if (err) {
1236                 en_err(priv, "Failed reserving drop qpn\n");
1237                 return err;
1238         }
1239         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp,
1240                             MEM_WAIT);
1241         if (err) {
1242                 en_err(priv, "Failed allocating drop qp\n");
1243                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1244                 return err;
1245         }
1246
1247         return 0;
1248 }
1249
1250 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1251 {
1252         uint32_t qpn;
1253
1254         qpn = priv->drop_qp.qpn;
1255         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1256         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1257         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1258 }
1259
1260 /* Allocate rx qp's and configure them according to rss map */
1261 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1262 {
1263         struct mlx4_en_dev *mdev = priv->mdev;
1264         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1265         struct mlx4_qp_context context;
1266         struct mlx4_rss_context *rss_context;
1267         int rss_rings;
1268         void *ptr;
1269         uint8_t rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1270                         MLX4_RSS_TCP_IPV6);
1271         int i, qpn;
1272         int err = 0;
1273         int good_qps = 0;
1274
1275         en_dbg(DRV, priv, "Configuring rss steering\n");
1276         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1277                                     priv->rx_ring_num,
1278                                     &rss_map->base_qpn, 0);
1279         if (err) {
1280                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1281                 return err;
1282         }
1283
1284         for (i = 0; i < priv->rx_ring_num; i++) {
1285                 qpn = rss_map->base_qpn + i;
1286                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1287                                             &rss_map->state[i],
1288                                             &rss_map->qps[i]);
1289                 if (err)
1290                         goto rss_err;
1291
1292                 ++good_qps;
1293         }
1294
1295         /* Configure RSS indirection qp */
1296         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp,
1297                             MEM_WAIT);
1298         if (err) {
1299                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1300                 goto rss_err;
1301         }
1302         rss_map->indir_qp.event = mlx4_en_sqp_event;
1303         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1304                                 priv->rx_ring[0]->cqn, -1, &context);
1305
1306         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1307                 rss_rings = priv->rx_ring_num;
1308         else
1309                 rss_rings = priv->prof->rss_rings;
1310
1311         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1312                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1313         rss_context = ptr;
1314         rss_context->base_qpn = cpu_to_be32(LOG2_UP(rss_rings) << 24 |
1315                                             (rss_map->base_qpn));
1316         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1317         if (priv->mdev->profile.udp_rss) {
1318                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1319                 rss_context->base_qpn_udp = rss_context->default_qpn;
1320         }
1321
1322         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1323                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1324                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1325         }
1326
1327         rss_context->flags = rss_mask;
1328         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1329         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1330                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1331         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1332                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1333                 memcpy(rss_context->rss_key, priv->rss_key,
1334                        MLX4_EN_RSS_KEY_SIZE);
1335                 netdev_rss_key_fill(rss_context->rss_key,
1336                                     MLX4_EN_RSS_KEY_SIZE);
1337         } else {
1338                 en_err(priv, "Unknown RSS hash function requested\n");
1339                 err = -EINVAL;
1340                 goto indir_err;
1341         }
1342         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1343                                &rss_map->indir_qp, &rss_map->indir_state);
1344         if (err)
1345                 goto indir_err;
1346
1347         return 0;
1348
1349 indir_err:
1350         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1351                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1352         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1353         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1354 rss_err:
1355         for (i = 0; i < good_qps; i++) {
1356                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1357                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1358                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1359                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1360         }
1361         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1362         return err;
1363 }
1364
1365 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1366 {
1367         struct mlx4_en_dev *mdev = priv->mdev;
1368         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1369         int i;
1370
1371         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1372                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1373         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1374         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1375
1376         for (i = 0; i < priv->rx_ring_num; i++) {
1377                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1378                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1379                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1380                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1381         }
1382         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1383 }