d29b814ac4b7df869a116a8367341d511d7b65d8
[akaros.git] / kern / drivers / net / mlx4 / en_port.c
1 /*
2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33
34
35 #include <linux/mlx4/device.h>
36 #include <linux/mlx4/cmd.h>
37 #include "en_port.h"
38 #include "mlx4_en.h"
39
40
41 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv)
42 {
43         panic("Disabled");
44 #if 0 // AKAROS_PORT
45         struct mlx4_cmd_mailbox *mailbox;
46         struct mlx4_set_vlan_fltr_mbox *filter;
47         int i;
48         int j;
49         int index = 0;
50         uint32_t entry;
51         int err = 0;
52
53         mailbox = mlx4_alloc_cmd_mailbox(dev);
54         if (IS_ERR(mailbox))
55                 return PTR_ERR(mailbox);
56
57         filter = mailbox->buf;
58         for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
59                 entry = 0;
60                 for (j = 0; j < 32; j++)
61                         if (test_bit(index++, priv->active_vlans))
62                                 entry |= 1 << j;
63                 filter->entry[i] = cpu_to_be32(entry);
64         }
65         err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
66                        MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
67         mlx4_free_cmd_mailbox(dev, mailbox);
68         return err;
69 #endif
70 }
71
72 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, uint8_t port)
73 {
74         struct mlx4_en_query_port_context *qport_context;
75         struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
76         struct mlx4_en_port_state *state = &priv->port_state;
77         struct mlx4_cmd_mailbox *mailbox;
78         int err;
79
80         mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
81         if (IS_ERR(mailbox))
82                 return PTR_ERR(mailbox);
83         err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
84                            MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
85                            MLX4_CMD_WRAPPED);
86         if (err)
87                 goto out;
88         qport_context = mailbox->buf;
89
90         /* This command is always accessed from Ethtool context
91          * already synchronized, no need in locking */
92         state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK);
93         switch (qport_context->link_speed & MLX4_EN_SPEED_MASK) {
94         case MLX4_EN_100M_SPEED:
95                 state->link_speed = SPEED_100;
96                 break;
97         case MLX4_EN_1G_SPEED:
98                 state->link_speed = SPEED_1000;
99                 break;
100         case MLX4_EN_10G_SPEED_XAUI:
101         case MLX4_EN_10G_SPEED_XFI:
102                 state->link_speed = SPEED_10000;
103                 break;
104         case MLX4_EN_20G_SPEED:
105                 state->link_speed = SPEED_20000;
106                 break;
107         case MLX4_EN_40G_SPEED:
108                 state->link_speed = SPEED_40000;
109                 break;
110         case MLX4_EN_56G_SPEED:
111                 state->link_speed = SPEED_56000;
112                 break;
113         default:
114                 state->link_speed = -1;
115                 break;
116         }
117
118         state->transceiver = qport_context->transceiver;
119
120         state->flags = 0; /* Reset and recalculate the port flags */
121         state->flags |= (qport_context->link_up & MLX4_EN_ANC_MASK) ?
122                 MLX4_EN_PORT_ANC : 0;
123         state->flags |= (qport_context->autoneg & MLX4_EN_AUTONEG_MASK) ?
124                 MLX4_EN_PORT_ANE : 0;
125
126 out:
127         mlx4_free_cmd_mailbox(mdev->dev, mailbox);
128         return err;
129 }
130
131 /* Each counter set is located in struct mlx4_en_stat_out_mbox
132  * with a const offset between its prio components.
133  * This function runs over a counter set and sum all of it's prio components.
134  */
135 static unsigned long en_stats_adder(__be64 *start, __be64 *next, int num)
136 {
137         __be64 *curr = start;
138         unsigned long ret = 0;
139         int i;
140         int offset = next - start;
141
142         for (i = 0; i < num; i++) {
143                 ret += be64_to_cpu(*curr);
144                 curr += offset;
145         }
146
147         return ret;
148 }
149
150 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, uint8_t port,
151                            uint8_t reset)
152 {
153         panic("Disabled");
154 #if 0 // AKAROS_PORT
155         struct mlx4_en_stat_out_mbox *mlx4_en_stats;
156         struct mlx4_en_stat_out_flow_control_mbox *flowstats;
157         struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
158         struct netif_stats *stats = &priv->stats;
159         struct mlx4_cmd_mailbox *mailbox;
160         uint64_t in_mod = reset << 8 | port;
161         int err;
162         int i;
163
164         mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
165         if (IS_ERR(mailbox))
166                 return PTR_ERR(mailbox);
167         err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
168                            MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
169                            MLX4_CMD_WRAPPED);
170         if (err)
171                 goto out;
172
173         mlx4_en_stats = mailbox->buf;
174
175         spin_lock(&priv->stats_lock);
176
177         stats->rx_packets = 0;
178         stats->rx_bytes = 0;
179         priv->port_stats.rx_chksum_good = 0;
180         priv->port_stats.rx_chksum_none = 0;
181         priv->port_stats.rx_chksum_complete = 0;
182         for (i = 0; i < priv->rx_ring_num; i++) {
183                 stats->rx_packets += priv->rx_ring[i]->packets;
184                 stats->rx_bytes += priv->rx_ring[i]->bytes;
185                 priv->port_stats.rx_chksum_good += priv->rx_ring[i]->csum_ok;
186                 priv->port_stats.rx_chksum_none += priv->rx_ring[i]->csum_none;
187                 priv->port_stats.rx_chksum_complete += priv->rx_ring[i]->csum_complete;
188         }
189         stats->tx_packets = 0;
190         stats->tx_bytes = 0;
191         priv->port_stats.tx_chksum_offload = 0;
192         priv->port_stats.queue_stopped = 0;
193         priv->port_stats.wake_queue = 0;
194         priv->port_stats.tso_packets = 0;
195         priv->port_stats.xmit_more = 0;
196
197         for (i = 0; i < priv->tx_ring_num; i++) {
198                 const struct mlx4_en_tx_ring *ring = priv->tx_ring[i];
199
200                 stats->tx_packets += ring->packets;
201                 stats->tx_bytes += ring->bytes;
202                 priv->port_stats.tx_chksum_offload += ring->tx_csum;
203                 priv->port_stats.queue_stopped     += ring->queue_stopped;
204                 priv->port_stats.wake_queue        += ring->wake_queue;
205                 priv->port_stats.tso_packets       += ring->tso_packets;
206                 priv->port_stats.xmit_more         += ring->xmit_more;
207         }
208
209         /* net device stats */
210         stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
211                            be32_to_cpu(mlx4_en_stats->RJBBR) +
212                            be32_to_cpu(mlx4_en_stats->RCRC) +
213                            be32_to_cpu(mlx4_en_stats->RRUNT) +
214                            be64_to_cpu(mlx4_en_stats->RInRangeLengthErr) +
215                            be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr) +
216                            be32_to_cpu(mlx4_en_stats->RSHORT) +
217                            en_stats_adder(&mlx4_en_stats->RGIANT_prio_0,
218                                           &mlx4_en_stats->RGIANT_prio_1,
219                                           NUM_PRIORITIES);
220         stats->tx_errors = en_stats_adder(&mlx4_en_stats->TGIANT_prio_0,
221                                           &mlx4_en_stats->TGIANT_prio_1,
222                                           NUM_PRIORITIES);
223         stats->multicast = en_stats_adder(&mlx4_en_stats->MCAST_prio_0,
224                                           &mlx4_en_stats->MCAST_prio_1,
225                                           NUM_PRIORITIES);
226         stats->collisions = 0;
227         stats->rx_dropped = be32_to_cpu(mlx4_en_stats->RDROP);
228         stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
229         stats->rx_over_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
230         stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
231         stats->rx_frame_errors = 0;
232         stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
233         stats->rx_missed_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
234         stats->tx_aborted_errors = 0;
235         stats->tx_carrier_errors = 0;
236         stats->tx_fifo_errors = 0;
237         stats->tx_heartbeat_errors = 0;
238         stats->tx_window_errors = 0;
239         stats->tx_dropped = be32_to_cpu(mlx4_en_stats->TDROP);
240
241         /* RX stats */
242         priv->pkstats.rx_multicast_packets = stats->multicast;
243         priv->pkstats.rx_broadcast_packets =
244                         en_stats_adder(&mlx4_en_stats->RBCAST_prio_0,
245                                        &mlx4_en_stats->RBCAST_prio_1,
246                                        NUM_PRIORITIES);
247         priv->pkstats.rx_jabbers = be32_to_cpu(mlx4_en_stats->RJBBR);
248         priv->pkstats.rx_in_range_length_error =
249                 be64_to_cpu(mlx4_en_stats->RInRangeLengthErr);
250         priv->pkstats.rx_out_range_length_error =
251                 be64_to_cpu(mlx4_en_stats->ROutRangeLengthErr);
252
253         /* Tx stats */
254         priv->pkstats.tx_multicast_packets =
255                 en_stats_adder(&mlx4_en_stats->TMCAST_prio_0,
256                                &mlx4_en_stats->TMCAST_prio_1,
257                                NUM_PRIORITIES);
258         priv->pkstats.tx_broadcast_packets =
259                 en_stats_adder(&mlx4_en_stats->TBCAST_prio_0,
260                                &mlx4_en_stats->TBCAST_prio_1,
261                                NUM_PRIORITIES);
262
263         priv->pkstats.rx_prio[0][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
264         priv->pkstats.rx_prio[0][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_0);
265         priv->pkstats.rx_prio[1][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
266         priv->pkstats.rx_prio[1][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_1);
267         priv->pkstats.rx_prio[2][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
268         priv->pkstats.rx_prio[2][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_2);
269         priv->pkstats.rx_prio[3][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
270         priv->pkstats.rx_prio[3][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_3);
271         priv->pkstats.rx_prio[4][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
272         priv->pkstats.rx_prio[4][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_4);
273         priv->pkstats.rx_prio[5][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
274         priv->pkstats.rx_prio[5][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_5);
275         priv->pkstats.rx_prio[6][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
276         priv->pkstats.rx_prio[6][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_6);
277         priv->pkstats.rx_prio[7][0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
278         priv->pkstats.rx_prio[7][1] = be64_to_cpu(mlx4_en_stats->ROCT_prio_7);
279         priv->pkstats.rx_prio[8][0] = be64_to_cpu(mlx4_en_stats->RTOT_novlan);
280         priv->pkstats.rx_prio[8][1] = be64_to_cpu(mlx4_en_stats->ROCT_novlan);
281         priv->pkstats.tx_prio[0][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
282         priv->pkstats.tx_prio[0][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_0);
283         priv->pkstats.tx_prio[1][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
284         priv->pkstats.tx_prio[1][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_1);
285         priv->pkstats.tx_prio[2][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
286         priv->pkstats.tx_prio[2][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_2);
287         priv->pkstats.tx_prio[3][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
288         priv->pkstats.tx_prio[3][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_3);
289         priv->pkstats.tx_prio[4][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
290         priv->pkstats.tx_prio[4][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_4);
291         priv->pkstats.tx_prio[5][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
292         priv->pkstats.tx_prio[5][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_5);
293         priv->pkstats.tx_prio[6][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
294         priv->pkstats.tx_prio[6][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_6);
295         priv->pkstats.tx_prio[7][0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
296         priv->pkstats.tx_prio[7][1] = be64_to_cpu(mlx4_en_stats->TOCT_prio_7);
297         priv->pkstats.tx_prio[8][0] = be64_to_cpu(mlx4_en_stats->TTOT_novlan);
298         priv->pkstats.tx_prio[8][1] = be64_to_cpu(mlx4_en_stats->TOCT_novlan);
299
300         spin_unlock(&priv->stats_lock);
301
302         /* 0xffs indicates invalid value */
303         memset(mailbox->buf, 0xff, sizeof(*flowstats) * MLX4_NUM_PRIORITIES);
304
305         if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN) {
306                 memset(mailbox->buf, 0,
307                        sizeof(*flowstats) * MLX4_NUM_PRIORITIES);
308                 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma,
309                                    in_mod | MLX4_DUMP_ETH_STATS_FLOW_CONTROL,
310                                    0, MLX4_CMD_DUMP_ETH_STATS,
311                                    MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
312                 if (err)
313                         goto out;
314         }
315
316         flowstats = mailbox->buf;
317
318         spin_lock(&priv->stats_lock);
319
320         for (i = 0; i < MLX4_NUM_PRIORITIES; i++)       {
321                 priv->rx_priority_flowstats[i].rx_pause =
322                         be64_to_cpu(flowstats[i].rx_pause);
323                 priv->rx_priority_flowstats[i].rx_pause_duration =
324                         be64_to_cpu(flowstats[i].rx_pause_duration);
325                 priv->rx_priority_flowstats[i].rx_pause_transition =
326                         be64_to_cpu(flowstats[i].rx_pause_transition);
327                 priv->tx_priority_flowstats[i].tx_pause =
328                         be64_to_cpu(flowstats[i].tx_pause);
329                 priv->tx_priority_flowstats[i].tx_pause_duration =
330                         be64_to_cpu(flowstats[i].tx_pause_duration);
331                 priv->tx_priority_flowstats[i].tx_pause_transition =
332                         be64_to_cpu(flowstats[i].tx_pause_transition);
333         }
334
335         /* if pfc is not in use, all priorities counters have the same value */
336         priv->rx_flowstats.rx_pause =
337                 be64_to_cpu(flowstats[0].rx_pause);
338         priv->rx_flowstats.rx_pause_duration =
339                 be64_to_cpu(flowstats[0].rx_pause_duration);
340         priv->rx_flowstats.rx_pause_transition =
341                 be64_to_cpu(flowstats[0].rx_pause_transition);
342         priv->tx_flowstats.tx_pause =
343                 be64_to_cpu(flowstats[0].tx_pause);
344         priv->tx_flowstats.tx_pause_duration =
345                 be64_to_cpu(flowstats[0].tx_pause_duration);
346         priv->tx_flowstats.tx_pause_transition =
347                 be64_to_cpu(flowstats[0].tx_pause_transition);
348
349         spin_unlock(&priv->stats_lock);
350
351 out:
352         mlx4_free_cmd_mailbox(mdev->dev, mailbox);
353         return err;
354 #endif
355 }
356