Struct ether accesses netif anonymously
[akaros.git] / kern / drivers / net / ether8169.c
1 /* This file is part of the UCB release of Plan 9. It is subject to the license
2  * terms in the LICENSE file found in the top-level directory of this
3  * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
4  * part of the UCB release of Plan 9, including this file, may be copied,
5  * modified, propagated, or distributed except according to the terms contained
6  * in the LICENSE file. */
7
8 /*
9  * Realtek RTL8110S/8169S.
10  * Mostly there. There are some magic register values used
11  * which are not described in any datasheet or driver but seem
12  * to be necessary.
13  * No tuning has been done. Only tested on an RTL8110S, there
14  * are slight differences between the chips in the series so some
15  * tweaks may be needed.
16  */
17 #include <vfs.h>
18 #include <kfs.h>
19 #include <slab.h>
20 #include <kmalloc.h>
21 #include <kref.h>
22 #include <string.h>
23 #include <stdio.h>
24 #include <assert.h>
25 #include <error.h>
26 #include <cpio.h>
27 #include <pmap.h>
28 #include <smp.h>
29 #include <arch/pci.h>
30 #include <assert.h>
31 #include <ip.h>
32 #include <ns.h>
33
34 #define ilock(x) spin_lock_irqsave(x)
35 #define iunlock(x) spin_unlock_irqsave(x)
36
37 #include "ethermii.h"
38
39 #define HOWMANY(x, y)   (((x)+((y)-1))/(y))
40 enum {                                  /* registers */
41         Idr0            = 0x00,         /* MAC address */
42         Mar0            = 0x08,         /* Multicast address */
43         Dtccr           = 0x10,         /* Dump Tally Counter Command */
44         Tnpds           = 0x20,         /* Transmit Normal Priority Descriptors */
45         Thpds           = 0x28,         /* Transmit High Priority Descriptors */
46         Flash           = 0x30,         /* Flash Memory Read/Write */
47         Erbcr           = 0x34,         /* Early Receive Byte Count */
48         Ersr            = 0x36,         /* Early Receive Status */
49         Cr              = 0x37,         /* Command Register */
50         Tppoll          = 0x38,         /* Transmit Priority Polling */
51         Imr             = 0x3C,         /* Interrupt Mask */
52         Isr             = 0x3E,         /* Interrupt Status */
53         Tcr             = 0x40,         /* Transmit Configuration */
54         Rcr             = 0x44,         /* Receive Configuration */
55         Tctr            = 0x48,         /* Timer Count */
56         Mpc             = 0x4C,         /* Missed Packet Counter */
57         Cr9346          = 0x50,         /* 9346 Command Register */
58         Config0         = 0x51,         /* Configuration Register 0 */
59         Config1         = 0x52,         /* Configuration Register 1 */
60         Config2         = 0x53,         /* Configuration Register 2 */
61         Config3         = 0x54,         /* Configuration Register 3 */
62         Config4         = 0x55,         /* Configuration Register 4 */
63         Config5         = 0x56,         /* Configuration Register 5 */
64         Timerint        = 0x58,         /* Timer Interrupt */
65         Mulint          = 0x5C,         /* Multiple Interrupt Select */
66         Phyar           = 0x60,         /* PHY Access */
67         Tbicsr0         = 0x64,         /* TBI Control and Status */
68         Tbianar         = 0x68,         /* TBI Auto-Negotiation Advertisment */
69         Tbilpar         = 0x6A,         /* TBI Auto-Negotiation Link Partner */
70
71         Rms             = 0xDA,         /* Receive Packet Maximum Size */
72         Cplusc          = 0xE0,         /* C+ Command */
73         Rdsar           = 0xE4,         /* Receive Descriptor Start Address */
74         Mtps            = 0xEC,         /* Max. Transmit Packet Size */
75 };
76
77 enum {                                  /* Dtccr */
78         Cmd             = 0x00000008,   /* Command */
79 };
80
81 enum {                                  /* Cr */
82         Te              = 0x04,         /* Transmitter Enable */
83         Re              = 0x08,         /* Receiver Enable */
84         Rst             = 0x10,         /* Software Reset */
85 };
86
87 enum {                                  /* Tppoll */
88         Fswint          = 0x01,         /* Forced Software Interrupt */
89         Npq             = 0x40,         /* Normal Priority Queue polling */
90         Hpq             = 0x80,         /* High Priority Queue polling */
91 };
92
93 enum {                                  /* Imr/Isr */
94         Rok             = 0x0001,       /* Receive OK */
95         Rer             = 0x0002,       /* Receive Error */
96         Tok             = 0x0004,       /* Transmit OK */
97         Ter             = 0x0008,       /* Transmit Error */
98         Rdu             = 0x0010,       /* Receive Descriptor Unavailable */
99         Punlc           = 0x0020,       /* Packet Underrun or Link Change */
100         Fovw            = 0x0040,       /* Receive FIFO Overflow */
101         Tdu             = 0x0080,       /* Transmit Descriptor Unavailable */
102         Swint           = 0x0100,       /* Software Interrupt */
103         Timeout         = 0x4000,       /* Timer */
104         Serr            = 0x8000,       /* System Error */
105 };
106
107 enum {                                  /* Tcr */
108         MtxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
109         MtxdmaMASK      = 0x00000700,
110         Mtxdmaunlimited = 0x00000700,
111         Acrc            = 0x00010000,   /* Append CRC (not) */
112         Lbk0            = 0x00020000,   /* Loopback Test 0 */
113         Lbk1            = 0x00040000,   /* Loopback Test 1 */
114         Ifg2            = 0x00080000,   /* Interframe Gap 2 */
115         HwveridSHIFT    = 23,           /* Hardware Version ID */
116         HwveridMASK     = 0x7C800000,
117         Macv01          = 0x00000000,   /* RTL8169 */
118         Macv02          = 0x00800000,   /* RTL8169S/8110S */
119         Macv03          = 0x04000000,   /* RTL8169S/8110S */
120         Macv04          = 0x10000000,   /* RTL8169SB/8110SB */
121         Macv05          = 0x18000000,   /* RTL8169SC/8110SC */
122         Macv11          = 0x30000000,   /* RTL8168B/8111B */
123         Macv12          = 0x38000000,   /* RTL8169B/8111B */
124         Macv13          = 0x34000000,   /* RTL8101E */
125         Macv14          = 0x30800000,   /* RTL8100E */
126         Macv15          = 0x38800000,   /* RTL8100E */
127         Ifg0            = 0x01000000,   /* Interframe Gap 0 */
128         Ifg1            = 0x02000000,   /* Interframe Gap 1 */
129 };
130
131 enum {                                  /* Rcr */
132         Aap             = 0x00000001,   /* Accept All Packets */
133         Apm             = 0x00000002,   /* Accept Physical Match */
134         Am              = 0x00000004,   /* Accept Multicast */
135         Ab              = 0x00000008,   /* Accept Broadcast */
136         Ar              = 0x00000010,   /* Accept Runt */
137         Aer             = 0x00000020,   /* Accept Error */
138         Sel9356         = 0x00000040,   /* 9356 EEPROM used */
139         MrxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
140         MrxdmaMASK      = 0x00000700,
141         Mrxdmaunlimited = 0x00000700,
142         RxfthSHIFT      = 13,           /* Receive Buffer Length */
143         RxfthMASK       = 0x0000E000,
144         Rxfth256        = 0x00008000,
145         Rxfthnone       = 0x0000E000,
146         Rer8            = 0x00010000,   /* Accept Error Packets > 8 bytes */
147         MulERINT        = 0x01000000,   /* Multiple Early Interrupt Select */
148 };
149
150 enum {                                  /* Cr9346 */
151         Eedo            = 0x01,         /* */
152         Eedi            = 0x02,         /* */
153         Eesk            = 0x04,         /* */
154         Eecs            = 0x08,         /* */
155         Eem0            = 0x40,         /* Operating Mode */
156         Eem1            = 0x80,
157 };
158
159 enum {                                  /* Phyar */
160         DataMASK        = 0x0000FFFF,   /* 16-bit GMII/MII Register Data */
161         DataSHIFT       = 0,
162         RegaddrMASK     = 0x001F0000,   /* 5-bit GMII/MII Register Address */
163         RegaddrSHIFT    = 16,
164         Flag            = 0x80000000,   /* */
165 };
166
167 enum {                                  /* Cplusc */
168         Mulrw           = 0x0008,       /* PCI Multiple R/W Enable */
169         Dac             = 0x0010,       /* PCI Dual Address Cycle Enable */
170         Rxchksum        = 0x0020,       /* Receive Checksum Offload Enable */
171         Rxvlan          = 0x0040,       /* Receive VLAN De-tagging Enable */
172         Endian          = 0x0200,       /* Endian Mode */
173 };
174
175 typedef struct D D;                     /* Transmit/Receive Descriptor */
176 struct D {
177         uint32_t        control;
178         uint32_t        vlan;
179         uint32_t        addrlo;
180         uint32_t        addrhi;
181 };
182
183 enum {                                  /* Transmit Descriptor control */
184         TxflMASK        = 0x0000FFFF,   /* Transmit Frame Length */
185         TxflSHIFT       = 0,
186         Tcps            = 0x00010000,   /* TCP Checksum Offload */
187         Udpcs           = 0x00020000,   /* UDP Checksum Offload */
188         Ipcs            = 0x00040000,   /* IP Checksum Offload */
189         Lgsen           = 0x08000000,   /* Large Send */
190 };
191
192 enum {                                  /* Receive Descriptor control */
193         RxflMASK        = 0x00003FFF,   /* Receive Frame Length */
194         RxflSHIFT       = 0,
195         Tcpf            = 0x00004000,   /* TCP Checksum Failure */
196         Udpf            = 0x00008000,   /* UDP Checksum Failure */
197         Ipf             = 0x00010000,   /* IP Checksum Failure */
198         Pid0            = 0x00020000,   /* Protocol ID0 */
199         Pid1            = 0x00040000,   /* Protocol ID1 */
200         Crce            = 0x00080000,   /* CRC Error */
201         Runt            = 0x00100000,   /* Runt Packet */
202         Res             = 0x00200000,   /* Receive Error Summary */
203         Rwt             = 0x00400000,   /* Receive Watchdog Timer Expired */
204         Fovf            = 0x00800000,   /* FIFO Overflow */
205         Bovf            = 0x01000000,   /* Buffer Overflow */
206         Bar             = 0x02000000,   /* Broadcast Address Received */
207         Pam             = 0x04000000,   /* Physical Address Matched */
208         Mar             = 0x08000000,   /* Multicast Address Received */
209 };
210
211 enum {                                  /* General Descriptor control */
212         Ls              = 0x10000000,   /* Last Segment Descriptor */
213         Fs              = 0x20000000,   /* First Segment Descriptor */
214         Eor             = 0x40000000,   /* End of Descriptor Ring */
215         Own             = 0x80000000,   /* Ownership */
216 };
217
218 /*
219  */
220 enum {                                  /* Ring sizes  (<= 1024) */
221         Ntd             = 32,           /* Transmit Ring */
222         Nrd             = 128,          /* Receive Ring */
223 };
224
225 #define Mps ROUNDUP(ETHERMAXTU + 4, 128)
226
227 typedef struct Dtcc Dtcc;
228 struct Dtcc {
229         uint64_t        txok;
230         uint64_t        rxok;
231         uint64_t        txer;
232         uint32_t        rxer;
233         uint16_t        misspkt;
234         uint16_t        fae;
235         uint32_t        tx1col;
236         uint32_t        txmcol;
237         uint64_t        rxokph;
238         uint64_t        rxokbrd;
239         uint32_t        rxokmu;
240         uint16_t        txabt;
241         uint16_t        txundrn;
242 };
243
244 enum {                                          /* Variants */
245         Rtl8100e        = (0x8136<<16)|0x10EC,  /* RTL810[01]E: pci -e */
246         Rtl8169c        = (0x0116<<16)|0x16EC,  /* RTL8169C+ (USR997902) */
247         Rtl8169sc       = (0x8167<<16)|0x10EC,  /* RTL8169SC */
248         Rtl8168b        = (0x8168<<16)|0x10EC,  /* RTL8168B: pci-e */
249         Rtl8169         = (0x8169<<16)|0x10EC,  /* RTL8169 */
250 };
251
252 struct ctlr {
253         int     port;
254         struct pci_device *pci;
255         struct ctlr*    next;
256         int     active;
257
258         qlock_t alock;                  /* attach */
259         spinlock_t      ilock;                  /* init */
260         int     init;                   /*  */
261
262         int     pciv;                   /*  */
263         int     macv;                   /* MAC version */
264         int     phyv;                   /* PHY version */
265         int     pcie;                   /* flag: pci-express device? */
266
267         uint64_t        mchash;                 /* multicast hash */
268
269         struct mii*     mii;
270
271         spinlock_t      tlock;                  /* transmit */
272         D*      td;                     /* descriptor ring */
273         struct block**  tb;                     /* transmit buffers */
274         int     ntd;
275
276         int     tdh;                    /* head - producer index (host) */
277         int     tdt;                    /* tail - consumer index (NIC) */
278         int     ntdfree;
279         int     ntq;
280
281         int     mtps;                   /* Max. Transmit Packet Size */
282
283         spinlock_t      rlock;                  /* receive */
284         D*      rd;                     /* descriptor ring */
285         struct block**  rb;                     /* receive buffers */
286         int     nrd;
287
288         int     rdh;                    /* head - producer index (NIC) */
289         int     rdt;                    /* tail - consumer index (host) */
290         int     nrdfree;
291
292         int     tcr;                    /* transmit configuration register */
293         int     rcr;                    /* receive configuration register */
294         int     imr;
295
296         qlock_t slock;                  /* statistics */
297         Dtcc*   dtcc;
298         unsigned int    txdu;
299         unsigned int    tcpf;
300         unsigned int    udpf;
301         unsigned int    ipf;
302         unsigned int    fovf;
303         unsigned int    ierrs;
304         unsigned int    rer;
305         unsigned int    rdu;
306         unsigned int    punlc;
307         unsigned int    fovw;
308         unsigned int    mcast;
309 };
310
311 static struct ctlr* rtl8169ctlrhead;
312 static struct ctlr* rtl8169ctlrtail;
313
314 #define csr8r(c, r)     (inb((c)->port+(r)))
315 #define csr16r(c, r)    (inw((c)->port+(r)))
316 #define csr32r(c, r)    (inl((c)->port+(r)))
317 #define csr8w(c, r, b)  (outb((c)->port+(r), (uint8_t)(b)))
318 #define csr16w(c, r, w) (outw((c)->port+(r), (uint16_t)(w)))
319 #define csr32w(c, r, l) (outl((c)->port+(r), (uint32_t)(l)))
320
321 static int
322 rtl8169miimir(struct ctlr* ctlr, int pa, int ra)
323 {
324         unsigned int r;
325         int timeo;
326
327         if(pa != 1)
328                 return -1;
329
330         r = (ra<<16) & RegaddrMASK;
331         csr32w(ctlr, Phyar, r);
332         udelay(1000*1);
333         for(timeo = 0; timeo < 2000; timeo++){
334                 if((r = csr32r(ctlr, Phyar)) & Flag)
335                         break;
336                 udelay(100);
337         }
338         if(!(r & Flag))
339                 return -1;
340
341         return (r & DataMASK)>>DataSHIFT;
342 }
343
344 static int
345 rtl8169miimiw(struct ctlr* ctlr, int pa, int ra, int data)
346 {
347         unsigned int r;
348         int timeo;
349
350         if(pa != 1)
351                 return -1;
352
353         r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
354         csr32w(ctlr, Phyar, r);
355         udelay(1000*1);
356         for(timeo = 0; timeo < 2000; timeo++){
357                 if(!((r = csr32r(ctlr, Phyar)) & Flag))
358                         break;
359                 udelay(100);
360         }
361         if(r & Flag)
362                 return -1;
363
364         return 0;
365 }
366
367 static int
368 rtl8169miirw(struct mii* mii, int write, int pa, int ra, int data)
369 {
370         if(write)
371                 return rtl8169miimiw(mii->ctlr, pa, ra, data);
372
373         return rtl8169miimir(mii->ctlr, pa, ra);
374 }
375
376 static struct mii*
377 rtl8169mii(struct ctlr* ctlr)
378 {
379         struct mii* mii;
380         struct miiphy *phy;
381
382         /*
383          * Link management.
384          *
385          * Get rev number out of Phyidr2 so can config properly.
386          * There's probably more special stuff for Macv0[234] needed here.
387          */
388         ctlr->phyv = rtl8169miimir(ctlr, 1, Phyidr2) & 0x0F;
389         if(ctlr->macv == Macv02){
390                 csr8w(ctlr, 0x82, 1);                           /* magic */
391                 rtl8169miimiw(ctlr, 1, 0x0B, 0x0000);           /* magic */
392         }
393         if((mii = miiattach(ctlr, (1<<1), rtl8169miirw)) == NULL)
394                 return NULL;
395
396         phy = mii->curphy;
397         printd("oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
398                 phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
399
400         if(miistatus(mii) < 0){
401                 miireset(mii);
402                 miiane(mii, ~0, ~0, ~0);
403         }
404
405         return mii;
406 }
407
408 static void
409 rtl8169promiscuous(void* arg, int on)
410 {
411         struct ether *edev;
412         struct ctlr * ctlr;
413
414         edev = arg;
415         ctlr = edev->ctlr;
416         ilock(&ctlr->ilock);
417
418         if(on)
419                 ctlr->rcr |= Aap;
420         else
421                 ctlr->rcr &= ~Aap;
422         csr32w(ctlr, Rcr, ctlr->rcr);
423         iunlock(&ctlr->ilock);
424 }
425
426 enum {
427         /* everyone else uses 0x04c11db7, but they both produce the same crc */
428         Etherpolybe = 0x04c11db6,
429         Bytemask = (1<<8) - 1,
430 };
431
432 static uint32_t
433 ethercrcbe(uint8_t *addr, long len)
434 {
435         int i, j;
436         uint32_t c, crc, carry;
437
438         crc = ~0U;
439         for (i = 0; i < len; i++) {
440                 c = addr[i];
441                 for (j = 0; j < 8; j++) {
442                         carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
443                         crc <<= 1;
444                         c >>= 1;
445                         if (carry)
446                                 crc = (crc ^ Etherpolybe) | carry;
447                 }
448         }
449         return crc;
450 }
451
452 static uint32_t
453 swabl(uint32_t l)
454 {
455         return (l>>24) | ((l>>8) & (Bytemask<<8)) |
456                 ((l<<8) & (Bytemask<<16)) | (l<<24);
457 }
458
459 static void
460 rtl8169multicast(void* ether, uint8_t *eaddr, int add)
461 {
462         struct ether *edev;
463         struct ctlr *ctlr;
464
465         if (!add)
466                 return; /* ok to keep receiving on old mcast addrs */
467
468         edev = ether;
469         ctlr = edev->ctlr;
470         ilock(&ctlr->ilock);
471
472         ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
473
474         ctlr->rcr |= Am;
475         csr32w(ctlr, Rcr, ctlr->rcr);
476
477         /* pci-e variants reverse the order of the hash byte registers */
478         if (ctlr->pcie) {
479                 csr32w(ctlr, Mar0,   swabl(ctlr->mchash>>32));
480                 csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
481         } else {
482                 csr32w(ctlr, Mar0,   ctlr->mchash);
483                 csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
484         }
485
486         iunlock(&ctlr->ilock);
487 }
488
489 static long
490 rtl8169ifstat(struct ether* edev, void* a, long n, uint32_t offset)
491 {
492         ERRSTACK(2);
493         struct ctlr *ctlr;
494         Dtcc *dtcc;
495         int timeo;
496         char *alloc, *e, *p;
497
498         ctlr = edev->ctlr;
499         qlock(&ctlr->slock);
500
501         alloc = NULL;
502         if(waserror()){
503                 qunlock(&ctlr->slock);
504                 kfree(alloc);
505                 nexterror();
506         }
507
508         csr32w(ctlr, Dtccr+4, 0);
509         csr32w(ctlr, Dtccr, paddr_low32(ctlr->dtcc)|Cmd);
510         for(timeo = 0; timeo < 1000; timeo++){
511                 if(!(csr32r(ctlr, Dtccr) & Cmd))
512                         break;
513                 udelay(1000*1);
514         }
515         if(csr32r(ctlr, Dtccr) & Cmd)
516                 error(Eio);
517         dtcc = ctlr->dtcc;
518
519         edev->oerrs = dtcc->txer;
520         edev->crcs = dtcc->rxer;
521         edev->frames = dtcc->fae;
522         edev->buffs = dtcc->misspkt;
523         edev->overflows = ctlr->txdu+ctlr->rdu;
524
525         if(n == 0){
526                 qunlock(&ctlr->slock);
527                 poperror();
528                 return 0;
529         }
530
531         if((alloc = kzmalloc(READSTR, 0)) == NULL)
532                 error(Enomem);
533         e = alloc+READSTR;
534
535         p = seprintf(alloc, e, "TxOk: %llu\n", dtcc->txok);
536         p = seprintf(p, e, "RxOk: %llu\n", dtcc->rxok);
537         p = seprintf(p, e, "TxEr: %llu\n", dtcc->txer);
538         p = seprintf(p, e, "RxEr: %u\n", dtcc->rxer);
539         p = seprintf(p, e, "MissPkt: %u\n", dtcc->misspkt);
540         p = seprintf(p, e, "FAE: %u\n", dtcc->fae);
541         p = seprintf(p, e, "Tx1Col: %u\n", dtcc->tx1col);
542         p = seprintf(p, e, "TxMCol: %u\n", dtcc->txmcol);
543         p = seprintf(p, e, "RxOkPh: %llu\n", dtcc->rxokph);
544         p = seprintf(p, e, "RxOkBrd: %llu\n", dtcc->rxokbrd);
545         p = seprintf(p, e, "RxOkMu: %u\n", dtcc->rxokmu);
546         p = seprintf(p, e, "TxAbt: %u\n", dtcc->txabt);
547         p = seprintf(p, e, "TxUndrn: %u\n", dtcc->txundrn);
548
549         p = seprintf(p, e, "txdu: %u\n", ctlr->txdu);
550         p = seprintf(p, e, "tcpf: %u\n", ctlr->tcpf);
551         p = seprintf(p, e, "udpf: %u\n", ctlr->udpf);
552         p = seprintf(p, e, "ipf: %u\n", ctlr->ipf);
553         p = seprintf(p, e, "fovf: %u\n", ctlr->fovf);
554         p = seprintf(p, e, "ierrs: %u\n", ctlr->ierrs);
555         p = seprintf(p, e, "rer: %u\n", ctlr->rer);
556         p = seprintf(p, e, "rdu: %u\n", ctlr->rdu);
557         p = seprintf(p, e, "punlc: %u\n", ctlr->punlc);
558         p = seprintf(p, e, "fovw: %u\n", ctlr->fovw);
559
560         p = seprintf(p, e, "tcr: 0x%#8.8u\n", ctlr->tcr);
561         p = seprintf(p, e, "rcr: 0x%#8.8u\n", ctlr->rcr);
562         p = seprintf(p, e, "multicast: %u\n", ctlr->mcast);
563
564         if(ctlr->mii != NULL && ctlr->mii->curphy != NULL)
565                 miidumpphy(ctlr->mii, p, e);
566
567         n = readstr(offset, a, n, alloc);
568
569         qunlock(&ctlr->slock);
570         poperror();
571         kfree(alloc);
572
573         return n;
574 }
575
576 static void
577 rtl8169halt(struct ctlr* ctlr)
578 {
579         csr8w(ctlr, Cr, 0);
580         csr16w(ctlr, Imr, 0);
581         csr16w(ctlr, Isr, ~0);
582 }
583
584 static int
585 rtl8169reset(struct ctlr* ctlr)
586 {
587         uint32_t r;
588         int timeo;
589
590         /*
591          * Soft reset the controller.
592          */
593         csr8w(ctlr, Cr, Rst);
594         for(r = timeo = 0; timeo < 1000; timeo++){
595                 r = csr8r(ctlr, Cr);
596                 if(!(r & Rst))
597                         break;
598                 udelay(1000*1);
599         }
600         rtl8169halt(ctlr);
601
602         if(r & Rst)
603                 return -1;
604         return 0;
605 }
606
607 static void
608 rtl8169replenish(struct ctlr* ctlr)
609 {
610         D *d;
611         int rdt;
612         struct block *bp;
613
614         rdt = ctlr->rdt;
615         while(NEXT_RING(rdt, ctlr->nrd) != ctlr->rdh){
616                 d = &ctlr->rd[rdt];
617                 if(ctlr->rb[rdt] == NULL){
618                         /*
619                          * Simple allocation for now.
620                          * This better be aligned on 8.
621                          */
622                         bp = iallocb(Mps);
623                         if(bp == NULL){
624                                 printk("no available buffers\n");
625                                 break;
626                         }
627                         ctlr->rb[rdt] = bp;
628                         d->addrlo = paddr_low32(bp->rp);
629                         d->addrhi = paddr_high32(bp->rp);
630                 }
631                 wmb();
632                 d->control |= Own|Mps;
633                 rdt = NEXT_RING(rdt, ctlr->nrd);
634                 ctlr->nrdfree++;
635         }
636         ctlr->rdt = rdt;
637 }
638
639 static int
640 rtl8169init(struct ether* edev)
641 {
642         int i;
643         uint32_t r;
644         struct block *bp;
645         struct ctlr *ctlr;
646         uint8_t cplusc;
647
648         ctlr = edev->ctlr;
649         ilock(&ctlr->ilock);
650
651         rtl8169halt(ctlr);
652
653         /*
654          * MAC Address.
655          * Must put chip into config register write enable mode.
656          */
657         csr8w(ctlr, Cr9346, Eem1|Eem0);
658         r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
659         csr32w(ctlr, Idr0, r);
660         r = (edev->ea[5]<<8)|edev->ea[4];
661         csr32w(ctlr, Idr0+4, r);
662
663         /*
664          * Transmitter.
665          */
666         memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
667         ctlr->tdh = ctlr->tdt = 0;
668         ctlr->td[ctlr->ntd-1].control = Eor;
669
670         /*
671          * Receiver.
672          * Need to do something here about the multicast filter.
673          */
674         memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
675         ctlr->nrdfree = ctlr->rdh = ctlr->rdt = 0;
676         ctlr->rd[ctlr->nrd-1].control = Eor;
677
678         for(i = 0; i < ctlr->nrd; i++){
679                 if((bp = ctlr->rb[i]) != NULL){
680                         ctlr->rb[i] = NULL;
681                         freeb(bp);
682                 }
683         }
684         rtl8169replenish(ctlr);
685         ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
686
687         /*
688          * Mtps is in units of 128 except for the RTL8169
689          * where is is 32. If using jumbo frames should be
690          * set to 0x3F.
691          * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst
692          * settings in Tcr/Rcr; the (1<<14) is magic.
693          */
694         ctlr->mtps = HOWMANY(Mps, 128);
695         cplusc = csr16r(ctlr, Cplusc) & ~(1<<14);
696         cplusc |= /*Rxchksum|*/Mulrw;
697         switch(ctlr->macv){
698         default:
699                 printd("rtl8169: unsupported macv %#ux\n", ctlr->macv);
700                 break;  /* perhaps it just works */
701         case Macv01:
702                 ctlr->mtps = HOWMANY(Mps, 32);
703                 break;
704         case Macv02:
705         case Macv03:
706                 cplusc |= (1<<14);                      /* magic */
707                 break;
708         case Macv05:
709                 /*
710                  * This is interpreted from clearly bogus code
711                  * in the manufacturer-supplied driver, it could
712                  * be wrong. Untested.
713                  */
714                 printk("untested\n");
715                 break;
716 #if 0         
717                 r = csr8r(ctlr, Config2) & 0x07;
718                 if(r == 0x01)                           /* 66MHz PCI */
719                         csr32w(ctlr, 0x7C, 0x0007FFFF); /* magic */
720                 else
721                         csr32w(ctlr, 0x7C, 0x0007FF00); /* magic */
722                 pciclrmwi(ctlr->pcidev);
723 #endif
724                 break;
725         case Macv13:
726                 printk("untested macv13 write\n");
727                 break;
728 #if 0
729                 /*
730                  * This is interpreted from clearly bogus code
731                  * in the manufacturer-supplied driver, it could
732                  * be wrong. Untested.
733                  */
734                 pcicfgw8(ctlr->pcidev, 0x68, 0x00);     /* magic */
735                 pcicfgw8(ctlr->pcidev, 0x69, 0x08);     /* magic */
736                 break;
737 #endif
738         case Macv04:
739         case Macv11:
740         case Macv12:
741         case Macv14:
742         case Macv15:
743                 break;
744         }
745
746         /*
747          * Enable receiver/transmitter.
748          * Need to do this first or some of the settings below
749          * won't take.
750          */
751         switch(ctlr->pciv){
752         default:
753                 csr8w(ctlr, Cr, Te|Re);
754                 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
755                 csr32w(ctlr, Rcr, ctlr->rcr);
756                 csr32w(ctlr, Mar0,   0);
757                 csr32w(ctlr, Mar0+4, 0);
758                 ctlr->mchash = 0;
759         case Rtl8169sc:
760         case Rtl8168b:
761                 break;
762         }
763
764         /*
765          * Interrupts.
766          * Disable Tdu|Tok for now, the transmit routine will tidy.
767          * Tdu means the NIC ran out of descriptors to send, so it
768          * doesn't really need to ever be on.
769          */
770         csr32w(ctlr, Timerint, 0);
771         ctlr->imr = Serr|Timeout|Fovw|Punlc|Rdu|Ter|Rer|Rok;
772         csr16w(ctlr, Imr, ctlr->imr);
773
774         /*
775          * Clear missed-packet counter;
776          * initial early transmit threshold value;
777          * set the descriptor ring base addresses;
778          * set the maximum receive packet size;
779          * no early-receive interrupts.
780          */
781         csr32w(ctlr, Mpc, 0);
782         csr8w(ctlr, Mtps, ctlr->mtps);
783         csr32w(ctlr, Tnpds + 4, paddr_high32(ctlr->td));
784         csr32w(ctlr, Tnpds, paddr_low32(ctlr->td));
785         csr32w(ctlr, Rdsar + 4, paddr_high32(ctlr->rd));
786         csr32w(ctlr, Rdsar, paddr_low32(ctlr->rd));
787         csr16w(ctlr, Rms, Mps);
788         r = csr16r(ctlr, Mulint) & 0xF000;
789         csr16w(ctlr, Mulint, r);
790         csr16w(ctlr, Cplusc, cplusc);
791
792         /*
793          * Set configuration.
794          */
795         switch(ctlr->pciv){
796         default:
797                 break;
798         case Rtl8169sc:
799                 csr16w(ctlr, 0xE2, 0);                  /* magic */
800                 csr8w(ctlr, Cr, Te|Re);
801                 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
802                 csr32w(ctlr, Rcr, ctlr->rcr);
803                 break;
804         case Rtl8168b:
805         case Rtl8169c:
806                 csr16w(ctlr, 0xE2, 0);                  /* magic */
807                 csr16w(ctlr, Cplusc, 0x2000);           /* magic */
808                 csr8w(ctlr, Cr, Te|Re);
809                 csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
810                 csr32w(ctlr, Rcr, ctlr->rcr);
811                 csr16w(ctlr, Rms, 0x0800);
812                 csr8w(ctlr, Mtps, 0x3F);
813                 break;
814         }
815         ctlr->tcr = csr32r(ctlr, Tcr);
816         csr8w(ctlr, Cr9346, 0);
817
818         iunlock(&ctlr->ilock);
819
820 //      rtl8169mii(ctlr);
821
822         return 0;
823 }
824
825 static void
826 rtl8169attach(struct ether* edev)
827 {
828         int timeo;
829         struct ctlr *ctlr;
830         struct miiphy *phy;
831
832         ctlr = edev->ctlr;
833         qlock(&ctlr->alock);
834         if(ctlr->init == 0){
835                 /*
836                  * Handle allocation/init errors here.
837                  */
838                 ctlr->td = kzmalloc_align(sizeof(D) * Ntd, KMALLOC_WAIT, 256);
839                 ctlr->tb = kzmalloc(Ntd * sizeof(struct block *), KMALLOC_WAIT);
840                 ctlr->ntd = Ntd;
841                 ctlr->rd = kzmalloc_align(sizeof(D) * Nrd, KMALLOC_WAIT, 256);
842                 ctlr->rb = kzmalloc(Nrd * sizeof(struct block *), KMALLOC_WAIT);
843                 ctlr->nrd = Nrd;
844                 ctlr->dtcc = kzmalloc_align(sizeof(Dtcc), KMALLOC_WAIT, 64);
845                 rtl8169init(edev);
846                 ctlr->init = 1;
847         }
848         qunlock(&ctlr->alock);
849
850         /*
851          * Wait for link to be ready.
852          */
853         for(timeo = 0; timeo < 350; timeo++){
854                 if(miistatus(ctlr->mii) == 0)
855                         break;
856                 udelay_sched(10000);
857         }
858         phy = ctlr->mii->curphy;
859         printd("%s: speed %d fd %d link %d rfc %d tfc %d\n",
860                 edev->name, phy->speed, phy->fd, phy->link, phy->rfc,
861                phy->tfc);
862 }
863
864 static void
865 rtl8169link(struct ether* edev)
866 {
867         int limit;
868         struct ctlr *ctlr;
869         struct miiphy *phy;
870
871         ctlr = edev->ctlr;
872
873         /*
874          * Maybe the link changed - do we care very much?
875          * Could stall transmits if no link, maybe?
876          */
877         if(ctlr->mii == NULL || ctlr->mii->curphy == NULL)
878                 return;
879
880         phy = ctlr->mii->curphy;
881         if(miistatus(ctlr->mii) < 0){
882                 // TODO : no name here
883                 printk("%slink n: speed %d fd %d link %d rfc %d tfc %d\n",
884                         edev->name, phy->speed, phy->fd, phy->link,
885                         phy->rfc, phy->tfc);
886                 edev->link = 0;
887                 return;
888         }
889         edev->link = 1;
890
891         limit = 256*1024;
892         if(phy->speed == 10){
893                 edev->mbps = 10;
894                 limit = 65*1024;
895         }
896         else if(phy->speed == 100)
897                 edev->mbps = 100;
898         else if(phy->speed == 1000)
899                 edev->mbps = 1000;
900         printk("%slink y: speed %d fd %d link %d rfc %d tfc %d\n",
901                 edev->name, phy->speed, phy->fd, phy->link,
902                 phy->rfc, phy->tfc);
903
904         if(edev->oq != NULL)
905                 qsetlimit(edev->oq, limit);
906 }
907
908 static void
909 rtl8169transmit(struct ether* edev)
910 {
911         D *d;
912         struct block *bp;
913         struct ctlr *ctlr;
914         int control, x;
915
916         ctlr = edev->ctlr;
917
918         ilock(&ctlr->tlock);
919         for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT_RING(x, ctlr->ntd)){
920                 d = &ctlr->td[x];
921                 if((control = d->control) & Own)
922                         break;
923
924                 /*
925                  * Check errors and log here.
926                  */
927
928                 /*
929                  * Free it up.
930                  * Need to clean the descriptor here? Not really.
931                  * Simple freeb for now (no chain and freeblist).
932                  * Use ntq count for now.
933                  */
934                 freeb(ctlr->tb[x]);
935                 ctlr->tb[x] = NULL;
936                 d->control &= Eor;
937
938                 ctlr->ntq--;
939         }
940         ctlr->tdh = x;
941
942         x = ctlr->tdt;
943         while(ctlr->ntq < (ctlr->ntd-1)){
944                 if((bp = qget(edev->oq)) == NULL)
945                         break;
946
947                 d = &ctlr->td[x];
948                 d->addrlo = paddr_low32(bp->rp);
949                 d->addrhi = paddr_high32(bp->rp);
950                 ctlr->tb[x] = bp;
951                 wmb();
952                 d->control |= Own|Fs|Ls|((BLEN(bp)<<TxflSHIFT) & TxflMASK);
953
954                 x = NEXT_RING(x, ctlr->ntd);
955                 ctlr->ntq++;
956         }
957         if(x != ctlr->tdt){
958                 ctlr->tdt = x;
959                 csr8w(ctlr, Tppoll, Npq);
960         }
961         else if(ctlr->ntq >= (ctlr->ntd-1))
962                 ctlr->txdu++;
963
964         iunlock(&ctlr->tlock);
965 }
966
967 static void
968 rtl8169receive(struct ether* edev)
969 {
970         D *d;
971         int rdh;
972         struct block *bp;
973         struct ctlr *ctlr;
974         uint32_t control;
975
976         ctlr = edev->ctlr;
977
978         rdh = ctlr->rdh;
979         for(;;){
980                 d = &ctlr->rd[rdh];
981
982                 if(d->control & Own)
983                         break;
984
985                 control = d->control;
986                 if((control & (Fs|Ls|Res)) == (Fs|Ls)){
987                         bp = ctlr->rb[rdh];
988                         ctlr->rb[rdh] = NULL;
989                         bp->wp = bp->rp + ((control & RxflMASK)>>RxflSHIFT)-4;
990                         bp->next = NULL;
991
992                         if(control & Fovf)
993                                 ctlr->fovf++;
994                         if(control & Mar)
995                                 ctlr->mcast++;
996
997                         switch(control & (Pid1|Pid0)){
998                         default:
999                                 break;
1000                         case Pid0:
1001                                 if(control & Tcpf){
1002                                         ctlr->tcpf++;
1003                                         break;
1004                                 }
1005                                 bp->flag |= Btcpck;
1006                                 break;
1007                         case Pid1:
1008                                 if(control & Udpf){
1009                                         ctlr->udpf++;
1010                                         break;
1011                                 }
1012                                 bp->flag |= Budpck;
1013                                 break;
1014                         case Pid1|Pid0:
1015                                 if(control & Ipf){
1016                                         ctlr->ipf++;
1017                                         break;
1018                                 }
1019                                 bp->flag |= Bipck;
1020                                 break;
1021                         }
1022                         etheriq(edev, bp, 1);
1023                 }
1024                 else{
1025                         /*
1026                          * Error stuff here.
1027                         print("control %#8.8ux\n", control);
1028                          */
1029                 }
1030                 d->control &= Eor;
1031                 ctlr->nrdfree--;
1032                 rdh = NEXT_RING(rdh, ctlr->nrd);
1033
1034                 if(ctlr->nrdfree < ctlr->nrd/2)
1035                         rtl8169replenish(ctlr);
1036         }
1037         ctlr->rdh = rdh;
1038 }
1039
1040 static void
1041 rtl8169interrupt(struct hw_trapframe *hw_tf, void *arg)
1042 {
1043         struct ctlr *ctlr;
1044         struct ether *edev;
1045         uint32_t isr;
1046
1047         edev = arg;
1048         ctlr = edev->ctlr;
1049
1050         while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
1051                 csr16w(ctlr, Isr, isr);
1052                 if((isr & ctlr->imr) == 0)
1053                         break;
1054                 if(isr & (Fovw|Punlc|Rdu|Rer|Rok)){
1055                         rtl8169receive(edev);
1056                         if(!(isr & (Punlc|Rok)))
1057                                 ctlr->ierrs++;
1058                         if(isr & Rer)
1059                                 ctlr->rer++;
1060                         if(isr & Rdu)
1061                                 ctlr->rdu++;
1062                         if(isr & Punlc)
1063                                 ctlr->punlc++;
1064                         if(isr & Fovw)
1065                                 ctlr->fovw++;
1066                         isr &= ~(Fovw|Rdu|Rer|Rok);
1067                 }
1068
1069                 if(isr & (Tdu|Ter|Tok)){
1070                         rtl8169transmit(edev);
1071                         isr &= ~(Tdu|Ter|Tok);
1072                 }
1073
1074                 if(isr & Punlc){
1075                         rtl8169link(edev);
1076                         isr &= ~Punlc;
1077                 }
1078
1079                 /*
1080                  * Some of the reserved bits get set sometimes...
1081                  */
1082                 if(isr & (Serr|Timeout|Tdu|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok))
1083                         panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux\n",
1084                                 csr16r(ctlr, Imr), isr);
1085         }
1086 }
1087
1088 static void
1089 rtl8169pci(void)
1090 {
1091         struct pci_device *pcidev;
1092
1093         struct ctlr *ctlr;
1094         int id, port, pcie;
1095
1096         STAILQ_FOREACH(pcidev, &pci_devices, all_dev) {
1097                 /* This checks that pcidev is a Network Controller for Ethernet */
1098                 if (pcidev->class != 0x02 || pcidev->subclass != 0x00)
1099                         continue;
1100                 id = pcidev->dev_id << 16 | pcidev->ven_id;
1101
1102                 pcie = 0;
1103                 switch(id) {
1104                 default:
1105                         continue;
1106                 case Rtl8100e:                  /* RTL810[01]E ? */
1107                 case Rtl8168b:                  /* RTL8168B */
1108                         pcie = 1;
1109                         break;
1110                 case Rtl8169c:                  /* RTL8169C */
1111                 case Rtl8169sc:                 /* RTL8169SC */
1112                 case Rtl8169:                   /* RTL8169 */
1113                         break;
1114                 case (0xC107<<16)|0x1259:       /* Corega CG-LAPCIGT */
1115                         id = Rtl8169;
1116                         break;
1117                 }
1118                 printk("rtl8169 driver found 0x%04x:%04x at %02x:%02x.%x\n",
1119                        pcidev->ven_id, pcidev->dev_id,
1120                        pcidev->bus, pcidev->dev, pcidev->func);
1121
1122                 port = pcidev->bar[0].pio_base;
1123
1124                 ctlr = kzmalloc(sizeof(struct ctlr), KMALLOC_WAIT);
1125                 spinlock_init_irqsave(&ctlr->ilock);
1126                 spinlock_init_irqsave(&ctlr->tlock);
1127                 spinlock_init_irqsave(&ctlr->rlock);
1128                 qlock_init(&ctlr->alock);
1129                 qlock_init(&ctlr->slock);
1130
1131                 ctlr->port = port;
1132                 ctlr->pci = pcidev;
1133                 ctlr->pciv = id;
1134                 ctlr->pcie = pcie;
1135
1136                 /* pcipms is something related to power mgmt, i think */
1137                 #if 0
1138                 if(pcigetpms(p) > 0){
1139                         pcisetpms(p, 0);
1140
1141                         for(int i = 0; i < 6; i++)
1142                                 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
1143                         pcicfgw8(p, PciINTL, p->intl);
1144                         pcicfgw8(p, PciLTR, p->ltr);
1145                         pcicfgw8(p, PciCLS, p->cls);
1146                         pcicfgw16(p, PciPCR, p->pcr);
1147                 }
1148                 #endif
1149
1150                 if(rtl8169reset(ctlr)){
1151                         kfree(ctlr);
1152                         continue;
1153                 }
1154
1155                 /*
1156                  * Extract the chip hardware version,
1157                  * needed to configure each properly.
1158                  */
1159                 ctlr->macv = csr32r(ctlr, Tcr) & HwveridMASK;
1160                 if((ctlr->mii = rtl8169mii(ctlr)) == NULL){
1161                         kfree(ctlr);
1162                         continue;
1163                 }
1164
1165                 pci_set_bus_master(pcidev);
1166
1167                 if(rtl8169ctlrhead != NULL)
1168                         rtl8169ctlrtail->next = ctlr;
1169                 else
1170                         rtl8169ctlrhead = ctlr;
1171                 rtl8169ctlrtail = ctlr;
1172         }
1173 }
1174
1175 static int
1176 rtl8169pnp(struct ether* edev)
1177 {
1178         uint32_t r;
1179         struct ctlr *ctlr;
1180         uint8_t ea[Eaddrlen];
1181
1182         run_once(rtl8169pci());
1183
1184         /*
1185          * Any adapter matches if no edev->port is supplied,
1186          * otherwise the ports must match.
1187          */
1188         for(ctlr = rtl8169ctlrhead; ctlr != NULL; ctlr = ctlr->next){
1189                 if(ctlr->active)
1190                         continue;
1191                 if(edev->port == 0 || edev->port == ctlr->port){
1192                         ctlr->active = 1;
1193                         break;
1194                 }
1195         }
1196         if(ctlr == NULL)
1197                 return -1;
1198
1199         edev->ctlr = ctlr;
1200         edev->port = ctlr->port;
1201         edev->irq = ctlr->pci->irqline;
1202         edev->mbps = 100;
1203
1204         /*
1205          * Check if the adapter's station address is to be overridden.
1206          * If not, read it from the device and set in edev->ea.
1207          */
1208         memset(ea, 0, Eaddrlen);
1209         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
1210                 r = csr32r(ctlr, Idr0);
1211                 edev->ea[0] = r;
1212                 edev->ea[1] = r>>8;
1213                 edev->ea[2] = r>>16;
1214                 edev->ea[3] = r>>24;
1215                 r = csr32r(ctlr, Idr0+4);
1216                 edev->ea[4] = r;
1217                 edev->ea[5] = r>>8;
1218         }
1219
1220         edev->tbdf = pci_to_tbdf(ctlr->pci);
1221         edev->attach = rtl8169attach;
1222         edev->transmit = rtl8169transmit;
1223         edev->ifstat = rtl8169ifstat;
1224
1225         edev->arg = edev;
1226         edev->promiscuous = rtl8169promiscuous;
1227         edev->multicast = rtl8169multicast;
1228 //      edev->netif.shutdown = rtl8169shutdown;
1229
1230         rtl8169link(edev);
1231         register_irq(edev->irq, rtl8169interrupt, edev, edev->tbdf);
1232
1233         return 0;
1234 }
1235
1236 linker_func_3(ether8169link)
1237 {
1238         addethercard("rtl8169", rtl8169pnp);
1239 }