rtl8139 port
[akaros.git] / kern / drivers / net / ether8139.c
1 // INFERNO
2 /*
3  * Realtek 8139 (but not the 8129).
4  * Error recovery for the various over/under -flow conditions
5  * may need work.
6  */
7 #include <vfs.h>
8 #include <kfs.h>
9 #include <slab.h>
10 #include <kmalloc.h>
11 #include <kref.h>
12 #include <string.h>
13 #include <stdio.h>
14 #include <assert.h>
15 #include <error.h>
16 #include <cpio.h>
17 #include <pmap.h>
18 #include <smp.h>
19 #include <ip.h>
20
21 enum {                                                  /* registers */
22         Idr0 = 0x0000,                          /* MAC address */
23         Mar0 = 0x0008,  /* Multicast address */
24         Tsd0 = 0x0010,  /* Transmit Status Descriptor0 */
25         Tsad0 = 0x0020, /* Transmit Start Address Descriptor0 */
26         Rbstart = 0x0030,       /* Receive Buffer Start Address */
27         Erbcr = 0x0034, /* Early Receive Byte Count */
28         Ersr = 0x0036,  /* Early Receive Status */
29         Cr = 0x0037,    /* Command Register */
30         Capr = 0x0038,  /* Current Address of Packet Read */
31         Cbr = 0x003A,   /* Current Buffer Address */
32         Imr = 0x003C,   /* Interrupt Mask */
33         Isr = 0x003E,   /* Interrupt Status */
34         Tcr = 0x0040,   /* Transmit Configuration */
35         Rcr = 0x0044,   /* Receive Configuration */
36         Tctr = 0x0048,  /* Timer Count */
37         Mpc = 0x004C,   /* Missed Packet Counter */
38         Cr9346 = 0x0050,        /* 9346 Command Register */
39         Config0 = 0x0051,       /* Configuration Register 0 */
40         Config1 = 0x0052,       /* Configuration Register 1 */
41         TimerInt = 0x0054,      /* Timer Interrupt */
42         Msr = 0x0058,   /* Media Status */
43         Config3 = 0x0059,       /* Configuration Register 3 */
44         Config4 = 0x005A,       /* Configuration Register 4 */
45         Mulint = 0x005C,        /* Multiple Interrupt Select */
46         RerID = 0x005E, /* PCI Revision ID */
47         Tsad = 0x0060,  /* Transmit Status of all Descriptors */
48
49         Bmcr = 0x0062,  /* Basic Mode Control */
50         Bmsr = 0x0064,  /* Basic Mode Status */
51         Anar = 0x0066,  /* Auto-Negotiation Advertisment */
52         Anlpar = 0x0068,        /* Auto-Negotiation Link Partner */
53         Aner = 0x006A,  /* Auto-Negotiation Expansion */
54         Dis = 0x006C,   /* Disconnect Counter */
55         Fcsc = 0x006E,  /* False Carrier Sense Counter */
56         Nwaytr = 0x0070,        /* N-way Test */
57         Rec = 0x0072,   /* RX_ER Counter */
58         Cscr = 0x0074,  /* CS Configuration */
59         Phy1parm = 0x0078,      /* PHY Parameter 1 */
60         Twparm = 0x007C,        /* Twister Parameter */
61         Phy2parm = 0x0080,      /* PHY Parameter 2 */
62 };
63
64 enum {                                                  /* Cr */
65         Bufe = 0x01,                            /* Rx Buffer Empty */
66         Te = 0x04,      /* Transmitter Enable */
67         Re = 0x08,      /* Receiver Enable */
68         Rst = 0x10,     /* Software Reset */
69 };
70
71 enum {                                                  /* Imr/Isr */
72         Rok = 0x0001,                           /* Receive OK */
73         Rer = 0x0002,   /* Receive Error */
74         Tok = 0x0004,   /* Transmit OK */
75         Ter = 0x0008,   /* Transmit Error */
76         Rxovw = 0x0010, /* Receive Buffer Overflow */
77         PunLc = 0x0020, /* Packet Underrun or Link Change */
78         Fovw = 0x0040,  /* Receive FIFO Overflow */
79         Clc = 0x2000,   /* Cable Length Change */
80         Timerbit = 0x4000,      /* Timer */
81         Serr = 0x8000,  /* System Error */
82 };
83
84 enum {                                                  /* Tcr */
85         Clrabt = 0x00000001,            /* Clear Abort */
86         TxrrSHIFT = 4,  /* Transmit Retry Count */
87         TxrrMASK = 0x000000F0,
88         MtxdmaSHIFT = 8,        /* Max. DMA Burst Size */
89         MtxdmaMASK = 0x00000700,
90         Mtxdma2048 = 0x00000700,
91         Acrc = 0x00010000,      /* Append CRC (not) */
92         LbkSHIFT = 17,  /* Loopback Test */
93         LbkMASK = 0x00060000,
94         Rtl8139ArevG = 0x00800000,      /* RTL8139A Rev. G ID */
95         IfgSHIFT = 24,  /* Interframe Gap */
96         IfgMASK = 0x03000000,
97         HwveridSHIFT = 26,      /* Hardware Version ID */
98         HwveridMASK = 0x7C000000,
99 };
100
101 enum {                                                  /* Rcr */
102         Aap = 0x00000001,                       /* Accept All Packets */
103         Apm = 0x00000002,       /* Accept Physical Match */
104         Am = 0x00000004,        /* Accept Multicast */
105         Ab = 0x00000008,        /* Accept Broadcast */
106         Ar = 0x00000010,        /* Accept Runt */
107         Aer = 0x00000020,       /* Accept Error */
108         Sel9356 = 0x00000040,   /* 9356 EEPROM used */
109         Wrap = 0x00000080,      /* Rx Buffer Wrap Control */
110         MrxdmaSHIFT = 8,        /* Max. DMA Burst Size */
111         MrxdmaMASK = 0x00000700,
112         Mrxdmaunlimited = 0x00000700,
113         RblenSHIFT = 11,        /* Receive Buffer Length */
114         RblenMASK = 0x00001800,
115         Rblen8K = 0x00000000,   /* 8KB+16 */
116         Rblen16K = 0x00000800,  /* 16KB+16 */
117         Rblen32K = 0x00001000,  /* 32KB+16 */
118         Rblen64K = 0x00001800,  /* 64KB+16 */
119         RxfthSHIFT = 13,        /* Receive Buffer Length */
120         RxfthMASK = 0x0000E000,
121         Rxfth256 = 0x00008000,
122         Rxfthnone = 0x0000E000,
123         Rer8 = 0x00010000,      /* Accept Error Packets > 8 bytes */
124         MulERINT = 0x00020000,  /* Multiple Early Interrupt Select */
125         ErxthSHIFT = 24,        /* Early Rx Threshold */
126         ErxthMASK = 0x0F000000,
127         Erxthnone = 0x00000000,
128 };
129
130 enum {                                                  /* Received Packet Status */
131         Rcok = 0x0001,                          /* Receive Completed OK */
132         Fae = 0x0002,   /* Frame Alignment Error */
133         Crc = 0x0004,   /* CRC Error */
134         Long = 0x0008,  /* Long Packet */
135         Runt = 0x0010,  /* Runt Packet Received */
136         Ise = 0x0020,   /* Invalid Symbol Error */
137         Bar = 0x2000,   /* Broadcast Address Received */
138         Pam = 0x4000,   /* Physical Address Matched */
139         Mar = 0x8000,   /* Multicast Address Received */
140 };
141
142 enum {                                                  /* Media Status Register */
143         Rxpf = 0x01,                            /* Pause Flag */
144         Txpf = 0x02,    /* Pause Flag */
145         Linkb = 0x04,   /* Inverse of Link Status */
146         Speed10 = 0x08, /* 10Mbps */
147         Auxstatus = 0x10,       /* Aux. Power Present Status */
148         Rxfce = 0x40,   /* Receive Flow Control Enable */
149         Txfce = 0x80,   /* Transmit Flow Control Enable */
150 };
151
152 typedef struct Td Td;
153 struct Td {                                             /* Soft Transmit Descriptor */
154         int tsd;
155         int tsad;
156         uint8_t *data;
157         struct block *bp;
158 };
159
160 enum {                                                  /* Tsd0 */
161         SizeSHIFT = 0,                          /* Descriptor Size */
162         SizeMASK = 0x00001FFF,
163         Own = 0x00002000,
164         Tun = 0x00004000,       /* Transmit FIFO Underrun */
165         Tcok = 0x00008000,      /* Transmit COmpleted OK */
166         EtxthSHIFT = 16,        /* Early Tx Threshold */
167         EtxthMASK = 0x001F0000,
168         NccSHIFT = 24,  /* Number of Collisions Count */
169         NccMASK = 0x0F000000,
170         Cdh = 0x10000000,       /* CD Heartbeat */
171         Owc = 0x20000000,       /* Out of Window Collision */
172         Tabt = 0x40000000,      /* Transmit Abort */
173         Crs = 0x80000000,       /* Carrier Sense Lost */
174 };
175
176 enum {
177         Rblen = Rblen64K,                       /* Receive Buffer Length */
178         Ntd = 4,        /* Number of Transmit Descriptors */
179 };
180 #define         Tdbsz           ROUNDUP(sizeof(struct etherpkt), 4)
181
182 typedef struct ctlr {
183         int port;
184         struct pci_device *pcidev;
185         struct ctlr *next;
186         int active;
187         int id;
188
189         qlock_t alock;                          /* attach */
190         spinlock_t ilock;                       /* init */
191         void *alloc;                            /* base of per-ctlr allocated data */
192
193         int rcr;                                        /* receive configuration register */
194         uint8_t *rbstart;                       /* receive buffer */
195         int rblen;                                      /* receive buffer length */
196         int ierrs;                                      /* receive errors */
197
198         spinlock_t tlock;                       /* transmit */
199         Td td[Ntd];
200         int ntd;                                        /* descriptors active */
201         int tdh;                                        /* host index into td */
202         int tdi;                                        /* interface index into td */
203         int etxth;                                      /* early transmit threshold */
204         int taligned;                           /* packet required no alignment */
205         int tunaligned;                         /* packet required alignment */
206
207         int dis;                                        /* disconnect counter */
208         int fcsc;                                       /* false carrier sense counter */
209         int rec;                                        /* RX_ER counter */
210 } ctlr;
211
212 static struct ctlr *ctlrhead;
213 static struct ctlr *ctlrtail;
214
215 #define csr8r(c, r)     (inb((c)->port+(r)))
216 #define csr16r(c, r)    (inw((c)->port+(r)))
217 #define csr32r(c, r)    (inl((c)->port+(r)))
218 #define csr8w(c, r, b)  (outb((c)->port+(r), (int)(b)))
219 #define csr16w(c, r, w) (outw((c)->port+(r), (uint16_t)(w)))
220 #define csr32w(c, r, l) (outl((c)->port+(r), (uint32_t)(l)))
221
222 /* Helper for checking physical memory calculations.  This driver doesn't
223  * support 64 bit DMA, so we can't handle kaddrs that map to pages that are
224  * above the 32 bit phyiscal memory line (4GB) */
225 static void paddr_check(void *kaddr)
226 {
227         if (paddr_high32(kaddr))
228                 panic("rtl8139: attempted to publish paddr > 4GB!.  "
229                       "Try running with less memory.");
230 }
231
232 static void rtl8139promiscuous(void *arg, int on)
233 {
234         struct ether *edev;
235         struct ctlr *ctlr;
236
237         edev = arg;
238         ctlr = edev->ctlr;
239         spin_lock_irqsave(&ctlr->ilock);
240
241         if (on)
242                 ctlr->rcr |= Aap;
243         else
244                 ctlr->rcr &= ~Aap;
245         csr32w(ctlr, Rcr, ctlr->rcr);
246         spin_unlock_irqsave(&ctlr->ilock);
247 }
248
249 static long rtl8139ifstat(struct ether *edev, void *a, long n, uint32_t offset)
250 {
251         int l;
252         char *p;
253         struct ctlr *ctlr;
254
255         ctlr = edev->ctlr;
256         p = kzmalloc(READSTR, 0);
257         l = snprintf(p, READSTR, "rcr 0x%8.8x\n", ctlr->rcr);
258         l += snprintf(p + l, READSTR - l, "ierrs %d\n", ctlr->ierrs);
259         l += snprintf(p + l, READSTR - l, "etxth %d\n", ctlr->etxth);
260         l += snprintf(p + l, READSTR - l, "taligned %d\n", ctlr->taligned);
261         l += snprintf(p + l, READSTR - l, "tunaligned %d\n", ctlr->tunaligned);
262         ctlr->dis += csr16r(ctlr, Dis);
263         l += snprintf(p + l, READSTR - l, "dis %d\n", ctlr->dis);
264         ctlr->fcsc += csr16r(ctlr, Fcsc);
265         l += snprintf(p + l, READSTR - l, "fcscnt %d\n", ctlr->fcsc);
266         ctlr->rec += csr16r(ctlr, Rec);
267         l += snprintf(p + l, READSTR - l, "rec %d\n", ctlr->rec);
268
269         l += snprintf(p + l, READSTR - l, "Tcr 0x%8.8lx\n", csr32r(ctlr, Tcr));
270         l += snprintf(p + l, READSTR - l, "Config0 0x%2.2x\n",
271                                   csr8r(ctlr, Config0));
272         l += snprintf(p + l, READSTR - l, "Config1 0x%2.2x\n",
273                                   csr8r(ctlr, Config1));
274         l += snprintf(p + l, READSTR - l, "Msr 0x%2.2x\n", csr8r(ctlr, Msr));
275         l += snprintf(p + l, READSTR - l, "Config3 0x%2.2x\n",
276                                   csr8r(ctlr, Config3));
277         l += snprintf(p + l, READSTR - l, "Config4 0x%2.2x\n",
278                                   csr8r(ctlr, Config4));
279
280         l += snprintf(p + l, READSTR - l, "Bmcr 0x%4.4x\n", csr16r(ctlr, Bmcr));
281         l += snprintf(p + l, READSTR - l, "Bmsr 0x%4.4x\n", csr16r(ctlr, Bmsr));
282         l += snprintf(p + l, READSTR - l, "Anar 0x%4.4x\n", csr16r(ctlr, Anar));
283         l += snprintf(p + l, READSTR - l, "Anlpar 0x%4.4x\n", csr16r(ctlr, Anlpar));
284         l += snprintf(p + l, READSTR - l, "Aner 0x%4.4x\n", csr16r(ctlr, Aner));
285         l += snprintf(p + l, READSTR - l, "Nwaytr 0x%4.4x\n", csr16r(ctlr, Nwaytr));
286         snprintf(p + l, READSTR - l, "Cscr 0x%4.4x\n", csr16r(ctlr, Cscr));
287         n = readstr(offset, a, n, p);
288         kfree(p);
289
290         return n;
291 }
292
293 static int rtl8139reset(struct ctlr *ctlr)
294 {
295         int timeo;
296
297         /*
298          * Soft reset the controller.
299          */
300         csr8w(ctlr, Cr, Rst);
301         for (timeo = 0; timeo < 1000; timeo++) {
302                 if (!(csr8r(ctlr, Cr) & Rst))
303                         return 0;
304                 udelay(1000);
305         }
306
307         return -1;
308 }
309
310 static void rtl8139halt(struct ctlr *ctlr)
311 {
312         int i;
313
314         csr8w(ctlr, Cr, 0);
315         csr16w(ctlr, Imr, 0);
316         csr16w(ctlr, Isr, ~0);
317
318         for (i = 0; i < Ntd; i++) {
319                 if (ctlr->td[i].bp == NULL)
320                         continue;
321                 freeb(ctlr->td[i].bp);
322                 ctlr->td[i].bp = NULL;
323         }
324 }
325
326 static void rtl8139init(struct ether *edev)
327 {
328         int i;
329         uint32_t r;
330         struct ctlr *ctlr;
331         uint8_t *alloc;
332
333         ctlr = edev->ctlr;
334         spin_lock_irqsave(&ctlr->ilock);
335
336         rtl8139halt(ctlr);
337
338         /*
339          * MAC Address.
340          */
341         r = (edev->ea[3] << 24) | (edev->ea[2] << 16) | (edev->ea[1] << 8) | edev->
342                 ea[0];
343         csr32w(ctlr, Idr0, r);
344         r = (edev->ea[5] << 8) | edev->ea[4];
345         csr32w(ctlr, Idr0 + 4, r);
346
347         /*
348          * Receiver
349          */
350         // inferno had mmucacheinhib here
351         alloc = (uint8_t*)ROUNDUP((uintptr_t)ctlr->alloc, ARCH_CL_SIZE);
352         ctlr->rbstart = alloc;
353         alloc += ctlr->rblen + 16;
354         memset(ctlr->rbstart, 0, ctlr->rblen + 16);
355         csr32w(ctlr, Rbstart, paddr_low32(ctlr->rbstart));
356         paddr_check(ctlr->rbstart);
357         ctlr->rcr = Rxfth256 | Rblen | Mrxdmaunlimited | Ab | Apm;
358
359         /*
360          * Transmitter.
361          */
362         for (i = 0; i < Ntd; i++) {
363                 ctlr->td[i].tsd = Tsd0 + i * 4;
364                 ctlr->td[i].tsad = Tsad0 + i * 4;
365                 ctlr->td[i].data = alloc;
366                 alloc += Tdbsz;
367                 ctlr->td[i].bp = NULL;
368         }
369         ctlr->ntd = ctlr->tdh = ctlr->tdi = 0;
370         ctlr->etxth = 128 / 32;
371
372         /*
373          * Interrupts.
374          */
375         csr32w(ctlr, TimerInt, 0);
376         csr16w(ctlr, Imr,
377                    Serr | Timerbit | Fovw | PunLc | Rxovw | Ter | Tok | Rer | Rok);
378         csr32w(ctlr, Mpc, 0);
379
380         /*
381          * Enable receiver/transmitter.
382          * Need to enable before writing the Rcr or it won't take.
383          */
384         csr8w(ctlr, Cr, Te | Re);
385         csr32w(ctlr, Tcr, Mtxdma2048);
386         csr32w(ctlr, Rcr, ctlr->rcr);
387
388         spin_unlock_irqsave(&ctlr->ilock);
389 }
390
391 static void rtl8139attach(struct ether *edev)
392 {
393         struct ctlr *ctlr;
394
395         ctlr = edev->ctlr;
396         qlock(&ctlr->alock);
397         if (ctlr->alloc == NULL) {
398                 ctlr->rblen = 1 << ((Rblen >> RblenSHIFT) + 13);
399                 ctlr->alloc = kzmalloc(ctlr->rblen + 16 + Ntd * Tdbsz + ARCH_CL_SIZE,
400                                        KMALLOC_WAIT);
401                 rtl8139init(edev);
402         }
403         qunlock(&ctlr->alock);
404 }
405
406 static void rtl8139txstart(struct ether *edev)
407 {
408         Td *td;
409         int size;
410         struct block *bp;
411         struct ctlr *ctlr;
412
413         ctlr = edev->ctlr;
414         while (ctlr->ntd < Ntd) {
415                 bp = qget(edev->oq);
416                 if (bp == NULL)
417                         break;
418                 size = BLEN(bp);
419
420                 td = &ctlr->td[ctlr->tdh];
421                 if (((uintptr_t)bp->rp) & 0x03) {
422                         memmove(td->data, bp->rp, size);
423                         /* flushing the data cache? */
424                         //dcflush(td->data, size);
425                         freeb(bp);
426                         csr32w(ctlr, td->tsad, paddr_low32(td->data));
427                         paddr_check(td->data);
428                         ctlr->tunaligned++;
429                 } else {
430                         td->bp = bp;
431                         csr32w(ctlr, td->tsad, paddr_low32(bp->rp));
432                         /* flushing the data cache? */
433                         //dcflush(bp->rp, size);
434                         paddr_check(bp->rp);
435                         ctlr->taligned++;
436                 }
437                 csr32w(ctlr, td->tsd, (ctlr->etxth << EtxthSHIFT) | size);
438
439                 ctlr->ntd++;
440                 ctlr->tdh = NEXT_RING(ctlr->tdh, Ntd);
441         }
442 }
443
444 static void rtl8139transmit(struct ether *edev)
445 {
446         struct ctlr *ctlr;
447
448         ctlr = edev->ctlr;
449         spin_lock_irqsave(&ctlr->tlock);
450         rtl8139txstart(edev);
451         spin_unlock_irqsave(&ctlr->tlock);
452 }
453
454 static void rtl8139receive(struct ether *edev)
455 {
456         struct block *bp;
457         struct ctlr *ctlr;
458         uint16_t capr;
459         uint8_t cr, *p;
460         int l, length, status;
461
462         ctlr = edev->ctlr;
463
464         /*
465          * Capr is where the host is reading from,
466          * Cbr is where the NIC is currently writing.
467          */
468         capr = (csr16r(ctlr, Capr) + 16) % ctlr->rblen;
469         while (!(csr8r(ctlr, Cr) & Bufe)) {
470                 p = ctlr->rbstart + capr;
471
472                 /*
473                  * Apparently the packet length may be 0xFFF0 if
474                  * the NIC is still copying the packet into memory.
475                  */
476                 length = (*(p + 3) << 8) | *(p + 2);
477                 if (length == 0xFFF0)
478                         break;
479                 status = (*(p + 1) << 8) | *p;
480                 if (!(status & Rcok)) {
481                         if (status & (Ise | Fae))
482                                 edev->netif.frames++;
483                         if (status & Crc)
484                                 edev->netif.crcs++;
485                         if (status & (Runt | Long))
486                                 edev->netif.buffs++;
487
488                         /*
489                          * Reset the receiver.
490                          * Also may have to restore the multicast list
491                          * here too if it ever gets used.
492                          */
493                         cr = csr8r(ctlr, Cr);
494                         csr8w(ctlr, Cr, cr & ~Re);
495                         csr32w(ctlr, Rbstart, paddr_low32(ctlr->rbstart));
496                         paddr_check(ctlr->rbstart);
497                         csr8w(ctlr, Cr, cr);
498                         csr32w(ctlr, Rcr, ctlr->rcr);
499
500                         continue;
501                 }
502
503                 /*
504                  * Receive Completed OK.
505                  * Very simplistic; there are ways this could be done
506                  * without copying, but the juice probably isn't worth
507                  * the squeeze.
508                  * The packet length includes a 4 byte CRC on the end.
509                  */
510                 capr = (capr + 4) % ctlr->rblen;
511                 p = ctlr->rbstart + capr;
512                 capr = (capr + length) % ctlr->rblen;
513
514                 if ((bp = iallocb(length)) != NULL) {
515                         if (p + length >= ctlr->rbstart + ctlr->rblen) {
516                                 l = ctlr->rbstart + ctlr->rblen - p;
517                                 memmove(bp->wp, p, l);
518                                 bp->wp += l;
519                                 length -= l;
520                                 p = ctlr->rbstart;
521                         }
522                         if (length > 0) {
523                                 memmove(bp->wp, p, length);
524                                 bp->wp += length;
525                         }
526                         bp->wp -= 4;
527                         etheriq(edev, bp, 1);
528                 }
529
530                 capr = ROUNDUP(capr, 4);
531                 csr16w(ctlr, Capr, capr - 16);
532         }
533 }
534
535 static void rtl8139interrupt(struct hw_trapframe *tf, void *arg)
536 {
537         Td *td;
538         struct ctlr *ctlr;
539         struct ether *edev;
540         int isr, msr, tsd;
541
542         edev = arg;
543         ctlr = edev->ctlr;
544
545         while ((isr = csr16r(ctlr, Isr)) != 0) {
546                 csr16w(ctlr, Isr, isr);
547                 if (isr & (Fovw | PunLc | Rxovw | Rer | Rok)) {
548                         rtl8139receive(edev);
549                         if (!(isr & Rok))
550                                 ctlr->ierrs++;
551                         isr &= ~(Fovw | Rxovw | Rer | Rok);
552                 }
553
554                 if (isr & (Ter | Tok)) {
555                         spin_lock_irqsave(&ctlr->tlock);
556                         while (ctlr->ntd) {
557                                 td = &ctlr->td[ctlr->tdi];
558                                 tsd = csr32r(ctlr, td->tsd);
559                                 if (!(tsd & (Tabt | Tun | Tcok)))
560                                         break;
561
562                                 if (!(tsd & Tcok)) {
563                                         if (tsd & Tun) {
564                                                 if (ctlr->etxth < ETHERMAXTU / 32)
565                                                         ctlr->etxth++;
566                                         }
567                                         edev->netif.oerrs++;
568                                 }
569
570                                 if (td->bp != NULL) {
571                                         freeb(td->bp);
572                                         td->bp = NULL;
573                                 }
574
575                                 ctlr->ntd--;
576                                 ctlr->tdi = NEXT_RING(ctlr->tdi, Ntd);
577                         }
578                         rtl8139txstart(edev);
579                         spin_unlock_irqsave(&ctlr->tlock);
580                         isr &= ~(Ter | Tok);
581                 }
582
583                 if (isr & PunLc) {
584                         /*
585                          * Maybe the link changed - do we care very much?
586                          */
587                         msr = csr8r(ctlr, Msr);
588                         if (!(msr & Linkb)) {
589                                 if (!(msr & Speed10) && edev->netif.mbps != 100) {
590                                         edev->netif.mbps = 100;
591                                         qsetlimit(edev->oq, 256 * 1024);
592                                 } else if ((msr & Speed10) && edev->netif.mbps != 10) {
593                                         edev->netif.mbps = 10;
594                                         qsetlimit(edev->oq, 65 * 1024);
595                                 }
596                         }
597                         isr &= ~(Clc | PunLc);
598                 }
599
600                 /*
601                  * Only Serr|Timer should be left by now.
602                  * Should anything be done to tidy up? TimerInt isn't
603                  * used so that can be cleared. A PCI bus error is indicated
604                  * by Serr, that's pretty serious; is there anyhing to do
605                  * other than try to reinitialise the chip?
606                  */
607                 if (isr != 0) {
608                         printk("rtl8139interrupt: imr 0x%4.4x isr 0x%4.4x\n",
609                                    csr16r(ctlr, Imr), isr);
610                         if (isr & Timerbit)
611                                 csr32w(ctlr, TimerInt, 0);
612                         if (isr & Serr)
613                                 rtl8139init(edev);
614                 }
615         }
616 }
617
618 static struct ctlr *rtl8139match(struct ether *edev, int id)
619 {
620         int port;
621         struct pci_device *pcidev;
622         struct ctlr *ctlr;
623
624         /*
625          * Any adapter matches if no edev->port is supplied,
626          * otherwise the ports must match.
627          */
628         for (ctlr = ctlrhead; ctlr != NULL; ctlr = ctlr->next) {
629                 if (ctlr->active)
630                         continue;
631                 pcidev = ctlr->pcidev;
632                 if (((pcidev->dev_id << 16) | pcidev->ven_id) != id)
633                         continue;
634                 port = pcidev->bar[0].pio_base;
635                 if (edev->port != 0 && edev->port != port)
636                         continue;
637
638                 #if 0
639                 /* trying to alloc PIO ports (.size of them?).  for now, we just assume
640                  * they are free */
641                 if (ioalloc(port, pcidev->mem[0].size, 0, "rtl8139") < 0) {
642                         printd("rtl8139: port 0x%x in use\n", port);
643                         continue;
644                 }
645                 #endif
646
647                 ctlr->port = port;
648                 if (rtl8139reset(ctlr))
649                         continue;
650                 pci_set_bus_master(pcidev);
651
652                 ctlr->active = 1;
653                 return ctlr;
654         }
655         return NULL;
656 }
657
658 static struct {
659         char *name;
660         int id;
661 } rtl8139pci[] = {
662         {
663         "rtl8139", (0x8139 << 16) | 0x10EC,},   /* generic */
664         {
665         "smc1211", (0x1211 << 16) | 0x1113,},   /* SMC EZ-Card */
666         {
667         "dfe-538tx", (0x1300 << 16) | 0x1186,}, /* D-Link DFE-538TX */
668         {
669         "dfe-560txd", (0x1340 << 16) | 0x1186,},        /* D-Link DFE-560TXD */
670         {
671 NULL},};
672
673 static int rtl8139pnp(struct ether *edev)
674 {
675         int i, id;
676         struct pci_device *pcidev;
677         struct ctlr *ctlr;
678         uint8_t ea[Eaddrlen];
679
680         /* Make a list of all ethernet controllers if not already done.
681          *
682          * brho: this style is a bit weird - we have ctlr structs for every NIC,
683          * including non-rtl NICs. */
684         if (ctlrhead == NULL) {
685                 STAILQ_FOREACH(pcidev, &pci_devices, all_dev) {
686                         /* this skips over non-ethernet devices. */
687                         if (pcidev->class != 0x02|| pcidev->subclass != 0)
688                                 continue;
689
690                         ctlr = kzmalloc(sizeof(struct ctlr), KMALLOC_WAIT);
691                         qlock_init(&ctlr->alock);
692                         spinlock_init_irqsave(&ctlr->ilock);
693                         spinlock_init_irqsave(&ctlr->tlock);
694                         ctlr->pcidev = pcidev;
695                         ctlr->id = (pcidev->dev_id << 16) | pcidev->ven_id;
696
697                         if (ctlrhead != NULL)
698                                 ctlrtail->next = ctlr;
699                         else
700                                 ctlrhead = ctlr;
701                         ctlrtail = ctlr;
702                 }
703         }
704
705         /*
706          * Is it an RTL8139 under a different name?
707          * Normally a search is made through all the found controllers
708          * for one which matches any of the known vid+did pairs.
709          * If a vid+did pair is specified a search is made for that
710          * specific controller only.
711          */
712         id = 0;
713         #if 0 // No struct ether options yet (goes with archenter, i think)
714         for (i = 0; i < edev->nopt; i++) {
715                 if (cistrncmp(edev->opt[i], "id=", 3) == 0)
716                         id = strtol(&edev->opt[i][3], NULL, 0);
717         }
718         #endif
719
720         ctlr = NULL;
721         if (id != 0)
722                 ctlr = rtl8139match(edev, id);
723         else
724                 for (i = 0; rtl8139pci[i].name; i++) {
725                         if ((ctlr = rtl8139match(edev, rtl8139pci[i].id)) != NULL)
726                                 break;
727                 }
728         if (ctlr == NULL)
729                 return -1;
730
731         printd("RTL8139 driver found %s at %02x:%02x.%x\n", rtl8139pci[i].name,
732                ctlr->pcidev->bus, ctlr->pcidev->dev, ctlr->pcidev->func);
733         edev->ctlr = ctlr;
734         edev->port = ctlr->port;
735         edev->irq = ctlr->pcidev->irqline;
736
737         /*
738          * Check if the adapter's station address is to be overridden.
739          * If not, read it from the device and set in edev->ea.
740          */
741         memset(ea, 0, Eaddrlen);
742         if (memcmp(ea, edev->ea, Eaddrlen) == 0) {
743                 i = csr32r(ctlr, Idr0);
744                 edev->ea[0] = i;
745                 edev->ea[1] = i >> 8;
746                 edev->ea[2] = i >> 16;
747                 edev->ea[3] = i >> 24;
748                 i = csr32r(ctlr, Idr0 + 4);
749                 edev->ea[4] = i;
750                 edev->ea[5] = i >> 8;
751         }
752         edev->attach = rtl8139attach;
753         edev->transmit = rtl8139transmit;
754         edev->interrupt = rtl8139interrupt;
755         edev->ifstat = rtl8139ifstat;
756
757         edev->netif.arg = edev;
758         edev->netif.promiscuous = rtl8139promiscuous;
759
760         /*
761          * This should be much more dynamic but will do for now.
762          */
763         if ((csr8r(ctlr, Msr) & (Speed10 | Linkb)) == 0)
764                 edev->netif.mbps = 100;
765
766         return 0;
767 }
768
769 void __etherlink ether8139link(void)
770 {
771         addethercard("rtl8139", rtl8139pnp);
772 }