5ba01a1e6b7829ee8f591e80e2925dfa55fa766e
[akaros.git] / kern / drivers / net / ether8139.c
1 // INFERNO
2 /*
3  * Realtek 8139 (but not the 8129).
4  * Error recovery for the various over/under -flow conditions
5  * may need work.
6  */
7 #include <vfs.h>
8 #include <kfs.h>
9 #include <slab.h>
10 #include <kmalloc.h>
11 #include <kref.h>
12 #include <string.h>
13 #include <stdio.h>
14 #include <assert.h>
15 #include <error.h>
16 #include <cpio.h>
17 #include <pmap.h>
18 #include <smp.h>
19 #include <ip.h>
20
21 #include <vfs.h>
22 #include <kfs.h>
23 #include <slab.h>
24 #include <kmalloc.h>
25 #include <kref.h>
26 #include <string.h>
27 #include <stdio.h>
28 #include <assert.h>
29 #include <error.h>
30 #include <cpio.h>
31 #include <pmap.h>
32 #include <smp.h>
33 #include <ip.h>
34
35 enum {                                  /* registers */
36         Idr0            = 0x0000,       /* MAC address */
37         Mar0            = 0x0008,       /* Multicast address */
38         Tsd0            = 0x0010,       /* Transmit Status Descriptor0 */
39         Tsad0           = 0x0020,       /* Transmit Start Address Descriptor0 */
40         Rbstart         = 0x0030,       /* Receive Buffer Start Address */
41         Erbcr           = 0x0034,       /* Early Receive Byte Count */
42         Ersr            = 0x0036,       /* Early Receive Status */
43         Cr              = 0x0037,       /* Command Register */
44         Capr            = 0x0038,       /* Current Address of Packet Read */
45         Cbr             = 0x003A,       /* Current Buffer Address */
46         Imr             = 0x003C,       /* Interrupt Mask */
47         Isr             = 0x003E,       /* Interrupt Status */
48         Tcr             = 0x0040,       /* Transmit Configuration */
49         Rcr             = 0x0044,       /* Receive Configuration */
50         Tctr            = 0x0048,       /* Timer Count */
51         Mpc             = 0x004C,       /* Missed Packet Counter */
52         Cr9346          = 0x0050,       /* 9346 Command Register */
53         Config0         = 0x0051,       /* Configuration Register 0 */
54         Config1         = 0x0052,       /* Configuration Register 1 */
55         TimerInt        = 0x0054,       /* Timer Interrupt */
56         Msr             = 0x0058,       /* Media Status */
57         Config3         = 0x0059,       /* Configuration Register 3 */
58         Config4         = 0x005A,       /* Configuration Register 4 */
59         Mulint          = 0x005C,       /* Multiple Interrupt Select */
60         RerID           = 0x005E,       /* PCI Revision ID */
61         Tsad            = 0x0060,       /* Transmit Status of all Descriptors */
62
63         Bmcr            = 0x0062,       /* Basic Mode Control */
64         Bmsr            = 0x0064,       /* Basic Mode Status */
65         Anar            = 0x0066,       /* Auto-Negotiation Advertisment */
66         Anlpar          = 0x0068,       /* Auto-Negotiation Link Partner */
67         Aner            = 0x006A,       /* Auto-Negotiation Expansion */
68         Dis             = 0x006C,       /* Disconnect Counter */
69         Fcsc            = 0x006E,       /* False Carrier Sense Counter */
70         Nwaytr          = 0x0070,       /* N-way Test */
71         Rec             = 0x0072,       /* RX_ER Counter */
72         Cscr            = 0x0074,       /* CS Configuration */
73         Phy1parm        = 0x0078,       /* PHY Parameter 1 */
74         Twparm          = 0x007C,       /* Twister Parameter */
75         Phy2parm        = 0x0080,       /* PHY Parameter 2 */
76 };
77
78 enum {                                  /* Cr */
79         Bufe            = 0x01,         /* Rx Buffer Empty */
80         Te              = 0x04,         /* Transmitter Enable */
81         Re              = 0x08,         /* Receiver Enable */
82         Rst             = 0x10,         /* Software Reset */
83 };
84
85 enum {                                  /* Imr/Isr */
86         Rok             = 0x0001,       /* Receive OK */
87         Rer             = 0x0002,       /* Receive Error */
88         Tok             = 0x0004,       /* Transmit OK */
89         Ter             = 0x0008,       /* Transmit Error */
90         Rxovw           = 0x0010,       /* Receive Buffer Overflow */
91         PunLc           = 0x0020,       /* Packet Underrun or Link Change */
92         Fovw            = 0x0040,       /* Receive FIFO Overflow */
93         Clc             = 0x2000,       /* Cable Length Change */
94         Timerbit        = 0x4000,       /* Timer */
95         Serr            = 0x8000,       /* System Error */
96 };
97
98 enum {                                  /* Tcr */
99         Clrabt          = 0x00000001,   /* Clear Abort */
100         TxrrSHIFT       = 4,            /* Transmit Retry Count */
101         TxrrMASK        = 0x000000F0,
102         MtxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
103         MtxdmaMASK      = 0x00000700,
104         Mtxdma2048      = 0x00000700,
105         Acrc            = 0x00010000,   /* Append CRC (not) */
106         LbkSHIFT        = 17,           /* Loopback Test */
107         LbkMASK         = 0x00060000,
108         Rtl8139ArevG    = 0x00800000,   /* RTL8139A Rev. G ID */
109         IfgSHIFT        = 24,           /* Interframe Gap */
110         IfgMASK         = 0x03000000,
111         HwveridSHIFT    = 26,           /* Hardware Version ID */
112         HwveridMASK     = 0x7C000000,
113 };
114
115 enum {                                  /* Rcr */
116         Aap             = 0x00000001,   /* Accept All Packets */
117         Apm             = 0x00000002,   /* Accept Physical Match */
118         Am              = 0x00000004,   /* Accept Multicast */
119         Ab              = 0x00000008,   /* Accept Broadcast */
120         Ar              = 0x00000010,   /* Accept Runt */
121         Aer             = 0x00000020,   /* Accept Error */
122         Sel9356         = 0x00000040,   /* 9356 EEPROM used */
123         Wrap            = 0x00000080,   /* Rx Buffer Wrap Control */
124         MrxdmaSHIFT     = 8,            /* Max. DMA Burst Size */
125         MrxdmaMASK      = 0x00000700,
126         Mrxdmaunlimited = 0x00000700,
127         RblenSHIFT      = 11,           /* Receive Buffer Length */
128         RblenMASK       = 0x00001800,
129         Rblen8K         = 0x00000000,   /* 8KB+16 */
130         Rblen16K        = 0x00000800,   /* 16KB+16 */
131         Rblen32K        = 0x00001000,   /* 32KB+16 */
132         Rblen64K        = 0x00001800,   /* 64KB+16 */
133         RxfthSHIFT      = 13,           /* Receive Buffer Length */
134         RxfthMASK       = 0x0000E000,
135         Rxfth256        = 0x00008000,
136         Rxfthnone       = 0x0000E000,
137         Rer8            = 0x00010000,   /* Accept Error Packets > 8 bytes */
138         MulERINT        = 0x00020000,   /* Multiple Early Interrupt Select */
139         ErxthSHIFT      = 24,           /* Early Rx Threshold */
140         ErxthMASK       = 0x0F000000,
141         Erxthnone       = 0x00000000,
142 };
143
144 enum {                                  /* Received Packet Status */
145         Rcok            = 0x0001,       /* Receive Completed OK */
146         Fae             = 0x0002,       /* Frame Alignment Error */
147         Crc             = 0x0004,       /* CRC Error */
148         Long            = 0x0008,       /* Long Packet */
149         Runt            = 0x0010,       /* Runt Packet Received */
150         Ise             = 0x0020,       /* Invalid Symbol Error */
151         Bar             = 0x2000,       /* Broadcast Address Received */
152         Pam             = 0x4000,       /* Physical Address Matched */
153         Mar             = 0x8000,       /* Multicast Address Received */
154 };
155
156 enum {                                  /* Media Status Register */
157         Rxpf            = 0x01,         /* Pause Flag */
158         Txpf            = 0x02,         /* Pause Flag */
159         Linkb           = 0x04,         /* Inverse of Link Status */
160         Speed10         = 0x08,         /* 10Mbps */
161         Auxstatus       = 0x10,         /* Aux. Power Present Status */
162         Rxfce           = 0x40,         /* Receive Flow Control Enable */
163         Txfce           = 0x80,         /* Transmit Flow Control Enable */
164 };
165
166 typedef struct Td Td;
167 struct Td {                     /* Soft Transmit Descriptor */
168         int     tsd;
169         int     tsad;
170         uint8_t*        data;
171         struct block*   bp;
172 };
173
174 enum {                                  /* Tsd0 */
175         SizeSHIFT       = 0,            /* Descriptor Size */
176         SizeMASK        = 0x00001FFF,
177         Own             = 0x00002000,
178         Tun             = 0x00004000,   /* Transmit FIFO Underrun */
179         Tcok            = 0x00008000,   /* Transmit COmpleted OK */
180         EtxthSHIFT      = 16,           /* Early Tx Threshold */
181         EtxthMASK       = 0x001F0000,
182         NccSHIFT        = 24,           /* Number of Collisions Count */
183         NccMASK         = 0x0F000000,
184         Cdh             = 0x10000000,   /* CD Heartbeat */
185         Owc             = 0x20000000,   /* Out of Window Collision */
186         Tabt            = 0x40000000,   /* Transmit Abort */
187         Crs             = 0x80000000,   /* Carrier Sense Lost */
188 };
189
190 enum {
191         Rblen           = Rblen64K,     /* Receive Buffer Length */
192         Ntd             = 4,            /* Number of Transmit Descriptors */
193         Tdbsz           = ROUNDUP(sizeof(Etherpkt), 4),
194 };
195
196 typedef struct Ctlr Ctlr;
197 typedef struct Ctlr {
198         int     port;
199         Pcidev* pcidev;
200         struct ctlr*    next;
201         int     active;
202         int     id;
203
204         qlock_t alock;                  /* attach */
205         spinlock_t      ilock;                  /* init */
206         void*   alloc;                  /* base of per-Ctlr allocated data */
207
208         int     rcr;                    /* receive configuration register */
209         uint8_t*        rbstart;                /* receive buffer */
210         int     rblen;                  /* receive buffer length */
211         int     ierrs;                  /* receive errors */
212
213         spinlock_t      tlock;                  /* transmit */
214         Td      td[Ntd];
215         int     ntd;                    /* descriptors active */
216         int     tdh;                    /* host index into td */
217         int     tdi;                    /* interface index into td */
218         int     etxth;                  /* early transmit threshold */
219         int     taligned;               /* packet required no alignment */
220         int     tunaligned;             /* packet required alignment */
221
222         int     dis;                    /* disconnect counter */
223         int     fcsc;                   /* false carrier sense counter */
224         int     rec;                    /* RX_ER counter */
225 } Ctlr;
226
227 static struct ctlr* ctlrhead;
228 static struct ctlr* ctlrtail;
229
230 #define csr8r(c, r)     (inb((c)->port+(r)))
231 #define csr16r(c, r)    (ins((c)->port+(r)))
232 #define csr32r(c, r)    (inl((c)->port+(r)))
233 #define csr8w(c, r, b)  (outb((c)->port+(r), (int)(b)))
234 #define csr16w(c, r, w) (outs((c)->port+(r), (uint16_t)(w)))
235 #define csr32w(c, r, l) (outl((c)->port+(r), (uint32_t)(l)))
236
237 static void
238 rtl8139promiscuous(void* arg, int on)
239 {
240         struct ether *edev;
241         struct ctlr * ctlr;
242
243         edev = arg;
244         ctlr = edev->ctlr;
245         spin_lock_irqsave(&(&ctlr->ilock)->lock);
246
247         if(on)
248                 ctlr->rcr |= Aap;
249         else
250                 ctlr->rcr &= ~Aap;
251         csr32w(ctlr, Rcr, ctlr->rcr);
252         spin_unlock_irqsave(&(&ctlr->ilock)->lock);
253 }
254
255 static long
256 rtl8139ifstat(struct ether* edev, void* a, long n, uint32_t offset)
257 {
258         int l;
259         char *p;
260         struct ctlr *ctlr;
261
262         ctlr = edev->ctlr;
263         p = kzmalloc(READSTR, 0);
264         l = snprintf(p, READSTR, "rcr 0x%8.8x\n", ctlr->rcr);
265         l += snprintf(p+l, READSTR-l, "ierrs %d\n", ctlr->ierrs);
266         l += snprintf(p+l, READSTR-l, "etxth %d\n", ctlr->etxth);
267         l += snprintf(p+l, READSTR-l, "taligned %d\n", ctlr->taligned);
268         l += snprintf(p+l, READSTR-l, "tunaligned %d\n", ctlr->tunaligned);
269         ctlr->dis += csr16r(ctlr, Dis);
270         l += snprintf(p+l, READSTR-l, "dis %d\n", ctlr->dis);
271         ctlr->fcsc += csr16r(ctlr, Fcsc);
272         l += snprintf(p+l, READSTR-l, "fcscnt %d\n", ctlr->fcsc);
273         ctlr->rec += csr16r(ctlr, Rec);
274         l += snprintf(p+l, READSTR-l, "rec %d\n", ctlr->rec);
275
276         l += snprintf(p+l, READSTR-l, "Tcr 0x%8.8lx\n", csr32r(ctlr, Tcr));
277         l += snprintf(p+l, READSTR-l, "Config0 0x%2.2x\n", csr8r(ctlr, Config0));
278         l += snprintf(p+l, READSTR-l, "Config1 0x%2.2x\n", csr8r(ctlr, Config1));
279         l += snprintf(p+l, READSTR-l, "Msr 0x%2.2x\n", csr8r(ctlr, Msr));
280         l += snprintf(p+l, READSTR-l, "Config3 0x%2.2x\n", csr8r(ctlr, Config3));
281         l += snprintf(p+l, READSTR-l, "Config4 0x%2.2x\n", csr8r(ctlr, Config4));
282
283         l += snprintf(p+l, READSTR-l, "Bmcr 0x%4.4x\n", csr16r(ctlr, Bmcr));
284         l += snprintf(p+l, READSTR-l, "Bmsr 0x%4.4x\n", csr16r(ctlr, Bmsr));
285         l += snprintf(p+l, READSTR-l, "Anar 0x%4.4x\n", csr16r(ctlr, Anar));
286         l += snprintf(p+l, READSTR-l, "Anlpar 0x%4.4x\n", csr16r(ctlr, Anlpar));
287         l += snprintf(p+l, READSTR-l, "Aner 0x%4.4x\n", csr16r(ctlr, Aner));
288         l += snprintf(p+l, READSTR-l, "Nwaytr 0x%4.4x\n", csr16r(ctlr, Nwaytr));
289         snprintf(p+l, READSTR-l, "Cscr 0x%4.4x\n", csr16r(ctlr, Cscr));
290         n = readstr(offset, a, n, p);
291         kfree(p);
292
293         return n;
294 }
295
296 static int
297 rtl8139reset(struct ctlr* ctlr)
298 {
299         int timeo;
300
301         /*
302          * Soft reset the controller.
303          */
304         csr8w(ctlr, Cr, Rst);
305         for(timeo = 0; timeo < 1000; timeo++){
306                 if(!(csr8r(ctlr, Cr) & Rst))
307                         return 0;
308                 delay(1);
309         }
310
311         return -1;
312 }
313
314 static void
315 rtl8139halt(struct ctlr* ctlr)
316 {
317         int i;
318
319         csr8w(ctlr, Cr, 0);
320         csr16w(ctlr, Imr, 0);
321         csr16w(ctlr, Isr, ~0);
322
323         for(i = 0; i < Ntd; i++){
324                 if(ctlr->td[i].bp == NULL)
325                         continue;
326                 freeb(ctlr->td[i].bp);
327                 ctlr->td[i].bp = NULL;
328         }
329 }
330
331 static void
332 rtl8139init(struct ether* edev)
333 {
334         int i;
335         uint32_t r;
336         struct ctlr *ctlr;
337         uint8_t *alloc;
338
339         ctlr = edev->ctlr;
340         spin_lock_irqsave(&(&ctlr->ilock)->lock);
341
342         rtl8139halt(ctlr);
343
344         /*
345          * MAC Address.
346          */
347         r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
348         csr32w(ctlr, Idr0, r);
349         r = (edev->ea[5]<<8)|edev->ea[4];
350         csr32w(ctlr, Idr0+4, r);
351
352         /*
353          * Receiver
354          */
355         alloc = mmucacheinhib(( char *unused_char_p_t)ROUNDUP((uint32_t)ctlr->alloc, CACHELINESZ), ctlr->rblen+16 + Ntd*Tdbsz);
356         ctlr->rbstart = alloc;
357         alloc += ctlr->rblen+16;
358         memset(ctlr->rbstart, 0, ctlr->rblen+16);
359         csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
360         ctlr->rcr = Rxfth256|Rblen|Mrxdmaunlimited|Ab|Apm;
361
362         /*
363          * Transmitter.
364          */
365         for(i = 0; i < Ntd; i++){
366                 ctlr->td[i].tsd = Tsd0+i*4;
367                 ctlr->td[i].tsad = Tsad0+i*4;
368                 ctlr->td[i].data = alloc;
369                 alloc += Tdbsz;
370                 ctlr->td[i].bp = NULL;
371         }
372         ctlr->ntd = ctlr->tdh = ctlr->tdi = 0;
373         ctlr->etxth = 128/32;
374
375         /*
376          * Interrupts.
377          */
378         csr32w(ctlr, TimerInt, 0);
379         csr16w(ctlr, Imr, Serr|Timerbit|Fovw|PunLc|Rxovw|Ter|Tok|Rer|Rok);
380         csr32w(ctlr, Mpc, 0);
381
382         /*
383          * Enable receiver/transmitter.
384          * Need to enable before writing the Rcr or it won't take.
385          */
386         csr8w(ctlr, Cr, Te|Re);
387         csr32w(ctlr, Tcr, Mtxdma2048);
388         csr32w(ctlr, Rcr, ctlr->rcr);
389
390         spin_unlock_irqsave(&(&ctlr->ilock)->lock);
391 }
392
393 static void
394 rtl8139attach(struct ether* edev)
395 {
396         struct ctlr *ctlr;
397
398         ctlr = edev->ctlr;
399         qlock(&(&ctlr->alock)->qlock);
400         if(ctlr->alloc == NULL){
401                 ctlr->rblen = 1<<((Rblen>>RblenSHIFT)+13);
402                 ctlr->alloc = mallocz(ctlr->rblen+16 + Ntd*Tdbsz + CACHELINESZ, 0);
403                 rtl8139init(edev);
404         }
405         qunlock(&(&ctlr->alock)->qlock);
406 }
407
408 static void
409 rtl8139txstart(struct ether* edev)
410 {
411         Td *td;
412         int size;
413         struct block *bp;
414         struct ctlr *ctlr;
415
416         ctlr = edev->ctlr;
417         while(ctlr->ntd < Ntd){
418                 bp = qget(edev->oq);
419                 if(bp == NULL)
420                         break;
421                 size = BLEN(bp);
422
423                 td = &ctlr->td[ctlr->tdh];
424                 if(((int)bp->rp) & 0x03){
425                         memmove(td->data, bp->rp, size);
426                         dcflush(td->data, size);
427                         freeb(bp);
428                         csr32w(ctlr, td->tsad, PCIWADDR(td->data));
429                         ctlr->tunaligned++;
430                 }
431                 else{
432                         td->bp = bp;
433                         csr32w(ctlr, td->tsad, PCIWADDR(bp->rp));
434                         dcflush(bp->rp, size);
435                         ctlr->taligned++;
436                 }
437                 csr32w(ctlr, td->tsd, (ctlr->etxth<<EtxthSHIFT)|size);
438
439                 ctlr->ntd++;
440                 ctlr->tdh = NEXT(ctlr->tdh, Ntd);
441         }
442 }
443
444 static void
445 rtl8139transmit(struct ether* edev)
446 {
447         struct ctlr *ctlr;
448
449         ctlr = edev->ctlr;
450         spin_lock_irqsave(&(&ctlr->tlock)->lock);
451         rtl8139txstart(edev);
452         spin_unlock_irqsave(&(&ctlr->tlock)->lock);
453 }
454
455 static void
456 rtl8139receive(struct ether* edev)
457 {
458         struct block *bp;
459         struct ctlr *ctlr;
460         uint16_t capr;
461         uint8_t cr, *p;
462         int l, length, status;
463
464         ctlr = edev->ctlr;
465
466         /*
467          * Capr is where the host is reading from,
468          * Cbr is where the NIC is currently writing.
469          */
470         capr = (csr16r(ctlr, Capr)+16) % ctlr->rblen;
471         while(!(csr8r(ctlr, Cr) & Bufe)){
472                 p = ctlr->rbstart+capr;
473
474                 /*
475                  * Apparently the packet length may be 0xFFF0 if
476                  * the NIC is still copying the packet into memory.
477                  */
478                 length = (*(p+3)<<8)|*(p+2);
479                 if(length == 0xFFF0)
480                         break;
481                 status = (*(p+1)<<8)|*p;
482                 if(!(status & Rcok)){
483                         if(status & (Ise|Fae))
484                                 edev->frames++;
485                         if(status & Crc)
486                                 edev->crcs++;
487                         if(status & (Runt|Long))
488                                 edev->buffs++;
489
490                         /*
491                          * Reset the receiver.
492                          * Also may have to restore the multicast list
493                          * here too if it ever gets used.
494                          */
495                         cr = csr8r(ctlr, Cr);
496                         csr8w(ctlr, Cr, cr & ~Re);
497                         csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
498                         csr8w(ctlr, Cr, cr);
499                         csr32w(ctlr, Rcr, ctlr->rcr);
500
501                         continue;
502                 }
503
504                 /*
505                  * Receive Completed OK.
506                  * Very simplistic; there are ways this could be done
507                  * without copying, but the juice probably isn't worth
508                  * the squeeze.
509                  * The packet length includes a 4 byte CRC on the end.
510                  */
511                 capr = (capr+4) % ctlr->rblen;
512                 p = ctlr->rbstart+capr;
513                 capr = (capr+length) % ctlr->rblen;
514
515                 if((bp = iallocb(length)) != NULL){
516                         if(p+length >= ctlr->rbstart+ctlr->rblen){
517                                 l = ctlr->rbstart+ctlr->rblen - p;
518                                 memmove(bp->wp, p, l);
519                                 bp->wp += l;
520                                 length -= l;
521                                 p = ctlr->rbstart;
522                         }
523                         if(length > 0){
524                                 memmove(bp->wp, p, length);
525                                 bp->wp += length;
526                         }
527                         bp->wp -= 4;
528                         etheriq(edev, bp, 1);
529                 }
530
531                 capr = ROUNDUP(capr, 4);
532                 csr16w(ctlr, Capr, capr-16);
533         }
534 }
535
536 static void
537 rtl8139interrupt(Ureg*, void* arg)
538 {
539         Td *td;
540         struct ctlr *ctlr;
541         struct ether *edev;
542         int isr, msr, tsd;
543
544         edev = arg;
545         ctlr = edev->ctlr;
546
547         while((isr = csr16r(ctlr, Isr)) != 0){
548                 csr16w(ctlr, Isr, isr);
549                 if(isr & (Fovw|PunLc|Rxovw|Rer|Rok)){
550                         rtl8139receive(edev);
551                         if(!(isr & Rok))
552                                 ctlr->ierrs++;
553                         isr &= ~(Fovw|Rxovw|Rer|Rok);
554                 }
555
556                 if(isr & (Ter|Tok)){
557                         spin_lock_irqsave(&(&ctlr->tlock)->lock);
558                         while(ctlr->ntd){
559                                 td = &ctlr->td[ctlr->tdi];
560                                 tsd = csr32r(ctlr, td->tsd);
561                                 if(!(tsd & (Tabt|Tun|Tcok)))
562                                         break;
563
564                                 if(!(tsd & Tcok)){
565                                         if(tsd & Tun){
566                                                 if(ctlr->etxth < ETHERMAXTU/32)
567                                                         ctlr->etxth++;
568                                         }
569                                         edev->oerrs++;
570                                 }
571
572                                 if(td->bp != NULL){
573                                         freeb(td->bp);
574                                         td->bp = NULL;
575                                 }
576
577                                 ctlr->ntd--;
578                                 ctlr->tdi = NEXT(ctlr->tdi, Ntd);
579                         }
580                         rtl8139txstart(edev);
581                         spin_unlock_irqsave(&(&ctlr->tlock)->lock);
582                         isr &= ~(Ter|Tok);
583                 }
584
585                 if(isr & PunLc){
586                         /*
587                          * Maybe the link changed - do we care very much?
588                          */
589                         msr = csr8r(ctlr, Msr);
590                         if(!(msr & Linkb)){
591                                 if(!(msr & Speed10) && edev->mbps != 100){
592                                         edev->mbps = 100;
593                                         qsetlimit(edev->oq, 256*1024);
594                                 }
595                                 else if((msr & Speed10) && edev->mbps != 10){
596                                         edev->mbps = 10;
597                                         qsetlimit(edev->oq, 65*1024);
598                                 }
599                         }
600                         isr &= ~(Clc|PunLc);
601                 }
602
603                 /*
604                  * Only Serr|Timer should be left by now.
605                  * Should anything be done to tidy up? TimerInt isn't
606                  * used so that can be cleared. A PCI bus error is indicated
607                  * by Serr, that's pretty serious; is there anyhing to do
608                  * other than try to reinitialise the chip?
609                  */
610                 if(isr != 0){
611                         iprint("rtl8139interrupt: imr 0x%4.4x isr 0x%4.4x\n",
612                                 csr16r(ctlr, Imr), isr);
613                         if(isr & Timerbit)
614                                 csr32w(ctlr, TimerInt, 0);
615                         if(isr & Serr)
616                                 rtl8139init(edev);
617                 }
618         }
619 }
620
621 static struct ctlr*
622 rtl8139match(struct ether* edev, int id)
623 {
624         int port;
625         Pcidev *p;
626         struct ctlr *ctlr;
627
628         /*
629          * Any adapter matches if no edev->port is supplied,
630          * otherwise the ports must match.
631          */
632         for(ctlr = ctlrhead; ctlr != NULL; ctlr = ctlr->next){
633                 if(ctlr->active)
634                         continue;
635                 p = ctlr->pcidev;
636                 if(((p->did<<16)|p->vid) != id)
637                         continue;
638                 port = p->mem[0].bar & ~0x01;
639                 if(edev->port != 0 && edev->port != port)
640                         continue;
641
642                 if(ioalloc(port, p->mem[0].size, 0, "rtl8139") < 0){
643                         printd("rtl8139: port 0x%x in use\n", port);
644                         continue;
645                 }
646
647                 ctlr->port = port;
648                 if(rtl8139reset(ctlr))
649                         continue;
650                 pcisetbme(p);
651
652                 ctlr->active = 1;
653                 return ctlr;
654         }
655         return NULL;
656 }
657
658 static struct {
659         char*   name;
660         int     id;
661 } rtl8139pci[] = {
662         { "rtl8139",    (0x8139<<16)|0x10EC, }, /* generic */
663         { "smc1211",    (0x1211<<16)|0x1113, }, /* SMC EZ-Card */
664         { "dfe-538tx",  (0x1300<<16)|0x1186, }, /* D-Link DFE-538TX */
665         { "dfe-560txd", (0x1340<<16)|0x1186, }, /* D-Link DFE-560TXD */
666         { NULL },
667 };
668
669 static int
670 rtl8139pnp(struct ether* edev)
671 {
672         int i, id;
673         Pcidev *p;
674         struct ctlr *ctlr;
675         uint8_t ea[Eaddrlen];
676
677         /*
678          * Make a list of all ethernet controllers
679          * if not already done.
680          */
681         if(ctlrhead == NULL){
682                 p = NULL;
683                 while(p = pcimatch(p, 0, 0)){
684                         if(p->ccrb != 0x02 || p->ccru != 0)
685                                 continue;
686                         ctlr = kzmalloc(sizeof(struct ctlr), 0);
687                         ctlr->pcidev = p;
688                         ctlr->id = (p->did<<16)|p->vid;
689
690                         if(ctlrhead != NULL)
691                                 ctlrtail->next = ctlr;
692                         else
693                                 ctlrhead = ctlr;
694                         ctlrtail = ctlr;
695                 }
696         }
697
698         /*
699          * Is it an RTL8139 under a different name?
700          * Normally a search is made through all the found controllers
701          * for one which matches any of the known vid+did pairs.
702          * If a vid+did pair is specified a search is made for that
703          * specific controller only.
704          */
705         id = 0;
706         for(i = 0; i < edev->nopt; i++){
707                 if(cistrncmp(edev->opt[i], "id=", 3) == 0)
708                         id = strtol(&edev->opt[i][3], NULL, 0);
709         }
710
711         ctlr = NULL;
712         if(id != 0)
713                 ctlr = rtl8139match(edev, id);
714         else for(i = 0; rtl8139pci[i].name; i++){
715                 if((ctlr = rtl8139match(edev, rtl8139pci[i].id)) != NULL)
716                         break;
717         }
718         if(ctlr == NULL)
719                 return -1;
720
721         edev->ctlr = ctlr;
722         edev->port = ctlr->port;
723         edev->irq = ctlr->pcidev->intl;
724         edev->tbdf = ctlr->pcidev->tbdf;
725
726         /*
727          * Check if the adapter's station address is to be overridden.
728          * If not, read it from the device and set in edev->ea.
729          */
730         memset(ea, 0, Eaddrlen);
731         if(memcmp(ea, edev->ea, Eaddrlen) == 0){
732                 i = csr32r(ctlr, Idr0);
733                 edev->ea[0] = i;
734                 edev->ea[1] = i>>8;
735                 edev->ea[2] = i>>16;
736                 edev->ea[3] = i>>24;
737                 i = csr32r(ctlr, Idr0+4);
738                 edev->ea[4] = i;
739                 edev->ea[5] = i>>8;
740         }
741         edev->attach = rtl8139attach;
742         edev->transmit = rtl8139transmit;
743         edev->interrupt = rtl8139interrupt;
744         edev->ifstat = rtl8139ifstat;
745
746         edev->arg = edev;
747         edev->promiscuous = rtl8139promiscuous;
748
749         /*
750          * This should be much more dynamic but will do for now.
751          */
752         if((csr8r(ctlr, Msr) & (Speed10|Linkb)) == 0)
753                 edev->mbps = 100;
754
755         return 0;
756 }
757
758 void __etherlink
759 ether8139link(void)
760 {
761         addethercard("rtl8139", rtl8139pnp);
762 }