Add the Inferno license to files we got from Inferno
[akaros.git] / kern / drivers / net / ether8139.c
1 /* Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
2  * Portions Copyright © 1997-1999 Vita Nuova Limited
3  * Portions Copyright © 2000-2007 Vita Nuova Holdings Limited
4  *                                (www.vitanuova.com)
5  * Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
6  *
7  * Modified for the Akaros operating system:
8  * Copyright (c) 2013-2014 The Regents of the University of California
9  * Copyright (c) 2013-2015 Google Inc.
10  *
11  * Permission is hereby granted, free of charge, to any person obtaining a copy
12  * of this software and associated documentation files (the "Software"), to deal
13  * in the Software without restriction, including without limitation the rights
14  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
15  * copies of the Software, and to permit persons to whom the Software is
16  * furnished to do so, subject to the following conditions:
17  *
18  * The above copyright notice and this permission notice shall be included in
19  * all copies or substantial portions of the Software.
20  *
21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
24  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
26  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27  * SOFTWARE. */
28
29 /*
30  * Realtek 8139 (but not the 8129).
31  * Error recovery for the various over/under -flow conditions
32  * may need work.
33  */
34 #include <vfs.h>
35 #include <kfs.h>
36 #include <slab.h>
37 #include <kmalloc.h>
38 #include <kref.h>
39 #include <string.h>
40 #include <stdio.h>
41 #include <assert.h>
42 #include <error.h>
43 #include <cpio.h>
44 #include <pmap.h>
45 #include <smp.h>
46 #include <ip.h>
47 #include <arch/io.h>
48
49 enum {                                                  /* registers */
50         Idr0 = 0x0000,                          /* MAC address */
51         Mar0 = 0x0008,  /* Multicast address */
52         Tsd0 = 0x0010,  /* Transmit Status Descriptor0 */
53         Tsad0 = 0x0020, /* Transmit Start Address Descriptor0 */
54         Rbstart = 0x0030,       /* Receive Buffer Start Address */
55         Erbcr = 0x0034, /* Early Receive Byte Count */
56         Ersr = 0x0036,  /* Early Receive Status */
57         Cr = 0x0037,    /* Command Register */
58         Capr = 0x0038,  /* Current Address of Packet Read */
59         Cbr = 0x003A,   /* Current Buffer Address */
60         Imr = 0x003C,   /* Interrupt Mask */
61         Isr = 0x003E,   /* Interrupt Status */
62         Tcr = 0x0040,   /* Transmit Configuration */
63         Rcr = 0x0044,   /* Receive Configuration */
64         Tctr = 0x0048,  /* Timer Count */
65         Mpc = 0x004C,   /* Missed Packet Counter */
66         Cr9346 = 0x0050,        /* 9346 Command Register */
67         Config0 = 0x0051,       /* Configuration Register 0 */
68         Config1 = 0x0052,       /* Configuration Register 1 */
69         TimerInt = 0x0054,      /* Timer Interrupt */
70         Msr = 0x0058,   /* Media Status */
71         Config3 = 0x0059,       /* Configuration Register 3 */
72         Config4 = 0x005A,       /* Configuration Register 4 */
73         Mulint = 0x005C,        /* Multiple Interrupt Select */
74         RerID = 0x005E, /* PCI Revision ID */
75         Tsad = 0x0060,  /* Transmit Status of all Descriptors */
76
77         Bmcr = 0x0062,  /* Basic Mode Control */
78         Bmsr = 0x0064,  /* Basic Mode Status */
79         Anar = 0x0066,  /* Auto-Negotiation Advertisment */
80         Anlpar = 0x0068,        /* Auto-Negotiation Link Partner */
81         Aner = 0x006A,  /* Auto-Negotiation Expansion */
82         Dis = 0x006C,   /* Disconnect Counter */
83         Fcsc = 0x006E,  /* False Carrier Sense Counter */
84         Nwaytr = 0x0070,        /* N-way Test */
85         Rec = 0x0072,   /* RX_ER Counter */
86         Cscr = 0x0074,  /* CS Configuration */
87         Phy1parm = 0x0078,      /* PHY Parameter 1 */
88         Twparm = 0x007C,        /* Twister Parameter */
89         Phy2parm = 0x0080,      /* PHY Parameter 2 */
90 };
91
92 enum {                                                  /* Cr */
93         Bufe = 0x01,                            /* Rx Buffer Empty */
94         Te = 0x04,      /* Transmitter Enable */
95         Re = 0x08,      /* Receiver Enable */
96         Rst = 0x10,     /* Software Reset */
97 };
98
99 enum {                                                  /* Imr/Isr */
100         Rok = 0x0001,                           /* Receive OK */
101         Rer = 0x0002,   /* Receive Error */
102         Tok = 0x0004,   /* Transmit OK */
103         Ter = 0x0008,   /* Transmit Error */
104         Rxovw = 0x0010, /* Receive Buffer Overflow */
105         PunLc = 0x0020, /* Packet Underrun or Link Change */
106         Fovw = 0x0040,  /* Receive FIFO Overflow */
107         Clc = 0x2000,   /* Cable Length Change */
108         Timerbit = 0x4000,      /* Timer */
109         Serr = 0x8000,  /* System Error */
110 };
111
112 enum {                                                  /* Tcr */
113         Clrabt = 0x00000001,            /* Clear Abort */
114         TxrrSHIFT = 4,  /* Transmit Retry Count */
115         TxrrMASK = 0x000000F0,
116         MtxdmaSHIFT = 8,        /* Max. DMA Burst Size */
117         MtxdmaMASK = 0x00000700,
118         Mtxdma2048 = 0x00000700,
119         Acrc = 0x00010000,      /* Append CRC (not) */
120         LbkSHIFT = 17,  /* Loopback Test */
121         LbkMASK = 0x00060000,
122         Rtl8139ArevG = 0x00800000,      /* RTL8139A Rev. G ID */
123         IfgSHIFT = 24,  /* Interframe Gap */
124         IfgMASK = 0x03000000,
125         HwveridSHIFT = 26,      /* Hardware Version ID */
126         HwveridMASK = 0x7C000000,
127 };
128
129 enum {                                                  /* Rcr */
130         Aap = 0x00000001,                       /* Accept All Packets */
131         Apm = 0x00000002,       /* Accept Physical Match */
132         Am = 0x00000004,        /* Accept Multicast */
133         Ab = 0x00000008,        /* Accept Broadcast */
134         Ar = 0x00000010,        /* Accept Runt */
135         Aer = 0x00000020,       /* Accept Error */
136         Sel9356 = 0x00000040,   /* 9356 EEPROM used */
137         Wrap = 0x00000080,      /* Rx Buffer Wrap Control */
138         MrxdmaSHIFT = 8,        /* Max. DMA Burst Size */
139         MrxdmaMASK = 0x00000700,
140         Mrxdmaunlimited = 0x00000700,
141         RblenSHIFT = 11,        /* Receive Buffer Length */
142         RblenMASK = 0x00001800,
143         Rblen8K = 0x00000000,   /* 8KB+16 */
144         Rblen16K = 0x00000800,  /* 16KB+16 */
145         Rblen32K = 0x00001000,  /* 32KB+16 */
146         Rblen64K = 0x00001800,  /* 64KB+16 */
147         RxfthSHIFT = 13,        /* Receive Buffer Length */
148         RxfthMASK = 0x0000E000,
149         Rxfth256 = 0x00008000,
150         Rxfthnone = 0x0000E000,
151         Rer8 = 0x00010000,      /* Accept Error Packets > 8 bytes */
152         MulERINT = 0x00020000,  /* Multiple Early Interrupt Select */
153         ErxthSHIFT = 24,        /* Early Rx Threshold */
154         ErxthMASK = 0x0F000000,
155         Erxthnone = 0x00000000,
156 };
157
158 enum {                                                  /* Received Packet Status */
159         Rcok = 0x0001,                          /* Receive Completed OK */
160         Fae = 0x0002,   /* Frame Alignment Error */
161         Crc = 0x0004,   /* CRC Error */
162         Long = 0x0008,  /* Long Packet */
163         Runt = 0x0010,  /* Runt Packet Received */
164         Ise = 0x0020,   /* Invalid Symbol Error */
165         Bar = 0x2000,   /* Broadcast Address Received */
166         Pam = 0x4000,   /* Physical Address Matched */
167         Mar = 0x8000,   /* Multicast Address Received */
168 };
169
170 enum {                                                  /* Media Status Register */
171         Rxpf = 0x01,                            /* Pause Flag */
172         Txpf = 0x02,    /* Pause Flag */
173         Linkb = 0x04,   /* Inverse of Link Status */
174         Speed10 = 0x08, /* 10Mbps */
175         Auxstatus = 0x10,       /* Aux. Power Present Status */
176         Rxfce = 0x40,   /* Receive Flow Control Enable */
177         Txfce = 0x80,   /* Transmit Flow Control Enable */
178 };
179
180 typedef struct Td Td;
181 struct Td {                                             /* Soft Transmit Descriptor */
182         int tsd;
183         int tsad;
184         uint8_t *data;
185         struct block *bp;
186 };
187
188 enum {                                                  /* Tsd0 */
189         SizeSHIFT = 0,                          /* Descriptor Size */
190         SizeMASK = 0x00001FFF,
191         Own = 0x00002000,
192         Tun = 0x00004000,       /* Transmit FIFO Underrun */
193         Tcok = 0x00008000,      /* Transmit COmpleted OK */
194         EtxthSHIFT = 16,        /* Early Tx Threshold */
195         EtxthMASK = 0x001F0000,
196         NccSHIFT = 24,  /* Number of Collisions Count */
197         NccMASK = 0x0F000000,
198         Cdh = 0x10000000,       /* CD Heartbeat */
199         Owc = 0x20000000,       /* Out of Window Collision */
200         Tabt = 0x40000000,      /* Transmit Abort */
201         Crs = 0x80000000,       /* Carrier Sense Lost */
202 };
203
204 enum {
205         Rblen = Rblen64K,                       /* Receive Buffer Length */
206         Ntd = 4,        /* Number of Transmit Descriptors */
207 };
208 #define         Tdbsz           ROUNDUP(sizeof(struct etherpkt), 4)
209
210 typedef struct ctlr {
211         int port;
212         struct pci_device *pcidev;
213         struct ctlr *next;
214         int active;
215         int id;
216
217         qlock_t alock;                          /* attach */
218         spinlock_t ilock;                       /* init */
219         void *alloc;                            /* base of per-ctlr allocated data */
220
221         int rcr;                                        /* receive configuration register */
222         uint8_t *rbstart;                       /* receive buffer */
223         int rblen;                                      /* receive buffer length */
224         int ierrs;                                      /* receive errors */
225
226         spinlock_t tlock;                       /* transmit */
227         Td td[Ntd];
228         int ntd;                                        /* descriptors active */
229         int tdh;                                        /* host index into td */
230         int tdi;                                        /* interface index into td */
231         int etxth;                                      /* early transmit threshold */
232         int taligned;                           /* packet required no alignment */
233         int tunaligned;                         /* packet required alignment */
234
235         int dis;                                        /* disconnect counter */
236         int fcsc;                                       /* false carrier sense counter */
237         int rec;                                        /* RX_ER counter */
238 } ctlr;
239
240 static struct ctlr *ctlrhead;
241 static struct ctlr *ctlrtail;
242
243 #define csr8r(c, r)     (inb((c)->port+(r)))
244 #define csr16r(c, r)    (inw((c)->port+(r)))
245 #define csr32r(c, r)    (inl((c)->port+(r)))
246 #define csr8w(c, r, b)  (outb((c)->port+(r), (int)(b)))
247 #define csr16w(c, r, w) (outw((c)->port+(r), (uint16_t)(w)))
248 #define csr32w(c, r, l) (outl((c)->port+(r), (uint32_t)(l)))
249
250 /* Helper for checking physical memory calculations.  This driver doesn't
251  * support 64 bit DMA, so we can't handle kaddrs that map to pages that are
252  * above the 32 bit phyiscal memory line (4GB) */
253 static void paddr_check(void *kaddr)
254 {
255         if (paddr_high32(kaddr))
256                 panic("rtl8139: attempted to publish paddr > 4GB!.  "
257                           "Try running with less memory.");
258 }
259
260 static void rtl8139promiscuous(void *arg, int on)
261 {
262         struct ether *edev;
263         struct ctlr *ctlr;
264
265         edev = arg;
266         ctlr = edev->ctlr;
267         spin_lock_irqsave(&ctlr->ilock);
268
269         if (on)
270                 ctlr->rcr |= Aap;
271         else
272                 ctlr->rcr &= ~Aap;
273         csr32w(ctlr, Rcr, ctlr->rcr);
274         spin_unlock_irqsave(&ctlr->ilock);
275 }
276
277 static long rtl8139ifstat(struct ether *edev, void *a, long n, uint32_t offset)
278 {
279         int l;
280         char *p;
281         struct ctlr *ctlr;
282
283         ctlr = edev->ctlr;
284         p = kzmalloc(READSTR, 0);
285         l = snprintf(p, READSTR, "rcr 0x%8.8x\n", ctlr->rcr);
286         l += snprintf(p + l, READSTR - l, "ierrs %d\n", ctlr->ierrs);
287         l += snprintf(p + l, READSTR - l, "etxth %d\n", ctlr->etxth);
288         l += snprintf(p + l, READSTR - l, "taligned %d\n", ctlr->taligned);
289         l += snprintf(p + l, READSTR - l, "tunaligned %d\n", ctlr->tunaligned);
290         ctlr->dis += csr16r(ctlr, Dis);
291         l += snprintf(p + l, READSTR - l, "dis %d\n", ctlr->dis);
292         ctlr->fcsc += csr16r(ctlr, Fcsc);
293         l += snprintf(p + l, READSTR - l, "fcscnt %d\n", ctlr->fcsc);
294         ctlr->rec += csr16r(ctlr, Rec);
295         l += snprintf(p + l, READSTR - l, "rec %d\n", ctlr->rec);
296
297         l += snprintf(p + l, READSTR - l, "Tcr 0x%8.8lx\n", csr32r(ctlr, Tcr));
298         l += snprintf(p + l, READSTR - l, "Config0 0x%2.2x\n",
299                                   csr8r(ctlr, Config0));
300         l += snprintf(p + l, READSTR - l, "Config1 0x%2.2x\n",
301                                   csr8r(ctlr, Config1));
302         l += snprintf(p + l, READSTR - l, "Msr 0x%2.2x\n", csr8r(ctlr, Msr));
303         l += snprintf(p + l, READSTR - l, "Config3 0x%2.2x\n",
304                                   csr8r(ctlr, Config3));
305         l += snprintf(p + l, READSTR - l, "Config4 0x%2.2x\n",
306                                   csr8r(ctlr, Config4));
307
308         l += snprintf(p + l, READSTR - l, "Bmcr 0x%4.4x\n", csr16r(ctlr, Bmcr));
309         l += snprintf(p + l, READSTR - l, "Bmsr 0x%4.4x\n", csr16r(ctlr, Bmsr));
310         l += snprintf(p + l, READSTR - l, "Anar 0x%4.4x\n", csr16r(ctlr, Anar));
311         l += snprintf(p + l, READSTR - l, "Anlpar 0x%4.4x\n", csr16r(ctlr, Anlpar));
312         l += snprintf(p + l, READSTR - l, "Aner 0x%4.4x\n", csr16r(ctlr, Aner));
313         l += snprintf(p + l, READSTR - l, "Nwaytr 0x%4.4x\n", csr16r(ctlr, Nwaytr));
314         snprintf(p + l, READSTR - l, "Cscr 0x%4.4x\n", csr16r(ctlr, Cscr));
315         n = readstr(offset, a, n, p);
316         kfree(p);
317
318         return n;
319 }
320
321 static int rtl8139reset(struct ctlr *ctlr)
322 {
323         int timeo;
324
325         /*
326          * Soft reset the controller.
327          */
328         csr8w(ctlr, Cr, Rst);
329         for (timeo = 0; timeo < 1000; timeo++) {
330                 if (!(csr8r(ctlr, Cr) & Rst))
331                         return 0;
332                 udelay(1000);
333         }
334
335         return -1;
336 }
337
338 static void rtl8139halt(struct ctlr *ctlr)
339 {
340         int i;
341
342         csr8w(ctlr, Cr, 0);
343         csr16w(ctlr, Imr, 0);
344         csr16w(ctlr, Isr, ~0);
345
346         for (i = 0; i < Ntd; i++) {
347                 if (ctlr->td[i].bp == NULL)
348                         continue;
349                 freeb(ctlr->td[i].bp);
350                 ctlr->td[i].bp = NULL;
351         }
352 }
353
354 static void rtl8139init(struct ether *edev)
355 {
356         int i;
357         uint32_t r;
358         struct ctlr *ctlr;
359         uint8_t *alloc;
360
361         ctlr = edev->ctlr;
362         spin_lock_irqsave(&ctlr->ilock);
363
364         rtl8139halt(ctlr);
365
366         /*
367          * MAC Address.
368          */
369         r = (edev->ea[3] << 24) | (edev->ea[2] << 16) | (edev->ea[1] << 8) | edev->
370                 ea[0];
371         csr32w(ctlr, Idr0, r);
372         r = (edev->ea[5] << 8) | edev->ea[4];
373         csr32w(ctlr, Idr0 + 4, r);
374
375         /*
376          * Receiver
377          */
378         // inferno had mmucacheinhib here
379         alloc = (uint8_t *) ROUNDUP((uintptr_t) ctlr->alloc, ARCH_CL_SIZE);
380         ctlr->rbstart = alloc;
381         alloc += ctlr->rblen + 16;
382         memset(ctlr->rbstart, 0, ctlr->rblen + 16);
383         csr32w(ctlr, Rbstart, paddr_low32(ctlr->rbstart));
384         paddr_check(ctlr->rbstart);
385         ctlr->rcr = Rxfth256 | Rblen | Mrxdmaunlimited | Ab | Apm;
386
387         /*
388          * Transmitter.
389          */
390         for (i = 0; i < Ntd; i++) {
391                 ctlr->td[i].tsd = Tsd0 + i * 4;
392                 ctlr->td[i].tsad = Tsad0 + i * 4;
393                 ctlr->td[i].data = alloc;
394                 alloc += Tdbsz;
395                 ctlr->td[i].bp = NULL;
396         }
397         ctlr->ntd = ctlr->tdh = ctlr->tdi = 0;
398         ctlr->etxth = 128 / 32;
399
400         /*
401          * Interrupts.
402          */
403         csr32w(ctlr, TimerInt, 0);
404         csr16w(ctlr, Imr,
405                    Serr | Timerbit | Fovw | PunLc | Rxovw | Ter | Tok | Rer | Rok);
406         csr32w(ctlr, Mpc, 0);
407
408         /*
409          * Enable receiver/transmitter.
410          * Need to enable before writing the Rcr or it won't take.
411          */
412         csr8w(ctlr, Cr, Te | Re);
413         csr32w(ctlr, Tcr, Mtxdma2048);
414         csr32w(ctlr, Rcr, ctlr->rcr);
415
416         spin_unlock_irqsave(&ctlr->ilock);
417 }
418
419 static void rtl8139attach(struct ether *edev)
420 {
421         struct ctlr *ctlr;
422
423         ctlr = edev->ctlr;
424         qlock(&ctlr->alock);
425         if (ctlr->alloc == NULL) {
426                 ctlr->rblen = 1 << ((Rblen >> RblenSHIFT) + 13);
427                 ctlr->alloc = kzmalloc(ctlr->rblen + 16 + Ntd * Tdbsz + ARCH_CL_SIZE,
428                                                            KMALLOC_WAIT);
429                 rtl8139init(edev);
430         }
431         qunlock(&ctlr->alock);
432 }
433
434 static void rtl8139txstart(struct ether *edev)
435 {
436         Td *td;
437         int size;
438         struct block *bp;
439         struct ctlr *ctlr;
440
441         ctlr = edev->ctlr;
442         while (ctlr->ntd < Ntd) {
443                 bp = qget(edev->oq);
444                 if (bp == NULL)
445                         break;
446                 size = BLEN(bp);
447
448                 td = &ctlr->td[ctlr->tdh];
449                 if (((uintptr_t) bp->rp) & 0x03) {
450                         memmove(td->data, bp->rp, size);
451                         /* flushing the data cache? */
452                         //dcflush(td->data, size);
453                         freeb(bp);
454                         csr32w(ctlr, td->tsad, paddr_low32(td->data));
455                         paddr_check(td->data);
456                         ctlr->tunaligned++;
457                 } else {
458                         td->bp = bp;
459                         csr32w(ctlr, td->tsad, paddr_low32(bp->rp));
460                         /* flushing the data cache? */
461                         //dcflush(bp->rp, size);
462                         paddr_check(bp->rp);
463                         ctlr->taligned++;
464                 }
465                 csr32w(ctlr, td->tsd, (ctlr->etxth << EtxthSHIFT) | size);
466
467                 ctlr->ntd++;
468                 ctlr->tdh = NEXT_RING(ctlr->tdh, Ntd);
469         }
470 }
471
472 static void rtl8139transmit(struct ether *edev)
473 {
474         struct ctlr *ctlr;
475
476         ctlr = edev->ctlr;
477         spin_lock_irqsave(&ctlr->tlock);
478         rtl8139txstart(edev);
479         spin_unlock_irqsave(&ctlr->tlock);
480 }
481
482 static void rtl8139receive(struct ether *edev)
483 {
484         struct block *bp;
485         struct ctlr *ctlr;
486         uint16_t capr;
487         uint8_t cr, *p;
488         int l, length, status;
489
490         ctlr = edev->ctlr;
491
492         /*
493          * Capr is where the host is reading from,
494          * Cbr is where the NIC is currently writing.
495          */
496         capr = (csr16r(ctlr, Capr) + 16) % ctlr->rblen;
497         while (!(csr8r(ctlr, Cr) & Bufe)) {
498                 p = ctlr->rbstart + capr;
499
500                 /*
501                  * Apparently the packet length may be 0xFFF0 if
502                  * the NIC is still copying the packet into memory.
503                  */
504                 length = (*(p + 3) << 8) | *(p + 2);
505                 if (length == 0xFFF0)
506                         break;
507                 status = (*(p + 1) << 8) | *p;
508                 if (!(status & Rcok)) {
509                         if (status & (Ise | Fae))
510                                 edev->frames++;
511                         if (status & Crc)
512                                 edev->crcs++;
513                         if (status & (Runt | Long))
514                                 edev->buffs++;
515
516                         /*
517                          * Reset the receiver.
518                          * Also may have to restore the multicast list
519                          * here too if it ever gets used.
520                          */
521                         cr = csr8r(ctlr, Cr);
522                         csr8w(ctlr, Cr, cr & ~Re);
523                         csr32w(ctlr, Rbstart, paddr_low32(ctlr->rbstart));
524                         paddr_check(ctlr->rbstart);
525                         csr8w(ctlr, Cr, cr);
526                         csr32w(ctlr, Rcr, ctlr->rcr);
527
528                         continue;
529                 }
530
531                 /*
532                  * Receive Completed OK.
533                  * Very simplistic; there are ways this could be done
534                  * without copying, but the juice probably isn't worth
535                  * the squeeze.
536                  * The packet length includes a 4 byte CRC on the end.
537                  */
538                 capr = (capr + 4) % ctlr->rblen;
539                 p = ctlr->rbstart + capr;
540                 capr = (capr + length) % ctlr->rblen;
541
542                 if ((bp = iallocb(length)) != NULL) {
543                         if (p + length >= ctlr->rbstart + ctlr->rblen) {
544                                 l = ctlr->rbstart + ctlr->rblen - p;
545                                 memmove(bp->wp, p, l);
546                                 bp->wp += l;
547                                 length -= l;
548                                 p = ctlr->rbstart;
549                         }
550                         if (length > 0) {
551                                 memmove(bp->wp, p, length);
552                                 bp->wp += length;
553                         }
554                         bp->wp -= 4;
555                         etheriq(edev, bp, 1);
556                 }
557
558                 capr = ROUNDUP(capr, 4);
559                 csr16w(ctlr, Capr, capr - 16);
560         }
561 }
562
563 static void rtl8139interrupt(struct hw_trapframe *tf, void *arg)
564 {
565         Td *td;
566         struct ctlr *ctlr;
567         struct ether *edev;
568         int isr, msr, tsd;
569
570         edev = arg;
571         ctlr = edev->ctlr;
572
573         while ((isr = csr16r(ctlr, Isr)) != 0) {
574                 csr16w(ctlr, Isr, isr);
575                 if (isr & (Fovw | PunLc | Rxovw | Rer | Rok)) {
576                         rtl8139receive(edev);
577                         if (!(isr & Rok))
578                                 ctlr->ierrs++;
579                         isr &= ~(Fovw | Rxovw | Rer | Rok);
580                 }
581
582                 if (isr & (Ter | Tok)) {
583                         spin_lock_irqsave(&ctlr->tlock);
584                         while (ctlr->ntd) {
585                                 td = &ctlr->td[ctlr->tdi];
586                                 tsd = csr32r(ctlr, td->tsd);
587                                 if (!(tsd & (Tabt | Tun | Tcok)))
588                                         break;
589
590                                 if (!(tsd & Tcok)) {
591                                         if (tsd & Tun) {
592                                                 if (ctlr->etxth < ETHERMAXTU / 32)
593                                                         ctlr->etxth++;
594                                         }
595                                         edev->oerrs++;
596                                 }
597
598                                 if (td->bp != NULL) {
599                                         freeb(td->bp);
600                                         td->bp = NULL;
601                                 }
602
603                                 ctlr->ntd--;
604                                 ctlr->tdi = NEXT_RING(ctlr->tdi, Ntd);
605                         }
606                         rtl8139txstart(edev);
607                         spin_unlock_irqsave(&ctlr->tlock);
608                         isr &= ~(Ter | Tok);
609                 }
610
611                 if (isr & PunLc) {
612                         /*
613                          * Maybe the link changed - do we care very much?
614                          */
615                         msr = csr8r(ctlr, Msr);
616                         if (!(msr & Linkb)) {
617                                 if (!(msr & Speed10) && edev->mbps != 100) {
618                                         edev->mbps = 100;
619                                         qsetlimit(edev->oq, 256 * 1024);
620                                 } else if ((msr & Speed10) && edev->mbps != 10) {
621                                         edev->mbps = 10;
622                                         qsetlimit(edev->oq, 65 * 1024);
623                                 }
624                         }
625                         isr &= ~(Clc | PunLc);
626                 }
627
628                 /*
629                  * Only Serr|Timer should be left by now.
630                  * Should anything be done to tidy up? TimerInt isn't
631                  * used so that can be cleared. A PCI bus error is indicated
632                  * by Serr, that's pretty serious; is there anyhing to do
633                  * other than try to reinitialise the chip?
634                  */
635                 if (isr != 0) {
636                         printk("rtl8139interrupt: imr 0x%4.4x isr 0x%4.4x\n",
637                                    csr16r(ctlr, Imr), isr);
638                         if (isr & Timerbit)
639                                 csr32w(ctlr, TimerInt, 0);
640                         if (isr & Serr)
641                                 rtl8139init(edev);
642                 }
643         }
644 }
645
646 static struct ctlr *rtl8139match(struct ether *edev, int id)
647 {
648         int port;
649         struct pci_device *pcidev;
650         struct ctlr *ctlr;
651
652         /*
653          * Any adapter matches if no edev->port is supplied,
654          * otherwise the ports must match.
655          */
656         for (ctlr = ctlrhead; ctlr != NULL; ctlr = ctlr->next) {
657                 if (ctlr->active)
658                         continue;
659                 pcidev = ctlr->pcidev;
660                 if (((pcidev->dev_id << 16) | pcidev->ven_id) != id)
661                         continue;
662                 port = pcidev->bar[0].pio_base;
663                 if (edev->port != 0 && edev->port != port)
664                         continue;
665
666 #if 0
667                 /* trying to alloc PIO ports (.size of them?).  for now, we just assume
668                  * they are free */
669                 if (ioalloc(port, pcidev->mem[0].size, 0, "rtl8139") < 0) {
670                         printd("rtl8139: port 0x%x in use\n", port);
671                         continue;
672                 }
673 #endif
674
675                 ctlr->port = port;
676                 if (rtl8139reset(ctlr))
677                         continue;
678                 pci_set_bus_master(pcidev);
679
680                 ctlr->active = 1;
681                 return ctlr;
682         }
683         return NULL;
684 }
685
686 static struct {
687         char *name;
688         int id;
689 } rtl8139pci[] = {
690         {
691         "rtl8139", (0x8139 << 16) | 0x10EC,},   /* generic */
692         {
693         "smc1211", (0x1211 << 16) | 0x1113,},   /* SMC EZ-Card */
694         {
695         "dfe-538tx", (0x1300 << 16) | 0x1186,}, /* D-Link DFE-538TX */
696         {
697         "dfe-560txd", (0x1340 << 16) | 0x1186,},        /* D-Link DFE-560TXD */
698         {
699 NULL},};
700
701 static int rtl8139pnp(struct ether *edev)
702 {
703         int i, id;
704         struct pci_device *pcidev;
705         struct ctlr *ctlr;
706         uint8_t ea[Eaddrlen];
707
708         /* Make a list of all ethernet controllers if not already done.
709          *
710          * brho: this style is a bit weird - we have ctlr structs for every NIC,
711          * including non-rtl NICs. */
712         if (ctlrhead == NULL) {
713                 STAILQ_FOREACH(pcidev, &pci_devices, all_dev) {
714                         /* this skips over non-ethernet devices. */
715                         if (pcidev->class != 0x02 || pcidev->subclass != 0)
716                                 continue;
717
718                         ctlr = kzmalloc(sizeof(struct ctlr), KMALLOC_WAIT);
719                         qlock_init(&ctlr->alock);
720                         spinlock_init_irqsave(&ctlr->ilock);
721                         spinlock_init_irqsave(&ctlr->tlock);
722                         ctlr->pcidev = pcidev;
723                         ctlr->id = (pcidev->dev_id << 16) | pcidev->ven_id;
724
725                         if (ctlrhead != NULL)
726                                 ctlrtail->next = ctlr;
727                         else
728                                 ctlrhead = ctlr;
729                         ctlrtail = ctlr;
730                 }
731         }
732
733         /*
734          * Is it an RTL8139 under a different name?
735          * Normally a search is made through all the found controllers
736          * for one which matches any of the known vid+did pairs.
737          * If a vid+did pair is specified a search is made for that
738          * specific controller only.
739          */
740         id = 0;
741 #if 0   // No struct ether options yet (goes with archenter, i think)
742         for (i = 0; i < edev->nopt; i++) {
743                 if (cistrncmp(edev->opt[i], "id=", 3) == 0)
744                         id = strtol(&edev->opt[i][3], NULL, 0);
745         }
746 #endif
747
748         ctlr = NULL;
749         if (id != 0)
750                 ctlr = rtl8139match(edev, id);
751         else
752                 for (i = 0; rtl8139pci[i].name; i++) {
753                         if ((ctlr = rtl8139match(edev, rtl8139pci[i].id)) != NULL)
754                                 break;
755                 }
756         if (ctlr == NULL)
757                 return -1;
758
759         printd("RTL8139 driver found %s at %02x:%02x.%x\n", rtl8139pci[i].name,
760                    ctlr->pcidev->bus, ctlr->pcidev->dev, ctlr->pcidev->func);
761         edev->ctlr = ctlr;
762         edev->port = ctlr->port;
763         edev->irq = ctlr->pcidev->irqline;
764
765         /*
766          * Check if the adapter's station address is to be overridden.
767          * If not, read it from the device and set in edev->ea.
768          */
769         memset(ea, 0, Eaddrlen);
770         if (memcmp(ea, edev->ea, Eaddrlen) == 0) {
771                 i = csr32r(ctlr, Idr0);
772                 edev->ea[0] = i;
773                 edev->ea[1] = i >> 8;
774                 edev->ea[2] = i >> 16;
775                 edev->ea[3] = i >> 24;
776                 i = csr32r(ctlr, Idr0 + 4);
777                 edev->ea[4] = i;
778                 edev->ea[5] = i >> 8;
779         }
780         edev->tbdf = pci_to_tbdf(ctlr->pcidev);
781         edev->attach = rtl8139attach;
782         edev->transmit = rtl8139transmit;
783         edev->ifstat = rtl8139ifstat;
784
785         edev->arg = edev;
786         edev->promiscuous = rtl8139promiscuous;
787
788         /*
789          * This should be much more dynamic but will do for now.
790          */
791         if ((csr8r(ctlr, Msr) & (Speed10 | Linkb)) == 0)
792                 edev->mbps = 100;
793
794         register_irq(edev->irq, rtl8139interrupt, edev, edev->tbdf);
795         return 0;
796 }
797
798 linker_func_3(ether8139link)
799 {
800         addethercard("rtl8139", rtl8139pnp);
801 }