BNX2X: usability fixups
[akaros.git] / kern / drivers / net / e1000 / e1000_phy.h
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #ifndef _E1000_PHY_H_
30 #define _E1000_PHY_H_
31
32 void e1000_init_phy_ops_generic(struct e1000_hw *hw);
33 int32_t e1000_null_read_reg(struct e1000_hw *hw, uint32_t offset,
34                                                         uint16_t * data);
35 void e1000_null_phy_generic(struct e1000_hw *hw);
36 int32_t e1000_null_lplu_state(struct e1000_hw *hw, bool active);
37 int32_t e1000_null_write_reg(struct e1000_hw *hw, uint32_t offset,
38                                                          uint16_t data);
39 int32_t e1000_check_downshift_generic(struct e1000_hw *hw);
40 int32_t e1000_check_polarity_m88(struct e1000_hw *hw);
41 int32_t e1000_check_polarity_igp(struct e1000_hw *hw);
42 int32_t e1000_check_polarity_ife(struct e1000_hw *hw);
43 int32_t e1000_check_reset_block_generic(struct e1000_hw *hw);
44 int32_t e1000_copper_link_autoneg(struct e1000_hw *hw);
45 int32_t e1000_copper_link_setup_igp(struct e1000_hw *hw);
46 int32_t e1000_copper_link_setup_m88(struct e1000_hw *hw);
47 #if 0
48 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
49 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
50 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
51 #endif
52 #if 0
53 s32 e1000_get_cable_length_m88(struct e1000_hw *hw);
54 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);
55 #endif
56 int32_t e1000_get_cfg_done_generic(struct e1000_hw *hw);
57 int32_t e1000_get_phy_id(struct e1000_hw *hw);
58 int32_t e1000_get_phy_info_igp(struct e1000_hw *hw);
59 int32_t e1000_get_phy_info_m88(struct e1000_hw *hw);
60 int32_t e1000_phy_sw_reset_generic(struct e1000_hw *hw);
61 #if 0
62 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 * phy_ctrl);
63 #endif
64 int32_t e1000_phy_hw_reset_generic(struct e1000_hw *hw);
65 int32_t e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
66 int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
67 int32_t e1000_read_kmrn_reg_generic(struct e1000_hw *hw, uint32_t offset,
68                                                                         uint16_t * data);
69 int32_t e1000_read_phy_reg_igp(struct e1000_hw *hw,
70                                                            uint32_t offset, uint16_t * data);
71 int32_t e1000_read_phy_reg_m88(struct e1000_hw *hw,
72                                                            uint32_t offset, uint16_t * data);
73 int32_t e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
74 int32_t e1000_setup_copper_link_generic(struct e1000_hw *hw);
75 int32_t e1000_wait_autoneg_generic(struct e1000_hw *hw);
76 int32_t e1000_write_kmrn_reg_generic(struct e1000_hw *hw, uint32_t offset,
77                                                                          uint16_t data);
78 int32_t e1000_write_phy_reg_igp(struct e1000_hw *hw,
79                                                                 uint32_t offset, uint16_t data);
80 int32_t e1000_write_phy_reg_m88(struct e1000_hw *hw,
81                                                                 uint32_t offset, uint16_t data);
82 int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
83 int32_t e1000_phy_has_link_generic(struct e1000_hw *hw, uint32_t iterations,
84                                                                    uint32_t usec_interval, bool * success);
85 int32_t e1000_phy_init_script_igp3(struct e1000_hw *hw);
86 enum e1000_phy_type e1000_get_phy_type_from_id(uint32_t phy_id);
87 int32_t e1000_determine_phy_address(struct e1000_hw *hw);
88 void e1000_power_up_phy_copper(struct e1000_hw *hw);
89 void e1000_power_down_phy_copper(struct e1000_hw *hw);
90 int32_t e1000_read_phy_reg_mdic(struct e1000_hw *hw,
91                                                                 uint32_t offset, uint16_t * data);
92 int32_t e1000_write_phy_reg_mdic(struct e1000_hw *hw,
93                                                                  uint32_t offset, uint16_t data);
94
95 #define E1000_MAX_PHY_ADDR                4
96
97 /* IGP01E1000 Specific Registers */
98 #define IGP01E1000_PHY_PORT_CONFIG        0x10  /* Port Config */
99 #define IGP01E1000_PHY_PORT_STATUS        0x11  /* Status */
100 #define IGP01E1000_PHY_PORT_CTRL          0x12  /* Control */
101 #define IGP01E1000_PHY_LINK_HEALTH        0x13  /* PHY Link Health */
102 #define IGP01E1000_GMII_FIFO              0x14  /* GMII FIFO */
103 #define IGP01E1000_PHY_CHANNEL_QUALITY    0x15  /* PHY Channel Quality */
104 #define IGP02E1000_PHY_POWER_MGMT         0x19  /* Power Management */
105 #define IGP01E1000_PHY_PAGE_SELECT        0x1F  /* Page Select */
106 #define BM_PHY_PAGE_SELECT                22    /* Page Select for BM */
107 #define IGP_PAGE_SHIFT                    5
108 #define PHY_REG_MASK                      0x1F
109
110 #define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
111 #define IGP01E1000_PHY_POLARITY_MASK      0x0078
112
113 #define IGP01E1000_PSCR_AUTO_MDIX         0x1000
114 #define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000        /* 0=MDI, 1=MDIX */
115
116 #define IGP01E1000_PSCFR_SMART_SPEED      0x0080
117
118 /* Enable flexible speed on link-up */
119 #define IGP01E1000_GMII_FLEX_SPD          0x0010
120 #define IGP01E1000_GMII_SPD               0x0020        /* Enable SPD */
121
122 #define IGP02E1000_PM_SPD                 0x0001        /* Smart Power Down */
123 #define IGP02E1000_PM_D0_LPLU             0x0002        /* For D0a states */
124 #define IGP02E1000_PM_D3_LPLU             0x0004        /* For all other states */
125
126 #define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
127
128 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
129 #define IGP01E1000_PSSR_MDIX              0x0800
130 #define IGP01E1000_PSSR_SPEED_MASK        0xC000
131 #define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
132
133 #define IGP02E1000_PHY_CHANNEL_NUM        4
134 #define IGP02E1000_PHY_AGC_A              0x11B1
135 #define IGP02E1000_PHY_AGC_B              0x12B1
136 #define IGP02E1000_PHY_AGC_C              0x14B1
137 #define IGP02E1000_PHY_AGC_D              0x18B1
138
139 #define IGP02E1000_AGC_LENGTH_SHIFT       9     /* Course - 15:13, Fine - 12:9 */
140 #define IGP02E1000_AGC_LENGTH_MASK        0x7F
141 #define IGP02E1000_AGC_RANGE              15
142
143 #define IGP03E1000_PHY_MISC_CTRL          0x1B
144 #define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000   /* Manually Set Duplex */
145
146 #define E1000_CABLE_LENGTH_UNDEFINED      0xFF
147
148 #define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
149 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
150 #define E1000_KMRNCTRLSTA_REN             0x00200000
151 #define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3   /* Kumeran Diagnostic */
152 #define E1000_KMRNCTRLSTA_TIMEOUTS        0x4   /* Kumeran Timeouts */
153 #define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9   /* Kumeran InBand Parameters */
154 #define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000        /* Nearend Loopback mode */
155
156 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
157 #define IFE_PHY_SPECIAL_CONTROL     0x11        /* 100BaseTx PHY Special Control */
158 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B        /* PHY Special and LED Control */
159 #define IFE_PHY_MDIX_CONTROL        0x1C        /* MDI/MDI-X Control */
160
161 /* IFE PHY Extended Status Control */
162 #define IFE_PESC_POLARITY_REVERSED    0x0100
163
164 /* IFE PHY Special Control */
165 #define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
166 #define IFE_PSC_FORCE_POLARITY             0x0020
167 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
168
169 /* IFE PHY Special Control and LED Control */
170 #define IFE_PSCL_PROBE_MODE            0x0020
171 #define IFE_PSCL_PROBE_LEDS_OFF        0x0006   /* Force LEDs 0 and 2 off */
172 #define IFE_PSCL_PROBE_LEDS_ON         0x0007   /* Force LEDs 0 and 2 on */
173
174 /* IFE PHY MDIX Control */
175 #define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
176 #define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
177 #define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
178
179 #endif