BNX2X: usability fixups
[akaros.git] / kern / drivers / net / e1000 / e1000_hw.h
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #ifndef _E1000_HW_H_
30 #define _E1000_HW_H_
31
32 #include <vfs.h>
33 #include <kfs.h>
34 #include <slab.h>
35 #include <kmalloc.h>
36 #include <kref.h>
37 #include <string.h>
38 #include <stdio.h>
39 #include <assert.h>
40 #include <error.h>
41 #include <cpio.h>
42 #include <pmap.h>
43 #include <smp.h>
44 #include <ip.h>
45 #include "e1000_osdep.h"
46 #include "e1000_regs.h"
47 #include "e1000_defines.h"
48
49 struct e1000_hw;
50
51 #define E1000_DEV_ID_82542                    0x1000
52 #define E1000_DEV_ID_82543GC_FIBER            0x1001
53 #define E1000_DEV_ID_82543GC_COPPER           0x1004
54 #define E1000_DEV_ID_82544EI_COPPER           0x1008
55 #define E1000_DEV_ID_82544EI_FIBER            0x1009
56 #define E1000_DEV_ID_82544GC_COPPER           0x100C
57 #define E1000_DEV_ID_82544GC_LOM              0x100D
58 #define E1000_DEV_ID_82540EM                  0x100E
59 #define E1000_DEV_ID_82540EM_LOM              0x1015
60 #define E1000_DEV_ID_82540EP_LOM              0x1016
61 #define E1000_DEV_ID_82540EP                  0x1017
62 #define E1000_DEV_ID_82540EP_LP               0x101E
63 #define E1000_DEV_ID_82545EM_COPPER           0x100F
64 #define E1000_DEV_ID_82545EM_FIBER            0x1011
65 #define E1000_DEV_ID_82545GM_COPPER           0x1026
66 #define E1000_DEV_ID_82545GM_FIBER            0x1027
67 #define E1000_DEV_ID_82545GM_SERDES           0x1028
68 #define E1000_DEV_ID_82546EB_COPPER           0x1010
69 #define E1000_DEV_ID_82546EB_FIBER            0x1012
70 #define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
71 #define E1000_DEV_ID_82546GB_COPPER           0x1079
72 #define E1000_DEV_ID_82546GB_FIBER            0x107A
73 #define E1000_DEV_ID_82546GB_SERDES           0x107B
74 #define E1000_DEV_ID_82546GB_PCIE             0x108A
75 #define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
76 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
77 #define E1000_DEV_ID_82541EI                  0x1013
78 #define E1000_DEV_ID_82541EI_MOBILE           0x1018
79 #define E1000_DEV_ID_82541ER_LOM              0x1014
80 #define E1000_DEV_ID_82541ER                  0x1078
81 #define E1000_DEV_ID_82541GI                  0x1076
82 #define E1000_DEV_ID_82541GI_LF               0x107C
83 #define E1000_DEV_ID_82541GI_MOBILE           0x1077
84 #define E1000_DEV_ID_82547EI                  0x1019
85 #define E1000_DEV_ID_82547EI_MOBILE           0x101A
86 #define E1000_DEV_ID_82547GI                  0x1075
87 #define E1000_REVISION_0 0
88 #define E1000_REVISION_1 1
89 #define E1000_REVISION_2 2
90 #define E1000_REVISION_3 3
91 #define E1000_REVISION_4 4
92
93 #define E1000_FUNC_0     0
94 #define E1000_FUNC_1     1
95
96 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
97 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
98
99 enum e1000_mac_type {
100         e1000_undefined = 0,
101         e1000_82542,
102         e1000_82543,
103         e1000_82544,
104         e1000_82540,
105         e1000_82545,
106         e1000_82545_rev_3,
107         e1000_82546,
108         e1000_82546_rev_3,
109         e1000_82541,
110         e1000_82541_rev_2,
111         e1000_82547,
112         e1000_82547_rev_2,
113         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
114 };
115
116 enum e1000_media_type {
117         e1000_media_type_unknown = 0,
118         e1000_media_type_copper = 1,
119         e1000_media_type_fiber = 2,
120         e1000_media_type_internal_serdes = 3,
121         e1000_num_media_types
122 };
123
124 enum e1000_nvm_type {
125         e1000_nvm_unknown = 0,
126         e1000_nvm_none,
127         e1000_nvm_eeprom_spi,
128         e1000_nvm_eeprom_microwire,
129         e1000_nvm_flash_hw,
130         e1000_nvm_flash_sw
131 };
132
133 enum e1000_nvm_override {
134         e1000_nvm_override_none = 0,
135         e1000_nvm_override_spi_small,
136         e1000_nvm_override_spi_large,
137         e1000_nvm_override_microwire_small,
138         e1000_nvm_override_microwire_large
139 };
140
141 enum e1000_phy_type {
142         e1000_phy_unknown = 0,
143         e1000_phy_none,
144         e1000_phy_m88,
145         e1000_phy_igp,
146         e1000_phy_igp_2,
147         e1000_phy_gg82563,
148         e1000_phy_igp_3,
149         e1000_phy_ife,
150 };
151
152 enum e1000_bus_type {
153         e1000_bus_type_unknown = 0,
154         e1000_bus_type_pci,
155         e1000_bus_type_pcix,
156         e1000_bus_type_pci_express,
157         e1000_bus_type_reserved
158 };
159
160 enum e1000_bus_speed {
161         e1000_bus_speed_unknown = 0,
162         e1000_bus_speed_33,
163         e1000_bus_speed_66,
164         e1000_bus_speed_100,
165         e1000_bus_speed_120,
166         e1000_bus_speed_133,
167         e1000_bus_speed_2500,
168         e1000_bus_speed_5000,
169         e1000_bus_speed_reserved
170 };
171
172 enum e1000_bus_width {
173         e1000_bus_width_unknown = 0,
174         e1000_bus_width_pcie_x1,
175         e1000_bus_width_pcie_x2,
176         e1000_bus_width_pcie_x4 = 4,
177         e1000_bus_width_pcie_x8 = 8,
178         e1000_bus_width_32,
179         e1000_bus_width_64,
180         e1000_bus_width_reserved
181 };
182
183 enum e1000_1000t_rx_status {
184         e1000_1000t_rx_status_not_ok = 0,
185         e1000_1000t_rx_status_ok,
186         e1000_1000t_rx_status_undefined = 0xFF
187 };
188
189 enum e1000_rev_polarity {
190         e1000_rev_polarity_normal = 0,
191         e1000_rev_polarity_reversed,
192         e1000_rev_polarity_undefined = 0xFF
193 };
194
195 enum e1000_fc_mode {
196         e1000_fc_none = 0,
197         e1000_fc_rx_pause,
198         e1000_fc_tx_pause,
199         e1000_fc_full,
200         e1000_fc_default = 0xFF
201 };
202
203 enum e1000_ffe_config {
204         e1000_ffe_config_enabled = 0,
205         e1000_ffe_config_active,
206         e1000_ffe_config_blocked
207 };
208
209 enum e1000_dsp_config {
210         e1000_dsp_config_disabled = 0,
211         e1000_dsp_config_enabled,
212         e1000_dsp_config_activated,
213         e1000_dsp_config_undefined = 0xFF
214 };
215
216 enum e1000_ms_type {
217         e1000_ms_hw_default = 0,
218         e1000_ms_force_master,
219         e1000_ms_force_slave,
220         e1000_ms_auto
221 };
222
223 enum e1000_smart_speed {
224         e1000_smart_speed_default = 0,
225         e1000_smart_speed_on,
226         e1000_smart_speed_off
227 };
228
229 enum e1000_serdes_link_state {
230         e1000_serdes_link_down = 0,
231         e1000_serdes_link_autoneg_progress,
232         e1000_serdes_link_autoneg_complete,
233         e1000_serdes_link_forced_up
234 };
235
236 /* Receive Descriptor */
237 struct e1000_rx_desc {
238         uint64_t buffer_addr;           /* Address of the descriptor's data buffer */
239         uint16_t length;                        /* Length of data DMAed into data buffer */
240         uint16_t csum;                          /* Packet checksum */
241         uint8_t status;                         /* Descriptor status */
242         uint8_t errors;                         /* Descriptor Errors */
243         uint16_t special;
244 };
245
246 /* Receive Descriptor - Extended */
247 union e1000_rx_desc_extended {
248         struct {
249                 uint64_t buffer_addr;
250                 uint64_t reserved;
251         } read;
252         struct {
253                 struct {
254                         uint32_t mrq;           /* Multiple Rx Queues */
255                         union {
256                                 uint32_t rss;   /* RSS Hash */
257                                 struct {
258                                         uint16_t ip_id; /* IP id */
259                                         uint16_t csum;  /* Packet Checksum */
260                                 } csum_ip;
261                         } hi_dword;
262                 } lower;
263                 struct {
264                         uint32_t status_error;  /* ext status/error */
265                         uint16_t length;
266                         uint16_t vlan;          /* VLAN tag */
267                 } upper;
268         } wb;                                           /* writeback */
269 };
270
271 #define MAX_PS_BUFFERS 4
272 /* Receive Descriptor - Packet Split */
273 union e1000_rx_desc_packet_split {
274         struct {
275                 /* one buffer for protocol header(s), three data buffers */
276                 uint64_t buffer_addr[MAX_PS_BUFFERS];
277         } read;
278         struct {
279                 struct {
280                         uint32_t mrq;           /* Multiple Rx Queues */
281                         union {
282                                 uint32_t rss;   /* RSS Hash */
283                                 struct {
284                                         uint16_t ip_id; /* IP id */
285                                         uint16_t csum;  /* Packet Checksum */
286                                 } csum_ip;
287                         } hi_dword;
288                 } lower;
289                 struct {
290                         uint32_t status_error;  /* ext status/error */
291                         uint16_t length0;       /* length of buffer 0 */
292                         uint16_t vlan;          /* VLAN tag */
293                 } middle;
294                 struct {
295                         uint16_t header_status;
296                         uint16_t length[3];     /* length of buffers 1-3 */
297                 } upper;
298                 uint64_t reserved;
299         } wb;                                           /* writeback */
300 };
301
302 /* Transmit Descriptor */
303 struct e1000_tx_desc {
304         uint64_t buffer_addr;           /* Address of the descriptor's data buffer */
305         union {
306                 uint32_t data;
307                 struct {
308                         uint16_t length;        /* Data buffer length */
309                         uint8_t cso;            /* Checksum offset */
310                         uint8_t cmd;            /* Descriptor control */
311                 } flags;
312         } lower;
313         union {
314                 uint32_t data;
315                 struct {
316                         uint8_t status;         /* Descriptor status */
317                         uint8_t css;            /* Checksum start */
318                         uint16_t special;
319                 } fields;
320         } upper;
321 };
322
323 /* Offload Context Descriptor */
324 struct e1000_context_desc {
325         union {
326                 uint32_t ip_config;
327                 struct {
328                         uint8_t ipcss;          /* IP checksum start */
329                         uint8_t ipcso;          /* IP checksum offset */
330                         uint16_t ipcse;         /* IP checksum end */
331                 } ip_fields;
332         } lower_setup;
333         union {
334                 uint32_t tcp_config;
335                 struct {
336                         uint8_t tucss;          /* TCP checksum start */
337                         uint8_t tucso;          /* TCP checksum offset */
338                         uint16_t tucse;         /* TCP checksum end */
339                 } tcp_fields;
340         } upper_setup;
341         uint32_t cmd_and_length;
342         union {
343                 uint32_t data;
344                 struct {
345                         uint8_t status;         /* Descriptor status */
346                         uint8_t hdr_len;        /* Header length */
347                         uint16_t mss;           /* Maximum segment size */
348                 } fields;
349         } tcp_seg_setup;
350 };
351
352 /* Offload data descriptor */
353 struct e1000_data_desc {
354         uint64_t buffer_addr;           /* Address of the descriptor's buffer address */
355         union {
356                 uint32_t data;
357                 struct {
358                         uint16_t length;        /* Data buffer length */
359                         uint8_t typ_len_ext;
360                         uint8_t cmd;
361                 } flags;
362         } lower;
363         union {
364                 uint32_t data;
365                 struct {
366                         uint8_t status;         /* Descriptor status */
367                         uint8_t popts;          /* Packet Options */
368                         uint16_t special;
369                 } fields;
370         } upper;
371 };
372
373 /* Statistics counters collected by the MAC */
374 struct e1000_hw_stats {
375         uint64_t crcerrs;
376         uint64_t algnerrc;
377         uint64_t symerrs;
378         uint64_t rxerrc;
379         uint64_t mpc;
380         uint64_t scc;
381         uint64_t ecol;
382         uint64_t mcc;
383         uint64_t latecol;
384         uint64_t colc;
385         uint64_t dc;
386         uint64_t tncrs;
387         uint64_t sec;
388         uint64_t cexterr;
389         uint64_t rlec;
390         uint64_t xonrxc;
391         uint64_t xontxc;
392         uint64_t xoffrxc;
393         uint64_t xofftxc;
394         uint64_t fcruc;
395         uint64_t prc64;
396         uint64_t prc127;
397         uint64_t prc255;
398         uint64_t prc511;
399         uint64_t prc1023;
400         uint64_t prc1522;
401         uint64_t gprc;
402         uint64_t bprc;
403         uint64_t mprc;
404         uint64_t gptc;
405         uint64_t gorc;
406         uint64_t gotc;
407         uint64_t rnbc;
408         uint64_t ruc;
409         uint64_t rfc;
410         uint64_t roc;
411         uint64_t rjc;
412         uint64_t mgprc;
413         uint64_t mgpdc;
414         uint64_t mgptc;
415         uint64_t tor;
416         uint64_t tot;
417         uint64_t tpr;
418         uint64_t tpt;
419         uint64_t ptc64;
420         uint64_t ptc127;
421         uint64_t ptc255;
422         uint64_t ptc511;
423         uint64_t ptc1023;
424         uint64_t ptc1522;
425         uint64_t mptc;
426         uint64_t bptc;
427         uint64_t tsctc;
428         uint64_t tsctfc;
429         uint64_t iac;
430         uint64_t icrxptc;
431         uint64_t icrxatc;
432         uint64_t ictxptc;
433         uint64_t ictxatc;
434         uint64_t ictxqec;
435         uint64_t ictxqmtc;
436         uint64_t icrxdmtc;
437         uint64_t icrxoc;
438         uint64_t cbtmpc;
439         uint64_t htdpmc;
440         uint64_t cbrdpc;
441         uint64_t cbrmpc;
442         uint64_t rpthc;
443         uint64_t hgptc;
444         uint64_t htcbdpc;
445         uint64_t hgorc;
446         uint64_t hgotc;
447         uint64_t lenerrs;
448         uint64_t scvpc;
449         uint64_t hrmpc;
450         uint64_t doosync;
451 };
452
453 struct e1000_phy_stats {
454         uint32_t idle_errors;
455         uint32_t receive_errors;
456 };
457
458 struct e1000_host_mng_dhcp_cookie {
459         uint32_t signature;
460         uint8_t status;
461         uint8_t reserved0;
462         uint16_t vlan_id;
463         uint32_t reserved1;
464         uint16_t reserved2;
465         uint8_t reserved3;
466         uint8_t checksum;
467 };
468
469 /* Host Interface "Rev 1" */
470 struct e1000_host_command_header {
471         uint8_t command_id;
472         uint8_t command_length;
473         uint8_t command_options;
474         uint8_t checksum;
475 };
476
477 #define E1000_HI_MAX_DATA_LENGTH     252
478 struct e1000_host_command_info {
479         struct e1000_host_command_header command_header;
480         uint8_t command_data[E1000_HI_MAX_DATA_LENGTH];
481 };
482
483 /* Host Interface "Rev 2" */
484 struct e1000_host_mng_command_header {
485         uint8_t command_id;
486         uint8_t checksum;
487         uint16_t reserved1;
488         uint16_t reserved2;
489         uint16_t command_length;
490 };
491
492 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
493 struct e1000_host_mng_command_info {
494         struct e1000_host_mng_command_header command_header;
495         uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
496 };
497
498 #include "e1000_mac.h"
499 #include "e1000_phy.h"
500 #include "e1000_nvm.h"
501 #include "e1000_manage.h"
502
503 struct e1000_mac_operations {
504         /* Function pointers for the MAC. */
505         int32_t(*init_params) (struct e1000_hw *);
506         int32_t(*id_led_init) (struct e1000_hw *);
507         int32_t(*blink_led) (struct e1000_hw *);
508         int32_t(*check_for_link) (struct e1000_hw *);
509         bool(*check_mng_mode) (struct e1000_hw * hw);
510         int32_t(*cleanup_led) (struct e1000_hw *);
511         void (*clear_hw_cntrs) (struct e1000_hw *);
512         void (*clear_vfta) (struct e1000_hw *);
513          int32_t(*get_bus_info) (struct e1000_hw *);
514         void (*set_lan_id) (struct e1000_hw *);
515          int32_t(*get_link_up_info) (struct e1000_hw *, uint16_t *, uint16_t *);
516          int32_t(*led_on) (struct e1000_hw *);
517          int32_t(*led_off) (struct e1000_hw *);
518         void (*update_mc_addr_list) (struct e1000_hw *, uint8_t *, uint32_t);
519          int32_t(*reset_hw) (struct e1000_hw *);
520          int32_t(*init_hw) (struct e1000_hw *);
521          int32_t(*setup_link) (struct e1000_hw *);
522          int32_t(*setup_physical_interface) (struct e1000_hw *);
523          int32_t(*setup_led) (struct e1000_hw *);
524         void (*write_vfta) (struct e1000_hw *, uint32_t, uint32_t);
525         void (*mta_set) (struct e1000_hw *, uint32_t);
526         void (*config_collision_dist) (struct e1000_hw *);
527         void (*rar_set) (struct e1000_hw *, uint8_t *, uint32_t);
528          int32_t(*read_mac_addr) (struct e1000_hw *);
529          int32_t(*validate_mdi_setting) (struct e1000_hw *);
530          int32_t(*mng_host_if_write) (struct e1000_hw *, uint8_t *, uint16_t,
531                                                                   uint16_t, uint8_t *);
532          int32_t(*mng_write_cmd_header) (struct e1000_hw * hw,
533                                                                          struct e1000_host_mng_command_header *);
534          int32_t(*mng_enable_host_if) (struct e1000_hw *);
535          int32_t(*wait_autoneg) (struct e1000_hw *);
536 };
537
538 struct e1000_phy_operations {
539         int32_t(*init_params) (struct e1000_hw *);
540         int32_t(*acquire) (struct e1000_hw *);
541         int32_t(*check_polarity) (struct e1000_hw *);
542         int32_t(*check_reset_block) (struct e1000_hw *);
543         int32_t(*commit) (struct e1000_hw *);
544 #if 0
545         s32(*force_speed_duplex) (struct e1000_hw *);
546 #endif
547         int32_t(*get_cfg_done) (struct e1000_hw * hw);
548 #if 0
549         s32(*get_cable_length) (struct e1000_hw *);
550 #endif
551         int32_t(*get_info) (struct e1000_hw *);
552         int32_t(*read_reg) (struct e1000_hw *, uint32_t, uint16_t *);
553         void (*release) (struct e1000_hw *);
554          int32_t(*reset) (struct e1000_hw *);
555          int32_t(*set_d0_lplu_state) (struct e1000_hw *, bool);
556          int32_t(*set_d3_lplu_state) (struct e1000_hw *, bool);
557          int32_t(*write_reg) (struct e1000_hw *, uint32_t, uint16_t);
558         void (*power_up) (struct e1000_hw *);
559         void (*power_down) (struct e1000_hw *);
560 };
561
562 struct e1000_nvm_operations {
563         int32_t(*init_params) (struct e1000_hw *);
564         int32_t(*acquire) (struct e1000_hw *);
565         int32_t(*read) (struct e1000_hw *, uint16_t, uint16_t, uint16_t *);
566         void (*release) (struct e1000_hw *);
567         void (*reload) (struct e1000_hw *);
568          int32_t(*update) (struct e1000_hw *);
569          int32_t(*valid_led_default) (struct e1000_hw *, uint16_t *);
570          int32_t(*validate) (struct e1000_hw *);
571          int32_t(*write) (struct e1000_hw *, uint16_t, uint16_t, uint16_t *);
572 };
573
574 struct e1000_mac_info {
575         struct e1000_mac_operations ops;
576         uint8_t addr[6];
577         uint8_t perm_addr[6];
578
579         enum e1000_mac_type type;
580
581         uint32_t collision_delta;
582         uint32_t ledctl_default;
583         uint32_t ledctl_mode1;
584         uint32_t ledctl_mode2;
585         uint32_t mc_filter_type;
586         uint32_t tx_packet_delta;
587         uint32_t txcw;
588
589         uint16_t current_ifs_val;
590         uint16_t ifs_max_val;
591         uint16_t ifs_min_val;
592         uint16_t ifs_ratio;
593         uint16_t ifs_step_size;
594         uint16_t mta_reg_count;
595
596         /* Maximum size of the MTA register table in all supported adapters */
597 #define MAX_MTA_REG 128
598         uint32_t mta_shadow[MAX_MTA_REG];
599         uint16_t rar_entry_count;
600
601         uint8_t forced_speed_duplex;
602
603         bool adaptive_ifs;
604         bool arc_subsystem_valid;
605         bool asf_firmware_present;
606         bool autoneg;
607         bool autoneg_failed;
608         bool get_link_status;
609         bool in_ifs_mode;
610         bool report_tx_early;
611         enum e1000_serdes_link_state serdes_link_state;
612         bool serdes_has_link;
613         bool tx_pkt_filtering;
614 };
615
616 struct e1000_phy_info {
617         struct e1000_phy_operations ops;
618         enum e1000_phy_type type;
619
620         enum e1000_1000t_rx_status local_rx;
621         enum e1000_1000t_rx_status remote_rx;
622         enum e1000_ms_type ms_type;
623         enum e1000_ms_type original_ms_type;
624         enum e1000_rev_polarity cable_polarity;
625         enum e1000_smart_speed smart_speed;
626
627         uint32_t addr;
628         uint32_t id;
629         uint32_t reset_delay_us;        /* in usec */
630         uint32_t revision;
631
632         enum e1000_media_type media_type;
633
634         uint16_t autoneg_advertised;
635         uint16_t autoneg_mask;
636         uint16_t cable_length;
637         uint16_t max_cable_length;
638         uint16_t min_cable_length;
639
640         uint8_t mdix;
641
642         bool disable_polarity_correction;
643         bool is_mdix;
644         bool polarity_correction;
645         bool reset_disable;
646         bool speed_downgraded;
647         bool autoneg_wait_to_complete;
648 };
649
650 struct e1000_nvm_info {
651         struct e1000_nvm_operations ops;
652         enum e1000_nvm_type type;
653         enum e1000_nvm_override override;
654
655         uint32_t flash_bank_size;
656         uint32_t flash_base_addr;
657
658         uint16_t word_size;
659         uint16_t delay_usec;
660         uint16_t address_bits;
661         uint16_t opcode_bits;
662         uint16_t page_size;
663 };
664
665 struct e1000_bus_info {
666         enum e1000_bus_type type;
667         enum e1000_bus_speed speed;
668         enum e1000_bus_width width;
669
670         uint16_t func;
671         uint16_t pci_cmd_word;
672 };
673
674 struct e1000_fc_info {
675         uint32_t high_water;            /* Flow control high-water mark */
676         uint32_t low_water;                     /* Flow control low-water mark */
677         uint16_t pause_time;            /* Flow control pause timer */
678         bool send_xon;                          /* Flow control send XON */
679         bool strict_ieee;                       /* Strict IEEE mode */
680         enum e1000_fc_mode current_mode;        /* FC mode in effect */
681         enum e1000_fc_mode requested_mode;      /* FC mode requested by caller */
682 };
683
684 struct e1000_dev_spec_82541 {
685         enum e1000_dsp_config dsp_config;
686         enum e1000_ffe_config ffe_config;
687         uint16_t spd_default;
688         bool phy_init_script;
689 };
690
691 struct e1000_dev_spec_82542 {
692         bool dma_fairness;
693 };
694
695 struct e1000_dev_spec_82543 {
696         uint32_t tbi_compatibility;
697         bool dma_fairness;
698         bool init_phy_disabled;
699 };
700
701 struct e1000_hw {
702         void *back;
703
704         uint8_t *hw_addr;
705         uint8_t *flash_address;
706         unsigned long io_base;
707
708         struct e1000_mac_info mac;
709         struct e1000_fc_info fc;
710         struct e1000_phy_info phy;
711         struct e1000_nvm_info nvm;
712         struct e1000_bus_info bus;
713         struct e1000_host_mng_dhcp_cookie mng_cookie;
714
715         union {
716                 struct e1000_dev_spec_82541 _82541;
717                 struct e1000_dev_spec_82542 _82542;
718                 struct e1000_dev_spec_82543 _82543;
719         } dev_spec;
720
721         uint16_t device_id;
722         uint16_t subsystem_vendor_id;
723         uint16_t subsystem_device_id;
724         uint16_t vendor_id;
725
726         uint8_t revision_id;
727 };
728
729 #include <vfs.h>
730 #include <kfs.h>
731 #include <slab.h>
732 #include <kmalloc.h>
733 #include <kref.h>
734 #include <string.h>
735 #include <stdio.h>
736 #include <assert.h>
737 #include <error.h>
738 #include <cpio.h>
739 #include <pmap.h>
740 #include <smp.h>
741 #include <ip.h>
742
743 /* These functions must be implemented by drivers */
744 void e1000_pci_clear_mwi(struct e1000_hw *hw);
745 void e1000_pci_set_mwi(struct e1000_hw *hw);
746 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *hw,
747                                                                 uint32_t reg, uint16_t * value);
748 void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
749 void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
750
751 #endif