gpx e1000 driver.
[akaros.git] / kern / drivers / net / e1000 / e1000_hw.h
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 FILE_LICENCE ( GPL2_OR_LATER );
30
31 #ifndef _E1000_HW_H_
32 #define _E1000_HW_H_
33
34 #include "e1000_osdep.h"
35 #include "e1000_regs.h"
36 #include "e1000_defines.h"
37
38 struct e1000_hw;
39
40 #define E1000_DEV_ID_82542                    0x1000
41 #define E1000_DEV_ID_82543GC_FIBER            0x1001
42 #define E1000_DEV_ID_82543GC_COPPER           0x1004
43 #define E1000_DEV_ID_82544EI_COPPER           0x1008
44 #define E1000_DEV_ID_82544EI_FIBER            0x1009
45 #define E1000_DEV_ID_82544GC_COPPER           0x100C
46 #define E1000_DEV_ID_82544GC_LOM              0x100D
47 #define E1000_DEV_ID_82540EM                  0x100E
48 #define E1000_DEV_ID_82540EM_LOM              0x1015
49 #define E1000_DEV_ID_82540EP_LOM              0x1016
50 #define E1000_DEV_ID_82540EP                  0x1017
51 #define E1000_DEV_ID_82540EP_LP               0x101E
52 #define E1000_DEV_ID_82545EM_COPPER           0x100F
53 #define E1000_DEV_ID_82545EM_FIBER            0x1011
54 #define E1000_DEV_ID_82545GM_COPPER           0x1026
55 #define E1000_DEV_ID_82545GM_FIBER            0x1027
56 #define E1000_DEV_ID_82545GM_SERDES           0x1028
57 #define E1000_DEV_ID_82546EB_COPPER           0x1010
58 #define E1000_DEV_ID_82546EB_FIBER            0x1012
59 #define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
60 #define E1000_DEV_ID_82546GB_COPPER           0x1079
61 #define E1000_DEV_ID_82546GB_FIBER            0x107A
62 #define E1000_DEV_ID_82546GB_SERDES           0x107B
63 #define E1000_DEV_ID_82546GB_PCIE             0x108A
64 #define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
65 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
66 #define E1000_DEV_ID_82541EI                  0x1013
67 #define E1000_DEV_ID_82541EI_MOBILE           0x1018
68 #define E1000_DEV_ID_82541ER_LOM              0x1014
69 #define E1000_DEV_ID_82541ER                  0x1078
70 #define E1000_DEV_ID_82541GI                  0x1076
71 #define E1000_DEV_ID_82541GI_LF               0x107C
72 #define E1000_DEV_ID_82541GI_MOBILE           0x1077
73 #define E1000_DEV_ID_82547EI                  0x1019
74 #define E1000_DEV_ID_82547EI_MOBILE           0x101A
75 #define E1000_DEV_ID_82547GI                  0x1075
76 #define E1000_REVISION_0 0
77 #define E1000_REVISION_1 1
78 #define E1000_REVISION_2 2
79 #define E1000_REVISION_3 3
80 #define E1000_REVISION_4 4
81
82 #define E1000_FUNC_0     0
83 #define E1000_FUNC_1     1
84
85 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
86 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
87
88 enum e1000_mac_type {
89         e1000_undefined = 0,
90         e1000_82542,
91         e1000_82543,
92         e1000_82544,
93         e1000_82540,
94         e1000_82545,
95         e1000_82545_rev_3,
96         e1000_82546,
97         e1000_82546_rev_3,
98         e1000_82541,
99         e1000_82541_rev_2,
100         e1000_82547,
101         e1000_82547_rev_2,
102         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
103 };
104
105 enum e1000_media_type {
106         e1000_media_type_unknown = 0,
107         e1000_media_type_copper = 1,
108         e1000_media_type_fiber = 2,
109         e1000_media_type_internal_serdes = 3,
110         e1000_num_media_types
111 };
112
113 enum e1000_nvm_type {
114         e1000_nvm_unknown = 0,
115         e1000_nvm_none,
116         e1000_nvm_eeprom_spi,
117         e1000_nvm_eeprom_microwire,
118         e1000_nvm_flash_hw,
119         e1000_nvm_flash_sw
120 };
121
122 enum e1000_nvm_override {
123         e1000_nvm_override_none = 0,
124         e1000_nvm_override_spi_small,
125         e1000_nvm_override_spi_large,
126         e1000_nvm_override_microwire_small,
127         e1000_nvm_override_microwire_large
128 };
129
130 enum e1000_phy_type {
131         e1000_phy_unknown = 0,
132         e1000_phy_none,
133         e1000_phy_m88,
134         e1000_phy_igp,
135         e1000_phy_igp_2,
136         e1000_phy_gg82563,
137         e1000_phy_igp_3,
138         e1000_phy_ife,
139 };
140
141 enum e1000_bus_type {
142         e1000_bus_type_unknown = 0,
143         e1000_bus_type_pci,
144         e1000_bus_type_pcix,
145         e1000_bus_type_pci_express,
146         e1000_bus_type_reserved
147 };
148
149 enum e1000_bus_speed {
150         e1000_bus_speed_unknown = 0,
151         e1000_bus_speed_33,
152         e1000_bus_speed_66,
153         e1000_bus_speed_100,
154         e1000_bus_speed_120,
155         e1000_bus_speed_133,
156         e1000_bus_speed_2500,
157         e1000_bus_speed_5000,
158         e1000_bus_speed_reserved
159 };
160
161 enum e1000_bus_width {
162         e1000_bus_width_unknown = 0,
163         e1000_bus_width_pcie_x1,
164         e1000_bus_width_pcie_x2,
165         e1000_bus_width_pcie_x4 = 4,
166         e1000_bus_width_pcie_x8 = 8,
167         e1000_bus_width_32,
168         e1000_bus_width_64,
169         e1000_bus_width_reserved
170 };
171
172 enum e1000_1000t_rx_status {
173         e1000_1000t_rx_status_not_ok = 0,
174         e1000_1000t_rx_status_ok,
175         e1000_1000t_rx_status_undefined = 0xFF
176 };
177
178 enum e1000_rev_polarity {
179         e1000_rev_polarity_normal = 0,
180         e1000_rev_polarity_reversed,
181         e1000_rev_polarity_undefined = 0xFF
182 };
183
184 enum e1000_fc_mode {
185         e1000_fc_none = 0,
186         e1000_fc_rx_pause,
187         e1000_fc_tx_pause,
188         e1000_fc_full,
189         e1000_fc_default = 0xFF
190 };
191
192 enum e1000_ffe_config {
193         e1000_ffe_config_enabled = 0,
194         e1000_ffe_config_active,
195         e1000_ffe_config_blocked
196 };
197
198 enum e1000_dsp_config {
199         e1000_dsp_config_disabled = 0,
200         e1000_dsp_config_enabled,
201         e1000_dsp_config_activated,
202         e1000_dsp_config_undefined = 0xFF
203 };
204
205 enum e1000_ms_type {
206         e1000_ms_hw_default = 0,
207         e1000_ms_force_master,
208         e1000_ms_force_slave,
209         e1000_ms_auto
210 };
211
212 enum e1000_smart_speed {
213         e1000_smart_speed_default = 0,
214         e1000_smart_speed_on,
215         e1000_smart_speed_off
216 };
217
218 enum e1000_serdes_link_state {
219         e1000_serdes_link_down = 0,
220         e1000_serdes_link_autoneg_progress,
221         e1000_serdes_link_autoneg_complete,
222         e1000_serdes_link_forced_up
223 };
224
225 /* Receive Descriptor */
226 struct e1000_rx_desc {
227         __le64 buffer_addr; /* Address of the descriptor's data buffer */
228         __le16 length;      /* Length of data DMAed into data buffer */
229         __le16 csum;        /* Packet checksum */
230         u8  status;         /* Descriptor status */
231         u8  errors;         /* Descriptor Errors */
232         __le16 special;
233 };
234
235 /* Receive Descriptor - Extended */
236 union e1000_rx_desc_extended {
237         struct {
238                 __le64 buffer_addr;
239                 __le64 reserved;
240         } read;
241         struct {
242                 struct {
243                         __le32 mrq;           /* Multiple Rx Queues */
244                         union {
245                                 __le32 rss;         /* RSS Hash */
246                                 struct {
247                                         __le16 ip_id;  /* IP id */
248                                         __le16 csum;   /* Packet Checksum */
249                                 } csum_ip;
250                         } hi_dword;
251                 } lower;
252                 struct {
253                         __le32 status_error;  /* ext status/error */
254                         __le16 length;
255                         __le16 vlan;          /* VLAN tag */
256                 } upper;
257         } wb;  /* writeback */
258 };
259
260 #define MAX_PS_BUFFERS 4
261 /* Receive Descriptor - Packet Split */
262 union e1000_rx_desc_packet_split {
263         struct {
264                 /* one buffer for protocol header(s), three data buffers */
265                 __le64 buffer_addr[MAX_PS_BUFFERS];
266         } read;
267         struct {
268                 struct {
269                         __le32 mrq;           /* Multiple Rx Queues */
270                         union {
271                                 __le32 rss;           /* RSS Hash */
272                                 struct {
273                                         __le16 ip_id;    /* IP id */
274                                         __le16 csum;     /* Packet Checksum */
275                                 } csum_ip;
276                         } hi_dword;
277                 } lower;
278                 struct {
279                         __le32 status_error;  /* ext status/error */
280                         __le16 length0;       /* length of buffer 0 */
281                         __le16 vlan;          /* VLAN tag */
282                 } middle;
283                 struct {
284                         __le16 header_status;
285                         __le16 length[3];     /* length of buffers 1-3 */
286                 } upper;
287                 __le64 reserved;
288         } wb; /* writeback */
289 };
290
291 /* Transmit Descriptor */
292 struct e1000_tx_desc {
293         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
294         union {
295                 __le32 data;
296                 struct {
297                         __le16 length;    /* Data buffer length */
298                         u8 cso;           /* Checksum offset */
299                         u8 cmd;           /* Descriptor control */
300                 } flags;
301         } lower;
302         union {
303                 __le32 data;
304                 struct {
305                         u8 status;        /* Descriptor status */
306                         u8 css;           /* Checksum start */
307                         __le16 special;
308                 } fields;
309         } upper;
310 };
311
312 /* Offload Context Descriptor */
313 struct e1000_context_desc {
314         union {
315                 __le32 ip_config;
316                 struct {
317                         u8 ipcss;         /* IP checksum start */
318                         u8 ipcso;         /* IP checksum offset */
319                         __le16 ipcse;     /* IP checksum end */
320                 } ip_fields;
321         } lower_setup;
322         union {
323                 __le32 tcp_config;
324                 struct {
325                         u8 tucss;         /* TCP checksum start */
326                         u8 tucso;         /* TCP checksum offset */
327                         __le16 tucse;     /* TCP checksum end */
328                 } tcp_fields;
329         } upper_setup;
330         __le32 cmd_and_length;
331         union {
332                 __le32 data;
333                 struct {
334                         u8 status;        /* Descriptor status */
335                         u8 hdr_len;       /* Header length */
336                         __le16 mss;       /* Maximum segment size */
337                 } fields;
338         } tcp_seg_setup;
339 };
340
341 /* Offload data descriptor */
342 struct e1000_data_desc {
343         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
344         union {
345                 __le32 data;
346                 struct {
347                         __le16 length;    /* Data buffer length */
348                         u8 typ_len_ext;
349                         u8 cmd;
350                 } flags;
351         } lower;
352         union {
353                 __le32 data;
354                 struct {
355                         u8 status;        /* Descriptor status */
356                         u8 popts;         /* Packet Options */
357                         __le16 special;
358                 } fields;
359         } upper;
360 };
361
362 /* Statistics counters collected by the MAC */
363 struct e1000_hw_stats {
364         u64 crcerrs;
365         u64 algnerrc;
366         u64 symerrs;
367         u64 rxerrc;
368         u64 mpc;
369         u64 scc;
370         u64 ecol;
371         u64 mcc;
372         u64 latecol;
373         u64 colc;
374         u64 dc;
375         u64 tncrs;
376         u64 sec;
377         u64 cexterr;
378         u64 rlec;
379         u64 xonrxc;
380         u64 xontxc;
381         u64 xoffrxc;
382         u64 xofftxc;
383         u64 fcruc;
384         u64 prc64;
385         u64 prc127;
386         u64 prc255;
387         u64 prc511;
388         u64 prc1023;
389         u64 prc1522;
390         u64 gprc;
391         u64 bprc;
392         u64 mprc;
393         u64 gptc;
394         u64 gorc;
395         u64 gotc;
396         u64 rnbc;
397         u64 ruc;
398         u64 rfc;
399         u64 roc;
400         u64 rjc;
401         u64 mgprc;
402         u64 mgpdc;
403         u64 mgptc;
404         u64 tor;
405         u64 tot;
406         u64 tpr;
407         u64 tpt;
408         u64 ptc64;
409         u64 ptc127;
410         u64 ptc255;
411         u64 ptc511;
412         u64 ptc1023;
413         u64 ptc1522;
414         u64 mptc;
415         u64 bptc;
416         u64 tsctc;
417         u64 tsctfc;
418         u64 iac;
419         u64 icrxptc;
420         u64 icrxatc;
421         u64 ictxptc;
422         u64 ictxatc;
423         u64 ictxqec;
424         u64 ictxqmtc;
425         u64 icrxdmtc;
426         u64 icrxoc;
427         u64 cbtmpc;
428         u64 htdpmc;
429         u64 cbrdpc;
430         u64 cbrmpc;
431         u64 rpthc;
432         u64 hgptc;
433         u64 htcbdpc;
434         u64 hgorc;
435         u64 hgotc;
436         u64 lenerrs;
437         u64 scvpc;
438         u64 hrmpc;
439         u64 doosync;
440 };
441
442
443 struct e1000_phy_stats {
444         u32 idle_errors;
445         u32 receive_errors;
446 };
447
448 struct e1000_host_mng_dhcp_cookie {
449         u32 signature;
450         u8  status;
451         u8  reserved0;
452         u16 vlan_id;
453         u32 reserved1;
454         u16 reserved2;
455         u8  reserved3;
456         u8  checksum;
457 };
458
459 /* Host Interface "Rev 1" */
460 struct e1000_host_command_header {
461         u8 command_id;
462         u8 command_length;
463         u8 command_options;
464         u8 checksum;
465 };
466
467 #define E1000_HI_MAX_DATA_LENGTH     252
468 struct e1000_host_command_info {
469         struct e1000_host_command_header command_header;
470         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
471 };
472
473 /* Host Interface "Rev 2" */
474 struct e1000_host_mng_command_header {
475         u8  command_id;
476         u8  checksum;
477         u16 reserved1;
478         u16 reserved2;
479         u16 command_length;
480 };
481
482 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
483 struct e1000_host_mng_command_info {
484         struct e1000_host_mng_command_header command_header;
485         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
486 };
487
488 #include "e1000_mac.h"
489 #include "e1000_phy.h"
490 #include "e1000_nvm.h"
491 #include "e1000_manage.h"
492
493 struct e1000_mac_operations {
494         /* Function pointers for the MAC. */
495         s32  (*init_params)(struct e1000_hw *);
496         s32  (*id_led_init)(struct e1000_hw *);
497         s32  (*blink_led)(struct e1000_hw *);
498         s32  (*check_for_link)(struct e1000_hw *);
499         bool (*check_mng_mode)(struct e1000_hw *hw);
500         s32  (*cleanup_led)(struct e1000_hw *);
501         void (*clear_hw_cntrs)(struct e1000_hw *);
502         void (*clear_vfta)(struct e1000_hw *);
503         s32  (*get_bus_info)(struct e1000_hw *);
504         void (*set_lan_id)(struct e1000_hw *);
505         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
506         s32  (*led_on)(struct e1000_hw *);
507         s32  (*led_off)(struct e1000_hw *);
508         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
509         s32  (*reset_hw)(struct e1000_hw *);
510         s32  (*init_hw)(struct e1000_hw *);
511         s32  (*setup_link)(struct e1000_hw *);
512         s32  (*setup_physical_interface)(struct e1000_hw *);
513         s32  (*setup_led)(struct e1000_hw *);
514         void (*write_vfta)(struct e1000_hw *, u32, u32);
515         void (*mta_set)(struct e1000_hw *, u32);
516         void (*config_collision_dist)(struct e1000_hw *);
517         void (*rar_set)(struct e1000_hw *, u8*, u32);
518         s32  (*read_mac_addr)(struct e1000_hw *);
519         s32  (*validate_mdi_setting)(struct e1000_hw *);
520         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
521         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
522                       struct e1000_host_mng_command_header*);
523         s32  (*mng_enable_host_if)(struct e1000_hw *);
524         s32  (*wait_autoneg)(struct e1000_hw *);
525 };
526
527 struct e1000_phy_operations {
528         s32  (*init_params)(struct e1000_hw *);
529         s32  (*acquire)(struct e1000_hw *);
530         s32  (*check_polarity)(struct e1000_hw *);
531         s32  (*check_reset_block)(struct e1000_hw *);
532         s32  (*commit)(struct e1000_hw *);
533 #if 0
534         s32  (*force_speed_duplex)(struct e1000_hw *);
535 #endif
536         s32  (*get_cfg_done)(struct e1000_hw *hw);
537 #if 0
538         s32  (*get_cable_length)(struct e1000_hw *);
539 #endif
540         s32  (*get_info)(struct e1000_hw *);
541         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
542         void (*release)(struct e1000_hw *);
543         s32  (*reset)(struct e1000_hw *);
544         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
545         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
546         s32  (*write_reg)(struct e1000_hw *, u32, u16);
547         void (*power_up)(struct e1000_hw *);
548         void (*power_down)(struct e1000_hw *);
549 };
550
551 struct e1000_nvm_operations {
552         s32  (*init_params)(struct e1000_hw *);
553         s32  (*acquire)(struct e1000_hw *);
554         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
555         void (*release)(struct e1000_hw *);
556         void (*reload)(struct e1000_hw *);
557         s32  (*update)(struct e1000_hw *);
558         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
559         s32  (*validate)(struct e1000_hw *);
560         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
561 };
562
563 struct e1000_mac_info {
564         struct e1000_mac_operations ops;
565         u8 addr[6];
566         u8 perm_addr[6];
567
568         enum e1000_mac_type type;
569
570         u32 collision_delta;
571         u32 ledctl_default;
572         u32 ledctl_mode1;
573         u32 ledctl_mode2;
574         u32 mc_filter_type;
575         u32 tx_packet_delta;
576         u32 txcw;
577
578         u16 current_ifs_val;
579         u16 ifs_max_val;
580         u16 ifs_min_val;
581         u16 ifs_ratio;
582         u16 ifs_step_size;
583         u16 mta_reg_count;
584
585         /* Maximum size of the MTA register table in all supported adapters */
586         #define MAX_MTA_REG 128
587         u32 mta_shadow[MAX_MTA_REG];
588         u16 rar_entry_count;
589
590         u8  forced_speed_duplex;
591
592         bool adaptive_ifs;
593         bool arc_subsystem_valid;
594         bool asf_firmware_present;
595         bool autoneg;
596         bool autoneg_failed;
597         bool get_link_status;
598         bool in_ifs_mode;
599         bool report_tx_early;
600         enum e1000_serdes_link_state serdes_link_state;
601         bool serdes_has_link;
602         bool tx_pkt_filtering;
603 };
604
605 struct e1000_phy_info {
606         struct e1000_phy_operations ops;
607         enum e1000_phy_type type;
608
609         enum e1000_1000t_rx_status local_rx;
610         enum e1000_1000t_rx_status remote_rx;
611         enum e1000_ms_type ms_type;
612         enum e1000_ms_type original_ms_type;
613         enum e1000_rev_polarity cable_polarity;
614         enum e1000_smart_speed smart_speed;
615
616         u32 addr;
617         u32 id;
618         u32 reset_delay_us; /* in usec */
619         u32 revision;
620
621         enum e1000_media_type media_type;
622
623         u16 autoneg_advertised;
624         u16 autoneg_mask;
625         u16 cable_length;
626         u16 max_cable_length;
627         u16 min_cable_length;
628
629         u8 mdix;
630
631         bool disable_polarity_correction;
632         bool is_mdix;
633         bool polarity_correction;
634         bool reset_disable;
635         bool speed_downgraded;
636         bool autoneg_wait_to_complete;
637 };
638
639 struct e1000_nvm_info {
640         struct e1000_nvm_operations ops;
641         enum e1000_nvm_type type;
642         enum e1000_nvm_override override;
643
644         u32 flash_bank_size;
645         u32 flash_base_addr;
646
647         u16 word_size;
648         u16 delay_usec;
649         u16 address_bits;
650         u16 opcode_bits;
651         u16 page_size;
652 };
653
654 struct e1000_bus_info {
655         enum e1000_bus_type type;
656         enum e1000_bus_speed speed;
657         enum e1000_bus_width width;
658
659         u16 func;
660         u16 pci_cmd_word;
661 };
662
663 struct e1000_fc_info {
664         u32 high_water;          /* Flow control high-water mark */
665         u32 low_water;           /* Flow control low-water mark */
666         u16 pause_time;          /* Flow control pause timer */
667         bool send_xon;           /* Flow control send XON */
668         bool strict_ieee;        /* Strict IEEE mode */
669         enum e1000_fc_mode current_mode; /* FC mode in effect */
670         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
671 };
672
673 struct e1000_dev_spec_82541 {
674         enum e1000_dsp_config dsp_config;
675         enum e1000_ffe_config ffe_config;
676         u16 spd_default;
677         bool phy_init_script;
678 };
679
680 struct e1000_dev_spec_82542 {
681         bool dma_fairness;
682 };
683
684 struct e1000_dev_spec_82543 {
685         u32  tbi_compatibility;
686         bool dma_fairness;
687         bool init_phy_disabled;
688 };
689
690 struct e1000_hw {
691         void *back;
692
693         u8 __iomem *hw_addr;
694         u8 __iomem *flash_address;
695         unsigned long io_base;
696
697         struct e1000_mac_info  mac;
698         struct e1000_fc_info   fc;
699         struct e1000_phy_info  phy;
700         struct e1000_nvm_info  nvm;
701         struct e1000_bus_info  bus;
702         struct e1000_host_mng_dhcp_cookie mng_cookie;
703
704         union {
705                 struct e1000_dev_spec_82541     _82541;
706                 struct e1000_dev_spec_82542     _82542;
707                 struct e1000_dev_spec_82543     _82543;
708         } dev_spec;
709
710         u16 device_id;
711         u16 subsystem_vendor_id;
712         u16 subsystem_device_id;
713         u16 vendor_id;
714
715         u8  revision_id;
716 };
717
718 #include "e1000_82541.h"
719 #include "e1000_82543.h"
720
721 /* These functions must be implemented by drivers */
722 void e1000_pci_clear_mwi(struct e1000_hw *hw);
723 void e1000_pci_set_mwi(struct e1000_hw *hw);
724 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
725 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
726 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
727
728 #endif