BNX2X: usability fixups
[akaros.git] / kern / drivers / net / e1000 / e1000_82541.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 FILE_LICENCE(GPL2_OR_LATER);
30
31 /*
32  * 82541EI Gigabit Ethernet Controller
33  * 82541ER Gigabit Ethernet Controller
34  * 82541GI Gigabit Ethernet Controller
35  * 82541PI Gigabit Ethernet Controller
36  * 82547EI Gigabit Ethernet Controller
37  * 82547GI Gigabit Ethernet Controller
38  */
39
40 #include "e1000_api.h"
41
42 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw);
43 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw);
44 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw);
45 static s32 e1000_reset_hw_82541(struct e1000_hw *hw);
46 static s32 e1000_init_hw_82541(struct e1000_hw *hw);
47 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 * speed,
48                                                                                 u16 * duplex);
49 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);
50 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);
51 static s32 e1000_check_for_link_82541(struct e1000_hw *hw);
52 #if 0
53 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
54 #endif
55 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active);
56 static s32 e1000_setup_led_82541(struct e1000_hw *hw);
57 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
58 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
59 #if 0
60 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
61                                                                                                         bool link_up);
62 #endif
63 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
64 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
65
66 #if 0
67 static const u16 e1000_igp_cable_length_table[] =
68         { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
69         5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
70         25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
71         40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
72         60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
73         90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
74         100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
75                 110,
76         110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120,
77                 120
78 };
79
80 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
81                 (sizeof(e1000_igp_cable_length_table) / \
82                  sizeof(e1000_igp_cable_length_table[0]))
83 #endif
84 /**
85  *  e1000_init_phy_params_82541 - Init PHY func ptrs.
86  *  @hw: pointer to the HW structure
87  **/
88 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
89 {
90         struct e1000_phy_info *phy = &hw->phy;
91         s32 ret_val = E1000_SUCCESS;
92
93         DEBUGFUNC("e1000_init_phy_params_82541");
94
95         phy->addr = 1;
96         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
97         phy->reset_delay_us = 10000;
98         phy->type = e1000_phy_igp;
99
100         /* Function Pointers */
101         phy->ops.check_polarity = e1000_check_polarity_igp;
102 #if 0
103         phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
104 #endif
105 #if 0
106         phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
107 #endif
108         phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
109         phy->ops.get_info = e1000_get_phy_info_igp;
110         phy->ops.read_reg = e1000_read_phy_reg_igp;
111         phy->ops.reset = e1000_phy_hw_reset_82541;
112         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
113         phy->ops.write_reg = e1000_write_phy_reg_igp;
114         phy->ops.power_up = e1000_power_up_phy_copper;
115         phy->ops.power_down = e1000_power_down_phy_copper_82541;
116
117         ret_val = e1000_get_phy_id(hw);
118         if (ret_val)
119                 goto out;
120
121         /* Verify phy id */
122         if (phy->id != IGP01E1000_I_PHY_ID) {
123                 ret_val = -E1000_ERR_PHY;
124                 goto out;
125         }
126
127 out:
128         return ret_val;
129 }
130
131 /**
132  *  e1000_init_nvm_params_82541 - Init NVM func ptrs.
133  *  @hw: pointer to the HW structure
134  **/
135 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
136 {
137         struct e1000_nvm_info *nvm = &hw->nvm;
138         s32 ret_val = E1000_SUCCESS;
139         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
140         u16 size;
141
142         DEBUGFUNC("e1000_init_nvm_params_82541");
143
144         switch (nvm->override) {
145                 case e1000_nvm_override_spi_large:
146                         nvm->type = e1000_nvm_eeprom_spi;
147                         eecd |= E1000_EECD_ADDR_BITS;
148                         break;
149                 case e1000_nvm_override_spi_small:
150                         nvm->type = e1000_nvm_eeprom_spi;
151                         eecd &= ~E1000_EECD_ADDR_BITS;
152                         break;
153                 case e1000_nvm_override_microwire_large:
154                         nvm->type = e1000_nvm_eeprom_microwire;
155                         eecd |= E1000_EECD_SIZE;
156                         break;
157                 case e1000_nvm_override_microwire_small:
158                         nvm->type = e1000_nvm_eeprom_microwire;
159                         eecd &= ~E1000_EECD_SIZE;
160                         break;
161                 default:
162                         nvm->type = eecd & E1000_EECD_TYPE
163                                 ? e1000_nvm_eeprom_spi : e1000_nvm_eeprom_microwire;
164                         break;
165         }
166
167         if (nvm->type == e1000_nvm_eeprom_spi) {
168                 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
169                         ? 16 : 8;
170                 nvm->delay_usec = 1;
171                 nvm->opcode_bits = 8;
172                 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS)
173                         ? 32 : 8;
174
175                 /* Function Pointers */
176                 nvm->ops.acquire = e1000_acquire_nvm_generic;
177                 nvm->ops.read = e1000_read_nvm_spi;
178                 nvm->ops.release = e1000_release_nvm_generic;
179                 nvm->ops.update = e1000_update_nvm_checksum_generic;
180                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
181                 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
182                 nvm->ops.write = e1000_write_nvm_spi;
183
184                 /*
185                  * nvm->word_size must be discovered after the pointers
186                  * are set so we can verify the size from the nvm image
187                  * itself.  Temporarily set it to a dummy value so the
188                  * read will work.
189                  */
190                 nvm->word_size = 64;
191                 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
192                 if (ret_val)
193                         goto out;
194                 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
195                 /*
196                  * if size != 0, it can be added to a constant and become
197                  * the left-shift value to set the word_size.  Otherwise,
198                  * word_size stays at 64.
199                  */
200                 if (size) {
201                         size += NVM_WORD_SIZE_BASE_SHIFT_82541;
202                         nvm->word_size = 1 << size;
203                 }
204         } else {
205                 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
206                         ? 8 : 6;
207                 nvm->delay_usec = 50;
208                 nvm->opcode_bits = 3;
209                 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS)
210                         ? 256 : 64;
211
212                 /* Function Pointers */
213                 nvm->ops.acquire = e1000_acquire_nvm_generic;
214                 nvm->ops.read = e1000_read_nvm_microwire;
215                 nvm->ops.release = e1000_release_nvm_generic;
216                 nvm->ops.update = e1000_update_nvm_checksum_generic;
217                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
218                 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
219                 nvm->ops.write = e1000_write_nvm_microwire;
220         }
221
222 out:
223         return ret_val;
224 }
225
226 /**
227  *  e1000_init_mac_params_82541 - Init MAC func ptrs.
228  *  @hw: pointer to the HW structure
229  **/
230 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
231 {
232         struct e1000_mac_info *mac = &hw->mac;
233
234         DEBUGFUNC("e1000_init_mac_params_82541");
235
236         /* Set media type */
237         hw->phy.media_type = e1000_media_type_copper;
238         /* Set mta register count */
239         mac->mta_reg_count = 128;
240         /* Set rar entry count */
241         mac->rar_entry_count = E1000_RAR_ENTRIES;
242         /* Set if part includes ASF firmware */
243         mac->asf_firmware_present = true;
244
245         /* Function Pointers */
246
247         /* bus type/speed/width */
248         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
249         /* function id */
250         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
251         /* reset */
252         mac->ops.reset_hw = e1000_reset_hw_82541;
253         /* hw initialization */
254         mac->ops.init_hw = e1000_init_hw_82541;
255         /* link setup */
256         mac->ops.setup_link = e1000_setup_link_generic;
257         /* physical interface link setup */
258         mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
259         /* check for link */
260         mac->ops.check_for_link = e1000_check_for_link_82541;
261         /* link info */
262         mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
263         /* multicast address update */
264         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
265         /* writing VFTA */
266         mac->ops.write_vfta = e1000_write_vfta_generic;
267         /* clearing VFTA */
268         mac->ops.clear_vfta = e1000_clear_vfta_generic;
269         /* setting MTA */
270         mac->ops.mta_set = e1000_mta_set_generic;
271         /* ID LED init */
272         mac->ops.id_led_init = e1000_id_led_init_generic;
273         /* setup LED */
274         mac->ops.setup_led = e1000_setup_led_82541;
275         /* cleanup LED */
276         mac->ops.cleanup_led = e1000_cleanup_led_82541;
277         /* turn on/off LED */
278         mac->ops.led_on = e1000_led_on_generic;
279         mac->ops.led_off = e1000_led_off_generic;
280         /* clear hardware counters */
281         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
282
283         return E1000_SUCCESS;
284 }
285
286 /**
287  *  e1000_init_function_pointers_82541 - Init func ptrs.
288  *  @hw: pointer to the HW structure
289  *
290  *  Called to initialize all function pointers and parameters.
291  **/
292 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
293 {
294         DEBUGFUNC("e1000_init_function_pointers_82541");
295
296         hw->mac.ops.init_params = e1000_init_mac_params_82541;
297         hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
298         hw->phy.ops.init_params = e1000_init_phy_params_82541;
299 }
300
301 /**
302  *  e1000_reset_hw_82541 - Reset hardware
303  *  @hw: pointer to the HW structure
304  *
305  *  This resets the hardware into a known state.
306  **/
307 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
308 {
309         u32 ledctl, ctrl, icr, manc;
310
311         DEBUGFUNC("e1000_reset_hw_82541");
312
313         DEBUGOUT("Masking off all interrupts\n");
314         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
315
316         E1000_WRITE_REG(hw, E1000_RCTL, 0);
317         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
318         E1000_WRITE_FLUSH(hw);
319
320         /*
321          * Delay to allow any outstanding PCI transactions to complete
322          * before resetting the device.
323          */
324         msec_delay(10);
325
326         ctrl = E1000_READ_REG(hw, E1000_CTRL);
327
328         /* Must reset the Phy before resetting the MAC */
329         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
330                 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
331                 msec_delay(5);
332         }
333
334         DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
335         switch (hw->mac.type) {
336                 case e1000_82541:
337                 case e1000_82541_rev_2:
338                         /*
339                          * These controllers can't ack the 64-bit write when
340                          * issuing the reset, so we use IO-mapping as a
341                          * workaround to issue the reset.
342                          */
343                         E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
344                         break;
345                 default:
346                         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
347                         break;
348         }
349
350         /* Wait for NVM reload */
351         msec_delay(20);
352
353         /* Disable HW ARPs on ASF enabled adapters */
354         manc = E1000_READ_REG(hw, E1000_MANC);
355         manc &= ~E1000_MANC_ARP_EN;
356         E1000_WRITE_REG(hw, E1000_MANC, manc);
357
358         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
359                 e1000_phy_init_script_82541(hw);
360
361                 /* Configure activity LED after Phy reset */
362                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
363                 ledctl &= IGP_ACTIVITY_LED_MASK;
364                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
365                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
366         }
367
368         /* Once again, mask the interrupts */
369         DEBUGOUT("Masking off all interrupts\n");
370         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
371
372         /* Clear any pending interrupt events. */
373         icr = E1000_READ_REG(hw, E1000_ICR);
374
375         return E1000_SUCCESS;
376 }
377
378 /**
379  *  e1000_init_hw_82541 - Initialize hardware
380  *  @hw: pointer to the HW structure
381  *
382  *  This inits the hardware readying it for operation.
383  **/
384 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
385 {
386         struct e1000_mac_info *mac = &hw->mac;
387         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
388         u32 i, txdctl;
389         s32 ret_val;
390
391         DEBUGFUNC("e1000_init_hw_82541");
392
393         /* Initialize identification LED */
394         ret_val = mac->ops.id_led_init(hw);
395         if (ret_val) {
396                 DEBUGOUT("Error initializing identification LED\n");
397                 /* This is not fatal and we should not stop init due to this */
398         }
399
400         /* Storing the Speed Power Down  value for later use */
401         ret_val = hw->phy.ops.read_reg(hw,
402                                                                    IGP01E1000_GMII_FIFO,
403                                                                    &dev_spec->spd_default);
404         if (ret_val)
405                 goto out;
406
407         /* Disabling VLAN filtering */
408         DEBUGOUT("Initializing the IEEE VLAN\n");
409         mac->ops.clear_vfta(hw);
410
411         /* Setup the receive address. */
412         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
413
414         /* Zero out the Multicast HASH table */
415         DEBUGOUT("Zeroing the MTA\n");
416         for (i = 0; i < mac->mta_reg_count; i++) {
417                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
418                 /*
419                  * Avoid back to back register writes by adding the register
420                  * read (flush).  This is to protect against some strange
421                  * bridge configurations that may issue Memory Write Block
422                  * (MWB) to our register space.
423                  */
424                 E1000_WRITE_FLUSH(hw);
425         }
426
427         /* Setup link and flow control */
428         ret_val = mac->ops.setup_link(hw);
429
430         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
431         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
432         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
433
434         /*
435          * Clear all of the statistics registers (clear on read).  It is
436          * important that we do this after we have tried to establish link
437          * because the symbol error count will increment wildly if there
438          * is no link.
439          */
440         e1000_clear_hw_cntrs_82541(hw);
441
442 out:
443         return ret_val;
444 }
445
446 /**
447  * e1000_get_link_up_info_82541 - Report speed and duplex
448  * @hw: pointer to the HW structure
449  * @speed: pointer to speed buffer
450  * @duplex: pointer to duplex buffer
451  *
452  * Retrieve the current speed and duplex configuration.
453  **/
454 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 * speed,
455                                                                                 u16 * duplex)
456 {
457         struct e1000_phy_info *phy = &hw->phy;
458         s32 ret_val;
459         u16 data;
460
461         DEBUGFUNC("e1000_get_link_up_info_82541");
462
463         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
464         if (ret_val)
465                 goto out;
466
467         if (!phy->speed_downgraded)
468                 goto out;
469
470         /*
471          * IGP01 PHY may advertise full duplex operation after speed
472          * downgrade even if it is operating at half duplex.
473          * Here we set the duplex settings to match the duplex in the
474          * link partner's capabilities.
475          */
476         ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
477         if (ret_val)
478                 goto out;
479
480         if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
481                 *duplex = HALF_DUPLEX;
482         } else {
483                 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
484                 if (ret_val)
485                         goto out;
486
487                 if (*speed == SPEED_100) {
488                         if (!(data & NWAY_LPAR_100TX_FD_CAPS))
489                                 *duplex = HALF_DUPLEX;
490                 } else if (*speed == SPEED_10) {
491                         if (!(data & NWAY_LPAR_10T_FD_CAPS))
492                                 *duplex = HALF_DUPLEX;
493                 }
494         }
495
496 out:
497         return ret_val;
498 }
499
500 /**
501  *  e1000_phy_hw_reset_82541 - PHY hardware reset
502  *  @hw: pointer to the HW structure
503  *
504  *  Verify the reset block is not blocking us from resetting.  Acquire
505  *  semaphore (if necessary) and read/set/write the device control reset
506  *  bit in the PHY.  Wait the appropriate delay time for the device to
507  *  reset and release the semaphore (if necessary).
508  **/
509 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
510 {
511         s32 ret_val;
512         u32 ledctl;
513
514         DEBUGFUNC("e1000_phy_hw_reset_82541");
515
516         ret_val = e1000_phy_hw_reset_generic(hw);
517         if (ret_val)
518                 goto out;
519
520         e1000_phy_init_script_82541(hw);
521
522         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
523                 /* Configure activity LED after PHY reset */
524                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
525                 ledctl &= IGP_ACTIVITY_LED_MASK;
526                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
527                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
528         }
529
530 out:
531         return ret_val;
532 }
533
534 /**
535  *  e1000_setup_copper_link_82541 - Configure copper link settings
536  *  @hw: pointer to the HW structure
537  *
538  *  Calls the appropriate function to configure the link for auto-neg or forced
539  *  speed and duplex.  Then we check for link, once link is established calls
540  *  to configure collision distance and flow control are called.  If link is
541  *  not established, we return -E1000_ERR_PHY (-2).
542  **/
543 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
544 {
545         struct e1000_phy_info *phy = &hw->phy;
546         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
547         s32 ret_val;
548         u32 ctrl, ledctl;
549
550         DEBUGFUNC("e1000_setup_copper_link_82541");
551
552         ctrl = E1000_READ_REG(hw, E1000_CTRL);
553         ctrl |= E1000_CTRL_SLU;
554         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
555         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
556
557         hw->phy.reset_disable = false;
558
559         /* Earlier revs of the IGP phy require us to force MDI. */
560         if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
561                 dev_spec->dsp_config = e1000_dsp_config_disabled;
562                 phy->mdix = 1;
563         } else {
564                 dev_spec->dsp_config = e1000_dsp_config_enabled;
565         }
566
567         ret_val = e1000_copper_link_setup_igp(hw);
568         if (ret_val)
569                 goto out;
570
571         if (hw->mac.autoneg) {
572                 if (dev_spec->ffe_config == e1000_ffe_config_active)
573                         dev_spec->ffe_config = e1000_ffe_config_enabled;
574         }
575
576         /* Configure activity LED after Phy reset */
577         ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
578         ledctl &= IGP_ACTIVITY_LED_MASK;
579         ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
580         E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
581
582         ret_val = e1000_setup_copper_link_generic(hw);
583
584 out:
585         return ret_val;
586 }
587
588 /**
589  *  e1000_check_for_link_82541 - Check/Store link connection
590  *  @hw: pointer to the HW structure
591  *
592  *  This checks the link condition of the adapter and stores the
593  *  results in the hw->mac structure.
594  **/
595 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
596 {
597         struct e1000_mac_info *mac = &hw->mac;
598         s32 ret_val;
599         bool link;
600
601         DEBUGFUNC("e1000_check_for_link_82541");
602
603         /*
604          * We only want to go out to the PHY registers to see if Auto-Neg
605          * has completed and/or if our link status has changed.  The
606          * get_link_status flag is set upon receiving a Link Status
607          * Change or Rx Sequence Error interrupt.
608          */
609         if (!mac->get_link_status) {
610                 ret_val = E1000_SUCCESS;
611                 goto out;
612         }
613
614         /*
615          * First we want to see if the MII Status Register reports
616          * link.  If so, then we want to get the current speed/duplex
617          * of the PHY.
618          */
619         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
620         if (ret_val)
621                 goto out;
622
623         if (!link) {
624                 ret_val = -E1000_ERR_CONFIG;
625 #if 0
626                 ret_val = e1000_config_dsp_after_link_change_82541(hw, false);
627 #endif
628                 goto out;       /* No link detected */
629         }
630
631         mac->get_link_status = false;
632
633         /*
634          * Check if there was DownShift, must be checked
635          * immediately after link-up
636          */
637         e1000_check_downshift_generic(hw);
638
639         /*
640          * If we are forcing speed/duplex, then we simply return since
641          * we have already determined whether we have link or not.
642          */
643         if (!mac->autoneg) {
644                 ret_val = -E1000_ERR_CONFIG;
645                 goto out;
646         }
647 #if 0
648         ret_val = e1000_config_dsp_after_link_change_82541(hw, true);
649 #endif
650
651         /*
652          * Auto-Neg is enabled.  Auto Speed Detection takes care
653          * of MAC speed/duplex configuration.  So we only need to
654          * configure Collision Distance in the MAC.
655          */
656         e1000_config_collision_dist_generic(hw);
657
658         /*
659          * Configure Flow Control now that Auto-Neg has completed.
660          * First, we need to restore the desired flow control
661          * settings because we may have had to re-autoneg with a
662          * different link partner.
663          */
664         ret_val = e1000_config_fc_after_link_up_generic(hw);
665         if (ret_val) {
666                 DEBUGOUT("Error configuring flow control\n");
667         }
668
669 out:
670         return ret_val;
671 }
672
673 #if 0
674 /**
675  *  e1000_config_dsp_after_link_change_82541 - Config DSP after link
676  *  @hw: pointer to the HW structure
677  *  @link_up: boolean flag for link up status
678  *
679  *  Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
680  *  at any other case.
681  *
682  *  82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
683  *  gigabit link is achieved to improve link quality.
684  **/
685 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
686                                                                                                         bool link_up)
687 {
688         struct e1000_phy_info *phy = &hw->phy;
689         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
690         s32 ret_val;
691         u32 idle_errs = 0;
692         u16 phy_data, phy_saved_data, speed, duplex, i;
693         u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
694         u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
695                 { IGP01E1000_PHY_AGC_PARAM_A,
696                 IGP01E1000_PHY_AGC_PARAM_B,
697                 IGP01E1000_PHY_AGC_PARAM_C,
698                 IGP01E1000_PHY_AGC_PARAM_D
699         };
700
701         DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
702
703         if (link_up) {
704                 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
705                 if (ret_val) {
706                         DEBUGOUT("Error getting link speed and duplex\n");
707                         goto out;
708                 }
709
710                 if (speed != SPEED_1000) {
711                         ret_val = E1000_SUCCESS;
712                         goto out;
713                 }
714 #if 0
715                 ret_val = phy->ops.get_cable_length(hw);
716 #endif
717                 ret_val = -E1000_ERR_CONFIG;
718                 if (ret_val)
719                         goto out;
720
721                 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
722                         phy->min_cable_length >= 50) {
723
724                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
725                                 ret_val = phy->ops.read_reg(hw, dsp_reg_array[i], &phy_data);
726                                 if (ret_val)
727                                         goto out;
728
729                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
730
731                                 ret_val = phy->ops.write_reg(hw, dsp_reg_array[i], phy_data);
732                                 if (ret_val)
733                                         goto out;
734                         }
735                         dev_spec->dsp_config = e1000_dsp_config_activated;
736                 }
737
738                 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
739                         (phy->min_cable_length >= 50)) {
740                         ret_val = E1000_SUCCESS;
741                         goto out;
742                 }
743
744                 /* clear previous idle error counts */
745                 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
746                 if (ret_val)
747                         goto out;
748
749                 for (i = 0; i < ffe_idle_err_timeout; i++) {
750                         usec_delay(1000);
751                         ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
752                         if (ret_val)
753                                 goto out;
754
755                         idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
756                         if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
757                                 dev_spec->ffe_config = e1000_ffe_config_active;
758
759                                 ret_val = phy->ops.write_reg(hw,
760                                                                                          IGP01E1000_PHY_DSP_FFE,
761                                                                                          IGP01E1000_PHY_DSP_FFE_CM_CP);
762                                 if (ret_val)
763                                         goto out;
764                                 break;
765                         }
766
767                         if (idle_errs)
768                                 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
769                 }
770         } else {
771                 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
772                         /*
773                          * Save off the current value of register 0x2F5B
774                          * to be restored at the end of the routines.
775                          */
776                         ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
777                         if (ret_val)
778                                 goto out;
779
780                         /* Disable the PHY transmitter */
781                         ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
782                         if (ret_val)
783                                 goto out;
784
785                         msec_delay_irq(20);
786
787                         ret_val = phy->ops.write_reg(hw, 0x0000, IGP01E1000_IEEE_FORCE_GIG);
788                         if (ret_val)
789                                 goto out;
790                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
791                                 ret_val = phy->ops.read_reg(hw, dsp_reg_array[i], &phy_data);
792                                 if (ret_val)
793                                         goto out;
794
795                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
796                                 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
797
798                                 ret_val = phy->ops.write_reg(hw, dsp_reg_array[i], phy_data);
799                                 if (ret_val)
800                                         goto out;
801                         }
802
803                         ret_val = phy->ops.write_reg(hw,
804                                                                                  0x0000,
805                                                                                  IGP01E1000_IEEE_RESTART_AUTONEG);
806                         if (ret_val)
807                                 goto out;
808
809                         msec_delay_irq(20);
810
811                         /* Now enable the transmitter */
812                         ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
813                         if (ret_val)
814                                 goto out;
815
816                         dev_spec->dsp_config = e1000_dsp_config_enabled;
817                 }
818
819                 if (dev_spec->ffe_config != e1000_ffe_config_active) {
820                         ret_val = E1000_SUCCESS;
821                         goto out;
822                 }
823
824                 /*
825                  * Save off the current value of register 0x2F5B
826                  * to be restored at the end of the routines.
827                  */
828                 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
829                 if (ret_val)
830                         goto out;
831
832                 /* Disable the PHY transmitter */
833                 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
834                 if (ret_val)
835                         goto out;
836
837                 msec_delay_irq(20);
838
839                 ret_val = phy->ops.write_reg(hw, 0x0000, IGP01E1000_IEEE_FORCE_GIG);
840                 if (ret_val)
841                         goto out;
842
843                 ret_val = phy->ops.write_reg(hw,
844                                                                          IGP01E1000_PHY_DSP_FFE,
845                                                                          IGP01E1000_PHY_DSP_FFE_DEFAULT);
846                 if (ret_val)
847                         goto out;
848
849                 ret_val = phy->ops.write_reg(hw,
850                                                                          0x0000, IGP01E1000_IEEE_RESTART_AUTONEG);
851                 if (ret_val)
852                         goto out;
853
854                 msec_delay_irq(20);
855
856                 /* Now enable the transmitter */
857                 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
858
859                 if (ret_val)
860                         goto out;
861
862                 dev_spec->ffe_config = e1000_ffe_config_enabled;
863         }
864
865 out:
866         return ret_val;
867 }
868 #endif
869
870 #if 0
871 /**
872  *  e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
873  *  @hw: pointer to the HW structure
874  *
875  *  The automatic gain control (agc) normalizes the amplitude of the
876  *  received signal, adjusting for the attenuation produced by the
877  *  cable.  By reading the AGC registers, which represent the
878  *  combination of coarse and fine gain value, the value can be put
879  *  into a lookup table to obtain the approximate cable length
880  *  for each channel.
881  **/
882 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
883 {
884         struct e1000_phy_info *phy = &hw->phy;
885         s32 ret_val = E1000_SUCCESS;
886         u16 i, data;
887         u16 cur_agc_value, agc_value = 0;
888         u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
889         u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { IGP01E1000_PHY_AGC_A,
890                 IGP01E1000_PHY_AGC_B,
891                 IGP01E1000_PHY_AGC_C,
892                 IGP01E1000_PHY_AGC_D
893         };
894
895         DEBUGFUNC("e1000_get_cable_length_igp_82541");
896
897         /* Read the AGC registers for all channels */
898         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
899                 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
900                 if (ret_val)
901                         goto out;
902
903                 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
904
905                 /* Bounds checking */
906                 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
907                         (cur_agc_value == 0)) {
908                         ret_val = -E1000_ERR_PHY;
909                         goto out;
910                 }
911
912                 agc_value += cur_agc_value;
913
914                 if (min_agc_value > cur_agc_value)
915                         min_agc_value = cur_agc_value;
916         }
917
918         /* Remove the minimal AGC result for length < 50m */
919         if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
920                 agc_value -= min_agc_value;
921                 /* Average the three remaining channels for the length. */
922                 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
923         } else {
924                 /* Average the channels for the length. */
925                 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
926         }
927
928         phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
929                                                          IGP01E1000_AGC_RANGE)
930                 ? (e1000_igp_cable_length_table[agc_value] - IGP01E1000_AGC_RANGE)
931                 : 0;
932         phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
933                 IGP01E1000_AGC_RANGE;
934
935         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
936
937 out:
938         return ret_val;
939 }
940 #endif
941
942 /**
943  *  e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
944  *  @hw: pointer to the HW structure
945  *  @active: boolean used to enable/disable lplu
946  *
947  *  Success returns 0, Failure returns 1
948  *
949  *  The low power link up (lplu) state is set to the power management level D3
950  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
951  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
952  *  is used during Dx states where the power conservation is most important.
953  *  During driver activity, SmartSpeed should be enabled so performance is
954  *  maintained.
955  **/
956 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
957 {
958         struct e1000_phy_info *phy = &hw->phy;
959         s32 ret_val;
960         u16 data;
961
962         DEBUGFUNC("e1000_set_d3_lplu_state_82541");
963
964         switch (hw->mac.type) {
965                 case e1000_82541_rev_2:
966                 case e1000_82547_rev_2:
967                         break;
968                 default:
969                         ret_val = e1000_set_d3_lplu_state_generic(hw, active);
970                         goto out;
971                         break;
972         }
973
974         ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
975         if (ret_val)
976                 goto out;
977
978         if (!active) {
979                 data &= ~IGP01E1000_GMII_FLEX_SPD;
980                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
981                 if (ret_val)
982                         goto out;
983
984                 /*
985                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
986                  * during Dx states where the power conservation is most
987                  * important.  During driver activity we should enable
988                  * SmartSpeed, so performance is maintained.
989                  */
990                 if (phy->smart_speed == e1000_smart_speed_on) {
991                         ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
992                         if (ret_val)
993                                 goto out;
994
995                         data |= IGP01E1000_PSCFR_SMART_SPEED;
996                         ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data);
997                         if (ret_val)
998                                 goto out;
999                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1000                         ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1001                         if (ret_val)
1002                                 goto out;
1003
1004                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1005                         ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1006                         if (ret_val)
1007                                 goto out;
1008                 }
1009         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1010                            (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1011                            (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1012                 data |= IGP01E1000_GMII_FLEX_SPD;
1013                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1014                 if (ret_val)
1015                         goto out;
1016
1017                 /* When LPLU is enabled, we should disable SmartSpeed */
1018                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1019                 if (ret_val)
1020                         goto out;
1021
1022                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1023                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1024         }
1025
1026 out:
1027         return ret_val;
1028 }
1029
1030 /**
1031  *  e1000_setup_led_82541 - Configures SW controllable LED
1032  *  @hw: pointer to the HW structure
1033  *
1034  *  This prepares the SW controllable LED for use and saves the current state
1035  *  of the LED so it can be later restored.
1036  **/
1037 static s32 e1000_setup_led_82541(struct e1000_hw *hw __unused)
1038 {
1039 #if 0
1040         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1041         s32 ret_val;
1042
1043         DEBUGFUNC("e1000_setup_led_82541");
1044
1045         ret_val = hw->phy.ops.read_reg(hw,
1046                                                                    IGP01E1000_GMII_FIFO,
1047                                                                    &dev_spec->spd_default);
1048         if (ret_val)
1049                 goto out;
1050
1051         ret_val = hw->phy.ops.write_reg(hw,
1052                                                                         IGP01E1000_GMII_FIFO,
1053                                                                         (u16) (dev_spec->spd_default &
1054                                                                                    ~IGP01E1000_GMII_SPD));
1055         if (ret_val)
1056                 goto out;
1057
1058         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1059
1060 out:
1061         return ret_val;
1062 #endif
1063         return 0;
1064 }
1065
1066 /**
1067  *  e1000_cleanup_led_82541 - Set LED config to default operation
1068  *  @hw: pointer to the HW structure
1069  *
1070  *  Remove the current LED configuration and set the LED configuration
1071  *  to the default value, saved from the EEPROM.
1072  **/
1073 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw __unused)
1074 {
1075 #if 0
1076         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1077         s32 ret_val;
1078
1079         DEBUGFUNC("e1000_cleanup_led_82541");
1080
1081         ret_val = hw->phy.ops.write_reg(hw,
1082                                                                         IGP01E1000_GMII_FIFO,
1083                                                                         dev_spec->spd_default);
1084         if (ret_val)
1085                 goto out;
1086
1087         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1088
1089 out:
1090         return ret_val;
1091 #endif
1092         return 0;
1093 }
1094
1095 /**
1096  *  e1000_phy_init_script_82541 - Initialize GbE PHY
1097  *  @hw: pointer to the HW structure
1098  *
1099  *  Initializes the IGP PHY.
1100  **/
1101 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1102 {
1103         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1104         u32 ret_val;
1105         u16 phy_saved_data;
1106
1107         DEBUGFUNC("e1000_phy_init_script_82541");
1108
1109         if (!dev_spec->phy_init_script) {
1110                 ret_val = E1000_SUCCESS;
1111                 goto out;
1112         }
1113
1114         /* Delay after phy reset to enable NVM configuration to load */
1115         msec_delay(20);
1116
1117         /*
1118          * Save off the current value of register 0x2F5B to be restored at
1119          * the end of this routine.
1120          */
1121         ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1122
1123         /* Disabled the PHY transmitter */
1124         hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1125
1126         msec_delay(20);
1127
1128         hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1129
1130         msec_delay(5);
1131
1132         switch (hw->mac.type) {
1133                 case e1000_82541:
1134                 case e1000_82547:
1135                         hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1136
1137                         hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1138
1139                         hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1140
1141                         hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1142
1143                         hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1144
1145                         hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1146
1147                         hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1148
1149                         hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1150
1151                         hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1152                         break;
1153                 case e1000_82541_rev_2:
1154                 case e1000_82547_rev_2:
1155                         hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1156                         break;
1157                 default:
1158                         break;
1159         }
1160
1161         hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1162
1163         msec_delay(20);
1164
1165         /* Now enable the transmitter */
1166         hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1167
1168         if (hw->mac.type == e1000_82547) {
1169                 u16 fused, fine, coarse;
1170
1171                 /* Move to analog registers page */
1172                 hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
1173
1174                 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1175                         hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
1176
1177                         fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1178                         coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1179
1180                         if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1181                                 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1182                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1183                         } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1184                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1185
1186                         fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1187                                 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1188                                 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1189
1190                         hw->phy.ops.write_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
1191                         hw->phy.ops.write_reg(hw,
1192                                                                   IGP01E1000_ANALOG_FUSE_BYPASS,
1193                                                                   IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1194                 }
1195         }
1196
1197 out:
1198         return ret_val;
1199 }
1200
1201 /**
1202  * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1203  * @hw: pointer to the HW structure
1204  *
1205  * In the case of a PHY power down to save power, or to turn off link during a
1206  * driver unload, or wake on lan is not enabled, remove the link.
1207  **/
1208 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1209 {
1210         /* If the management interface is not enabled, then power down */
1211         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1212                 e1000_power_down_phy_copper(hw);
1213
1214         return;
1215 }
1216
1217 /**
1218  *  e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1219  *  @hw: pointer to the HW structure
1220  *
1221  *  Clears the hardware counters by reading the counter registers.
1222  **/
1223 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1224 {
1225         DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1226
1227         e1000_clear_hw_cntrs_base_generic(hw);
1228
1229 #if 0
1230         E1000_READ_REG(hw, E1000_PRC64);
1231         E1000_READ_REG(hw, E1000_PRC127);
1232         E1000_READ_REG(hw, E1000_PRC255);
1233         E1000_READ_REG(hw, E1000_PRC511);
1234         E1000_READ_REG(hw, E1000_PRC1023);
1235         E1000_READ_REG(hw, E1000_PRC1522);
1236         E1000_READ_REG(hw, E1000_PTC64);
1237         E1000_READ_REG(hw, E1000_PTC127);
1238         E1000_READ_REG(hw, E1000_PTC255);
1239         E1000_READ_REG(hw, E1000_PTC511);
1240         E1000_READ_REG(hw, E1000_PTC1023);
1241         E1000_READ_REG(hw, E1000_PTC1522);
1242
1243         E1000_READ_REG(hw, E1000_ALGNERRC);
1244         E1000_READ_REG(hw, E1000_RXERRC);
1245         E1000_READ_REG(hw, E1000_TNCRS);
1246         E1000_READ_REG(hw, E1000_CEXTERR);
1247         E1000_READ_REG(hw, E1000_TSCTC);
1248         E1000_READ_REG(hw, E1000_TSCTFC);
1249
1250         E1000_READ_REG(hw, E1000_MGTPRC);
1251         E1000_READ_REG(hw, E1000_MGTPDC);
1252         E1000_READ_REG(hw, E1000_MGTPTC);
1253 #endif
1254 }
1255
1256 static struct pci_device_id e1000_82541_nics[] = {
1257         PCI_ROM(0x8086, 0x1013, "E1000_DEV_ID_82541EI", "E1000_DEV_ID_82541EI",
1258                         e1000_82541),
1259         PCI_ROM(0x8086, 0x1014, "E1000_DEV_ID_82541ER_LOM",
1260                         "E1000_DEV_ID_82541ER_LOM", e1000_82541),
1261         PCI_ROM(0x8086, 0x1018, "E1000_DEV_ID_82541EI_MOBILE",
1262                         "E1000_DEV_ID_82541EI_MOBILE", e1000_82541),
1263         PCI_ROM(0x8086, 0x1019, "E1000_DEV_ID_82547EI", "E1000_DEV_ID_82547EI",
1264                         e1000_82547),
1265         PCI_ROM(0x8086, 0x101A, "E1000_DEV_ID_82547EI_MOBILE",
1266                         "E1000_DEV_ID_82547EI_MOBILE", e1000_82547),
1267         PCI_ROM(0x8086, 0x1075, "E1000_DEV_ID_82547GI", "E1000_DEV_ID_82547GI",
1268                         e1000_82547_rev_2),
1269         PCI_ROM(0x8086, 0x1076, "E1000_DEV_ID_82541GI", "E1000_DEV_ID_82541GI",
1270                         e1000_82541_rev_2),
1271         PCI_ROM(0x8086, 0x1077, "E1000_DEV_ID_82541GI_MOBILE",
1272                         "E1000_DEV_ID_82541GI_MOBILE", e1000_82541_rev_2),
1273         PCI_ROM(0x8086, 0x1078, "E1000_DEV_ID_82541ER", "E1000_DEV_ID_82541ER",
1274                         e1000_82541_rev_2),
1275         PCI_ROM(0x8086, 0x107C, "E1000_DEV_ID_82541GI_LF",
1276                         "E1000_DEV_ID_82541GI_LF", e1000_82541_rev_2),
1277 };
1278
1279 struct pci_driver e1000_82541_driver __pci_driver = {
1280         .ids = e1000_82541_nics,
1281         .id_count = (sizeof(e1000_82541_nics) / sizeof(e1000_82541_nics[0])),
1282         .probe = e1000_probe,
1283         .remove = e1000_remove,
1284 };