A bit further.
[akaros.git] / kern / drivers / net / e1000 / e1000_82540.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 FILE_LICENCE ( GPL2_OR_LATER );
30
31 /*
32  * 82540EM Gigabit Ethernet Controller
33  * 82540EP Gigabit Ethernet Controller
34  * 82545EM Gigabit Ethernet Controller (Copper)
35  * 82545EM Gigabit Ethernet Controller (Fiber)
36  * 82545GM Gigabit Ethernet Controller
37  * 82546EB Gigabit Ethernet Controller (Copper)
38  * 82546EB Gigabit Ethernet Controller (Fiber)
39  * 82546GB Gigabit Ethernet Controller
40  */
41
42 #include "e1000_api.h"
43
44 static s32  e1000_init_phy_params_82540(struct e1000_hw *hw);
45 static s32  e1000_init_nvm_params_82540(struct e1000_hw *hw);
46 static s32  e1000_init_mac_params_82540(struct e1000_hw *hw);
47 static s32  e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
48 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
49 static s32  e1000_init_hw_82540(struct e1000_hw *hw);
50 static s32  e1000_reset_hw_82540(struct e1000_hw *hw);
51 static s32  e1000_set_phy_mode_82540(struct e1000_hw *hw);
52 static s32  e1000_set_vco_speed_82540(struct e1000_hw *hw);
53 static s32  e1000_setup_copper_link_82540(struct e1000_hw *hw);
54 static s32  e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
55 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
56 static s32  e1000_read_mac_addr_82540(struct e1000_hw *hw);
57
58 /**
59  * e1000_init_phy_params_82540 - Init PHY func ptrs.
60  * @hw: pointer to the HW structure
61  **/
62 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
63 {
64         struct e1000_phy_info *phy = &hw->phy;
65         s32 ret_val = E1000_SUCCESS;
66
67         phy->addr                      = 1;
68         phy->autoneg_mask              = AUTONEG_ADVERTISE_SPEED_DEFAULT;
69         phy->reset_delay_us            = 10000;
70         phy->type                      = e1000_phy_m88;
71
72         /* Function Pointers */
73         phy->ops.check_polarity        = e1000_check_polarity_m88;
74         phy->ops.commit                = e1000_phy_sw_reset_generic;
75 #if 0
76         phy->ops.force_speed_duplex    = e1000_phy_force_speed_duplex_m88;
77 #endif
78 #if 0
79         phy->ops.get_cable_length      = e1000_get_cable_length_m88;
80 #endif
81         phy->ops.get_cfg_done          = e1000_get_cfg_done_generic;
82         phy->ops.read_reg              = e1000_read_phy_reg_m88;
83         phy->ops.reset                 = e1000_phy_hw_reset_generic;
84         phy->ops.write_reg             = e1000_write_phy_reg_m88;
85         phy->ops.get_info              = e1000_get_phy_info_m88;
86         phy->ops.power_up              = e1000_power_up_phy_copper;
87         phy->ops.power_down            = e1000_power_down_phy_copper_82540;
88
89         ret_val = e1000_get_phy_id(hw);
90         if (ret_val)
91                 goto out;
92
93         /* Verify phy id */
94         switch (hw->mac.type) {
95         case e1000_82540:
96         case e1000_82545:
97         case e1000_82545_rev_3:
98         case e1000_82546:
99         case e1000_82546_rev_3:
100                 if (phy->id == M88E1011_I_PHY_ID)
101                         break;
102                 /* Fall Through */
103         default:
104                 ret_val = -E1000_ERR_PHY;
105                 goto out;
106                 break;
107         }
108
109 out:
110         return ret_val;
111 }
112
113 /**
114  * e1000_init_nvm_params_82540 - Init NVM func ptrs.
115  * @hw: pointer to the HW structure
116  **/
117 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
118 {
119         struct e1000_nvm_info *nvm = &hw->nvm;
120         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
121
122         DEBUGFUNC("e1000_init_nvm_params_82540");
123
124         nvm->type               = e1000_nvm_eeprom_microwire;
125         nvm->delay_usec         = 50;
126         nvm->opcode_bits        = 3;
127         switch (nvm->override) {
128         case e1000_nvm_override_microwire_large:
129                 nvm->address_bits       = 8;
130                 nvm->word_size          = 256;
131                 break;
132         case e1000_nvm_override_microwire_small:
133                 nvm->address_bits       = 6;
134                 nvm->word_size          = 64;
135                 break;
136         default:
137                 nvm->address_bits       = eecd & E1000_EECD_SIZE ? 8 : 6;
138                 nvm->word_size          = eecd & E1000_EECD_SIZE ? 256 : 64;
139                 break;
140         }
141
142         /* Function Pointers */
143         nvm->ops.acquire            = e1000_acquire_nvm_generic;
144         nvm->ops.read               = e1000_read_nvm_microwire;
145         nvm->ops.release            = e1000_release_nvm_generic;
146         nvm->ops.update             = e1000_update_nvm_checksum_generic;
147         nvm->ops.valid_led_default  = e1000_valid_led_default_generic;
148         nvm->ops.validate           = e1000_validate_nvm_checksum_generic;
149         nvm->ops.write              = e1000_write_nvm_microwire;
150
151         return E1000_SUCCESS;
152 }
153
154 /**
155  * e1000_init_mac_params_82540 - Init MAC func ptrs.
156  * @hw: pointer to the HW structure
157  **/
158 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
159 {
160         struct e1000_mac_info *mac = &hw->mac;
161         s32 ret_val = E1000_SUCCESS;
162
163         DEBUGFUNC("e1000_init_mac_params_82540");
164
165         /* Set media type */
166         switch (hw->device_id) {
167         case E1000_DEV_ID_82545EM_FIBER:
168         case E1000_DEV_ID_82545GM_FIBER:
169         case E1000_DEV_ID_82546EB_FIBER:
170         case E1000_DEV_ID_82546GB_FIBER:
171                 hw->phy.media_type = e1000_media_type_fiber;
172                 break;
173         case E1000_DEV_ID_82545GM_SERDES:
174         case E1000_DEV_ID_82546GB_SERDES:
175                 hw->phy.media_type = e1000_media_type_internal_serdes;
176                 break;
177         default:
178                 hw->phy.media_type = e1000_media_type_copper;
179                 break;
180         }
181
182         /* Set mta register count */
183         mac->mta_reg_count = 128;
184         /* Set rar entry count */
185         mac->rar_entry_count = E1000_RAR_ENTRIES;
186
187         /* Function pointers */
188
189         /* bus type/speed/width */
190         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
191         /* function id */
192         mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
193         /* reset */
194         mac->ops.reset_hw = e1000_reset_hw_82540;
195         /* hw initialization */
196         mac->ops.init_hw = e1000_init_hw_82540;
197         /* link setup */
198         mac->ops.setup_link = e1000_setup_link_generic;
199         /* physical interface setup */
200         mac->ops.setup_physical_interface =
201                 (hw->phy.media_type == e1000_media_type_copper)
202                         ? e1000_setup_copper_link_82540
203                         : e1000_setup_fiber_serdes_link_82540;
204         /* check for link */
205         switch (hw->phy.media_type) {
206         case e1000_media_type_copper:
207                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
208                 break;
209         case e1000_media_type_fiber:
210                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
211                 break;
212         case e1000_media_type_internal_serdes:
213                 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
214                 break;
215         default:
216                 ret_val = -E1000_ERR_CONFIG;
217                 goto out;
218                 break;
219         }
220         /* link info */
221         mac->ops.get_link_up_info =
222                 (hw->phy.media_type == e1000_media_type_copper)
223                         ? e1000_get_speed_and_duplex_copper_generic
224                         : e1000_get_speed_and_duplex_fiber_serdes_generic;
225         /* multicast address update */
226         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
227         /* writing VFTA */
228         mac->ops.write_vfta = e1000_write_vfta_generic;
229         /* clearing VFTA */
230         mac->ops.clear_vfta = e1000_clear_vfta_generic;
231         /* setting MTA */
232         mac->ops.mta_set = e1000_mta_set_generic;
233         /* read mac address */
234         mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
235         /* ID LED init */
236         mac->ops.id_led_init = e1000_id_led_init_generic;
237         /* setup LED */
238         mac->ops.setup_led = e1000_setup_led_generic;
239         /* cleanup LED */
240         mac->ops.cleanup_led = e1000_cleanup_led_generic;
241         /* turn on/off LED */
242         mac->ops.led_on = e1000_led_on_generic;
243         mac->ops.led_off = e1000_led_off_generic;
244         /* clear hardware counters */
245         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
246
247 out:
248         return ret_val;
249 }
250
251 /**
252  * e1000_init_function_pointers_82540 - Init func ptrs.
253  * @hw: pointer to the HW structure
254  *
255  * Called to initialize all function pointers and parameters.
256  **/
257 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
258 {
259         DEBUGFUNC("e1000_init_function_pointers_82540");
260
261         hw->mac.ops.init_params = e1000_init_mac_params_82540;
262         hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
263         hw->phy.ops.init_params = e1000_init_phy_params_82540;
264 }
265
266 /**
267  *  e1000_reset_hw_82540 - Reset hardware
268  *  @hw: pointer to the HW structure
269  *
270  *  This resets the hardware into a known state.
271  **/
272 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
273 {
274         u32 ctrl, icr, manc;
275         s32 ret_val = E1000_SUCCESS;
276
277         DEBUGFUNC("e1000_reset_hw_82540");
278
279         DEBUGOUT("Masking off all interrupts\n");
280         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
281
282         E1000_WRITE_REG(hw, E1000_RCTL, 0);
283         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
284         E1000_WRITE_FLUSH(hw);
285
286         /*
287          * Delay to allow any outstanding PCI transactions to complete
288          * before resetting the device.
289          */
290         msec_delay(10);
291
292         ctrl = E1000_READ_REG(hw, E1000_CTRL);
293
294         DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
295         switch (hw->mac.type) {
296         case e1000_82545_rev_3:
297         case e1000_82546_rev_3:
298                 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
299                 break;
300         default:
301                 /*
302                  * These controllers can't ack the 64-bit write when
303                  * issuing the reset, so we use IO-mapping as a
304                  * workaround to issue the reset.
305                  */
306                 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
307                 break;
308         }
309
310         /* Wait for EEPROM reload */
311         msec_delay(5);
312
313         /* Disable HW ARPs on ASF enabled adapters */
314         manc = E1000_READ_REG(hw, E1000_MANC);
315         manc &= ~E1000_MANC_ARP_EN;
316         E1000_WRITE_REG(hw, E1000_MANC, manc);
317
318         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
319         icr = E1000_READ_REG(hw, E1000_ICR);
320
321         return ret_val;
322 }
323
324 /**
325  *  e1000_init_hw_82540 - Initialize hardware
326  *  @hw: pointer to the HW structure
327  *
328  *  This inits the hardware readying it for operation.
329  **/
330 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
331 {
332         struct e1000_mac_info *mac = &hw->mac;
333         u32 txdctl, ctrl_ext;
334         s32 ret_val = E1000_SUCCESS;
335         u16 i;
336
337         DEBUGFUNC("e1000_init_hw_82540");
338
339         /* Initialize identification LED */
340         ret_val = mac->ops.id_led_init(hw);
341         if (ret_val) {
342                 DEBUGOUT("Error initializing identification LED\n");
343                 /* This is not fatal and we should not stop init due to this */
344         }
345
346         /* Disabling VLAN filtering */
347         DEBUGOUT("Initializing the IEEE VLAN\n");
348         if (mac->type < e1000_82545_rev_3)
349                 E1000_WRITE_REG(hw, E1000_VET, 0);
350
351         mac->ops.clear_vfta(hw);
352
353         /* Setup the receive address. */
354         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
355
356         /* Zero out the Multicast HASH table */
357         DEBUGOUT("Zeroing the MTA\n");
358         for (i = 0; i < mac->mta_reg_count; i++) {
359                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
360                 /*
361                  * Avoid back to back register writes by adding the register
362                  * read (flush).  This is to protect against some strange
363                  * bridge configurations that may issue Memory Write Block
364                  * (MWB) to our register space.  The *_rev_3 hardware at
365                  * least doesn't respond correctly to every other dword in an
366                  * MWB to our register space.
367                  */
368                 E1000_WRITE_FLUSH(hw);
369         }
370
371         if (mac->type < e1000_82545_rev_3)
372                 e1000_pcix_mmrbc_workaround_generic(hw);
373
374         /* Setup link and flow control */
375         ret_val = mac->ops.setup_link(hw);
376
377         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
378         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
379                  E1000_TXDCTL_FULL_TX_DESC_WB;
380         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
381
382         /*
383          * Clear all of the statistics registers (clear on read).  It is
384          * important that we do this after we have tried to establish link
385          * because the symbol error count will increment wildly if there
386          * is no link.
387          */
388         e1000_clear_hw_cntrs_82540(hw);
389
390         if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
391             (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
392                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
393                 /*
394                  * Relaxed ordering must be disabled to avoid a parity
395                  * error crash in a PCI slot.
396                  */
397                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
398                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
399         }
400
401         return ret_val;
402 }
403
404 /**
405  *  e1000_setup_copper_link_82540 - Configure copper link settings
406  *  @hw: pointer to the HW structure
407  *
408  *  Calls the appropriate function to configure the link for auto-neg or forced
409  *  speed and duplex.  Then we check for link, once link is established calls
410  *  to configure collision distance and flow control are called.  If link is
411  *  not established, we return -E1000_ERR_PHY (-2).
412  **/
413 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
414 {
415         u32 ctrl;
416         s32 ret_val = E1000_SUCCESS;
417         u16 data;
418
419         DEBUGFUNC("e1000_setup_copper_link_82540");
420
421         ctrl = E1000_READ_REG(hw, E1000_CTRL);
422         ctrl |= E1000_CTRL_SLU;
423         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
424         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
425
426         ret_val = e1000_set_phy_mode_82540(hw);
427         if (ret_val)
428                 goto out;
429
430         if (hw->mac.type == e1000_82545_rev_3 ||
431             hw->mac.type == e1000_82546_rev_3) {
432                 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
433                 if (ret_val)
434                         goto out;
435                 data |= 0x00000008;
436                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
437                 if (ret_val)
438                         goto out;
439         }
440
441         ret_val = e1000_copper_link_setup_m88(hw);
442         if (ret_val)
443                 goto out;
444
445         ret_val = e1000_setup_copper_link_generic(hw);
446
447 out:
448         return ret_val;
449 }
450
451 /**
452  *  e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
453  *  @hw: pointer to the HW structure
454  *
455  *  Set the output amplitude to the value in the EEPROM and adjust the VCO
456  *  speed to improve Bit Error Rate (BER) performance.  Configures collision
457  *  distance and flow control for fiber and serdes links.  Upon successful
458  *  setup, poll for link.
459  **/
460 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
461 {
462         struct e1000_mac_info *mac = &hw->mac;
463         s32 ret_val = E1000_SUCCESS;
464
465         DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
466
467         switch (mac->type) {
468         case e1000_82545_rev_3:
469         case e1000_82546_rev_3:
470                 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
471                         /*
472                          * If we're on serdes media, adjust the output
473                          * amplitude to value set in the EEPROM.
474                          */
475                         ret_val = e1000_adjust_serdes_amplitude_82540(hw);
476                         if (ret_val)
477                                 goto out;
478                 }
479                 /* Adjust VCO speed to improve BER performance */
480                 ret_val = e1000_set_vco_speed_82540(hw);
481                 if (ret_val)
482                         goto out;
483         default:
484                 break;
485         }
486
487         ret_val = e1000_setup_fiber_serdes_link_generic(hw);
488
489 out:
490         return ret_val;
491 }
492
493 /**
494  *  e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
495  *  @hw: pointer to the HW structure
496  *
497  *  Adjust the SERDES output amplitude based on the EEPROM settings.
498  **/
499 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
500 {
501         s32 ret_val = E1000_SUCCESS;
502         u16 nvm_data;
503
504         DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
505
506         ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
507         if (ret_val)
508                 goto out;
509
510         if (nvm_data != NVM_RESERVED_WORD) {
511                 /* Adjust serdes output amplitude only. */
512                 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
513                 ret_val = hw->phy.ops.write_reg(hw,
514                                              M88E1000_PHY_EXT_CTRL,
515                                              nvm_data);
516                 if (ret_val)
517                         goto out;
518         }
519
520 out:
521         return ret_val;
522 }
523
524 /**
525  *  e1000_set_vco_speed_82540 - Set VCO speed for better performance
526  *  @hw: pointer to the HW structure
527  *
528  *  Set the VCO speed to improve Bit Error Rate (BER) performance.
529  **/
530 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
531 {
532         s32  ret_val = E1000_SUCCESS;
533         u16 default_page = 0;
534         u16 phy_data;
535
536         DEBUGFUNC("e1000_set_vco_speed_82540");
537
538         /* Set PHY register 30, page 5, bit 8 to 0 */
539
540         ret_val = hw->phy.ops.read_reg(hw,
541                                     M88E1000_PHY_PAGE_SELECT,
542                                     &default_page);
543         if (ret_val)
544                 goto out;
545
546         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
547         if (ret_val)
548                 goto out;
549
550         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
551         if (ret_val)
552                 goto out;
553
554         phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
555         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
556         if (ret_val)
557                 goto out;
558
559         /* Set PHY register 30, page 4, bit 11 to 1 */
560
561         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
562         if (ret_val)
563                 goto out;
564
565         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
566         if (ret_val)
567                 goto out;
568
569         phy_data |= M88E1000_PHY_VCO_REG_BIT11;
570         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
571         if (ret_val)
572                 goto out;
573
574         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
575                                       default_page);
576
577 out:
578         return ret_val;
579 }
580
581 /**
582  *  e1000_set_phy_mode_82540 - Set PHY to class A mode
583  *  @hw: pointer to the HW structure
584  *
585  *  Sets the PHY to class A mode and assumes the following operations will
586  *  follow to enable the new class mode:
587  *    1.  Do a PHY soft reset.
588  *    2.  Restart auto-negotiation or force link.
589  **/
590 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
591 {
592         struct e1000_phy_info *phy = &hw->phy;
593         s32 ret_val = E1000_SUCCESS;
594         u16 nvm_data;
595
596         DEBUGFUNC("e1000_set_phy_mode_82540");
597
598         if (hw->mac.type != e1000_82545_rev_3)
599                 goto out;
600
601         ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
602         if (ret_val) {
603                 ret_val = -E1000_ERR_PHY;
604                 goto out;
605         }
606
607         if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
608                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
609                                               0x000B);
610                 if (ret_val) {
611                         ret_val = -E1000_ERR_PHY;
612                         goto out;
613                 }
614                 ret_val = hw->phy.ops.write_reg(hw,
615                                               M88E1000_PHY_GEN_CONTROL,
616                                               0x8104);
617                 if (ret_val) {
618                         ret_val = -E1000_ERR_PHY;
619                         goto out;
620                 }
621
622                 phy->reset_disable = false;
623         }
624
625 out:
626         return ret_val;
627 }
628
629 /**
630  * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
631  * @hw: pointer to the HW structure
632  *
633  * In the case of a PHY power down to save power, or to turn off link during a
634  * driver unload, or wake on lan is not enabled, remove the link.
635  **/
636 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
637 {
638         /* If the management interface is not enabled, then power down */
639         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
640                 e1000_power_down_phy_copper(hw);
641
642         return;
643 }
644
645 /**
646  *  e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
647  *  @hw: pointer to the HW structure
648  *
649  *  Clears the hardware counters by reading the counter registers.
650  **/
651 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
652 {
653         DEBUGFUNC("e1000_clear_hw_cntrs_82540");
654
655         e1000_clear_hw_cntrs_base_generic(hw);
656
657 #if 0
658         E1000_READ_REG(hw, E1000_PRC64);
659         E1000_READ_REG(hw, E1000_PRC127);
660         E1000_READ_REG(hw, E1000_PRC255);
661         E1000_READ_REG(hw, E1000_PRC511);
662         E1000_READ_REG(hw, E1000_PRC1023);
663         E1000_READ_REG(hw, E1000_PRC1522);
664         E1000_READ_REG(hw, E1000_PTC64);
665         E1000_READ_REG(hw, E1000_PTC127);
666         E1000_READ_REG(hw, E1000_PTC255);
667         E1000_READ_REG(hw, E1000_PTC511);
668         E1000_READ_REG(hw, E1000_PTC1023);
669         E1000_READ_REG(hw, E1000_PTC1522);
670
671         E1000_READ_REG(hw, E1000_ALGNERRC);
672         E1000_READ_REG(hw, E1000_RXERRC);
673         E1000_READ_REG(hw, E1000_TNCRS);
674         E1000_READ_REG(hw, E1000_CEXTERR);
675         E1000_READ_REG(hw, E1000_TSCTC);
676         E1000_READ_REG(hw, E1000_TSCTFC);
677
678         E1000_READ_REG(hw, E1000_MGTPRC);
679         E1000_READ_REG(hw, E1000_MGTPDC);
680         E1000_READ_REG(hw, E1000_MGTPTC);
681 #endif
682 }
683
684 /**
685  *  e1000_read_mac_addr_82540 - Read device MAC address
686  *  @hw: pointer to the HW structure
687  *
688  *  Reads the device MAC address from the EEPROM and stores the value.
689  *  Since devices with two ports use the same EEPROM, we increment the
690  *  last bit in the MAC address for the second port.
691  *
692  *  This version is being used over generic because of customer issues
693  *  with VmWare and Virtual Box when using generic. It seems in
694  *  the emulated 82545, RAR[0] does NOT have a valid address after a
695  *  reset, this older method works and using this breaks nothing for
696  *  these legacy adapters.
697  **/
698 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
699 {
700         s32  ret_val = E1000_SUCCESS;
701         u16 offset, nvm_data, i;
702
703         DEBUGFUNC("e1000_read_mac_addr");
704
705         for (i = 0; i < ETH_ADDR_LEN; i += 2) {
706                 offset = i >> 1;
707                 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
708                 if (ret_val) {
709                         DEBUGOUT("NVM Read Error\n");
710                         goto out;
711                 }
712                 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
713                 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
714         }
715
716         /* Flip last bit of mac address if we're on second port */
717         if (hw->bus.func == E1000_FUNC_1)
718                 hw->mac.perm_addr[5] ^= 1;
719
720         for (i = 0; i < ETH_ADDR_LEN; i++)
721                 hw->mac.addr[i] = hw->mac.perm_addr[i];
722
723 out:
724         return ret_val;
725 }
726
727 static struct pci_device_id e1000_82540_nics[] = {
728      PCI_ROM(0x8086, 0x100E, "E1000_DEV_ID_82540EM", "E1000_DEV_ID_82540EM", e1000_82540),
729      PCI_ROM(0x8086, 0x1015, "E1000_DEV_ID_82540EM_LOM", "E1000_DEV_ID_82540EM_LOM", e1000_82540),
730      PCI_ROM(0x8086, 0x1016, "E1000_DEV_ID_82540EP_LOM", "E1000_DEV_ID_82540EP_LOM", e1000_82540),
731      PCI_ROM(0x8086, 0x1017, "E1000_DEV_ID_82540EP", "E1000_DEV_ID_82540EP", e1000_82540),
732      PCI_ROM(0x8086, 0x101E, "E1000_DEV_ID_82540EP_LP", "E1000_DEV_ID_82540EP_LP", e1000_82540),
733      PCI_ROM(0x8086, 0x100F, "E1000_DEV_ID_82545EM_COPPER", "E1000_DEV_ID_82545EM_COPPER", e1000_82545),
734      PCI_ROM(0x8086, 0x1011, "E1000_DEV_ID_82545EM_FIBER", "E1000_DEV_ID_82545EM_FIBER", e1000_82545),
735      PCI_ROM(0x8086, 0x1026, "E1000_DEV_ID_82545GM_COPPER", "E1000_DEV_ID_82545GM_COPPER", e1000_82545_rev_3),
736      PCI_ROM(0x8086, 0x1027, "E1000_DEV_ID_82545GM_FIBER", "E1000_DEV_ID_82545GM_FIBER", e1000_82545_rev_3),
737      PCI_ROM(0x8086, 0x1028, "E1000_DEV_ID_82545GM_SERDES", "E1000_DEV_ID_82545GM_SERDES", e1000_82545_rev_3),
738      PCI_ROM(0x8086, 0x1010, "E1000_DEV_ID_82546EB_COPPER", "E1000_DEV_ID_82546EB_COPPER", e1000_82546),
739      PCI_ROM(0x8086, 0x1012, "E1000_DEV_ID_82546EB_FIBER", "E1000_DEV_ID_82546EB_FIBER", e1000_82546),
740      PCI_ROM(0x8086, 0x101D, "E1000_DEV_ID_82546EB_QUAD_COPPER", "E1000_DEV_ID_82546EB_QUAD_COPPER", e1000_82546),
741      PCI_ROM(0x8086, 0x1079, "E1000_DEV_ID_82546GB_COPPER", "E1000_DEV_ID_82546GB_COPPER", e1000_82546_rev_3),
742      PCI_ROM(0x8086, 0x107A, "E1000_DEV_ID_82546GB_FIBER", "E1000_DEV_ID_82546GB_FIBER", e1000_82546_rev_3),
743      PCI_ROM(0x8086, 0x107B, "E1000_DEV_ID_82546GB_SERDES", "E1000_DEV_ID_82546GB_SERDES", e1000_82546_rev_3),
744      PCI_ROM(0x8086, 0x108A, "E1000_DEV_ID_82546GB_PCIE", "E1000_DEV_ID_82546GB_PCIE", e1000_82546_rev_3),
745      PCI_ROM(0x8086, 0x1099, "E1000_DEV_ID_82546GB_QUAD_COPPER", "E1000_DEV_ID_82546GB_QUAD_COPPER", e1000_82546_rev_3),
746      PCI_ROM(0x8086, 0x10B5, "E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3", "E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3", e1000_82546_rev_3),
747 };
748
749 struct pci_driver e1000_82540_driver __pci_driver = {
750         .ids = e1000_82540_nics,
751         .id_count = (sizeof (e1000_82540_nics) / sizeof (e1000_82540_nics[0])),
752         .probe = e1000_probe,
753         .remove = e1000_remove,
754 };