BNX2X: usability fixups
[akaros.git] / kern / drivers / net / e1000 / e1000_82540.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 FILE_LICENCE(GPL2_OR_LATER);
30
31 /*
32  * 82540EM Gigabit Ethernet Controller
33  * 82540EP Gigabit Ethernet Controller
34  * 82545EM Gigabit Ethernet Controller (Copper)
35  * 82545EM Gigabit Ethernet Controller (Fiber)
36  * 82545GM Gigabit Ethernet Controller
37  * 82546EB Gigabit Ethernet Controller (Copper)
38  * 82546EB Gigabit Ethernet Controller (Fiber)
39  * 82546GB Gigabit Ethernet Controller
40  */
41
42 #include "e1000_api.h"
43
44 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
45 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
46 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
47 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
48 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
49 static s32 e1000_init_hw_82540(struct e1000_hw *hw);
50 static s32 e1000_reset_hw_82540(struct e1000_hw *hw);
51 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
52 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
53 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
54 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
55 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
56 static s32 e1000_read_mac_addr_82540(struct e1000_hw *hw);
57
58 /**
59  * e1000_init_phy_params_82540 - Init PHY func ptrs.
60  * @hw: pointer to the HW structure
61  **/
62 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
63 {
64         struct e1000_phy_info *phy = &hw->phy;
65         s32 ret_val = E1000_SUCCESS;
66
67         phy->addr = 1;
68         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
69         phy->reset_delay_us = 10000;
70         phy->type = e1000_phy_m88;
71
72         /* Function Pointers */
73         phy->ops.check_polarity = e1000_check_polarity_m88;
74         phy->ops.commit = e1000_phy_sw_reset_generic;
75 #if 0
76         phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
77 #endif
78 #if 0
79         phy->ops.get_cable_length = e1000_get_cable_length_m88;
80 #endif
81         phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
82         phy->ops.read_reg = e1000_read_phy_reg_m88;
83         phy->ops.reset = e1000_phy_hw_reset_generic;
84         phy->ops.write_reg = e1000_write_phy_reg_m88;
85         phy->ops.get_info = e1000_get_phy_info_m88;
86         phy->ops.power_up = e1000_power_up_phy_copper;
87         phy->ops.power_down = e1000_power_down_phy_copper_82540;
88
89         ret_val = e1000_get_phy_id(hw);
90         if (ret_val)
91                 goto out;
92
93         /* Verify phy id */
94         switch (hw->mac.type) {
95                 case e1000_82540:
96                 case e1000_82545:
97                 case e1000_82545_rev_3:
98                 case e1000_82546:
99                 case e1000_82546_rev_3:
100                         if (phy->id == M88E1011_I_PHY_ID)
101                                 break;
102                         /* Fall Through */
103                 default:
104                         ret_val = -E1000_ERR_PHY;
105                         goto out;
106                         break;
107         }
108
109 out:
110         return ret_val;
111 }
112
113 /**
114  * e1000_init_nvm_params_82540 - Init NVM func ptrs.
115  * @hw: pointer to the HW structure
116  **/
117 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
118 {
119         struct e1000_nvm_info *nvm = &hw->nvm;
120         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
121
122         DEBUGFUNC("e1000_init_nvm_params_82540");
123
124         nvm->type = e1000_nvm_eeprom_microwire;
125         nvm->delay_usec = 50;
126         nvm->opcode_bits = 3;
127         switch (nvm->override) {
128                 case e1000_nvm_override_microwire_large:
129                         nvm->address_bits = 8;
130                         nvm->word_size = 256;
131                         break;
132                 case e1000_nvm_override_microwire_small:
133                         nvm->address_bits = 6;
134                         nvm->word_size = 64;
135                         break;
136                 default:
137                         nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
138                         nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
139                         break;
140         }
141
142         /* Function Pointers */
143         nvm->ops.acquire = e1000_acquire_nvm_generic;
144         nvm->ops.read = e1000_read_nvm_microwire;
145         nvm->ops.release = e1000_release_nvm_generic;
146         nvm->ops.update = e1000_update_nvm_checksum_generic;
147         nvm->ops.valid_led_default = e1000_valid_led_default_generic;
148         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
149         nvm->ops.write = e1000_write_nvm_microwire;
150
151         return E1000_SUCCESS;
152 }
153
154 /**
155  * e1000_init_mac_params_82540 - Init MAC func ptrs.
156  * @hw: pointer to the HW structure
157  **/
158 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
159 {
160         struct e1000_mac_info *mac = &hw->mac;
161         s32 ret_val = E1000_SUCCESS;
162
163         DEBUGFUNC("e1000_init_mac_params_82540");
164
165         /* Set media type */
166         switch (hw->device_id) {
167                 case E1000_DEV_ID_82545EM_FIBER:
168                 case E1000_DEV_ID_82545GM_FIBER:
169                 case E1000_DEV_ID_82546EB_FIBER:
170                 case E1000_DEV_ID_82546GB_FIBER:
171                         hw->phy.media_type = e1000_media_type_fiber;
172                         break;
173                 case E1000_DEV_ID_82545GM_SERDES:
174                 case E1000_DEV_ID_82546GB_SERDES:
175                         hw->phy.media_type = e1000_media_type_internal_serdes;
176                         break;
177                 default:
178                         hw->phy.media_type = e1000_media_type_copper;
179                         break;
180         }
181
182         /* Set mta register count */
183         mac->mta_reg_count = 128;
184         /* Set rar entry count */
185         mac->rar_entry_count = E1000_RAR_ENTRIES;
186
187         /* Function pointers */
188
189         /* bus type/speed/width */
190         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
191         /* function id */
192         mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
193         /* reset */
194         mac->ops.reset_hw = e1000_reset_hw_82540;
195         /* hw initialization */
196         mac->ops.init_hw = e1000_init_hw_82540;
197         /* link setup */
198         mac->ops.setup_link = e1000_setup_link_generic;
199         /* physical interface setup */
200         mac->ops.setup_physical_interface =
201                 (hw->phy.media_type == e1000_media_type_copper)
202                 ? e1000_setup_copper_link_82540 : e1000_setup_fiber_serdes_link_82540;
203         /* check for link */
204         switch (hw->phy.media_type) {
205                 case e1000_media_type_copper:
206                         mac->ops.check_for_link = e1000_check_for_copper_link_generic;
207                         break;
208                 case e1000_media_type_fiber:
209                         mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
210                         break;
211                 case e1000_media_type_internal_serdes:
212                         mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
213                         break;
214                 default:
215                         ret_val = -E1000_ERR_CONFIG;
216                         goto out;
217                         break;
218         }
219         /* link info */
220         mac->ops.get_link_up_info = (hw->phy.media_type == e1000_media_type_copper)
221                 ? e1000_get_speed_and_duplex_copper_generic
222                 : e1000_get_speed_and_duplex_fiber_serdes_generic;
223         /* multicast address update */
224         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
225         /* writing VFTA */
226         mac->ops.write_vfta = e1000_write_vfta_generic;
227         /* clearing VFTA */
228         mac->ops.clear_vfta = e1000_clear_vfta_generic;
229         /* setting MTA */
230         mac->ops.mta_set = e1000_mta_set_generic;
231         /* read mac address */
232         mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
233         /* ID LED init */
234         mac->ops.id_led_init = e1000_id_led_init_generic;
235         /* setup LED */
236         mac->ops.setup_led = e1000_setup_led_generic;
237         /* cleanup LED */
238         mac->ops.cleanup_led = e1000_cleanup_led_generic;
239         /* turn on/off LED */
240         mac->ops.led_on = e1000_led_on_generic;
241         mac->ops.led_off = e1000_led_off_generic;
242         /* clear hardware counters */
243         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
244
245 out:
246         return ret_val;
247 }
248
249 /**
250  * e1000_init_function_pointers_82540 - Init func ptrs.
251  * @hw: pointer to the HW structure
252  *
253  * Called to initialize all function pointers and parameters.
254  **/
255 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
256 {
257         DEBUGFUNC("e1000_init_function_pointers_82540");
258
259         hw->mac.ops.init_params = e1000_init_mac_params_82540;
260         hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
261         hw->phy.ops.init_params = e1000_init_phy_params_82540;
262 }
263
264 /**
265  *  e1000_reset_hw_82540 - Reset hardware
266  *  @hw: pointer to the HW structure
267  *
268  *  This resets the hardware into a known state.
269  **/
270 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
271 {
272         u32 ctrl, icr, manc;
273         s32 ret_val = E1000_SUCCESS;
274
275         DEBUGFUNC("e1000_reset_hw_82540");
276
277         DEBUGOUT("Masking off all interrupts\n");
278         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
279
280         E1000_WRITE_REG(hw, E1000_RCTL, 0);
281         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
282         E1000_WRITE_FLUSH(hw);
283
284         /*
285          * Delay to allow any outstanding PCI transactions to complete
286          * before resetting the device.
287          */
288         msec_delay(10);
289
290         ctrl = E1000_READ_REG(hw, E1000_CTRL);
291
292         DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
293         switch (hw->mac.type) {
294                 case e1000_82545_rev_3:
295                 case e1000_82546_rev_3:
296                         E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
297                         break;
298                 default:
299                         /*
300                          * These controllers can't ack the 64-bit write when
301                          * issuing the reset, so we use IO-mapping as a
302                          * workaround to issue the reset.
303                          */
304                         E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
305                         break;
306         }
307
308         /* Wait for EEPROM reload */
309         msec_delay(5);
310
311         /* Disable HW ARPs on ASF enabled adapters */
312         manc = E1000_READ_REG(hw, E1000_MANC);
313         manc &= ~E1000_MANC_ARP_EN;
314         E1000_WRITE_REG(hw, E1000_MANC, manc);
315
316         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
317         icr = E1000_READ_REG(hw, E1000_ICR);
318
319         return ret_val;
320 }
321
322 /**
323  *  e1000_init_hw_82540 - Initialize hardware
324  *  @hw: pointer to the HW structure
325  *
326  *  This inits the hardware readying it for operation.
327  **/
328 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
329 {
330         struct e1000_mac_info *mac = &hw->mac;
331         u32 txdctl, ctrl_ext;
332         s32 ret_val = E1000_SUCCESS;
333         u16 i;
334
335         DEBUGFUNC("e1000_init_hw_82540");
336
337         /* Initialize identification LED */
338         ret_val = mac->ops.id_led_init(hw);
339         if (ret_val) {
340                 DEBUGOUT("Error initializing identification LED\n");
341                 /* This is not fatal and we should not stop init due to this */
342         }
343
344         /* Disabling VLAN filtering */
345         DEBUGOUT("Initializing the IEEE VLAN\n");
346         if (mac->type < e1000_82545_rev_3)
347                 E1000_WRITE_REG(hw, E1000_VET, 0);
348
349         mac->ops.clear_vfta(hw);
350
351         /* Setup the receive address. */
352         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
353
354         /* Zero out the Multicast HASH table */
355         DEBUGOUT("Zeroing the MTA\n");
356         for (i = 0; i < mac->mta_reg_count; i++) {
357                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
358                 /*
359                  * Avoid back to back register writes by adding the register
360                  * read (flush).  This is to protect against some strange
361                  * bridge configurations that may issue Memory Write Block
362                  * (MWB) to our register space.  The *_rev_3 hardware at
363                  * least doesn't respond correctly to every other dword in an
364                  * MWB to our register space.
365                  */
366                 E1000_WRITE_FLUSH(hw);
367         }
368
369         if (mac->type < e1000_82545_rev_3)
370                 e1000_pcix_mmrbc_workaround_generic(hw);
371
372         /* Setup link and flow control */
373         ret_val = mac->ops.setup_link(hw);
374
375         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
376         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
377         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
378
379         /*
380          * Clear all of the statistics registers (clear on read).  It is
381          * important that we do this after we have tried to establish link
382          * because the symbol error count will increment wildly if there
383          * is no link.
384          */
385         e1000_clear_hw_cntrs_82540(hw);
386
387         if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
388                 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
389                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
390                 /*
391                  * Relaxed ordering must be disabled to avoid a parity
392                  * error crash in a PCI slot.
393                  */
394                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
395                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
396         }
397
398         return ret_val;
399 }
400
401 /**
402  *  e1000_setup_copper_link_82540 - Configure copper link settings
403  *  @hw: pointer to the HW structure
404  *
405  *  Calls the appropriate function to configure the link for auto-neg or forced
406  *  speed and duplex.  Then we check for link, once link is established calls
407  *  to configure collision distance and flow control are called.  If link is
408  *  not established, we return -E1000_ERR_PHY (-2).
409  **/
410 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
411 {
412         u32 ctrl;
413         s32 ret_val = E1000_SUCCESS;
414         u16 data;
415
416         DEBUGFUNC("e1000_setup_copper_link_82540");
417
418         ctrl = E1000_READ_REG(hw, E1000_CTRL);
419         ctrl |= E1000_CTRL_SLU;
420         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
421         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
422
423         ret_val = e1000_set_phy_mode_82540(hw);
424         if (ret_val)
425                 goto out;
426
427         if (hw->mac.type == e1000_82545_rev_3 || hw->mac.type == e1000_82546_rev_3) {
428                 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
429                 if (ret_val)
430                         goto out;
431                 data |= 0x00000008;
432                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
433                 if (ret_val)
434                         goto out;
435         }
436
437         ret_val = e1000_copper_link_setup_m88(hw);
438         if (ret_val)
439                 goto out;
440
441         ret_val = e1000_setup_copper_link_generic(hw);
442
443 out:
444         return ret_val;
445 }
446
447 /**
448  *  e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
449  *  @hw: pointer to the HW structure
450  *
451  *  Set the output amplitude to the value in the EEPROM and adjust the VCO
452  *  speed to improve Bit Error Rate (BER) performance.  Configures collision
453  *  distance and flow control for fiber and serdes links.  Upon successful
454  *  setup, poll for link.
455  **/
456 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
457 {
458         struct e1000_mac_info *mac = &hw->mac;
459         s32 ret_val = E1000_SUCCESS;
460
461         DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
462
463         switch (mac->type) {
464                 case e1000_82545_rev_3:
465                 case e1000_82546_rev_3:
466                         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
467                                 /*
468                                  * If we're on serdes media, adjust the output
469                                  * amplitude to value set in the EEPROM.
470                                  */
471                                 ret_val = e1000_adjust_serdes_amplitude_82540(hw);
472                                 if (ret_val)
473                                         goto out;
474                         }
475                         /* Adjust VCO speed to improve BER performance */
476                         ret_val = e1000_set_vco_speed_82540(hw);
477                         if (ret_val)
478                                 goto out;
479                 default:
480                         break;
481         }
482
483         ret_val = e1000_setup_fiber_serdes_link_generic(hw);
484
485 out:
486         return ret_val;
487 }
488
489 /**
490  *  e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
491  *  @hw: pointer to the HW structure
492  *
493  *  Adjust the SERDES output amplitude based on the EEPROM settings.
494  **/
495 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
496 {
497         s32 ret_val = E1000_SUCCESS;
498         u16 nvm_data;
499
500         DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
501
502         ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
503         if (ret_val)
504                 goto out;
505
506         if (nvm_data != NVM_RESERVED_WORD) {
507                 /* Adjust serdes output amplitude only. */
508                 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
509                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL, nvm_data);
510                 if (ret_val)
511                         goto out;
512         }
513
514 out:
515         return ret_val;
516 }
517
518 /**
519  *  e1000_set_vco_speed_82540 - Set VCO speed for better performance
520  *  @hw: pointer to the HW structure
521  *
522  *  Set the VCO speed to improve Bit Error Rate (BER) performance.
523  **/
524 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
525 {
526         s32 ret_val = E1000_SUCCESS;
527         u16 default_page = 0;
528         u16 phy_data;
529
530         DEBUGFUNC("e1000_set_vco_speed_82540");
531
532         /* Set PHY register 30, page 5, bit 8 to 0 */
533
534         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
535         if (ret_val)
536                 goto out;
537
538         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
539         if (ret_val)
540                 goto out;
541
542         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
543         if (ret_val)
544                 goto out;
545
546         phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
547         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
548         if (ret_val)
549                 goto out;
550
551         /* Set PHY register 30, page 4, bit 11 to 1 */
552
553         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
554         if (ret_val)
555                 goto out;
556
557         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
558         if (ret_val)
559                 goto out;
560
561         phy_data |= M88E1000_PHY_VCO_REG_BIT11;
562         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
563         if (ret_val)
564                 goto out;
565
566         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
567
568 out:
569         return ret_val;
570 }
571
572 /**
573  *  e1000_set_phy_mode_82540 - Set PHY to class A mode
574  *  @hw: pointer to the HW structure
575  *
576  *  Sets the PHY to class A mode and assumes the following operations will
577  *  follow to enable the new class mode:
578  *    1.  Do a PHY soft reset.
579  *    2.  Restart auto-negotiation or force link.
580  **/
581 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
582 {
583         struct e1000_phy_info *phy = &hw->phy;
584         s32 ret_val = E1000_SUCCESS;
585         u16 nvm_data;
586
587         DEBUGFUNC("e1000_set_phy_mode_82540");
588
589         if (hw->mac.type != e1000_82545_rev_3)
590                 goto out;
591
592         ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
593         if (ret_val) {
594                 ret_val = -E1000_ERR_PHY;
595                 goto out;
596         }
597
598         if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
599                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
600                 if (ret_val) {
601                         ret_val = -E1000_ERR_PHY;
602                         goto out;
603                 }
604                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
605                 if (ret_val) {
606                         ret_val = -E1000_ERR_PHY;
607                         goto out;
608                 }
609
610                 phy->reset_disable = false;
611         }
612
613 out:
614         return ret_val;
615 }
616
617 /**
618  * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
619  * @hw: pointer to the HW structure
620  *
621  * In the case of a PHY power down to save power, or to turn off link during a
622  * driver unload, or wake on lan is not enabled, remove the link.
623  **/
624 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
625 {
626         /* If the management interface is not enabled, then power down */
627         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
628                 e1000_power_down_phy_copper(hw);
629
630         return;
631 }
632
633 /**
634  *  e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
635  *  @hw: pointer to the HW structure
636  *
637  *  Clears the hardware counters by reading the counter registers.
638  **/
639 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
640 {
641         DEBUGFUNC("e1000_clear_hw_cntrs_82540");
642
643         e1000_clear_hw_cntrs_base_generic(hw);
644
645 #if 0
646         E1000_READ_REG(hw, E1000_PRC64);
647         E1000_READ_REG(hw, E1000_PRC127);
648         E1000_READ_REG(hw, E1000_PRC255);
649         E1000_READ_REG(hw, E1000_PRC511);
650         E1000_READ_REG(hw, E1000_PRC1023);
651         E1000_READ_REG(hw, E1000_PRC1522);
652         E1000_READ_REG(hw, E1000_PTC64);
653         E1000_READ_REG(hw, E1000_PTC127);
654         E1000_READ_REG(hw, E1000_PTC255);
655         E1000_READ_REG(hw, E1000_PTC511);
656         E1000_READ_REG(hw, E1000_PTC1023);
657         E1000_READ_REG(hw, E1000_PTC1522);
658
659         E1000_READ_REG(hw, E1000_ALGNERRC);
660         E1000_READ_REG(hw, E1000_RXERRC);
661         E1000_READ_REG(hw, E1000_TNCRS);
662         E1000_READ_REG(hw, E1000_CEXTERR);
663         E1000_READ_REG(hw, E1000_TSCTC);
664         E1000_READ_REG(hw, E1000_TSCTFC);
665
666         E1000_READ_REG(hw, E1000_MGTPRC);
667         E1000_READ_REG(hw, E1000_MGTPDC);
668         E1000_READ_REG(hw, E1000_MGTPTC);
669 #endif
670 }
671
672 /**
673  *  e1000_read_mac_addr_82540 - Read device MAC address
674  *  @hw: pointer to the HW structure
675  *
676  *  Reads the device MAC address from the EEPROM and stores the value.
677  *  Since devices with two ports use the same EEPROM, we increment the
678  *  last bit in the MAC address for the second port.
679  *
680  *  This version is being used over generic because of customer issues
681  *  with VmWare and Virtual Box when using generic. It seems in
682  *  the emulated 82545, RAR[0] does NOT have a valid address after a
683  *  reset, this older method works and using this breaks nothing for
684  *  these legacy adapters.
685  **/
686 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
687 {
688         s32 ret_val = E1000_SUCCESS;
689         u16 offset, nvm_data, i;
690
691         DEBUGFUNC("e1000_read_mac_addr");
692
693         for (i = 0; i < ETH_ADDR_LEN; i += 2) {
694                 offset = i >> 1;
695                 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
696                 if (ret_val) {
697                         DEBUGOUT("NVM Read Error\n");
698                         goto out;
699                 }
700                 hw->mac.perm_addr[i] = (u8) (nvm_data & 0xFF);
701                 hw->mac.perm_addr[i + 1] = (u8) (nvm_data >> 8);
702         }
703
704         /* Flip last bit of mac address if we're on second port */
705         if (hw->bus.func == E1000_FUNC_1)
706                 hw->mac.perm_addr[5] ^= 1;
707
708         for (i = 0; i < ETH_ADDR_LEN; i++)
709                 hw->mac.addr[i] = hw->mac.perm_addr[i];
710
711 out:
712         return ret_val;
713 }
714
715 static struct pci_device_id e1000_82540_nics[] = {
716         PCI_ROM(0x8086, 0x100E, "E1000_DEV_ID_82540EM", "E1000_DEV_ID_82540EM",
717                         e1000_82540),
718         PCI_ROM(0x8086, 0x1015, "E1000_DEV_ID_82540EM_LOM",
719                         "E1000_DEV_ID_82540EM_LOM", e1000_82540),
720         PCI_ROM(0x8086, 0x1016, "E1000_DEV_ID_82540EP_LOM",
721                         "E1000_DEV_ID_82540EP_LOM", e1000_82540),
722         PCI_ROM(0x8086, 0x1017, "E1000_DEV_ID_82540EP", "E1000_DEV_ID_82540EP",
723                         e1000_82540),
724         PCI_ROM(0x8086, 0x101E, "E1000_DEV_ID_82540EP_LP",
725                         "E1000_DEV_ID_82540EP_LP", e1000_82540),
726         PCI_ROM(0x8086, 0x100F, "E1000_DEV_ID_82545EM_COPPER",
727                         "E1000_DEV_ID_82545EM_COPPER", e1000_82545),
728         PCI_ROM(0x8086, 0x1011, "E1000_DEV_ID_82545EM_FIBER",
729                         "E1000_DEV_ID_82545EM_FIBER", e1000_82545),
730         PCI_ROM(0x8086, 0x1026, "E1000_DEV_ID_82545GM_COPPER",
731                         "E1000_DEV_ID_82545GM_COPPER", e1000_82545_rev_3),
732         PCI_ROM(0x8086, 0x1027, "E1000_DEV_ID_82545GM_FIBER",
733                         "E1000_DEV_ID_82545GM_FIBER", e1000_82545_rev_3),
734         PCI_ROM(0x8086, 0x1028, "E1000_DEV_ID_82545GM_SERDES",
735                         "E1000_DEV_ID_82545GM_SERDES", e1000_82545_rev_3),
736         PCI_ROM(0x8086, 0x1010, "E1000_DEV_ID_82546EB_COPPER",
737                         "E1000_DEV_ID_82546EB_COPPER", e1000_82546),
738         PCI_ROM(0x8086, 0x1012, "E1000_DEV_ID_82546EB_FIBER",
739                         "E1000_DEV_ID_82546EB_FIBER", e1000_82546),
740         PCI_ROM(0x8086, 0x101D, "E1000_DEV_ID_82546EB_QUAD_COPPER",
741                         "E1000_DEV_ID_82546EB_QUAD_COPPER", e1000_82546),
742         PCI_ROM(0x8086, 0x1079, "E1000_DEV_ID_82546GB_COPPER",
743                         "E1000_DEV_ID_82546GB_COPPER", e1000_82546_rev_3),
744         PCI_ROM(0x8086, 0x107A, "E1000_DEV_ID_82546GB_FIBER",
745                         "E1000_DEV_ID_82546GB_FIBER", e1000_82546_rev_3),
746         PCI_ROM(0x8086, 0x107B, "E1000_DEV_ID_82546GB_SERDES",
747                         "E1000_DEV_ID_82546GB_SERDES", e1000_82546_rev_3),
748         PCI_ROM(0x8086, 0x108A, "E1000_DEV_ID_82546GB_PCIE",
749                         "E1000_DEV_ID_82546GB_PCIE", e1000_82546_rev_3),
750         PCI_ROM(0x8086, 0x1099, "E1000_DEV_ID_82546GB_QUAD_COPPER",
751                         "E1000_DEV_ID_82546GB_QUAD_COPPER", e1000_82546_rev_3),
752         PCI_ROM(0x8086, 0x10B5, "E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3",
753                         "E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3", e1000_82546_rev_3),
754 };
755
756 struct pci_driver e1000_82540_driver __pci_driver = {
757         .ids = e1000_82540_nics,
758         .id_count = (sizeof(e1000_82540_nics) / sizeof(e1000_82540_nics[0])),
759         .probe = e1000_probe,
760         .remove = e1000_remove,
761 };