Bus space barriers (XCC)
[akaros.git] / kern / drivers / net / bxe / ecore_hsi.h
1 /*-
2  * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
18  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24  * THE POSSIBILITY OF SUCH DAMAGE.
25  */
26
27
28 //__FBSDID("$FreeBSD: head/sys/dev/bxe/ecore_hsi.h 265411 2014-05-06 02:32:27Z davidcs $");
29
30 #ifndef ECORE_HSI_H
31 #define ECORE_HSI_H
32
33 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
34
35 struct license_key {
36     uint32_t reserved[6];
37
38     uint32_t max_iscsi_conn;
39 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK  0xFFFF
40 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
41 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK  0xFFFF0000
42 #define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16
43
44     uint32_t reserved_a;
45
46     uint32_t max_fcoe_conn;
47 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK  0xFFFF
48 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
49 #define LICENSE_MAX_FCOE_INIT_CONN_MASK  0xFFFF0000
50 #define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16
51
52     uint32_t reserved_b[4];
53 };
54
55 typedef struct license_key license_key_t;
56
57
58 /****************************************************************************
59  * Shared HW configuration                                                  *
60  ****************************************************************************/
61 #define PIN_CFG_NA                          0x00000000
62 #define PIN_CFG_GPIO0_P0                    0x00000001
63 #define PIN_CFG_GPIO1_P0                    0x00000002
64 #define PIN_CFG_GPIO2_P0                    0x00000003
65 #define PIN_CFG_GPIO3_P0                    0x00000004
66 #define PIN_CFG_GPIO0_P1                    0x00000005
67 #define PIN_CFG_GPIO1_P1                    0x00000006
68 #define PIN_CFG_GPIO2_P1                    0x00000007
69 #define PIN_CFG_GPIO3_P1                    0x00000008
70 #define PIN_CFG_EPIO0                       0x00000009
71 #define PIN_CFG_EPIO1                       0x0000000a
72 #define PIN_CFG_EPIO2                       0x0000000b
73 #define PIN_CFG_EPIO3                       0x0000000c
74 #define PIN_CFG_EPIO4                       0x0000000d
75 #define PIN_CFG_EPIO5                       0x0000000e
76 #define PIN_CFG_EPIO6                       0x0000000f
77 #define PIN_CFG_EPIO7                       0x00000010
78 #define PIN_CFG_EPIO8                       0x00000011
79 #define PIN_CFG_EPIO9                       0x00000012
80 #define PIN_CFG_EPIO10                      0x00000013
81 #define PIN_CFG_EPIO11                      0x00000014
82 #define PIN_CFG_EPIO12                      0x00000015
83 #define PIN_CFG_EPIO13                      0x00000016
84 #define PIN_CFG_EPIO14                      0x00000017
85 #define PIN_CFG_EPIO15                      0x00000018
86 #define PIN_CFG_EPIO16                      0x00000019
87 #define PIN_CFG_EPIO17                      0x0000001a
88 #define PIN_CFG_EPIO18                      0x0000001b
89 #define PIN_CFG_EPIO19                      0x0000001c
90 #define PIN_CFG_EPIO20                      0x0000001d
91 #define PIN_CFG_EPIO21                      0x0000001e
92 #define PIN_CFG_EPIO22                      0x0000001f
93 #define PIN_CFG_EPIO23                      0x00000020
94 #define PIN_CFG_EPIO24                      0x00000021
95 #define PIN_CFG_EPIO25                      0x00000022
96 #define PIN_CFG_EPIO26                      0x00000023
97 #define PIN_CFG_EPIO27                      0x00000024
98 #define PIN_CFG_EPIO28                      0x00000025
99 #define PIN_CFG_EPIO29                      0x00000026
100 #define PIN_CFG_EPIO30                      0x00000027
101 #define PIN_CFG_EPIO31                      0x00000028
102
103 /* EPIO definition */
104 #define EPIO_CFG_NA                         0x00000000
105 #define EPIO_CFG_EPIO0                      0x00000001
106 #define EPIO_CFG_EPIO1                      0x00000002
107 #define EPIO_CFG_EPIO2                      0x00000003
108 #define EPIO_CFG_EPIO3                      0x00000004
109 #define EPIO_CFG_EPIO4                      0x00000005
110 #define EPIO_CFG_EPIO5                      0x00000006
111 #define EPIO_CFG_EPIO6                      0x00000007
112 #define EPIO_CFG_EPIO7                      0x00000008
113 #define EPIO_CFG_EPIO8                      0x00000009
114 #define EPIO_CFG_EPIO9                      0x0000000a
115 #define EPIO_CFG_EPIO10                     0x0000000b
116 #define EPIO_CFG_EPIO11                     0x0000000c
117 #define EPIO_CFG_EPIO12                     0x0000000d
118 #define EPIO_CFG_EPIO13                     0x0000000e
119 #define EPIO_CFG_EPIO14                     0x0000000f
120 #define EPIO_CFG_EPIO15                     0x00000010
121 #define EPIO_CFG_EPIO16                     0x00000011
122 #define EPIO_CFG_EPIO17                     0x00000012
123 #define EPIO_CFG_EPIO18                     0x00000013
124 #define EPIO_CFG_EPIO19                     0x00000014
125 #define EPIO_CFG_EPIO20                     0x00000015
126 #define EPIO_CFG_EPIO21                     0x00000016
127 #define EPIO_CFG_EPIO22                     0x00000017
128 #define EPIO_CFG_EPIO23                     0x00000018
129 #define EPIO_CFG_EPIO24                     0x00000019
130 #define EPIO_CFG_EPIO25                     0x0000001a
131 #define EPIO_CFG_EPIO26                     0x0000001b
132 #define EPIO_CFG_EPIO27                     0x0000001c
133 #define EPIO_CFG_EPIO28                     0x0000001d
134 #define EPIO_CFG_EPIO29                     0x0000001e
135 #define EPIO_CFG_EPIO30                     0x0000001f
136 #define EPIO_CFG_EPIO31                     0x00000020
137
138 struct mac_addr {
139         uint32_t upper;
140         uint32_t lower;
141 };
142
143
144 struct shared_hw_cfg {                   /* NVRAM Offset */
145         /* Up to 16 bytes of NULL-terminated string */
146         uint8_t  part_num[16];              /* 0x104 */
147
148         uint32_t config;                        /* 0x114 */
149         #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
150                 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT             0
151                 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V              0x00000000
152                 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V              0x00000001
153
154         #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
155
156             #define SHARED_HW_CFG_BEACON_WOL_EN                  0x00000008
157
158             #define SHARED_HW_CFG_PCIE_GEN3_DISABLED            0x00000000
159             #define SHARED_HW_CFG_PCIE_GEN3_ENABLED             0x00000010
160
161         #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
162                 #define SHARED_HW_CFG_MFW_SELECT_SHIFT               8
163         /* Whatever MFW found in NVM
164            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
165                 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT             0x00000000
166                 #define SHARED_HW_CFG_MFW_SELECT_NC_SI               0x00000100
167                 #define SHARED_HW_CFG_MFW_SELECT_UMP                 0x00000200
168                 #define SHARED_HW_CFG_MFW_SELECT_IPMI                0x00000300
169         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
170           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
171                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI    0x00000400
172         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
173           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
174                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI      0x00000500
175         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
176           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
177                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP     0x00000600
178
179         /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For
180            backwards compatibility, value of 0 is disabling this feature.
181             That means that though 0 is a valid value, it cannot be
182             configured. */
183         #define SHARED_HW_CFG_G2_TX_DRIVE_MASK                        0x0000F000
184         #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT                       12
185
186         #define SHARED_HW_CFG_LED_MODE_MASK                 0x000F0000
187                 #define SHARED_HW_CFG_LED_MODE_SHIFT                 16
188                 #define SHARED_HW_CFG_LED_MAC1                       0x00000000
189                 #define SHARED_HW_CFG_LED_PHY1                       0x00010000
190                 #define SHARED_HW_CFG_LED_PHY2                       0x00020000
191                 #define SHARED_HW_CFG_LED_PHY3                       0x00030000
192                 #define SHARED_HW_CFG_LED_MAC2                       0x00040000
193                 #define SHARED_HW_CFG_LED_PHY4                       0x00050000
194                 #define SHARED_HW_CFG_LED_PHY5                       0x00060000
195                 #define SHARED_HW_CFG_LED_PHY6                       0x00070000
196                 #define SHARED_HW_CFG_LED_MAC3                       0x00080000
197                 #define SHARED_HW_CFG_LED_PHY7                       0x00090000
198                 #define SHARED_HW_CFG_LED_PHY9                       0x000a0000
199                 #define SHARED_HW_CFG_LED_PHY11                      0x000b0000
200                 #define SHARED_HW_CFG_LED_MAC4                       0x000c0000
201                 #define SHARED_HW_CFG_LED_PHY8                       0x000d0000
202                 #define SHARED_HW_CFG_LED_EXTPHY1                    0x000e0000
203                 #define SHARED_HW_CFG_LED_EXTPHY2                    0x000f0000
204
205     #define SHARED_HW_CFG_SRIOV_MASK                    0x40000000
206                 #define SHARED_HW_CFG_SRIOV_DISABLED                 0x00000000
207                 #define SHARED_HW_CFG_SRIOV_ENABLED                  0x40000000
208
209         #define SHARED_HW_CFG_ATC_MASK                      0x80000000
210                 #define SHARED_HW_CFG_ATC_DISABLED                   0x00000000
211                 #define SHARED_HW_CFG_ATC_ENABLED                    0x80000000
212
213         uint32_t config2;                           /* 0x118 */
214
215         #define SHARED_HW_CFG_PCIE_GEN2_MASK                0x00000100
216             #define SHARED_HW_CFG_PCIE_GEN2_SHIFT                8
217             #define SHARED_HW_CFG_PCIE_GEN2_DISABLED             0x00000000
218         #define SHARED_HW_CFG_PCIE_GEN2_ENABLED              0x00000100
219
220         #define SHARED_HW_CFG_SMBUS_TIMING_MASK             0x00001000
221                 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ            0x00000000
222                 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ            0x00001000
223
224         #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
225
226
227                 /* Output low when PERST is asserted */
228         #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK       0x00008000
229                 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED    0x00000000
230                 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED     0x00008000
231
232         #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK    0x00070000
233                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT    16
234                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW       0x00000000
235                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB      0x00010000
236                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB    0x00020000
237                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB    0x00030000
238
239         /*  The fan failure mechanism is usually related to the PHY type
240               since the power consumption of the board is determined by the PHY.
241               Currently, fan is required for most designs with SFX7101, BCM8727
242               and BCM8481. If a fan is not required for a board which uses one
243               of those PHYs, this field should be set to "Disabled". If a fan is
244               required for a different PHY type, this option should be set to
245               "Enabled". The fan failure indication is expected on SPIO5 */
246         #define SHARED_HW_CFG_FAN_FAILURE_MASK              0x00180000
247                 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT              19
248                 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE           0x00000000
249                 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED           0x00080000
250                 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED            0x00100000
251
252                 /* ASPM Power Management support */
253         #define SHARED_HW_CFG_ASPM_SUPPORT_MASK             0x00600000
254                 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT             21
255                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED    0x00000000
256                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED      0x00200000
257                 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED       0x00400000
258                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED   0x00600000
259
260         /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
261            tl_control_0 (register 0x2800) */
262         #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK         0x00800000
263                 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED      0x00000000
264                 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED       0x00800000
265
266
267         /*  Set the MDC/MDIO access for the first external phy */
268         #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000
269                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT         26
270                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE      0x00000000
271                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0         0x04000000
272                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1         0x08000000
273                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH          0x0c000000
274                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED       0x10000000
275
276         /*  Set the MDC/MDIO access for the second external phy */
277         #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000
278                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT         29
279                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE      0x00000000
280                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0         0x20000000
281                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1         0x40000000
282                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH          0x60000000
283                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED       0x80000000
284
285         /*  Max number of PF MSIX vectors */
286         uint32_t config_3;                                       /* 0x11C */
287         #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK                    0x0000007F
288         #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT                   0
289
290         uint32_t ump_nc_si_config;                      /* 0x120 */
291         #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
292                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT       0
293                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC         0x00000000
294                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY         0x00000001
295                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII         0x00000000
296                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII        0x00000002
297
298         /* Reserved bits: 226-230 */
299
300         /*  The output pin template BSC_SEL which selects the I2C for this
301         port in the I2C Mux */
302         uint32_t board;                 /* 0x124 */
303         #define SHARED_HW_CFG_E3_I2C_MUX0_MASK              0x0000003F
304             #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT              0
305
306         #define SHARED_HW_CFG_E3_I2C_MUX1_MASK              0x00000FC0
307         #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT                      6
308         /* Use the PIN_CFG_XXX defines on top */
309         #define SHARED_HW_CFG_BOARD_REV_MASK                0x00FF0000
310         #define SHARED_HW_CFG_BOARD_REV_SHIFT                        16
311
312         #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0F000000
313         #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT                  24
314
315         #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xF0000000
316         #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT                  28
317
318         uint32_t wc_lane_config;                                    /* 0x128 */
319         #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK            0x0000FFFF
320                 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT            0
321                 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210         0x00001b1b
322                 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123         0x00001be4
323                 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213         0x000027d8
324                 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120         0x0000d827
325                 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210         0x0000e41b
326                 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123         0x0000e4e4
327         #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK         0x000000FF
328         #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                 0
329         #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK         0x0000FF00
330         #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                 8
331
332         /* TX lane Polarity swap */
333         #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED     0x00010000
334         #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED     0x00020000
335         #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED     0x00040000
336         #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED     0x00080000
337         /* TX lane Polarity swap */
338         #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED     0x00100000
339         #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED     0x00200000
340         #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED     0x00400000
341         #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED     0x00800000
342
343         /*  Selects the port layout of the board */
344         #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK           0x0F000000
345                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT           24
346                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01           0x00000000
347                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10           0x01000000
348                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123         0x02000000
349                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032         0x03000000
350                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301         0x04000000
351                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210         0x05000000
352 };
353
354
355 /****************************************************************************
356  * Port HW configuration                                                    *
357  ****************************************************************************/
358 struct port_hw_cfg {                /* port 0: 0x12c  port 1: 0x2bc */
359
360         uint32_t pci_id;
361         #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000FFFF
362         #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT             0
363
364         #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xFFFF0000
365         #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT             16
366
367         uint32_t pci_sub_id;
368         #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000FFFF
369         #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT      0
370
371         #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xFFFF0000
372         #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT      16
373
374         uint32_t power_dissipated;
375         #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000FF
376         #define PORT_HW_CFG_POWER_DIS_D0_SHIFT                       0
377         #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000FF00
378         #define PORT_HW_CFG_POWER_DIS_D1_SHIFT                       8
379         #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00FF0000
380         #define PORT_HW_CFG_POWER_DIS_D2_SHIFT                       16
381         #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xFF000000
382         #define PORT_HW_CFG_POWER_DIS_D3_SHIFT                       24
383
384         uint32_t power_consumed;
385         #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000FF
386         #define PORT_HW_CFG_POWER_CONS_D0_SHIFT                      0
387         #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000FF00
388         #define PORT_HW_CFG_POWER_CONS_D1_SHIFT                      8
389         #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00FF0000
390         #define PORT_HW_CFG_POWER_CONS_D2_SHIFT                      16
391         #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xFF000000
392         #define PORT_HW_CFG_POWER_CONS_D3_SHIFT                      24
393
394         uint32_t mac_upper;
395         uint32_t mac_lower;                                      /* 0x140 */
396         #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000FFFF
397         #define PORT_HW_CFG_UPPERMAC_SHIFT                           0
398
399
400         uint32_t iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
401         uint32_t iscsi_mac_lower;
402
403         uint32_t rdma_mac_upper;   /* Upper 16 bits are always zeroes */
404         uint32_t rdma_mac_lower;
405
406         uint32_t serdes_config;
407         #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
408         #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT         0
409
410         #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0xFFFF0000
411         #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT            16
412
413
414         /*  Default values: 2P-64, 4P-32 */
415         uint32_t reserved;
416
417         uint32_t vf_config;                                         /* 0x15C */
418         #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK           0xFFFF0000
419         #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT                   16
420
421         uint32_t mf_pci_id;                                         /* 0x160 */
422         #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK           0x0000FFFF
423         #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT                   0
424
425         /*  Controls the TX laser of the SFP+ module */
426         uint32_t sfp_ctrl;                                          /* 0x164 */
427         #define PORT_HW_CFG_TX_LASER_MASK                   0x000000FF
428                 #define PORT_HW_CFG_TX_LASER_SHIFT                   0
429                 #define PORT_HW_CFG_TX_LASER_MDIO                    0x00000000
430                 #define PORT_HW_CFG_TX_LASER_GPIO0                   0x00000001
431                 #define PORT_HW_CFG_TX_LASER_GPIO1                   0x00000002
432                 #define PORT_HW_CFG_TX_LASER_GPIO2                   0x00000003
433                 #define PORT_HW_CFG_TX_LASER_GPIO3                   0x00000004
434
435         /*  Controls the fault module LED of the SFP+ */
436         #define PORT_HW_CFG_FAULT_MODULE_LED_MASK           0x0000FF00
437                 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT           8
438                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0           0x00000000
439                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1           0x00000100
440                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2           0x00000200
441                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3           0x00000300
442                 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED        0x00000400
443
444         /*  The output pin TX_DIS that controls the TX laser of the SFP+
445           module. Use the PIN_CFG_XXX defines on top */
446         uint32_t e3_sfp_ctrl;                               /* 0x168 */
447         #define PORT_HW_CFG_E3_TX_LASER_MASK                0x000000FF
448         #define PORT_HW_CFG_E3_TX_LASER_SHIFT                        0
449
450         /*  The output pin for SFPP_TYPE which turns on the Fault module LED */
451         #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK           0x0000FF00
452         #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT                   8
453
454         /*  The input pin MOD_ABS that indicates whether SFP+ module is
455           present or not. Use the PIN_CFG_XXX defines on top */
456         #define PORT_HW_CFG_E3_MOD_ABS_MASK                 0x00FF0000
457         #define PORT_HW_CFG_E3_MOD_ABS_SHIFT                         16
458
459         /*  The output pin PWRDIS_SFP_X which disable the power of the SFP+
460           module. Use the PIN_CFG_XXX defines on top */
461         #define PORT_HW_CFG_E3_PWR_DIS_MASK                 0xFF000000
462         #define PORT_HW_CFG_E3_PWR_DIS_SHIFT                         24
463
464         /*
465          * The input pin which signals module transmit fault. Use the
466          * PIN_CFG_XXX defines on top
467          */
468         uint32_t e3_cmn_pin_cfg;                                    /* 0x16C */
469         #define PORT_HW_CFG_E3_TX_FAULT_MASK                0x000000FF
470         #define PORT_HW_CFG_E3_TX_FAULT_SHIFT                        0
471
472         /*  The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
473          top */
474         #define PORT_HW_CFG_E3_PHY_RESET_MASK               0x0000FF00
475         #define PORT_HW_CFG_E3_PHY_RESET_SHIFT                       8
476
477         /*
478          * The output pin which powers down the PHY. Use the PIN_CFG_XXX
479          * defines on top
480          */
481         #define PORT_HW_CFG_E3_PWR_DOWN_MASK                0x00FF0000
482         #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT                        16
483
484         /*  The output pin values BSC_SEL which selects the I2C for this port
485           in the I2C Mux */
486         #define PORT_HW_CFG_E3_I2C_MUX0_MASK                0x01000000
487         #define PORT_HW_CFG_E3_I2C_MUX1_MASK                0x02000000
488
489
490         /*
491          * The input pin I_FAULT which indicate over-current has occurred.
492          * Use the PIN_CFG_XXX defines on top
493          */
494         uint32_t e3_cmn_pin_cfg1;                                   /* 0x170 */
495         #define PORT_HW_CFG_E3_OVER_CURRENT_MASK            0x000000FF
496         #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT                    0
497
498         /*  pause on host ring */
499         uint32_t generic_features;                               /* 0x174 */
500         #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK                   0x00000001
501         #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT                  0
502         #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED               0x00000000
503         #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED                0x00000001
504
505         /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
506          * LOM recommended and tested value is 0xBEB2. Using a different
507          * value means using a value not tested by BRCM
508          */
509         uint32_t sfi_tap_values;                                 /* 0x178 */
510         #define PORT_HW_CFG_TX_EQUALIZATION_MASK                      0x0000FFFF
511         #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT                     0
512
513         /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
514          * value is 0x2. LOM recommended and tested value is 0x2. Using a
515          * different value means using a value not tested by BRCM
516          */
517         #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK                     0x000F0000
518         #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT                    16
519
520         uint32_t reserved0[5];                              /* 0x17c */
521
522         uint32_t aeu_int_mask;                              /* 0x190 */
523
524         uint32_t media_type;                                        /* 0x194 */
525         #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK            0x000000FF
526         #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT                    0
527
528         #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK            0x0000FF00
529         #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT                    8
530
531         #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK            0x00FF0000
532         #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT                    16
533
534         /*  4 times 16 bits for all 4 lanes. In case external PHY is present
535               (not direct mode), those values will not take effect on the 4 XGXS
536               lanes. For some external PHYs (such as 8706 and 8726) the values
537               will be used to configure the external PHY  in those cases, not
538               all 4 values are needed. */
539         uint16_t xgxs_config_rx[4];                     /* 0x198 */
540         uint16_t xgxs_config_tx[4];                     /* 0x1A0 */
541
542
543         /* For storing FCOE mac on shared memory */
544         uint32_t fcoe_fip_mac_upper;
545         #define PORT_HW_CFG_FCOE_UPPERMAC_MASK              0x0000ffff
546         #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT                      0
547         uint32_t fcoe_fip_mac_lower;
548
549         uint32_t fcoe_wwn_port_name_upper;
550         uint32_t fcoe_wwn_port_name_lower;
551
552         uint32_t fcoe_wwn_node_name_upper;
553         uint32_t fcoe_wwn_node_name_lower;
554
555         /*  wwpn for npiv enabled */
556         uint32_t wwpn_for_npiv_config;                           /* 0x1C0 */
557         #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK                0x00000001
558         #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT               0
559         #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED            0x00000000
560         #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED             0x00000001
561
562         /*  wwpn for npiv valid addresses */
563         uint32_t wwpn_for_npiv_valid_addresses;                  /* 0x1C4 */
564         #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK         0x0000FFFF
565         #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT        0
566
567         struct mac_addr wwpn_for_niv_macs[16];
568
569         /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */
570         uint32_t Reserved1[14];
571
572         uint32_t pf_allocation;                                  /* 0x280 */
573         /* number of vfs per PF, if 0 - sriov disabled */
574         #define PORT_HW_CFG_NUMBER_OF_VFS_MASK                        0x000000FF
575         #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT                       0
576
577         /*  Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
578               84833 only */
579         uint32_t xgbt_phy_cfg;                              /* 0x284 */
580         #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK             0x000000FF
581         #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT                     0
582
583                 uint32_t default_cfg;                       /* 0x288 */
584         #define PORT_HW_CFG_GPIO0_CONFIG_MASK               0x00000003
585                 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT               0
586                 #define PORT_HW_CFG_GPIO0_CONFIG_NA                  0x00000000
587                 #define PORT_HW_CFG_GPIO0_CONFIG_LOW                 0x00000001
588                 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH                0x00000002
589                 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT               0x00000003
590
591         #define PORT_HW_CFG_GPIO1_CONFIG_MASK               0x0000000C
592                 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT               2
593                 #define PORT_HW_CFG_GPIO1_CONFIG_NA                  0x00000000
594                 #define PORT_HW_CFG_GPIO1_CONFIG_LOW                 0x00000004
595                 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH                0x00000008
596                 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT               0x0000000c
597
598         #define PORT_HW_CFG_GPIO2_CONFIG_MASK               0x00000030
599                 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT               4
600                 #define PORT_HW_CFG_GPIO2_CONFIG_NA                  0x00000000
601                 #define PORT_HW_CFG_GPIO2_CONFIG_LOW                 0x00000010
602                 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH                0x00000020
603                 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT               0x00000030
604
605         #define PORT_HW_CFG_GPIO3_CONFIG_MASK               0x000000C0
606                 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT               6
607                 #define PORT_HW_CFG_GPIO3_CONFIG_NA                  0x00000000
608                 #define PORT_HW_CFG_GPIO3_CONFIG_LOW                 0x00000040
609                 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH                0x00000080
610                 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT               0x000000c0
611
612         /*  When KR link is required to be set to force which is not
613               KR-compliant, this parameter determine what is the trigger for it.
614               When GPIO is selected, low input will force the speed. Currently
615               default speed is 1G. In the future, it may be widen to select the
616               forced speed in with another parameter. Note when force-1G is
617               enabled, it override option 56: Link Speed option. */
618         #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK           0x00000F00
619                 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT           8
620                 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED      0x00000000
621                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0        0x00000100
622                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0        0x00000200
623                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0        0x00000300
624                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0        0x00000400
625                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1        0x00000500
626                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1        0x00000600
627                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1        0x00000700
628                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1        0x00000800
629                 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED          0x00000900
630         /*  Enable to determine with which GPIO to reset the external phy */
631         #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK           0x000F0000
632                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT           16
633                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE        0x00000000
634                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0        0x00010000
635                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0        0x00020000
636                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0        0x00030000
637                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0        0x00040000
638                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1        0x00050000
639                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1        0x00060000
640                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1        0x00070000
641                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1        0x00080000
642
643         /*  Enable BAM on KR */
644         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK           0x00100000
645         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT                   20
646         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED                0x00000000
647         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED                 0x00100000
648
649         /*  Enable Common Mode Sense */
650         #define PORT_HW_CFG_ENABLE_CMS_MASK                 0x00200000
651         #define PORT_HW_CFG_ENABLE_CMS_SHIFT                         21
652         #define PORT_HW_CFG_ENABLE_CMS_DISABLED                      0x00000000
653         #define PORT_HW_CFG_ENABLE_CMS_ENABLED                       0x00200000
654
655         /*  Determine the Serdes electrical interface   */
656         #define PORT_HW_CFG_NET_SERDES_IF_MASK              0x0F000000
657         #define PORT_HW_CFG_NET_SERDES_IF_SHIFT                      24
658         #define PORT_HW_CFG_NET_SERDES_IF_SGMII                      0x00000000
659         #define PORT_HW_CFG_NET_SERDES_IF_XFI                        0x01000000
660         #define PORT_HW_CFG_NET_SERDES_IF_SFI                        0x02000000
661         #define PORT_HW_CFG_NET_SERDES_IF_KR                         0x03000000
662         #define PORT_HW_CFG_NET_SERDES_IF_DXGXS                      0x04000000
663         #define PORT_HW_CFG_NET_SERDES_IF_KR2                        0x05000000
664
665         /*  SFP+ main TAP and post TAP volumes */
666         #define PORT_HW_CFG_TAP_LEVELS_MASK                           0x70000000
667         #define PORT_HW_CFG_TAP_LEVELS_SHIFT                          28
668         #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43                0x00000000
669         #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44                0x10000000
670         #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45                0x20000000
671         #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46                0x30000000
672         #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47                0x40000000
673         #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48                0x50000000
674
675         uint32_t speed_capability_mask2;                            /* 0x28C */
676         #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK       0x0000FFFF
677                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT       0
678                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL    0x00000001
679                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF    0x00000002
680             #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF   0x00000004
681                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL   0x00000008
682                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G          0x00000010
683                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G        0x00000020
684                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G         0x00000040
685                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G         0x00000080
686
687         #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK       0xFFFF0000
688                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT       16
689                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL    0x00010000
690                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF    0x00020000
691             #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF   0x00040000
692                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL   0x00080000
693                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G          0x00100000
694                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G        0x00200000
695                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G         0x00400000
696                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G         0x00800000
697
698
699         /*  In the case where two media types (e.g. copper and fiber) are
700               present and electrically active at the same time, PHY Selection
701               will determine which of the two PHYs will be designated as the
702               Active PHY and used for a connection to the network.  */
703         uint32_t multi_phy_config;                                  /* 0x290 */
704         #define PORT_HW_CFG_PHY_SELECTION_MASK              0x00000007
705                 #define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
706                 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
707                 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001
708                 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002
709                 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
710                 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
711
712         /*  When enabled, all second phy nvram parameters will be swapped
713               with the first phy parameters */
714         #define PORT_HW_CFG_PHY_SWAPPED_MASK                0x00000008
715                 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3
716                 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000
717                 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008
718
719
720         /*  Address of the second external phy */
721         uint32_t external_phy_config2;                      /* 0x294 */
722         #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
723         #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT                 0
724
725         /*  The second XGXS external PHY type */
726         #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00
727                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT         8
728                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT        0x00000000
729                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071       0x00000100
730                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072       0x00000200
731                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073       0x00000300
732                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705       0x00000400
733                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706       0x00000500
734                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726       0x00000600
735                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481       0x00000700
736                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101       0x00000800
737                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727       0x00000900
738                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC   0x00000a00
739                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823      0x00000b00
740                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640      0x00000c00
741                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833      0x00000d00
742                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE    0x00000e00
743                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722       0x00000f00
744                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616      0x00001000
745                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834      0x00001100
746                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE       0x0000fd00
747                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN      0x0000ff00
748
749
750         /*  4 times 16 bits for all 4 lanes. For some external PHYs (such as
751               8706, 8726 and 8727) not all 4 values are needed. */
752         uint16_t xgxs_config2_rx[4];                                /* 0x296 */
753         uint16_t xgxs_config2_tx[4];                                /* 0x2A0 */
754
755         uint32_t lane_config;
756         #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000FFFF
757                 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT              0
758                 /* AN and forced */
759                 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123           0x00001b1b
760                 /* forced only */
761                 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210           0x00001be4
762                 /* forced only */
763                 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120           0x0000d8d8
764                 /* forced only */
765                 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210           0x0000e4e4
766         #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000FF
767         #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                   0
768         #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000FF00
769         #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                   8
770         #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000C000
771         #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT               14
772
773         /*  Indicate whether to swap the external phy polarity */
774         #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK          0x00010000
775                 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED       0x00000000
776                 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED        0x00010000
777
778
779         uint32_t external_phy_config;
780         #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000FF
781         #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT                  0
782
783         #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000FF00
784                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT          8
785                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT         0x00000000
786                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071        0x00000100
787                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072        0x00000200
788                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073        0x00000300
789                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705        0x00000400
790                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706        0x00000500
791                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726        0x00000600
792                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481        0x00000700
793                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101        0x00000800
794                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727        0x00000900
795                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC    0x00000a00
796                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823       0x00000b00
797                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640       0x00000c00
798                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833       0x00000d00
799                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE     0x00000e00
800                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722        0x00000f00
801                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616       0x00001000
802                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834       0x00001100
803                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC      0x0000fc00
804                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE        0x0000fd00
805                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN       0x0000ff00
806
807         #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00FF0000
808         #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT                16
809
810         #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xFF000000
811                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT        24
812                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT       0x00000000
813                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482      0x01000000
814                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD    0x02000000
815                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN     0xff000000
816
817         uint32_t speed_capability_mask;
818         #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000FFFF
819                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT        0
820                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL     0x00000001
821                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF     0x00000002
822                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF    0x00000004
823                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL    0x00000008
824                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G           0x00000010
825                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G         0x00000020
826                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G          0x00000040
827                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G          0x00000080
828                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED     0x0000f000
829
830         #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xFFFF0000
831                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT        16
832                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL     0x00010000
833                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF     0x00020000
834                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF    0x00040000
835                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL    0x00080000
836                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G           0x00100000
837                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G         0x00200000
838                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G          0x00400000
839                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G          0x00800000
840                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED     0xf0000000
841
842         /*  A place to hold the original MAC address as a backup */
843         uint32_t backup_mac_upper;                      /* 0x2B4 */
844         uint32_t backup_mac_lower;                      /* 0x2B8 */
845
846 };
847
848
849 /****************************************************************************
850  * Shared Feature configuration                                             *
851  ****************************************************************************/
852 struct shared_feat_cfg {                 /* NVRAM Offset */
853
854         uint32_t config;                        /* 0x450 */
855         #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
856
857         /* Use NVRAM values instead of HW default values */
858         #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
859                                                             0x00000002
860                 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
861                                                                      0x00000000
862                 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
863                                                                      0x00000002
864
865         #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK         0x00000008
866                 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO          0x00000000
867                 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM         0x00000008
868
869         #define SHARED_FEAT_CFG_NCSI_ID_MASK                0x00000030
870         #define SHARED_FEAT_CFG_NCSI_ID_SHIFT                        4
871
872         /*  Override the OTP back to single function mode. When using GPIO,
873               high means only SF, 0 is according to CLP configuration */
874         #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK          0x00000700
875                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT          8
876                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED     0x00000000
877                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF      0x00000100
878                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4          0x00000200
879                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT  0x00000300
880                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE      0x00000400
881
882         /*  Act as if the FCoE license is invalid */
883         #define SHARED_FEAT_CFG_PREVENT_FCOE                0x00001000
884
885     /*  Force FLR capability to all ports */
886         #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY        0x00002000
887
888         /*  Act as if the iSCSI license is invalid */
889         #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK                    0x00004000
890         #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT                   14
891         #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED                0x00000000
892         #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED                 0x00004000
893
894         /* The interval in seconds between sending LLDP packets. Set to zero
895            to disable the feature */
896         #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK     0x00FF0000
897         #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT             16
898
899         /* The assigned device type ID for LLDP usage */
900         #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK    0xFF000000
901         #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT            24
902
903 };
904
905
906 /****************************************************************************
907  * Port Feature configuration                                               *
908  ****************************************************************************/
909 struct port_feat_cfg {              /* port 0: 0x454  port 1: 0x4c8 */
910
911         uint32_t config;
912         #define PORT_FEAT_CFG_BAR1_SIZE_MASK                 0x0000000F
913                 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT                 0
914                 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED              0x00000000
915                 #define PORT_FEAT_CFG_BAR1_SIZE_64K                   0x00000001
916                 #define PORT_FEAT_CFG_BAR1_SIZE_128K                  0x00000002
917                 #define PORT_FEAT_CFG_BAR1_SIZE_256K                  0x00000003
918                 #define PORT_FEAT_CFG_BAR1_SIZE_512K                  0x00000004
919                 #define PORT_FEAT_CFG_BAR1_SIZE_1M                    0x00000005
920                 #define PORT_FEAT_CFG_BAR1_SIZE_2M                    0x00000006
921                 #define PORT_FEAT_CFG_BAR1_SIZE_4M                    0x00000007
922                 #define PORT_FEAT_CFG_BAR1_SIZE_8M                    0x00000008
923                 #define PORT_FEAT_CFG_BAR1_SIZE_16M                   0x00000009
924                 #define PORT_FEAT_CFG_BAR1_SIZE_32M                   0x0000000a
925                 #define PORT_FEAT_CFG_BAR1_SIZE_64M                   0x0000000b
926                 #define PORT_FEAT_CFG_BAR1_SIZE_128M                  0x0000000c
927                 #define PORT_FEAT_CFG_BAR1_SIZE_256M                  0x0000000d
928                 #define PORT_FEAT_CFG_BAR1_SIZE_512M                  0x0000000e
929                 #define PORT_FEAT_CFG_BAR1_SIZE_1G                    0x0000000f
930         #define PORT_FEAT_CFG_BAR2_SIZE_MASK                 0x000000F0
931                 #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT                 4
932                 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED              0x00000000
933                 #define PORT_FEAT_CFG_BAR2_SIZE_64K                   0x00000010
934                 #define PORT_FEAT_CFG_BAR2_SIZE_128K                  0x00000020
935                 #define PORT_FEAT_CFG_BAR2_SIZE_256K                  0x00000030
936                 #define PORT_FEAT_CFG_BAR2_SIZE_512K                  0x00000040
937                 #define PORT_FEAT_CFG_BAR2_SIZE_1M                    0x00000050
938                 #define PORT_FEAT_CFG_BAR2_SIZE_2M                    0x00000060
939                 #define PORT_FEAT_CFG_BAR2_SIZE_4M                    0x00000070
940                 #define PORT_FEAT_CFG_BAR2_SIZE_8M                    0x00000080
941                 #define PORT_FEAT_CFG_BAR2_SIZE_16M                   0x00000090
942                 #define PORT_FEAT_CFG_BAR2_SIZE_32M                   0x000000a0
943                 #define PORT_FEAT_CFG_BAR2_SIZE_64M                   0x000000b0
944                 #define PORT_FEAT_CFG_BAR2_SIZE_128M                  0x000000c0
945                 #define PORT_FEAT_CFG_BAR2_SIZE_256M                  0x000000d0
946                 #define PORT_FEAT_CFG_BAR2_SIZE_512M                  0x000000e0
947                 #define PORT_FEAT_CFG_BAR2_SIZE_1G                    0x000000f0
948
949         #define PORT_FEAT_CFG_DCBX_MASK                     0x00000100
950                 #define PORT_FEAT_CFG_DCBX_DISABLED                  0x00000000
951                 #define PORT_FEAT_CFG_DCBX_ENABLED                   0x00000100
952
953     #define PORT_FEAT_CFG_AUTOGREEEN_MASK               0x00000200
954             #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT               9
955             #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED            0x00000000
956             #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED             0x00000200
957
958         #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK                0x00000C00
959         #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT               10
960         #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT             0x00000000
961         #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE                0x00000400
962         #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI               0x00000800
963         #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH                0x00000c00
964
965         #define PORT_FEATURE_EN_SIZE_MASK                   0x0f000000
966         #define PORT_FEATURE_EN_SIZE_SHIFT                       24
967         #define PORT_FEATURE_WOL_ENABLED                         0x01000000
968         #define PORT_FEATURE_MBA_ENABLED                         0x02000000
969         #define PORT_FEATURE_MFW_ENABLED                         0x04000000
970
971         /* Advertise expansion ROM even if MBA is disabled */
972         #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK        0x08000000
973                 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED     0x00000000
974                 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED      0x08000000
975
976         /* Check the optic vendor via i2c against a list of approved modules
977            in a separate nvram image */
978         #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK         0xE0000000
979                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT         29
980                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
981                                                                      0x00000000
982                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
983                                                                      0x20000000
984                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG   0x40000000
985                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN    0x60000000
986
987         uint32_t wol_config;
988         /* Default is used when driver sets to "auto" mode */
989         #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
990
991         uint32_t mba_config;
992         #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000007
993                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT       0
994                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0x00000000
995                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL         0x00000001
996                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP       0x00000002
997                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB      0x00000003
998                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT   0x00000004
999                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE        0x00000007
1000
1001         #define PORT_FEATURE_MBA_BOOT_RETRY_MASK            0x00000038
1002         #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT                    3
1003
1004     #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
1005         #define PORT_FEATURE_MBA_HOTKEY_MASK                0x00000800
1006                 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S               0x00000000
1007                 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B               0x00000800
1008
1009         #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000FF000
1010                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT          12
1011                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED       0x00000000
1012                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K             0x00001000
1013                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K             0x00002000
1014                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K             0x00003000
1015                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K            0x00004000
1016                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K            0x00005000
1017                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K            0x00006000
1018                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K           0x00007000
1019                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K           0x00008000
1020                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K           0x00009000
1021                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M             0x0000a000
1022                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M             0x0000b000
1023                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M             0x0000c000
1024                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M             0x0000d000
1025                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M            0x0000e000
1026                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M            0x0000f000
1027         #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00F00000
1028         #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT                   20
1029         #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
1030                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT        24
1031                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO         0x00000000
1032                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS          0x01000000
1033                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H       0x02000000
1034                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H       0x03000000
1035         #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3C000000
1036                 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT            26
1037                 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO             0x00000000
1038                 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF         0x04000000
1039                 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL         0x08000000
1040                 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF        0x0c000000
1041                 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL        0x10000000
1042                 #define PORT_FEATURE_MBA_LINK_SPEED_1G               0x14000000
1043                 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G             0x18000000
1044                 #define PORT_FEATURE_MBA_LINK_SPEED_10G              0x1c000000
1045                 #define PORT_FEATURE_MBA_LINK_SPEED_20G              0x20000000
1046
1047         uint32_t Reserved0;                                      /* 0x460 */
1048
1049         uint32_t mba_vlan_cfg;
1050         #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000FFFF
1051         #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT                      0
1052         #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
1053         #define PORT_FEATUTE_BOFM_CFGD_EN                   0x00020000
1054         #define PORT_FEATURE_BOFM_CFGD_FTGT                 0x00040000
1055         #define PORT_FEATURE_BOFM_CFGD_VEN                  0x00080000
1056
1057         uint32_t Reserved1;
1058         uint32_t smbus_config;
1059         #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
1060         #define PORT_FEATURE_SMBUS_ADDR_SHIFT                        1
1061
1062         uint32_t vf_config;
1063         #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK             0x0000000F
1064                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT             0
1065                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED          0x00000000
1066                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K                0x00000001
1067                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K                0x00000002
1068                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K               0x00000003
1069                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K               0x00000004
1070                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K               0x00000005
1071                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K              0x00000006
1072                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K              0x00000007
1073                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K              0x00000008
1074                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M                0x00000009
1075                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M                0x0000000a
1076                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M                0x0000000b
1077                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M                0x0000000c
1078                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M               0x0000000d
1079                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M               0x0000000e
1080                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M               0x0000000f
1081
1082         uint32_t link_config;    /* Used as HW defaults for the driver */
1083
1084     #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
1085                 #define PORT_FEATURE_FLOW_CONTROL_SHIFT              8
1086                 #define PORT_FEATURE_FLOW_CONTROL_AUTO               0x00000000
1087                 #define PORT_FEATURE_FLOW_CONTROL_TX                 0x00000100
1088                 #define PORT_FEATURE_FLOW_CONTROL_RX                 0x00000200
1089                 #define PORT_FEATURE_FLOW_CONTROL_BOTH               0x00000300
1090                 #define PORT_FEATURE_FLOW_CONTROL_NONE               0x00000400
1091                 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX            0x00000500
1092                 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX            0x00000600
1093                 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH          0x00000700
1094
1095     #define PORT_FEATURE_LINK_SPEED_MASK                0x000F0000
1096                 #define PORT_FEATURE_LINK_SPEED_SHIFT                16
1097                 #define PORT_FEATURE_LINK_SPEED_AUTO                 0x00000000
1098                 #define PORT_FEATURE_LINK_SPEED_10M_HALF             0x00010000
1099                 #define PORT_FEATURE_LINK_SPEED_10M_FULL             0x00020000
1100                 #define PORT_FEATURE_LINK_SPEED_100M_HALF            0x00030000
1101                 #define PORT_FEATURE_LINK_SPEED_100M_FULL            0x00040000
1102                 #define PORT_FEATURE_LINK_SPEED_1G                   0x00050000
1103                 #define PORT_FEATURE_LINK_SPEED_2_5G                 0x00060000
1104                 #define PORT_FEATURE_LINK_SPEED_10G_CX4              0x00070000
1105                 #define PORT_FEATURE_LINK_SPEED_20G                  0x00080000
1106
1107         #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
1108                 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT          24
1109                 /* (forced) low speed switch (< 10G) */
1110                 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH            0x00000000
1111                 /* (forced) high speed switch (>= 10G) */
1112                 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH           0x01000000
1113                 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT          0x02000000
1114                 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT      0x03000000
1115
1116
1117         /* The default for MCP link configuration,
1118            uses the same defines as link_config */
1119         uint32_t mfw_wol_link_cfg;
1120
1121         /* The default for the driver of the second external phy,
1122            uses the same defines as link_config */
1123         uint32_t link_config2;                              /* 0x47C */
1124
1125         /* The default for MCP of the second external phy,
1126            uses the same defines as link_config */
1127         uint32_t mfw_wol_link_cfg2;                                 /* 0x480 */
1128
1129
1130         /*  EEE power saving mode */
1131         uint32_t eee_power_mode;                                 /* 0x484 */
1132         #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK                     0x000000FF
1133         #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT                    0
1134         #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED                 0x00000000
1135         #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED                 0x00000001
1136         #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE               0x00000002
1137         #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY              0x00000003
1138
1139
1140         uint32_t Reserved2[16];                                  /* 0x488 */
1141 };
1142
1143 /****************************************************************************
1144  * Device Information                                                       *
1145  ****************************************************************************/
1146 struct shm_dev_info {                           /* size */
1147
1148         uint32_t    bc_rev; /* 8 bits each: major, minor, build */             /* 4 */
1149
1150         struct shared_hw_cfg     shared_hw_config;            /* 40 */
1151
1152         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
1153
1154         struct shared_feat_cfg   shared_feature_config;            /* 4 */
1155
1156         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
1157
1158 };
1159
1160 struct extended_dev_info_shared_cfg {             /* NVRAM OFFSET */
1161
1162         /*  Threshold in celcius to start using the fan */
1163         uint32_t temperature_monitor1;                           /* 0x4000 */
1164         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK     0x0000007F
1165         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT    0
1166
1167         /*  Threshold in celcius to shut down the board */
1168         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK    0x00007F00
1169         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT   8
1170
1171         /*  EPIO of fan temperature status */
1172         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK       0x00FF0000
1173         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT      16
1174         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA         0x00000000
1175         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0      0x00010000
1176         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1      0x00020000
1177         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2      0x00030000
1178         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3      0x00040000
1179         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4      0x00050000
1180         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5      0x00060000
1181         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6      0x00070000
1182         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7      0x00080000
1183         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8      0x00090000
1184         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9      0x000a0000
1185         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10     0x000b0000
1186         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11     0x000c0000
1187         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12     0x000d0000
1188         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13     0x000e0000
1189         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14     0x000f0000
1190         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15     0x00100000
1191         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16     0x00110000
1192         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17     0x00120000
1193         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18     0x00130000
1194         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19     0x00140000
1195         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20     0x00150000
1196         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21     0x00160000
1197         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22     0x00170000
1198         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23     0x00180000
1199         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24     0x00190000
1200         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25     0x001a0000
1201         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26     0x001b0000
1202         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27     0x001c0000
1203         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28     0x001d0000
1204         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29     0x001e0000
1205         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30     0x001f0000
1206         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31     0x00200000
1207
1208         /*  EPIO of shut down temperature status */
1209         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK      0xFF000000
1210         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT     24
1211         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA        0x00000000
1212         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0     0x01000000
1213         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1     0x02000000
1214         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2     0x03000000
1215         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3     0x04000000
1216         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4     0x05000000
1217         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5     0x06000000
1218         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6     0x07000000
1219         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7     0x08000000
1220         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8     0x09000000
1221         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9     0x0a000000
1222         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10    0x0b000000
1223         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11    0x0c000000
1224         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12    0x0d000000
1225         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13    0x0e000000
1226         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14    0x0f000000
1227         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15    0x10000000
1228         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16    0x11000000
1229         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17    0x12000000
1230         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18    0x13000000
1231         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19    0x14000000
1232         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20    0x15000000
1233         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21    0x16000000
1234         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22    0x17000000
1235         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23    0x18000000
1236         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24    0x19000000
1237         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25    0x1a000000
1238         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26    0x1b000000
1239         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27    0x1c000000
1240         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28    0x1d000000
1241         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29    0x1e000000
1242         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30    0x1f000000
1243         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31    0x20000000
1244
1245
1246         /*  EPIO of shut down temperature status */
1247         uint32_t temperature_monitor2;                           /* 0x4004 */
1248         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK         0x0000FFFF
1249         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT        0
1250
1251
1252         /*  MFW flavor to be used */
1253         uint32_t mfw_cfg;                                        /* 0x4008 */
1254         #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK          0x000000FF
1255         #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT         0
1256         #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA            0x00000000
1257         #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A             0x00000001
1258
1259         /*  Should NIC data query remain enabled upon last drv unload */
1260         #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK     0x00000100
1261         #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT    8
1262         #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000
1263         #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED  0x00000100
1264
1265         /*  Hide DCBX feature in CCM/BACS menus */
1266         #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK      0x00010000
1267         #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT     16
1268         #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED  0x00000000
1269         #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED   0x00010000
1270
1271         uint32_t smbus_config;                                   /* 0x400C */
1272         #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK          0x000000FF
1273         #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT         0
1274
1275         /*  Switching regulator loop gain */
1276         uint32_t board_cfg;                                      /* 0x4010 */
1277         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK           0x0000000F
1278         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT          0
1279         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT     0x00000000
1280         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2             0x00000008
1281         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4             0x00000009
1282         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8             0x0000000a
1283         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16            0x0000000b
1284         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8           0x0000000c
1285         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4           0x0000000d
1286         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2           0x0000000e
1287         #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1             0x0000000f
1288
1289         /*  whether shadow swim feature is supported */
1290         #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK         0x00000100
1291         #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT        8
1292         #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED     0x00000000
1293         #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED      0x00000100
1294
1295     /*  whether to show/hide SRIOV menu in CCM */
1296         #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK     0x00000200
1297         #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT    9
1298         #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU          0x00000000
1299         #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU          0x00000200
1300
1301         /*  Overide PCIE revision ID when enabled the,
1302             revision ID will set to B1=='0x11' */
1303         #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK          0x00000400
1304         #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT         10
1305         #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED      0x00000000
1306         #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED       0x00000400
1307
1308         /*  Threshold in celcius for max continuous operation */
1309         uint32_t temperature_report;                             /* 0x4014 */
1310         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK           0x0000007F
1311         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT          0
1312
1313         /*  Threshold in celcius for sensor caution */
1314         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK            0x00007F00
1315         #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT           8
1316
1317         /*  wwn node prefix to be used (unless value is 0) */
1318         uint32_t wwn_prefix;                                     /* 0x4018 */
1319         #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK    0x000000FF
1320         #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT   0
1321
1322         #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK    0x0000FF00
1323         #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT   8
1324
1325         /*  wwn port prefix to be used (unless value is 0) */
1326         #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK    0x00FF0000
1327         #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT   16
1328
1329         /*  wwn port prefix to be used (unless value is 0) */
1330         #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK    0xFF000000
1331         #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT   24
1332
1333         /*  General debug nvm cfg */
1334         uint32_t dbg_cfg_flags;                                  /* 0x401C */
1335         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK                 0x000FFFFF
1336         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT                0
1337         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE               0x00000001
1338         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER     0x00000002
1339         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7    0x00000004
1340         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT   0x00000008
1341         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT  0x00000010
1342         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE   0x00000020
1343         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT   0x00000040
1344         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK  0x00000080
1345         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS      0x00000100
1346         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE       0x00000200
1347         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ          0x00000400
1348         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE   0x00000800
1349         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET     0x00001000
1350         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT  0x00002000
1351         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1       0x00004000
1352         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE        0x00008000
1353         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8     0x00010000
1354         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR   0x00020000
1355         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI          0x00040000
1356         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA      0x00080000
1357
1358         /*  Debug signet rx threshold */
1359         uint32_t dbg_rx_sigdet_threshold;                        /* 0x4020 */
1360         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK       0x00000007
1361         #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT      0
1362
1363     /*  Enable IFFE feature */
1364         uint32_t iffe_features;                                  /* 0x4024 */
1365         #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK         0x00000001
1366         #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT        0
1367         #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED     0x00000000
1368         #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED      0x00000001
1369
1370         /*  Allowable port enablement (bitmask for ports 3-1) */
1371         #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK       0x0000000E
1372         #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT      1
1373
1374         /*  Allow iSCSI offload override */
1375         #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK      0x00000010
1376         #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT     4
1377         #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED  0x00000000
1378         #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED   0x00000010
1379
1380         /*  Allow FCoE offload override */
1381         #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK       0x00000020
1382         #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT      5
1383         #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED   0x00000000
1384         #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED    0x00000020
1385
1386         /*  Tie to adaptor */
1387         #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK         0x00008000
1388         #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT        15
1389         #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED     0x00000000
1390         #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED      0x00008000
1391
1392         /*  Currently enabled port(s) (bitmask for ports 3-1) */
1393         uint32_t current_iffe_mask;                              /* 0x4028 */
1394         #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK         0x0000000E
1395         #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT        1
1396
1397         /*  Current iSCSI offload  */
1398         #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK       0x00000010
1399         #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT      4
1400         #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED   0x00000000
1401         #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED    0x00000010
1402
1403         /*  Current FCoE offload  */
1404         #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK        0x00000020
1405         #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT       5
1406         #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED    0x00000000
1407         #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED     0x00000020
1408
1409         /* FW set this pin to "0" (assert) these signal if either of its MAC
1410          * or PHY specific threshold values is exceeded.
1411          * Values are standard GPIO/EPIO pins.
1412          */
1413         uint32_t threshold_pin;                                  /* 0x402C */
1414         #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK        0x000000FF
1415         #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT       0
1416         #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK        0x0000FF00
1417         #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT       8
1418         #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK       0x00FF0000
1419         #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT      16
1420
1421         /* MAC die temperature threshold in Celsius. */
1422         uint32_t mac_threshold_val;                              /* 0x4030 */
1423         #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK  0x000000FF
1424         #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0
1425         #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK  0x0000FF00
1426         #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8
1427         #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000
1428         #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16
1429
1430         /*  PHY die temperature threshold in Celsius. */
1431         uint32_t phy_threshold_val;                              /* 0x4034 */
1432         #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK  0x000000FF
1433         #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0
1434         #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK  0x0000FF00
1435         #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8
1436         #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000
1437         #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16
1438
1439         /* External pins to communicate with host.
1440          * Values are standard GPIO/EPIO pins.
1441          */
1442         uint32_t host_pin;                                       /* 0x4038 */
1443         #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK         0x000000FF
1444         #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT        0
1445         #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK          0x0000FF00
1446         #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT         8
1447         #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK     0x00FF0000
1448         #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT    16
1449         #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK      0xFF000000
1450         #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT     24
1451 };
1452
1453
1454 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1455         #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1456 #endif
1457
1458 #define FUNC_0              0
1459 #define FUNC_1              1
1460 #define FUNC_2              2
1461 #define FUNC_3              3
1462 #define FUNC_4              4
1463 #define FUNC_5              5
1464 #define FUNC_6              6
1465 #define FUNC_7              7
1466 #define E1_FUNC_MAX         2
1467 #define E1H_FUNC_MAX            8
1468 #define E2_FUNC_MAX         4   /* per path */
1469
1470 #define VN_0                0
1471 #define VN_1                1
1472 #define VN_2                2
1473 #define VN_3                3
1474 #define E1VN_MAX            1
1475 #define E1HVN_MAX           4
1476
1477 #define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */
1478 /* This value (in milliseconds) determines the frequency of the driver
1479  * issuing the PULSE message code.  The firmware monitors this periodic
1480  * pulse to determine when to switch to an OS-absent mode. */
1481 #define DRV_PULSE_PERIOD_MS     250
1482
1483 /* This value (in milliseconds) determines how long the driver should
1484  * wait for an acknowledgement from the firmware before timing out.  Once
1485  * the firmware has timed out, the driver will assume there is no firmware
1486  * running and there won't be any firmware-driver synchronization during a
1487  * driver reset. */
1488 #define FW_ACK_TIME_OUT_MS      5000
1489
1490 #define FW_ACK_POLL_TIME_MS     1
1491
1492 #define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1493
1494 #define MFW_TRACE_SIGNATURE     0x54524342
1495
1496 /****************************************************************************
1497  * Driver <-> FW Mailbox                                                    *
1498  ****************************************************************************/
1499 struct drv_port_mb {
1500
1501         uint32_t link_status;
1502         /* Driver should update this field on any link change event */
1503
1504         #define LINK_STATUS_NONE                                (0<<0)
1505         #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
1506         #define LINK_STATUS_LINK_UP                             0x00000001
1507         #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
1508         #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
1509         #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
1510         #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
1511         #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
1512         #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
1513         #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
1514         #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
1515         #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
1516         #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
1517         #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
1518         #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
1519         #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
1520         #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
1521         #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
1522         #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD             (11<<1)
1523         #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD             (11<<1)
1524
1525         #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
1526         #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
1527
1528         #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
1529         #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
1530         #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
1531
1532         #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
1533         #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
1534         #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
1535         #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
1536         #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
1537         #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
1538         #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
1539
1540         #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
1541         #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
1542
1543         #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
1544         #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
1545
1546         #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
1547         #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
1548         #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
1549         #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
1550         #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
1551
1552         #define LINK_STATUS_SERDES_LINK                         0x00100000
1553
1554         #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
1555         #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
1556         #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
1557         #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE         0x10000000
1558
1559         #define LINK_STATUS_PFC_ENABLED                         0x20000000
1560
1561         #define LINK_STATUS_PHYSICAL_LINK_FLAG                  0x40000000
1562         #define LINK_STATUS_SFP_TX_FAULT                        0x80000000
1563
1564         uint32_t port_stx;
1565
1566         uint32_t stat_nig_timer;
1567
1568         /* MCP firmware does not use this field */
1569         uint32_t ext_phy_fw_version;
1570
1571 };
1572
1573
1574 struct drv_func_mb {
1575
1576         uint32_t drv_mb_header;
1577         #define DRV_MSG_CODE_MASK                       0xffff0000
1578         #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
1579         #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
1580         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
1581         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
1582         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
1583         #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
1584         #define DRV_MSG_CODE_DCC_OK                     0x30000000
1585         #define DRV_MSG_CODE_DCC_FAILURE                0x31000000
1586         #define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
1587         #define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
1588         #define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
1589         #define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
1590         #define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
1591         #define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
1592         #define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
1593
1594         /*
1595          * The optic module verification command requires bootcode
1596          * v5.0.6 or later, te specific optic module verification command
1597          * requires bootcode v5.2.12 or later
1598          */
1599         #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
1600         #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
1601         #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa1000000
1602         #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x00050234
1603         #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED        0xa2000000
1604         #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED        0x00070002
1605         #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x00070014
1606         #define REQ_BC_VER_4_MT_SUPPORTED               0x00070201
1607         #define REQ_BC_VER_4_PFC_STATS_SUPPORTED        0x00070201
1608         #define REQ_BC_VER_4_FCOE_FEATURES              0x00070209
1609
1610         #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb0000000
1611         #define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb2000000
1612         #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF     0x00070401
1613
1614         #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
1615
1616         #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC         0xd0000000
1617         #define DRV_MSG_CODE_AFEX_LISTGET_ACK           0xd1000000
1618         #define DRV_MSG_CODE_AFEX_LISTSET_ACK           0xd2000000
1619         #define DRV_MSG_CODE_AFEX_STATSGET_ACK          0xd3000000
1620         #define DRV_MSG_CODE_AFEX_VIFSET_ACK            0xd4000000
1621
1622         #define DRV_MSG_CODE_DRV_INFO_ACK               0xd8000000
1623         #define DRV_MSG_CODE_DRV_INFO_NACK              0xd9000000
1624
1625         #define DRV_MSG_CODE_EEE_RESULTS_ACK            0xda000000
1626
1627         #define DRV_MSG_CODE_RMMOD                      0xdb000000
1628         #define REQ_BC_VER_4_RMMOD_CMD                  0x0007080f
1629
1630         #define DRV_MSG_CODE_SET_MF_BW                  0xe0000000
1631         #define REQ_BC_VER_4_SET_MF_BW                  0x00060202
1632         #define DRV_MSG_CODE_SET_MF_BW_ACK              0xe1000000
1633
1634         #define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x01000000
1635
1636         #define DRV_MSG_CODE_INITIATE_FLR               0x02000000
1637         #define REQ_BC_VER_4_INITIATE_FLR               0x00070213
1638
1639         #define BIOS_MSG_CODE_LIC_CHALLENGE             0xff010000
1640         #define BIOS_MSG_CODE_LIC_RESPONSE              0xff020000
1641         #define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff030000
1642         #define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff040000
1643
1644         #define DRV_MSG_CODE_IMG_OFFSET_REQ             0xe2000000
1645         #define DRV_MSG_CODE_IMG_SIZE_REQ               0xe3000000
1646
1647         #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
1648
1649         uint32_t drv_mb_param;
1650         #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
1651         #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000
1652
1653         #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER        0x00000001
1654         #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET     0x00000002
1655
1656         #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA          0x0000100a
1657         #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA         0x00002000
1658
1659         #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ          0x00000001
1660         #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ       0x00000002
1661
1662         uint32_t fw_mb_header;
1663         #define FW_MSG_CODE_MASK                        0xffff0000
1664         #define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
1665         #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
1666         #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
1667         /* Load common chip is supported from bc 6.0.0  */
1668         #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
1669         #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
1670
1671         #define FW_MSG_CODE_DRV_LOAD_REFUSED            0x10200000
1672         #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
1673         #define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x20100000
1674         #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20110000
1675         #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20120000
1676         #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
1677         #define FW_MSG_CODE_DCC_DONE                    0x30100000
1678         #define FW_MSG_CODE_LLDP_DONE                   0x40100000
1679         #define FW_MSG_CODE_DIAG_ENTER_DONE             0x50100000
1680         #define FW_MSG_CODE_DIAG_REFUSE                 0x50200000
1681         #define FW_MSG_CODE_DIAG_EXIT_DONE              0x60100000
1682         #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70100000
1683         #define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x70200000
1684         #define FW_MSG_CODE_GET_KEY_DONE                0x80100000
1685         #define FW_MSG_CODE_NO_KEY                      0x80f00000
1686         #define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f80000
1687         #define FW_MSG_CODE_L2B_PRAM_LOADED             0x90100000
1688         #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x90210000
1689         #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x90220000
1690         #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x90230000
1691         #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x90240000
1692         #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa0100000
1693         #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa0200000
1694         #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa0300000
1695         #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
1696         #define FW_MSG_CODE_HW_SET_INVALID_IMAGE        0xb0100000
1697
1698         #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE     0xd0100000
1699         #define FW_MSG_CODE_AFEX_LISTGET_ACK            0xd1100000
1700         #define FW_MSG_CODE_AFEX_LISTSET_ACK            0xd2100000
1701         #define FW_MSG_CODE_AFEX_STATSGET_ACK           0xd3100000
1702         #define FW_MSG_CODE_AFEX_VIFSET_ACK             0xd4100000
1703
1704         #define FW_MSG_CODE_DRV_INFO_ACK                0xd8100000
1705         #define FW_MSG_CODE_DRV_INFO_NACK               0xd9100000
1706
1707         #define FW_MSG_CODE_EEE_RESULS_ACK              0xda100000
1708
1709         #define FW_MSG_CODE_RMMOD_ACK                   0xdb100000
1710
1711         #define FW_MSG_CODE_SET_MF_BW_SENT              0xe0000000
1712         #define FW_MSG_CODE_SET_MF_BW_DONE              0xe1000000
1713
1714         #define FW_MSG_CODE_LINK_CHANGED_ACK            0x01100000
1715
1716         #define FW_MSG_CODE_FLR_ACK                     0x02000000
1717         #define FW_MSG_CODE_FLR_NACK                    0x02100000
1718
1719         #define FW_MSG_CODE_LIC_CHALLENGE               0xff010000
1720         #define FW_MSG_CODE_LIC_RESPONSE                0xff020000
1721         #define FW_MSG_CODE_VIRT_MAC_PRIM               0xff030000
1722         #define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff040000
1723
1724         #define FW_MSG_CODE_IMG_OFFSET_RESPONSE         0xe2100000
1725         #define FW_MSG_CODE_IMG_SIZE_RESPONSE           0xe3100000
1726
1727         #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
1728
1729         uint32_t fw_mb_param;
1730
1731         #define FW_PARAM_INVALID_IMG                    0xffffffff
1732
1733         uint32_t drv_pulse_mb;
1734         #define DRV_PULSE_SEQ_MASK                      0x00007fff
1735         #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
1736         /*
1737          * The system time is in the format of
1738          * (year-2001)*12*32 + month*32 + day.
1739          */
1740         #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
1741         /*
1742          * Indicate to the firmware not to go into the
1743          * OS-absent when it is not getting driver pulse.
1744          * This is used for debugging as well for PXE(MBA).
1745          */
1746
1747         uint32_t mcp_pulse_mb;
1748         #define MCP_PULSE_SEQ_MASK                      0x00007fff
1749         #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
1750         /* Indicates to the driver not to assert due to lack
1751          * of MCP response */
1752         #define MCP_EVENT_MASK                          0xffff0000
1753         #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
1754
1755         uint32_t iscsi_boot_signature;
1756         uint32_t iscsi_boot_block_offset;
1757
1758         uint32_t drv_status;
1759         #define DRV_STATUS_PMF                          0x00000001
1760         #define DRV_STATUS_VF_DISABLED                  0x00000002
1761         #define DRV_STATUS_SET_MF_BW                    0x00000004
1762         #define DRV_STATUS_LINK_EVENT                   0x00000008
1763
1764         #define DRV_STATUS_DCC_EVENT_MASK               0x0000ff00
1765         #define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x00000100
1766         #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x00000200
1767         #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x00000400
1768         #define DRV_STATUS_DCC_RESERVED1                0x00000800
1769         #define DRV_STATUS_DCC_SET_PROTOCOL             0x00001000
1770         #define DRV_STATUS_DCC_SET_PRIORITY             0x00002000
1771
1772         #define DRV_STATUS_DCBX_EVENT_MASK              0x000f0000
1773         #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x00010000
1774         #define DRV_STATUS_AFEX_EVENT_MASK              0x03f00000
1775         #define DRV_STATUS_AFEX_LISTGET_REQ             0x00100000
1776         #define DRV_STATUS_AFEX_LISTSET_REQ             0x00200000
1777         #define DRV_STATUS_AFEX_STATSGET_REQ            0x00400000
1778         #define DRV_STATUS_AFEX_VIFSET_REQ              0x00800000
1779
1780         #define DRV_STATUS_DRV_INFO_REQ                 0x04000000
1781
1782         #define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x08000000
1783
1784         uint32_t virt_mac_upper;
1785         #define VIRT_MAC_SIGN_MASK                      0xffff0000
1786         #define VIRT_MAC_SIGNATURE                      0x564d0000
1787         uint32_t virt_mac_lower;
1788
1789 };
1790
1791
1792 /****************************************************************************
1793  * Management firmware state                                                *
1794  ****************************************************************************/
1795 /* Allocate 440 bytes for management firmware */
1796 #define MGMTFW_STATE_WORD_SIZE                          110
1797
1798 struct mgmtfw_state {
1799         uint32_t opaque[MGMTFW_STATE_WORD_SIZE];
1800 };
1801
1802
1803 /****************************************************************************
1804  * Multi-Function configuration                                             *
1805  ****************************************************************************/
1806 struct shared_mf_cfg {
1807
1808         uint32_t clp_mb;
1809         #define SHARED_MF_CLP_SET_DEFAULT               0x00000000
1810         /* set by CLP */
1811         #define SHARED_MF_CLP_EXIT                      0x00000001
1812         /* set by MCP */
1813         #define SHARED_MF_CLP_EXIT_DONE                 0x00010000
1814
1815 };
1816
1817 struct port_mf_cfg {
1818
1819         uint32_t dynamic_cfg;    /* device control channel */
1820         #define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1821         #define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
1822         #define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK
1823
1824         uint32_t reserved[1];
1825
1826 };
1827
1828 struct func_mf_cfg {
1829
1830         uint32_t config;
1831         /* E/R/I/D */
1832         /* function 0 of each port cannot be hidden */
1833         #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
1834
1835         #define FUNC_MF_CFG_PROTOCOL_MASK               0x00000006
1836         #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000000
1837         #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000002
1838         #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1839         #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000006
1840         #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1841                                 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1842
1843         #define FUNC_MF_CFG_FUNC_DISABLED               0x00000008
1844         #define FUNC_MF_CFG_FUNC_DELETED                0x00000010
1845
1846         #define FUNC_MF_CFG_FUNC_BOOT_MASK              0x00000060
1847         #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL         0x00000000
1848         #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED      0x00000020
1849         #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED       0x00000040
1850
1851         /* PRI */
1852         /* 0 - low priority, 3 - high priority */
1853         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x00000300
1854         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     8
1855         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x00000000
1856
1857         /* MINBW, MAXBW */
1858         /* value range - 0..100, increments in 100Mbps */
1859         #define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff0000
1860         #define FUNC_MF_CFG_MIN_BW_SHIFT                16
1861         #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
1862         #define FUNC_MF_CFG_MAX_BW_MASK                 0xff000000
1863         #define FUNC_MF_CFG_MAX_BW_SHIFT                24
1864         #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000
1865
1866         uint32_t mac_upper;         /* MAC */
1867         #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
1868         #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
1869         #define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
1870         uint32_t mac_lower;
1871         #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
1872
1873         uint32_t e1hov_tag;     /* VNI */
1874         #define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1875         #define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
1876         #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK
1877
1878         /* afex default VLAN ID - 12 bits */
1879         #define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff0000
1880         #define FUNC_MF_CFG_AFEX_VLAN_SHIFT             16
1881
1882         uint32_t afex_config;
1883         #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff
1884         #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    0
1885         #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff00
1886         #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT                   8
1887         #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL                     0x00000100
1888         #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f0000
1889         #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     16
1890
1891         uint32_t pf_allocation;
1892         /* number of vfs in function, if 0 - sriov disabled */
1893         #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK                      0x000000FF
1894         #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT                     0
1895 };
1896
1897 enum mf_cfg_afex_vlan_mode {
1898         FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1899         FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1900         FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1901 };
1902
1903 /* This structure is not applicable and should not be accessed on 57711 */
1904 struct func_ext_cfg {
1905         uint32_t func_cfg;
1906         #define MACP_FUNC_CFG_FLAGS_MASK                0x0000007F
1907         #define MACP_FUNC_CFG_FLAGS_SHIFT               0
1908         #define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
1909         #define MACP_FUNC_CFG_FLAGS_ETHERNET            0x00000002
1910         #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x00000004
1911         #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
1912     #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING        0x00000080
1913
1914         uint32_t iscsi_mac_addr_upper;
1915         uint32_t iscsi_mac_addr_lower;
1916
1917         uint32_t fcoe_mac_addr_upper;
1918         uint32_t fcoe_mac_addr_lower;
1919
1920         uint32_t fcoe_wwn_port_name_upper;
1921         uint32_t fcoe_wwn_port_name_lower;
1922
1923         uint32_t fcoe_wwn_node_name_upper;
1924         uint32_t fcoe_wwn_node_name_lower;
1925
1926         uint32_t preserve_data;
1927         #define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
1928         #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
1929         #define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
1930         #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)
1931         #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)
1932         #define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)
1933 };
1934
1935 struct mf_cfg {
1936
1937         struct shared_mf_cfg    shared_mf_config;       /* 0x4 */
1938         struct port_mf_cfg  port_mf_config[NVM_PATH_MAX][PORT_MAX];
1939     /* 0x10*2=0x20 */
1940         /* for all chips, there are 8 mf functions */
1941         struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1942         /*
1943          * Extended configuration per function  - this array does not exist and
1944          * should not be accessed on 57711
1945          */
1946         struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1947 }; /* 0x224 */
1948
1949 /****************************************************************************
1950  * Shared Memory Region                                                     *
1951  ****************************************************************************/
1952 struct shmem_region {                  /*   SharedMem Offset (size) */
1953
1954         uint32_t         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
1955         #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
1956         #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
1957         /* validity bits */
1958         #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
1959         #define SHR_MEM_VALIDITY_MB                         0x00200000
1960         #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
1961         #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
1962         /* One licensing bit should be set */
1963         #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
1964         #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
1965         #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
1966         #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
1967         /* Active MFW */
1968         #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
1969         #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
1970         #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
1971         #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
1972         #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
1973         #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
1974
1975         struct shm_dev_info dev_info;        /* 0x8     (0x438) */
1976
1977         license_key_t       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1978
1979         /* FW information (for internal FW use) */
1980         uint32_t         fw_info_fio_offset;            /* 0x4a8       (0x4) */
1981         struct mgmtfw_state mgmtfw_state;       /* 0x4ac     (0x1b8) */
1982
1983         struct drv_port_mb  port_mb[PORT_MAX];  /* 0x664 (16*2=0x20) */
1984
1985
1986 #ifdef BMAPI
1987         /* This is a variable length array */
1988         /* the number of function depends on the chip type */
1989         struct drv_func_mb func_mb[1];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1990 #else
1991         /* the number of function depends on the chip type */
1992         struct drv_func_mb  func_mb[];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1993 #endif /* BMAPI */
1994
1995 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1996
1997 /****************************************************************************
1998  * Shared Memory 2 Region                                                   *
1999  ****************************************************************************/
2000 /* The fw_flr_ack is actually built in the following way:                   */
2001 /* 8 bit:  PF ack                                                           */
2002 /* 64 bit: VF ack                                                           */
2003 /* 8 bit:  ios_dis_ack                                                      */
2004 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
2005 /* uint32_t. The fw must have the VF right after the PF since this is how it     */
2006 /* access arrays(it expects always the VF to reside after the PF, and that  */
2007 /* makes the calculation much easier for it. )                              */
2008 /* In order to answer both limitations, and keep the struct small, the code */
2009 /* will abuse the structure defined here to achieve the actual partition    */
2010 /* above                                                                    */
2011 /****************************************************************************/
2012 struct fw_flr_ack {
2013         uint32_t         pf_ack;
2014         uint32_t         vf_ack[1];
2015         uint32_t         iov_dis_ack;
2016 };
2017
2018 struct fw_flr_mb {
2019         uint32_t         aggint;
2020         uint32_t         opgen_addr;
2021         struct fw_flr_ack ack;
2022 };
2023
2024 struct eee_remote_vals {
2025         uint32_t         tx_tw;
2026         uint32_t         rx_tw;
2027 };
2028
2029 /**** SUPPORT FOR SHMEM ARRRAYS ***
2030  * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
2031  * define arrays with storage types smaller then unsigned dwords.
2032  * The macros below add generic support for SHMEM arrays with numeric elements
2033  * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
2034  * array with individual bit-filed elements accessed using shifts and masks.
2035  *
2036  */
2037
2038 /* eb is the bitwidth of a single element */
2039 #define SHMEM_ARRAY_MASK(eb)            ((1<<(eb))-1)
2040 #define SHMEM_ARRAY_ENTRY(i, eb)        ((i)/(32/(eb)))
2041
2042 /* the bit-position macro allows the used to flip the order of the arrays
2043  * elements on a per byte or word boundary.
2044  *
2045  * example: an array with 8 entries each 4 bit wide. This array will fit into
2046  * a single dword. The diagrmas below show the array order of the nibbles.
2047  *
2048  * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
2049  *
2050  *                |                |                |               |
2051  *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |
2052  *                |                |                |               |
2053  *
2054  * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
2055  *
2056  *                |                |                |               |
2057  *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |
2058  *                |                |                |               |
2059  *
2060  * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
2061  *
2062  *                |                |                |               |
2063  *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |
2064  *                |                |                |               |
2065  */
2066 #define SHMEM_ARRAY_BITPOS(i, eb, fb)   \
2067         ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
2068         (((i)%((fb)/(eb))) * (eb)))
2069
2070 #define SHMEM_ARRAY_GET(a, i, eb, fb)                                   \
2071         ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
2072         SHMEM_ARRAY_MASK(eb))
2073
2074 #define SHMEM_ARRAY_SET(a, i, eb, fb, val)                              \
2075 do {                                                                       \
2076         a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<           \
2077         SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
2078         a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
2079         SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
2080 } while (0)
2081
2082
2083 /****START OF DCBX STRUCTURES DECLARATIONS****/
2084 #define DCBX_MAX_NUM_PRI_PG_ENTRIES     8
2085 #define DCBX_PRI_PG_BITWIDTH            4
2086 #define DCBX_PRI_PG_FBITS               8
2087 #define DCBX_PRI_PG_GET(a, i)           \
2088         SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
2089 #define DCBX_PRI_PG_SET(a, i, val)      \
2090         SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
2091 #define DCBX_MAX_NUM_PG_BW_ENTRIES      8
2092 #define DCBX_BW_PG_BITWIDTH             8
2093 #define DCBX_PG_BW_GET(a, i)            \
2094         SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
2095 #define DCBX_PG_BW_SET(a, i, val)       \
2096         SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
2097 #define DCBX_STRICT_PRI_PG              15
2098 #define DCBX_MAX_APP_PROTOCOL           16
2099 #define DCBX_MAX_APP_LOCAL          32
2100 #define FCOE_APP_IDX                    0
2101 #define ISCSI_APP_IDX                   1
2102 #define PREDEFINED_APP_IDX_MAX          2
2103
2104
2105 /* Big/Little endian have the same representation. */
2106 struct dcbx_ets_feature {
2107         /*
2108          * For Admin MIB - is this feature supported by the
2109          * driver | For Local MIB - should this feature be enabled.
2110          */
2111         uint32_t enabled;
2112         uint32_t  pg_bw_tbl[2];
2113         uint32_t  pri_pg_tbl[1];
2114 };
2115
2116 /* Driver structure in LE */
2117 struct dcbx_pfc_feature {
2118 #ifdef __BIG_ENDIAN
2119         uint8_t pri_en_bitmap;
2120         #define DCBX_PFC_PRI_0 0x01
2121         #define DCBX_PFC_PRI_1 0x02
2122         #define DCBX_PFC_PRI_2 0x04
2123         #define DCBX_PFC_PRI_3 0x08
2124         #define DCBX_PFC_PRI_4 0x10
2125         #define DCBX_PFC_PRI_5 0x20
2126         #define DCBX_PFC_PRI_6 0x40
2127         #define DCBX_PFC_PRI_7 0x80
2128         uint8_t pfc_caps;
2129         uint8_t reserved;
2130         uint8_t enabled;
2131 #elif defined(__LITTLE_ENDIAN)
2132         uint8_t enabled;
2133         uint8_t reserved;
2134         uint8_t pfc_caps;
2135         uint8_t pri_en_bitmap;
2136         #define DCBX_PFC_PRI_0 0x01
2137         #define DCBX_PFC_PRI_1 0x02
2138         #define DCBX_PFC_PRI_2 0x04
2139         #define DCBX_PFC_PRI_3 0x08
2140         #define DCBX_PFC_PRI_4 0x10
2141         #define DCBX_PFC_PRI_5 0x20
2142         #define DCBX_PFC_PRI_6 0x40
2143         #define DCBX_PFC_PRI_7 0x80
2144 #endif
2145 };
2146
2147 struct dcbx_app_priority_entry {
2148 #ifdef __BIG_ENDIAN
2149         uint16_t  app_id;
2150         uint8_t  pri_bitmap;
2151         uint8_t  appBitfield;
2152         #define DCBX_APP_ENTRY_VALID         0x01
2153         #define DCBX_APP_ENTRY_SF_MASK       0x30
2154         #define DCBX_APP_ENTRY_SF_SHIFT      4
2155         #define DCBX_APP_SF_ETH_TYPE         0x10
2156         #define DCBX_APP_SF_PORT             0x20
2157 #elif defined(__LITTLE_ENDIAN)
2158         uint8_t appBitfield;
2159         #define DCBX_APP_ENTRY_VALID         0x01
2160         #define DCBX_APP_ENTRY_SF_MASK       0x30
2161         #define DCBX_APP_ENTRY_SF_SHIFT      4
2162         #define DCBX_APP_SF_ETH_TYPE         0x10
2163         #define DCBX_APP_SF_PORT             0x20
2164         uint8_t  pri_bitmap;
2165         uint16_t  app_id;
2166 #endif
2167 };
2168
2169
2170 /* FW structure in BE */
2171 struct dcbx_app_priority_feature {
2172 #ifdef __BIG_ENDIAN
2173         uint8_t reserved;
2174         uint8_t default_pri;
2175         uint8_t tc_supported;
2176         uint8_t enabled;
2177 #elif defined(__LITTLE_ENDIAN)
2178         uint8_t enabled;
2179         uint8_t tc_supported;
2180         uint8_t default_pri;
2181         uint8_t reserved;
2182 #endif
2183         struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
2184 };
2185
2186 /* FW structure in BE */
2187 struct dcbx_features {
2188         /* PG feature */
2189         struct dcbx_ets_feature ets;
2190         /* PFC feature */
2191         struct dcbx_pfc_feature pfc;
2192         /* APP feature */
2193         struct dcbx_app_priority_feature app;
2194 };
2195
2196 /* LLDP protocol parameters */
2197 /* FW structure in BE */
2198 struct lldp_params {
2199 #ifdef __BIG_ENDIAN
2200         uint8_t  msg_fast_tx_interval;
2201         uint8_t  msg_tx_hold;
2202         uint8_t  msg_tx_interval;
2203         uint8_t  admin_status;
2204         #define LLDP_TX_ONLY  0x01
2205         #define LLDP_RX_ONLY  0x02
2206         #define LLDP_TX_RX    0x03
2207         #define LLDP_DISABLED 0x04
2208         uint8_t  reserved1;
2209         uint8_t  tx_fast;
2210         uint8_t  tx_crd_max;
2211         uint8_t  tx_crd;
2212 #elif defined(__LITTLE_ENDIAN)
2213         uint8_t  admin_status;
2214         #define LLDP_TX_ONLY  0x01
2215         #define LLDP_RX_ONLY  0x02
2216         #define LLDP_TX_RX    0x03
2217         #define LLDP_DISABLED 0x04
2218         uint8_t  msg_tx_interval;
2219         uint8_t  msg_tx_hold;
2220         uint8_t  msg_fast_tx_interval;
2221         uint8_t  tx_crd;
2222         uint8_t  tx_crd_max;
2223         uint8_t  tx_fast;
2224         uint8_t  reserved1;
2225 #endif
2226         #define REM_CHASSIS_ID_STAT_LEN 4
2227         #define REM_PORT_ID_STAT_LEN 4
2228         /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
2229         uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
2230         /* Holds remote Port ID TLV header, subtype and 9B of payload. */
2231         uint32_t peer_port_id[REM_PORT_ID_STAT_LEN];
2232 };
2233
2234 struct lldp_dcbx_stat {
2235         #define LOCAL_CHASSIS_ID_STAT_LEN 2
2236         #define LOCAL_PORT_ID_STAT_LEN 2
2237         /* Holds local Chassis ID 8B payload of constant subtype 4. */
2238         uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
2239         /* Holds local Port ID 8B payload of constant subtype 3. */
2240         uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN];
2241         /* Number of DCBX frames transmitted. */
2242         uint32_t num_tx_dcbx_pkts;
2243         /* Number of DCBX frames received. */
2244         uint32_t num_rx_dcbx_pkts;
2245 };
2246
2247 /* ADMIN MIB - DCBX local machine default configuration. */
2248 struct lldp_admin_mib {
2249         uint32_t     ver_cfg_flags;
2250         #define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
2251         #define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
2252         #define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
2253         #define DCBX_ETS_RECO_TX_ENABLED         0x00000008
2254         #define DCBX_ETS_RECO_VALID              0x00000010
2255         #define DCBX_ETS_WILLING                 0x00000020
2256         #define DCBX_PFC_WILLING                 0x00000040
2257         #define DCBX_APP_WILLING                 0x00000080
2258         #define DCBX_VERSION_CEE                 0x00000100
2259         #define DCBX_VERSION_IEEE                0x00000200
2260         #define DCBX_DCBX_ENABLED                0x00000400
2261         #define DCBX_CEE_VERSION_MASK            0x0000f000
2262         #define DCBX_CEE_VERSION_SHIFT           12
2263         #define DCBX_CEE_MAX_VERSION_MASK        0x000f0000
2264         #define DCBX_CEE_MAX_VERSION_SHIFT       16
2265         struct dcbx_features     features;
2266 };
2267
2268 /* REMOTE MIB - remote machine DCBX configuration. */
2269 struct lldp_remote_mib {
2270         uint32_t prefix_seq_num;
2271         uint32_t flags;
2272         #define DCBX_ETS_TLV_RX                  0x00000001
2273         #define DCBX_PFC_TLV_RX                  0x00000002
2274         #define DCBX_APP_TLV_RX                  0x00000004
2275         #define DCBX_ETS_RX_ERROR                0x00000010
2276         #define DCBX_PFC_RX_ERROR                0x00000020
2277         #define DCBX_APP_RX_ERROR                0x00000040
2278         #define DCBX_ETS_REM_WILLING             0x00000100
2279         #define DCBX_PFC_REM_WILLING             0x00000200
2280         #define DCBX_APP_REM_WILLING             0x00000400
2281         #define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
2282         #define DCBX_REMOTE_MIB_VALID            0x00002000
2283         struct dcbx_features features;
2284         uint32_t suffix_seq_num;
2285 };
2286
2287 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
2288 struct lldp_local_mib {
2289         uint32_t prefix_seq_num;
2290         /* Indicates if there is mismatch with negotiation results. */
2291         uint32_t error;
2292         #define DCBX_LOCAL_ETS_ERROR             0x00000001
2293         #define DCBX_LOCAL_PFC_ERROR             0x00000002
2294         #define DCBX_LOCAL_APP_ERROR             0x00000004
2295         #define DCBX_LOCAL_PFC_MISMATCH          0x00000010
2296         #define DCBX_LOCAL_APP_MISMATCH          0x00000020
2297         #define DCBX_REMOTE_MIB_ERROR            0x00000040
2298         #define DCBX_REMOTE_ETS_TLV_NOT_FOUND    0x00000080
2299         #define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x00000100
2300         #define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x00000200
2301         struct dcbx_features   features;
2302         uint32_t suffix_seq_num;
2303 };
2304
2305 struct lldp_local_mib_ext {
2306         uint32_t prefix_seq_num;
2307         /* APP TLV extension - 16 more entries for negotiation results*/
2308         struct dcbx_app_priority_entry  app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL];
2309         uint32_t suffix_seq_num;
2310 };
2311 /***END OF DCBX STRUCTURES DECLARATIONS***/
2312
2313 /***********************************************************/
2314 /*                         Elink section                   */
2315 /***********************************************************/
2316 #define SHMEM_LINK_CONFIG_SIZE 2
2317 struct shmem_lfa {
2318         uint32_t req_duplex;
2319         #define REQ_DUPLEX_PHY0_MASK        0x0000ffff
2320         #define REQ_DUPLEX_PHY0_SHIFT       0
2321         #define REQ_DUPLEX_PHY1_MASK        0xffff0000
2322         #define REQ_DUPLEX_PHY1_SHIFT       16
2323         uint32_t req_flow_ctrl;
2324         #define REQ_FLOW_CTRL_PHY0_MASK     0x0000ffff
2325         #define REQ_FLOW_CTRL_PHY0_SHIFT    0
2326         #define REQ_FLOW_CTRL_PHY1_MASK     0xffff0000
2327         #define REQ_FLOW_CTRL_PHY1_SHIFT    16
2328         uint32_t req_line_speed; /* Also determine AutoNeg */
2329         #define REQ_LINE_SPD_PHY0_MASK      0x0000ffff
2330         #define REQ_LINE_SPD_PHY0_SHIFT     0
2331         #define REQ_LINE_SPD_PHY1_MASK      0xffff0000
2332         #define REQ_LINE_SPD_PHY1_SHIFT     16
2333         uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
2334         uint32_t additional_config;
2335         #define REQ_FC_AUTO_ADV_MASK        0x0000ffff
2336         #define REQ_FC_AUTO_ADV0_SHIFT      0
2337         #define NO_LFA_DUE_TO_DCC_MASK      0x00010000
2338         uint32_t lfa_sts;
2339         #define LFA_LINK_FLAP_REASON_OFFSET             0
2340         #define LFA_LINK_FLAP_REASON_MASK               0x000000ff
2341                 #define LFA_LINK_DOWN                       0x1
2342                 #define LFA_LOOPBACK_ENABLED            0x2
2343                 #define LFA_DUPLEX_MISMATCH                 0x3
2344                 #define LFA_MFW_IS_TOO_OLD                  0x4
2345                 #define LFA_LINK_SPEED_MISMATCH         0x5
2346                 #define LFA_FLOW_CTRL_MISMATCH          0x6
2347                 #define LFA_SPEED_CAP_MISMATCH          0x7
2348                 #define LFA_DCC_LFA_DISABLED            0x8
2349                 #define LFA_EEE_MISMATCH                0x9
2350
2351         #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET        8
2352         #define LINK_FLAP_AVOIDANCE_COUNT_MASK          0x0000ff00
2353
2354         #define LINK_FLAP_COUNT_OFFSET                  16
2355         #define LINK_FLAP_COUNT_MASK                    0x00ff0000
2356
2357         #define LFA_FLAGS_MASK                          0xff000000
2358         #define SHMEM_LFA_DONT_CLEAR_STAT               (1<<24)
2359
2360 };
2361
2362 struct shmem2_region {
2363
2364         uint32_t size;                                  /* 0x0000 */
2365
2366         uint32_t dcc_support;                           /* 0x0004 */
2367         #define SHMEM_DCC_SUPPORT_NONE                      0x00000000
2368         #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
2369         #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
2370         #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
2371         #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
2372         #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
2373
2374         uint32_t ext_phy_fw_version2[PORT_MAX];         /* 0x0008 */
2375         /*
2376          * For backwards compatibility, if the mf_cfg_addr does not exist
2377          * (the size filed is smaller than 0xc) the mf_cfg resides at the
2378          * end of struct shmem_region
2379          */
2380         uint32_t mf_cfg_addr;                           /* 0x0010 */
2381         #define SHMEM_MF_CFG_ADDR_NONE                  0x00000000
2382
2383         struct fw_flr_mb flr_mb;                        /* 0x0014 */
2384         uint32_t dcbx_lldp_params_offset;                       /* 0x0028 */
2385         #define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
2386         uint32_t dcbx_neg_res_offset;                   /* 0x002c */
2387         #define SHMEM_DCBX_NEG_RES_NONE                 0x00000000
2388         uint32_t dcbx_remote_mib_offset;                        /* 0x0030 */
2389         #define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
2390         /*
2391          * The other shmemX_base_addr holds the other path's shmem address
2392          * required for example in case of common phy init, or for path1 to know
2393          * the address of mcp debug trace which is located in offset from shmem
2394          * of path0
2395          */
2396         uint32_t other_shmem_base_addr;                 /* 0x0034 */
2397         uint32_t other_shmem2_base_addr;                        /* 0x0038 */
2398         /*
2399          * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2400          * which were disabled/flred
2401          */
2402         uint32_t mcp_vf_disabled[E2_VF_MAX / 32];               /* 0x003c */
2403
2404         /*
2405          * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2406          * VFs
2407          */
2408         uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2409
2410         uint32_t dcbx_lldp_dcbx_stat_offset;                    /* 0x0064 */
2411         #define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000
2412
2413         /*
2414          * edebug_driver_if field is used to transfer messages between edebug
2415          * app to the driver through shmem2.
2416          *
2417          * message format:
2418          * bits 0-2 -  function number / instance of driver to perform request
2419          * bits 3-5 -  op code / is_ack?
2420          * bits 6-63 - data
2421          */
2422         uint32_t edebug_driver_if[2];                   /* 0x0068 */
2423         #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
2424         #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
2425         #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3
2426
2427         uint32_t nvm_retain_bitmap_addr;                        /* 0x0070 */
2428
2429         /* afex support of that driver */
2430         uint32_t afex_driver_support;                   /* 0x0074 */
2431         #define SHMEM_AFEX_VERSION_MASK                  0x100f
2432         #define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x1001
2433         #define SHMEM_AFEX_REDUCED_DRV_LOADED            0x8000
2434
2435         /* driver receives addr in scratchpad to which it should respond */
2436         uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2437
2438         /*
2439          * generic params from MCP to driver (value depends on the msg sent
2440          * to driver
2441          */
2442         uint32_t afex_param1_to_driver[E2_FUNC_MAX];            /* 0x0088 */
2443         uint32_t afex_param2_to_driver[E2_FUNC_MAX];            /* 0x0098 */
2444
2445         uint32_t swim_base_addr;                                /* 0x0108 */
2446         uint32_t swim_funcs;
2447         uint32_t swim_main_cb;
2448
2449         /*
2450          * bitmap notifying which VIF profiles stored in nvram are enabled by
2451          * switch
2452          */
2453         uint32_t afex_profiles_enabled[2];
2454
2455         /* generic flags controlled by the driver */
2456         uint32_t drv_flags;
2457         #define DRV_FLAGS_DCB_CONFIGURED                0x0
2458         #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED     0x1
2459         #define DRV_FLAGS_DCB_MFW_CONFIGURED    0x2
2460
2461     #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2462                         (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2463                         (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2464         /* Port offset*/
2465         #define DRV_FLAGS_P0_OFFSET             0
2466         #define DRV_FLAGS_P1_OFFSET             16
2467         #define DRV_FLAGS_GET_PORT_OFFSET(_port)        ((0 == _port) ? \
2468                                                 DRV_FLAGS_P0_OFFSET : \
2469                                                 DRV_FLAGS_P1_OFFSET)
2470
2471         #define DRV_FLAGS_GET_PORT_MASK(_port)  (DRV_FLAGS_PORT_MASK << \
2472         DRV_FLAGS_GET_PORT_OFFSET(_port))
2473
2474         #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port)      (1 << ( \
2475         (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))
2476
2477         /* pointer to extended dev_info shared data copied from nvm image */
2478         uint32_t extended_dev_info_shared_addr;
2479         uint32_t ncsi_oem_data_addr;
2480
2481         uint32_t sensor_data_addr;
2482         uint32_t buffer_block_addr;
2483         uint32_t sensor_data_req_update_interval;
2484         uint32_t temperature_in_half_celsius;
2485         uint32_t glob_struct_in_host;
2486
2487         uint32_t dcbx_neg_res_ext_offset;
2488         #define SHMEM_DCBX_NEG_RES_EXT_NONE                     0x00000000
2489
2490         uint32_t drv_capabilities_flag[E2_FUNC_MAX];
2491         #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2492         #define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x00000002
2493         #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x00000004
2494         #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x00000008
2495
2496         uint32_t extended_dev_info_shared_cfg_size;
2497
2498         uint32_t dcbx_en[PORT_MAX];
2499
2500         /* The offset points to the multi threaded meta structure */
2501         uint32_t multi_thread_data_offset;
2502
2503         /* address of DMAable host address holding values from the drivers */
2504         uint32_t drv_info_host_addr_lo;
2505         uint32_t drv_info_host_addr_hi;
2506
2507         /* general values written by the MFW (such as current version) */
2508         uint32_t drv_info_control;
2509         #define DRV_INFO_CONTROL_VER_MASK          0x000000ff
2510         #define DRV_INFO_CONTROL_VER_SHIFT         0
2511         #define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff00
2512         #define DRV_INFO_CONTROL_OP_CODE_SHIFT     8
2513         uint32_t ibft_host_addr; /* initialized by option ROM */
2514
2515         struct eee_remote_vals eee_remote_vals[PORT_MAX];
2516         uint32_t pf_allocation[E2_FUNC_MAX];
2517         #define PF_ALLOACTION_MSIX_VECTORS_MASK    0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */
2518         #define PF_ALLOACTION_MSIX_VECTORS_SHIFT   0
2519
2520         /* the status of EEE auto-negotiation
2521          * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2522          * bits 19:16 the supported modes for EEE.
2523          * bits 23:20 the speeds advertised for EEE.
2524          * bits 27:24 the speeds the Link partner advertised for EEE.
2525          * The supported/adv. modes in bits 27:19 originate from the
2526          * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2527          * bit 28 when 1'b1 EEE was requested.
2528          * bit 29 when 1'b1 tx lpi was requested.
2529          * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2530          * 30:29 are 2'b11.
2531          * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2532          * value. When 1'b1 those bits contains a value times 16 microseconds.
2533          */
2534         uint32_t eee_status[PORT_MAX];
2535         #define SHMEM_EEE_TIMER_MASK               0x0000ffff
2536         #define SHMEM_EEE_SUPPORTED_MASK           0x000f0000
2537         #define SHMEM_EEE_SUPPORTED_SHIFT          16
2538         #define SHMEM_EEE_ADV_STATUS_MASK          0x00f00000
2539                 #define SHMEM_EEE_100M_ADV         (1<<0)
2540                 #define SHMEM_EEE_1G_ADV           (1<<1)
2541                 #define SHMEM_EEE_10G_ADV          (1<<2)
2542         #define SHMEM_EEE_ADV_STATUS_SHIFT         20
2543         #define SHMEM_EEE_LP_ADV_STATUS_MASK       0x0f000000
2544         #define SHMEM_EEE_LP_ADV_STATUS_SHIFT      24
2545         #define SHMEM_EEE_REQUESTED_BIT            0x10000000
2546         #define SHMEM_EEE_LPI_REQUESTED_BIT        0x20000000
2547         #define SHMEM_EEE_ACTIVE_BIT               0x40000000
2548         #define SHMEM_EEE_TIME_OUTPUT_BIT          0x80000000
2549
2550         uint32_t sizeof_port_stats;
2551
2552         /* Link Flap Avoidance */
2553         uint32_t lfa_host_addr[PORT_MAX];
2554
2555     /* External PHY temperature in deg C. */
2556         uint32_t extphy_temps_in_celsius;
2557         #define EXTPHY1_TEMP_MASK                  0x0000ffff
2558         #define EXTPHY1_TEMP_SHIFT                 0
2559
2560         uint32_t ocdata_info_addr;                      /* Offset 0x148 */
2561         uint32_t drv_func_info_addr;                    /* Offset 0x14C */
2562         uint32_t drv_func_info_size;                    /* Offset 0x150 */
2563         uint32_t link_attr_sync[PORT_MAX];              /* Offset 0x154 */
2564         #define LINK_ATTR_SYNC_KR2_ENABLE       (1<<0)
2565
2566         uint32_t ibft_host_addr_hi;  /* Initialize by uEFI ROM */
2567 };
2568
2569
2570 struct emac_stats {
2571         uint32_t     rx_stat_ifhcinoctets;
2572         uint32_t     rx_stat_ifhcinbadoctets;
2573         uint32_t     rx_stat_etherstatsfragments;
2574         uint32_t     rx_stat_ifhcinucastpkts;
2575         uint32_t     rx_stat_ifhcinmulticastpkts;
2576         uint32_t     rx_stat_ifhcinbroadcastpkts;
2577         uint32_t     rx_stat_dot3statsfcserrors;
2578         uint32_t     rx_stat_dot3statsalignmenterrors;
2579         uint32_t     rx_stat_dot3statscarriersenseerrors;
2580         uint32_t     rx_stat_xonpauseframesreceived;
2581         uint32_t     rx_stat_xoffpauseframesreceived;
2582         uint32_t     rx_stat_maccontrolframesreceived;
2583         uint32_t     rx_stat_xoffstateentered;
2584         uint32_t     rx_stat_dot3statsframestoolong;
2585         uint32_t     rx_stat_etherstatsjabbers;
2586         uint32_t     rx_stat_etherstatsundersizepkts;
2587         uint32_t     rx_stat_etherstatspkts64octets;
2588         uint32_t     rx_stat_etherstatspkts65octetsto127octets;
2589         uint32_t     rx_stat_etherstatspkts128octetsto255octets;
2590         uint32_t     rx_stat_etherstatspkts256octetsto511octets;
2591         uint32_t     rx_stat_etherstatspkts512octetsto1023octets;
2592         uint32_t     rx_stat_etherstatspkts1024octetsto1522octets;
2593         uint32_t     rx_stat_etherstatspktsover1522octets;
2594
2595         uint32_t     rx_stat_falsecarriererrors;
2596
2597         uint32_t     tx_stat_ifhcoutoctets;
2598         uint32_t     tx_stat_ifhcoutbadoctets;
2599         uint32_t     tx_stat_etherstatscollisions;
2600         uint32_t     tx_stat_outxonsent;
2601         uint32_t     tx_stat_outxoffsent;
2602         uint32_t     tx_stat_flowcontroldone;
2603         uint32_t     tx_stat_dot3statssinglecollisionframes;
2604         uint32_t     tx_stat_dot3statsmultiplecollisionframes;
2605         uint32_t     tx_stat_dot3statsdeferredtransmissions;
2606         uint32_t     tx_stat_dot3statsexcessivecollisions;
2607         uint32_t     tx_stat_dot3statslatecollisions;
2608         uint32_t     tx_stat_ifhcoutucastpkts;
2609         uint32_t     tx_stat_ifhcoutmulticastpkts;
2610         uint32_t     tx_stat_ifhcoutbroadcastpkts;
2611         uint32_t     tx_stat_etherstatspkts64octets;
2612         uint32_t     tx_stat_etherstatspkts65octetsto127octets;
2613         uint32_t     tx_stat_etherstatspkts128octetsto255octets;
2614         uint32_t     tx_stat_etherstatspkts256octetsto511octets;
2615         uint32_t     tx_stat_etherstatspkts512octetsto1023octets;
2616         uint32_t     tx_stat_etherstatspkts1024octetsto1522octets;
2617         uint32_t     tx_stat_etherstatspktsover1522octets;
2618         uint32_t     tx_stat_dot3statsinternalmactransmiterrors;
2619 };
2620
2621
2622 struct bmac1_stats {
2623         uint32_t        tx_stat_gtpkt_lo;
2624         uint32_t        tx_stat_gtpkt_hi;
2625         uint32_t        tx_stat_gtxpf_lo;
2626         uint32_t        tx_stat_gtxpf_hi;
2627         uint32_t        tx_stat_gtfcs_lo;
2628         uint32_t        tx_stat_gtfcs_hi;
2629         uint32_t        tx_stat_gtmca_lo;
2630         uint32_t        tx_stat_gtmca_hi;
2631         uint32_t        tx_stat_gtbca_lo;
2632         uint32_t        tx_stat_gtbca_hi;
2633         uint32_t        tx_stat_gtfrg_lo;
2634         uint32_t        tx_stat_gtfrg_hi;
2635         uint32_t        tx_stat_gtovr_lo;
2636         uint32_t        tx_stat_gtovr_hi;
2637         uint32_t        tx_stat_gt64_lo;
2638         uint32_t        tx_stat_gt64_hi;
2639         uint32_t        tx_stat_gt127_lo;
2640         uint32_t        tx_stat_gt127_hi;
2641         uint32_t        tx_stat_gt255_lo;
2642         uint32_t        tx_stat_gt255_hi;
2643         uint32_t        tx_stat_gt511_lo;
2644         uint32_t        tx_stat_gt511_hi;
2645         uint32_t        tx_stat_gt1023_lo;
2646         uint32_t        tx_stat_gt1023_hi;
2647         uint32_t        tx_stat_gt1518_lo;
2648         uint32_t        tx_stat_gt1518_hi;
2649         uint32_t        tx_stat_gt2047_lo;
2650         uint32_t        tx_stat_gt2047_hi;
2651         uint32_t        tx_stat_gt4095_lo;
2652         uint32_t        tx_stat_gt4095_hi;
2653         uint32_t        tx_stat_gt9216_lo;
2654         uint32_t        tx_stat_gt9216_hi;
2655         uint32_t        tx_stat_gt16383_lo;
2656         uint32_t        tx_stat_gt16383_hi;
2657         uint32_t        tx_stat_gtmax_lo;
2658         uint32_t        tx_stat_gtmax_hi;
2659         uint32_t        tx_stat_gtufl_lo;
2660         uint32_t        tx_stat_gtufl_hi;
2661         uint32_t        tx_stat_gterr_lo;
2662         uint32_t        tx_stat_gterr_hi;
2663         uint32_t        tx_stat_gtbyt_lo;
2664         uint32_t        tx_stat_gtbyt_hi;
2665
2666         uint32_t        rx_stat_gr64_lo;
2667         uint32_t        rx_stat_gr64_hi;
2668         uint32_t        rx_stat_gr127_lo;
2669         uint32_t        rx_stat_gr127_hi;
2670         uint32_t        rx_stat_gr255_lo;
2671         uint32_t        rx_stat_gr255_hi;
2672         uint32_t        rx_stat_gr511_lo;
2673         uint32_t        rx_stat_gr511_hi;
2674         uint32_t        rx_stat_gr1023_lo;
2675         uint32_t        rx_stat_gr1023_hi;
2676         uint32_t        rx_stat_gr1518_lo;
2677         uint32_t        rx_stat_gr1518_hi;
2678         uint32_t        rx_stat_gr2047_lo;
2679         uint32_t        rx_stat_gr2047_hi;
2680         uint32_t        rx_stat_gr4095_lo;
2681         uint32_t        rx_stat_gr4095_hi;
2682         uint32_t        rx_stat_gr9216_lo;
2683         uint32_t        rx_stat_gr9216_hi;
2684         uint32_t        rx_stat_gr16383_lo;
2685         uint32_t        rx_stat_gr16383_hi;
2686         uint32_t        rx_stat_grmax_lo;
2687         uint32_t        rx_stat_grmax_hi;
2688         uint32_t        rx_stat_grpkt_lo;
2689         uint32_t        rx_stat_grpkt_hi;
2690         uint32_t        rx_stat_grfcs_lo;
2691         uint32_t        rx_stat_grfcs_hi;
2692         uint32_t        rx_stat_grmca_lo;
2693         uint32_t        rx_stat_grmca_hi;
2694         uint32_t        rx_stat_grbca_lo;
2695         uint32_t        rx_stat_grbca_hi;
2696         uint32_t        rx_stat_grxcf_lo;
2697         uint32_t        rx_stat_grxcf_hi;
2698         uint32_t        rx_stat_grxpf_lo;
2699         uint32_t        rx_stat_grxpf_hi;
2700         uint32_t        rx_stat_grxuo_lo;
2701         uint32_t        rx_stat_grxuo_hi;
2702         uint32_t        rx_stat_grjbr_lo;
2703         uint32_t        rx_stat_grjbr_hi;
2704         uint32_t        rx_stat_grovr_lo;
2705         uint32_t        rx_stat_grovr_hi;
2706         uint32_t        rx_stat_grflr_lo;
2707         uint32_t        rx_stat_grflr_hi;
2708         uint32_t        rx_stat_grmeg_lo;
2709         uint32_t        rx_stat_grmeg_hi;
2710         uint32_t        rx_stat_grmeb_lo;
2711         uint32_t        rx_stat_grmeb_hi;
2712         uint32_t        rx_stat_grbyt_lo;
2713         uint32_t        rx_stat_grbyt_hi;
2714         uint32_t        rx_stat_grund_lo;
2715         uint32_t        rx_stat_grund_hi;
2716         uint32_t        rx_stat_grfrg_lo;
2717         uint32_t        rx_stat_grfrg_hi;
2718         uint32_t        rx_stat_grerb_lo;
2719         uint32_t        rx_stat_grerb_hi;
2720         uint32_t        rx_stat_grfre_lo;
2721         uint32_t        rx_stat_grfre_hi;
2722         uint32_t        rx_stat_gripj_lo;
2723         uint32_t        rx_stat_gripj_hi;
2724 };
2725
2726 struct bmac2_stats {
2727         uint32_t        tx_stat_gtpk_lo; /* gtpok */
2728         uint32_t        tx_stat_gtpk_hi; /* gtpok */
2729         uint32_t        tx_stat_gtxpf_lo; /* gtpf */
2730         uint32_t        tx_stat_gtxpf_hi; /* gtpf */
2731         uint32_t        tx_stat_gtpp_lo; /* NEW BMAC2 */
2732         uint32_t        tx_stat_gtpp_hi; /* NEW BMAC2 */
2733         uint32_t        tx_stat_gtfcs_lo;
2734         uint32_t        tx_stat_gtfcs_hi;
2735         uint32_t        tx_stat_gtuca_lo; /* NEW BMAC2 */
2736         uint32_t        tx_stat_gtuca_hi; /* NEW BMAC2 */
2737         uint32_t        tx_stat_gtmca_lo;
2738         uint32_t        tx_stat_gtmca_hi;
2739         uint32_t        tx_stat_gtbca_lo;
2740         uint32_t        tx_stat_gtbca_hi;
2741         uint32_t        tx_stat_gtovr_lo;
2742         uint32_t        tx_stat_gtovr_hi;
2743         uint32_t        tx_stat_gtfrg_lo;
2744         uint32_t        tx_stat_gtfrg_hi;
2745         uint32_t        tx_stat_gtpkt1_lo; /* gtpkt */
2746         uint32_t        tx_stat_gtpkt1_hi; /* gtpkt */
2747         uint32_t        tx_stat_gt64_lo;
2748         uint32_t        tx_stat_gt64_hi;
2749         uint32_t        tx_stat_gt127_lo;
2750         uint32_t        tx_stat_gt127_hi;
2751         uint32_t        tx_stat_gt255_lo;
2752         uint32_t        tx_stat_gt255_hi;
2753         uint32_t        tx_stat_gt511_lo;
2754         uint32_t        tx_stat_gt511_hi;
2755         uint32_t        tx_stat_gt1023_lo;
2756         uint32_t        tx_stat_gt1023_hi;
2757         uint32_t        tx_stat_gt1518_lo;
2758         uint32_t        tx_stat_gt1518_hi;
2759         uint32_t        tx_stat_gt2047_lo;
2760         uint32_t        tx_stat_gt2047_hi;
2761         uint32_t        tx_stat_gt4095_lo;
2762         uint32_t        tx_stat_gt4095_hi;
2763         uint32_t        tx_stat_gt9216_lo;
2764         uint32_t        tx_stat_gt9216_hi;
2765         uint32_t        tx_stat_gt16383_lo;
2766         uint32_t        tx_stat_gt16383_hi;
2767         uint32_t        tx_stat_gtmax_lo;
2768         uint32_t        tx_stat_gtmax_hi;
2769         uint32_t        tx_stat_gtufl_lo;
2770         uint32_t        tx_stat_gtufl_hi;
2771         uint32_t        tx_stat_gterr_lo;
2772         uint32_t        tx_stat_gterr_hi;
2773         uint32_t        tx_stat_gtbyt_lo;
2774         uint32_t        tx_stat_gtbyt_hi;
2775
2776         uint32_t        rx_stat_gr64_lo;
2777         uint32_t        rx_stat_gr64_hi;
2778         uint32_t        rx_stat_gr127_lo;
2779         uint32_t        rx_stat_gr127_hi;
2780         uint32_t        rx_stat_gr255_lo;
2781         uint32_t        rx_stat_gr255_hi;
2782         uint32_t        rx_stat_gr511_lo;
2783         uint32_t        rx_stat_gr511_hi;
2784         uint32_t        rx_stat_gr1023_lo;
2785         uint32_t        rx_stat_gr1023_hi;
2786         uint32_t        rx_stat_gr1518_lo;
2787         uint32_t        rx_stat_gr1518_hi;
2788         uint32_t        rx_stat_gr2047_lo;
2789         uint32_t        rx_stat_gr2047_hi;
2790         uint32_t        rx_stat_gr4095_lo;
2791         uint32_t        rx_stat_gr4095_hi;
2792         uint32_t        rx_stat_gr9216_lo;
2793         uint32_t        rx_stat_gr9216_hi;
2794         uint32_t        rx_stat_gr16383_lo;
2795         uint32_t        rx_stat_gr16383_hi;
2796         uint32_t        rx_stat_grmax_lo;
2797         uint32_t        rx_stat_grmax_hi;
2798         uint32_t        rx_stat_grpkt_lo;
2799         uint32_t        rx_stat_grpkt_hi;
2800         uint32_t        rx_stat_grfcs_lo;
2801         uint32_t        rx_stat_grfcs_hi;
2802         uint32_t        rx_stat_gruca_lo;
2803         uint32_t        rx_stat_gruca_hi;
2804         uint32_t        rx_stat_grmca_lo;
2805         uint32_t        rx_stat_grmca_hi;
2806         uint32_t        rx_stat_grbca_lo;
2807         uint32_t        rx_stat_grbca_hi;
2808         uint32_t        rx_stat_grxpf_lo; /* grpf */
2809         uint32_t        rx_stat_grxpf_hi; /* grpf */
2810         uint32_t        rx_stat_grpp_lo;
2811         uint32_t        rx_stat_grpp_hi;
2812         uint32_t        rx_stat_grxuo_lo; /* gruo */
2813         uint32_t        rx_stat_grxuo_hi; /* gruo */
2814         uint32_t        rx_stat_grjbr_lo;
2815         uint32_t        rx_stat_grjbr_hi;
2816         uint32_t        rx_stat_grovr_lo;
2817         uint32_t        rx_stat_grovr_hi;
2818         uint32_t        rx_stat_grxcf_lo; /* grcf */
2819         uint32_t        rx_stat_grxcf_hi; /* grcf */
2820         uint32_t        rx_stat_grflr_lo;
2821         uint32_t        rx_stat_grflr_hi;
2822         uint32_t        rx_stat_grpok_lo;
2823         uint32_t        rx_stat_grpok_hi;
2824         uint32_t        rx_stat_grmeg_lo;
2825         uint32_t        rx_stat_grmeg_hi;
2826         uint32_t        rx_stat_grmeb_lo;
2827         uint32_t        rx_stat_grmeb_hi;
2828         uint32_t        rx_stat_grbyt_lo;
2829         uint32_t        rx_stat_grbyt_hi;
2830         uint32_t        rx_stat_grund_lo;
2831         uint32_t        rx_stat_grund_hi;
2832         uint32_t        rx_stat_grfrg_lo;
2833         uint32_t        rx_stat_grfrg_hi;
2834         uint32_t        rx_stat_grerb_lo; /* grerrbyt */
2835         uint32_t        rx_stat_grerb_hi; /* grerrbyt */
2836         uint32_t        rx_stat_grfre_lo; /* grfrerr */
2837         uint32_t        rx_stat_grfre_hi; /* grfrerr */
2838         uint32_t        rx_stat_gripj_lo;
2839         uint32_t        rx_stat_gripj_hi;
2840 };
2841
2842 struct mstat_stats {
2843         struct {
2844                 /* OTE MSTAT on E3 has a bug where this register's contents are
2845                  * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2846                  */
2847                 uint32_t tx_gtxpok_lo;
2848                 uint32_t tx_gtxpok_hi;
2849                 uint32_t tx_gtxpf_lo;
2850                 uint32_t tx_gtxpf_hi;
2851                 uint32_t tx_gtxpp_lo;
2852                 uint32_t tx_gtxpp_hi;
2853                 uint32_t tx_gtfcs_lo;
2854                 uint32_t tx_gtfcs_hi;
2855                 uint32_t tx_gtuca_lo;
2856                 uint32_t tx_gtuca_hi;
2857                 uint32_t tx_gtmca_lo;
2858                 uint32_t tx_gtmca_hi;
2859                 uint32_t tx_gtgca_lo;
2860                 uint32_t tx_gtgca_hi;
2861                 uint32_t tx_gtpkt_lo;
2862                 uint32_t tx_gtpkt_hi;
2863                 uint32_t tx_gt64_lo;
2864                 uint32_t tx_gt64_hi;
2865                 uint32_t tx_gt127_lo;
2866                 uint32_t tx_gt127_hi;
2867                 uint32_t tx_gt255_lo;
2868                 uint32_t tx_gt255_hi;
2869                 uint32_t tx_gt511_lo;
2870                 uint32_t tx_gt511_hi;
2871                 uint32_t tx_gt1023_lo;
2872                 uint32_t tx_gt1023_hi;
2873                 uint32_t tx_gt1518_lo;
2874                 uint32_t tx_gt1518_hi;
2875                 uint32_t tx_gt2047_lo;
2876                 uint32_t tx_gt2047_hi;
2877                 uint32_t tx_gt4095_lo;
2878                 uint32_t tx_gt4095_hi;
2879                 uint32_t tx_gt9216_lo;
2880                 uint32_t tx_gt9216_hi;
2881                 uint32_t tx_gt16383_lo;
2882                 uint32_t tx_gt16383_hi;
2883                 uint32_t tx_gtufl_lo;
2884                 uint32_t tx_gtufl_hi;
2885                 uint32_t tx_gterr_lo;
2886                 uint32_t tx_gterr_hi;
2887                 uint32_t tx_gtbyt_lo;
2888                 uint32_t tx_gtbyt_hi;
2889                 uint32_t tx_collisions_lo;
2890                 uint32_t tx_collisions_hi;
2891                 uint32_t tx_singlecollision_lo;
2892                 uint32_t tx_singlecollision_hi;
2893                 uint32_t tx_multiplecollisions_lo;
2894                 uint32_t tx_multiplecollisions_hi;