BNX2X: initialization
[akaros.git] / kern / drivers / net / bnx2x / bnx2x_init_ops.h
1 /* bnx2x_init_ops.h: Broadcom Everest network driver.
2  *               Static functions needed during the initialization.
3  *               This file is "included" in bnx2x_main.c.
4  *
5  * Copyright (c) 2007-2013 Broadcom Corporation
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation.
10  *
11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12  * Written by: Vladislav Zolotarov
13  */
14
15 #ifndef BNX2X_INIT_OPS_H
16 #define BNX2X_INIT_OPS_H
17
18
19 #ifndef BP_ILT
20 #define BP_ILT(bp)      NULL
21 #endif
22
23 #ifndef BP_FUNC
24 #define BP_FUNC(bp)     0
25 #endif
26
27 #ifndef BP_PORT
28 #define BP_PORT(bp)     0
29 #endif
30
31 #ifndef BNX2X_ILT_FREE
32 #define BNX2X_ILT_FREE(x, y, sz)
33 #endif
34
35 #ifndef BNX2X_ILT_ZALLOC
36 #define BNX2X_ILT_ZALLOC(x, y, sz)
37 #endif
38
39 #ifndef ILOG2
40 #define ILOG2(x)        x
41 #endif
42
43 static int bnx2x_gunzip(struct bnx2x *bp, const uint8_t *zbuf, int len);
44 static void bnx2x_reg_wr_ind(struct bnx2x *bp, uint32_t addr, uint32_t val);
45 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp,
46                                       dma_addr_t phys_addr, uint32_t addr,
47                                       uint32_t len);
48
49 static void bnx2x_init_str_wr(struct bnx2x *bp, uint32_t addr,
50                               const uint32_t *data, uint32_t len)
51 {
52         uint32_t i;
53
54         for (i = 0; i < len; i++)
55                 REG_WR(bp, addr + i*4, data[i]);
56 }
57
58 static void bnx2x_init_ind_wr(struct bnx2x *bp, uint32_t addr,
59                               const uint32_t *data, uint32_t len)
60 {
61         uint32_t i;
62
63         for (i = 0; i < len; i++)
64                 bnx2x_reg_wr_ind(bp, addr + i*4, data[i]);
65 }
66
67 static void bnx2x_write_big_buf(struct bnx2x *bp, uint32_t addr,
68                                 uint32_t len,
69                                 uint8_t wb)
70 {
71         if (bp->dmae_ready)
72                 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
73
74         /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
75         else if (wb && CHIP_IS_E1(bp))
76                 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
77
78         /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
79         else
80                 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
81 }
82
83 static void bnx2x_init_fill(struct bnx2x *bp, uint32_t addr, int fill,
84                             uint32_t len, uint8_t wb)
85 {
86         uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
87         uint32_t buf_len32 = buf_len/4;
88         uint32_t i;
89
90         memset(GUNZIP_BUF(bp), (uint8_t)fill, buf_len);
91
92         for (i = 0; i < len; i += buf_len32) {
93                 uint32_t cur_len = MIN(buf_len32, len - i);
94
95                 bnx2x_write_big_buf(bp, addr + i*4, cur_len, wb);
96         }
97 }
98
99 static void bnx2x_write_big_buf_wb(struct bnx2x *bp, uint32_t addr,
100                                    uint32_t len)
101 {
102         if (bp->dmae_ready)
103                 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
104
105         /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
106         else if (CHIP_IS_E1(bp))
107                 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
108
109         /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
110         else
111                 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
112 }
113
114 static void bnx2x_init_wr_64(struct bnx2x *bp, uint32_t addr,
115                              const uint32_t *data, uint32_t len64)
116 {
117         uint32_t buf_len32 = FW_BUF_SIZE/4;
118         uint32_t len = len64*2;
119         uint64_t data64 = 0;
120         uint32_t i;
121
122         /* 64 bit value is in a blob: first low DWORD, then high DWORD */
123         data64 = HILO_U64((*(data + 1)), (*data));
124
125         len64 = MIN((uint32_t)(FW_BUF_SIZE / 8), len64);
126         for (i = 0; i < len64; i++) {
127                 uint64_t *pdata = ((uint64_t *)(GUNZIP_BUF(bp))) + i;
128
129                 *pdata = data64;
130         }
131
132         for (i = 0; i < len; i += buf_len32) {
133                 uint32_t cur_len = MIN(buf_len32, len - i);
134
135                 bnx2x_write_big_buf_wb(bp, addr + i*4, cur_len);
136         }
137 }
138
139 /*********************************************************
140    There are different blobs for each PRAM section.
141    In addition, each blob write operation is divided into a few operations
142    in order to decrease the amount of phys. contiguous buffer needed.
143    Thus, when we select a blob the address may be with some offset
144    from the beginning of PRAM section.
145    The same holds for the INT_TABLE sections.
146 **********************************************************/
147 #define IF_IS_INT_TABLE_ADDR(base, addr) \
148                         if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
149
150 #define IF_IS_PRAM_ADDR(base, addr) \
151                         if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
152
153 static const uint8_t *bnx2x_sel_blob(struct bnx2x *bp, uint32_t addr,
154                                 const uint8_t *data)
155 {
156         IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
157                 data = INIT_TSEM_INT_TABLE_DATA(bp);
158         else
159                 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
160                         data = INIT_CSEM_INT_TABLE_DATA(bp);
161         else
162                 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
163                         data = INIT_USEM_INT_TABLE_DATA(bp);
164         else
165                 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
166                         data = INIT_XSEM_INT_TABLE_DATA(bp);
167         else
168                 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
169                         data = INIT_TSEM_PRAM_DATA(bp);
170         else
171                 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
172                         data = INIT_CSEM_PRAM_DATA(bp);
173         else
174                 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
175                         data = INIT_USEM_PRAM_DATA(bp);
176         else
177                 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
178                         data = INIT_XSEM_PRAM_DATA(bp);
179
180         return data;
181 }
182
183 static void bnx2x_init_wr_wb(struct bnx2x *bp, uint32_t addr,
184                              const uint32_t *data, uint32_t len)
185 {
186         if (bp->dmae_ready)
187                 VIRT_WR_DMAE_LEN(bp, data, addr, len, 0);
188
189         /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
190         else if (CHIP_IS_E1(bp))
191                 bnx2x_init_ind_wr(bp, addr, data, len);
192
193         /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
194         else
195                 bnx2x_init_str_wr(bp, addr, data, len);
196 }
197
198 static void bnx2x_wr_64(struct bnx2x *bp, uint32_t reg, uint32_t val_lo,
199                         uint32_t val_hi)
200 {
201         uint32_t wb_write[2];
202
203         wb_write[0] = val_lo;
204         wb_write[1] = val_hi;
205         REG_WR_DMAE_LEN(bp, reg, wb_write, 2);
206 }
207 static void bnx2x_init_wr_zp(struct bnx2x *bp, uint32_t addr, uint32_t len,
208                              uint32_t blob_off)
209 {
210         const uint8_t *data = NULL;
211         int rc;
212         uint32_t i;
213
214         data = bnx2x_sel_blob(bp, addr, data) + blob_off*4;
215
216         rc = bnx2x_gunzip(bp, data, len);
217         if (rc)
218                 return;
219
220         /* gunzip_outlen is in dwords */
221         len = GUNZIP_OUTLEN(bp);
222         for (i = 0; i < len; i++)
223                 ((uint32_t *)GUNZIP_BUF(bp))[i] = (__force uint32_t)
224                                 cpu_to_le32(((uint32_t *)GUNZIP_BUF(bp))[i]);
225
226         bnx2x_write_big_buf_wb(bp, addr, len);
227 }
228
229 static void bnx2x_init_block(struct bnx2x *bp, uint32_t block,
230                              uint32_t stage)
231 {
232         uint16_t op_start =
233                 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
234                                                      STAGE_START)];
235         uint16_t op_end =
236                 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
237                                                      STAGE_END)];
238         const union init_op *op;
239         uint32_t op_idx, op_type, addr, len;
240         const uint32_t *data, *data_base;
241
242         /* If empty block */
243         if (op_start == op_end)
244                 return;
245
246         data_base = INIT_DATA(bp);
247
248         for (op_idx = op_start; op_idx < op_end; op_idx++) {
249
250                 op = (const union init_op *)&(INIT_OPS(bp)[op_idx]);
251                 /* Get generic data */
252                 op_type = op->raw.op;
253                 addr = op->raw.offset;
254                 /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
255                  * OP_WR64 (we assume that op_arr_write and op_write have the
256                  * same structure).
257                  */
258                 len = op->arr_wr.data_len;
259                 data = data_base + op->arr_wr.data_off;
260
261                 switch (op_type) {
262                 case OP_RD:
263                         REG_RD(bp, addr);
264                         break;
265                 case OP_WR:
266                         REG_WR(bp, addr, op->write.val);
267                         break;
268                 case OP_SW:
269                         bnx2x_init_str_wr(bp, addr, data, len);
270                         break;
271                 case OP_WB:
272                         bnx2x_init_wr_wb(bp, addr, data, len);
273                         break;
274                 case OP_ZR:
275                         bnx2x_init_fill(bp, addr, 0, op->zero.len, 0);
276                         break;
277                 case OP_WB_ZR:
278                         bnx2x_init_fill(bp, addr, 0, op->zero.len, 1);
279                         break;
280                 case OP_ZP:
281                         bnx2x_init_wr_zp(bp, addr, len,
282                                          op->arr_wr.data_off);
283                         break;
284                 case OP_WR_64:
285                         bnx2x_init_wr_64(bp, addr, data, len);
286                         break;
287                 case OP_IF_MODE_AND:
288                         /* if any of the flags doesn't match, skip the
289                          * conditional block.
290                          */
291                         if ((INIT_MODE_FLAGS(bp) &
292                                 op->if_mode.mode_bit_map) !=
293                                 op->if_mode.mode_bit_map)
294                                 op_idx += op->if_mode.cmd_offset;
295                         break;
296                 case OP_IF_MODE_OR:
297                         /* if all the flags don't match, skip the conditional
298                          * block.
299                          */
300                         if ((INIT_MODE_FLAGS(bp) &
301                                 op->if_mode.mode_bit_map) == 0)
302                                 op_idx += op->if_mode.cmd_offset;
303                         break;
304                 default:
305                         /* Should never get here! */
306
307                         break;
308                 }
309         }
310 }
311
312
313 /****************************************************************************
314 * PXP Arbiter
315 ****************************************************************************/
316 /*
317  * This code configures the PCI read/write arbiter
318  * which implements a weighted round robin
319  * between the virtual queues in the chip.
320  *
321  * The values were derived for each PCI max payload and max request size.
322  * since max payload and max request size are only known at run time,
323  * this is done as a separate init stage.
324  */
325
326 #define NUM_WR_Q                        13
327 #define NUM_RD_Q                        29
328 #define MAX_RD_ORD                      3
329 #define MAX_WR_ORD                      2
330
331 /* configuration for one arbiter queue */
332 struct arb_line {
333         int l;
334         int add;
335         int ubound;
336 };
337
338 /* derived configuration for each read queue for each max request size */
339 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
340 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
341         { {4, 8,  4},  {4,  8,  4},  {4,  8,  4},  {4,  8,  4}  },
342         { {4, 3,  3},  {4,  3,  3},  {4,  3,  3},  {4,  3,  3}  },
343         { {8, 3,  6},  {16, 3,  11}, {16, 3,  11}, {16, 3,  11} },
344         { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
345         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
346         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
347         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
348         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
349 /* 10 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
350         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
351         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
352         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
353         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
354         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
355         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
356         { {8, 64, 6},  {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
357         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
358         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
359 /* 20 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
360         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
361         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
362         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
363         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
364         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
365         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
366         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
367         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
368         { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
369 };
370
371 /* derived configuration for each write queue for each max request size */
372 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
373 /* 1 */ { {4, 6,  3},  {4,  6,  3},  {4,  6,  3} },
374         { {4, 2,  3},  {4,  2,  3},  {4,  2,  3} },
375         { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
376         { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
377         { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
378         { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
379         { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
380         { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
381         { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
382 /* 10 */{ {8, 9,  6},  {16, 9,  11}, {32, 9,  21} },
383         { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
384         { {8, 9,  6},  {16, 9,  11}, {16, 9,  11} },
385         { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
386 };
387
388 /* register addresses for read queues */
389 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
390 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
391                 PXP2_REG_RQ_BW_RD_UBOUND0},
392         {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
393                 PXP2_REG_PSWRQ_BW_UB1},
394         {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
395                 PXP2_REG_PSWRQ_BW_UB2},
396         {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
397                 PXP2_REG_PSWRQ_BW_UB3},
398         {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
399                 PXP2_REG_RQ_BW_RD_UBOUND4},
400         {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
401                 PXP2_REG_RQ_BW_RD_UBOUND5},
402         {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
403                 PXP2_REG_PSWRQ_BW_UB6},
404         {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
405                 PXP2_REG_PSWRQ_BW_UB7},
406         {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
407                 PXP2_REG_PSWRQ_BW_UB8},
408 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
409                 PXP2_REG_PSWRQ_BW_UB9},
410         {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
411                 PXP2_REG_PSWRQ_BW_UB10},
412         {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
413                 PXP2_REG_PSWRQ_BW_UB11},
414         {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
415                 PXP2_REG_RQ_BW_RD_UBOUND12},
416         {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
417                 PXP2_REG_RQ_BW_RD_UBOUND13},
418         {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
419                 PXP2_REG_RQ_BW_RD_UBOUND14},
420         {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
421                 PXP2_REG_RQ_BW_RD_UBOUND15},
422         {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
423                 PXP2_REG_RQ_BW_RD_UBOUND16},
424         {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
425                 PXP2_REG_RQ_BW_RD_UBOUND17},
426         {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
427                 PXP2_REG_RQ_BW_RD_UBOUND18},
428 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
429                 PXP2_REG_RQ_BW_RD_UBOUND19},
430         {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
431                 PXP2_REG_RQ_BW_RD_UBOUND20},
432         {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
433                 PXP2_REG_RQ_BW_RD_UBOUND22},
434         {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
435                 PXP2_REG_RQ_BW_RD_UBOUND23},
436         {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
437                 PXP2_REG_RQ_BW_RD_UBOUND24},
438         {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
439                 PXP2_REG_RQ_BW_RD_UBOUND25},
440         {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
441                 PXP2_REG_RQ_BW_RD_UBOUND26},
442         {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
443                 PXP2_REG_RQ_BW_RD_UBOUND27},
444         {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
445                 PXP2_REG_PSWRQ_BW_UB28}
446 };
447
448 /* register addresses for write queues */
449 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
450 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
451                 PXP2_REG_PSWRQ_BW_UB1},
452         {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
453                 PXP2_REG_PSWRQ_BW_UB2},
454         {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
455                 PXP2_REG_PSWRQ_BW_UB3},
456         {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
457                 PXP2_REG_PSWRQ_BW_UB6},
458         {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
459                 PXP2_REG_PSWRQ_BW_UB7},
460         {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
461                 PXP2_REG_PSWRQ_BW_UB8},
462         {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
463                 PXP2_REG_PSWRQ_BW_UB9},
464         {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
465                 PXP2_REG_PSWRQ_BW_UB10},
466         {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
467                 PXP2_REG_PSWRQ_BW_UB11},
468 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
469                 PXP2_REG_PSWRQ_BW_UB28},
470         {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
471                 PXP2_REG_RQ_BW_WR_UBOUND29},
472         {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
473                 PXP2_REG_RQ_BW_WR_UBOUND30}
474 };
475
476 static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order,
477                                int w_order)
478 {
479         uint32_t val, i;
480
481         if (r_order > MAX_RD_ORD) {
482                 DP(NETIF_MSG_HW, "read order of %d  order adjusted to %d\n",
483                    r_order, MAX_RD_ORD);
484                 r_order = MAX_RD_ORD;
485         }
486         if (w_order > MAX_WR_ORD) {
487                 DP(NETIF_MSG_HW, "write order of %d  order adjusted to %d\n",
488                    w_order, MAX_WR_ORD);
489                 w_order = MAX_WR_ORD;
490         }
491         if (CHIP_REV_IS_FPGA(bp)) {
492                 DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
493                 w_order = 0;
494         }
495         DP(NETIF_MSG_HW, "read order %d  write order %d\n", r_order, w_order);
496
497         for (i = 0; i < NUM_RD_Q-1; i++) {
498                 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
499                 REG_WR(bp, read_arb_addr[i].add,
500                        read_arb_data[i][r_order].add);
501                 REG_WR(bp, read_arb_addr[i].ubound,
502                        read_arb_data[i][r_order].ubound);
503         }
504
505         for (i = 0; i < NUM_WR_Q-1; i++) {
506                 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
507                     (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
508
509                         REG_WR(bp, write_arb_addr[i].l,
510                                write_arb_data[i][w_order].l);
511
512                         REG_WR(bp, write_arb_addr[i].add,
513                                write_arb_data[i][w_order].add);
514
515                         REG_WR(bp, write_arb_addr[i].ubound,
516                                write_arb_data[i][w_order].ubound);
517                 } else {
518
519                         val = REG_RD(bp, write_arb_addr[i].l);
520                         REG_WR(bp, write_arb_addr[i].l,
521                                val | (write_arb_data[i][w_order].l << 10));
522
523                         val = REG_RD(bp, write_arb_addr[i].add);
524                         REG_WR(bp, write_arb_addr[i].add,
525                                val | (write_arb_data[i][w_order].add << 10));
526
527                         val = REG_RD(bp, write_arb_addr[i].ubound);
528                         REG_WR(bp, write_arb_addr[i].ubound,
529                                val | (write_arb_data[i][w_order].ubound << 7));
530                 }
531         }
532
533         val =  write_arb_data[NUM_WR_Q-1][w_order].add;
534         val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
535         val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
536         REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
537
538         val =  read_arb_data[NUM_RD_Q-1][r_order].add;
539         val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
540         val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
541         REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
542
543         REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
544         REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
545         REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
546         REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
547
548         if ((CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) && (r_order == MAX_RD_ORD))
549                 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
550
551         if (CHIP_IS_E3(bp))
552                 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
553         else if (CHIP_IS_E2(bp))
554                 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
555         else
556                 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
557
558         if (!CHIP_IS_E1(bp)) {
559                 /*    MPS      w_order     optimal TH      presently TH
560                  *    128         0             0               2
561                  *    256         1             1               3
562                  *    >=512       2             2               3
563                  */
564                 /* DMAE is special */
565                 if (!CHIP_IS_E1H(bp)) {
566                         /* E2 can use optimal TH */
567                         val = w_order;
568                         REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val);
569                 } else {
570                         val = ((w_order == 0) ? 2 : 3);
571                         REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2);
572                 }
573
574                 REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
575                 REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
576                 REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
577                 REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
578                 REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
579                 REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
580                 REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
581                 REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
582                 REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
583                 REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
584         }
585
586         /* Validate number of tags suppoted by device */
587 #define PCIE_REG_PCIER_TL_HDR_FC_ST             0x2980
588         val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST);
589         val &= 0xFF;
590         if (val <= 0x20)
591                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
592 }
593
594 /****************************************************************************
595 * ILT management
596 ****************************************************************************/
597 /*
598  * This codes hides the low level HW interaction for ILT management and
599  * configuration. The API consists of a shadow ILT table which is set by the
600  * driver and a set of routines to use it to configure the HW.
601  *
602  */
603
604 /* ILT HW init operations */
605
606 /* ILT memory management operations */
607 #define ILT_MEMOP_ALLOC         0
608 #define ILT_MEMOP_FREE          1
609
610 /* the phys address is shifted right 12 bits and has an added
611  * 1=valid bit added to the 53rd bit
612  * then since this is a wide register(TM)
613  * we split it into two 32 bit writes
614  */
615 #define ILT_ADDR1(x)            ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
616 #define ILT_ADDR2(x)            ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
617 #define ILT_RANGE(f, l)         (((l) << 10) | f)
618
619 static int bnx2x_ilt_line_mem_op(struct bnx2x *bp,
620                                  struct ilt_line *line, uint32_t size,
621                                  uint8_t memop)
622 {
623         if (memop == ILT_MEMOP_FREE) {
624                 BNX2X_ILT_FREE(line->page, line->page_mapping, line->size);
625                 return 0;
626         }
627         BNX2X_ILT_ZALLOC(line->page, &line->page_mapping, size);
628         if (!line->page)
629                 return -1;
630         line->size = size;
631         return 0;
632 }
633
634
635 static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num,
636                                    uint8_t memop)
637 {
638         int i, rc;
639         struct bnx2x_ilt *ilt = BP_ILT(bp);
640         struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
641
642         if (!ilt || !ilt->lines)
643                 return -1;
644
645         if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
646                 return 0;
647
648         for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
649                 rc = bnx2x_ilt_line_mem_op(bp, &ilt->lines[i],
650                                            ilt_cli->page_size, memop);
651         }
652         return rc;
653 }
654
655 static int bnx2x_ilt_mem_op_cnic(struct bnx2x *bp, uint8_t memop)
656 {
657         int rc = 0;
658
659         if (CONFIGURE_NIC_MODE(bp))
660                 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
661         if (!rc)
662                 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_TM, memop);
663
664         return rc;
665 }
666
667 static int bnx2x_ilt_mem_op(struct bnx2x *bp, uint8_t memop)
668 {
669         int rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_CDU, memop);
670         if (!rc)
671                 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_QM, memop);
672         if (!rc && CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp))
673                 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
674
675         return rc;
676 }
677
678 static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx,
679                               dma_addr_t page_mapping)
680 {
681         uint32_t reg;
682
683         if (CHIP_IS_E1(bp))
684                 reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
685         else
686                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
687
688         bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
689 }
690
691 static void bnx2x_ilt_line_init_op(struct bnx2x *bp,
692                                    struct bnx2x_ilt *ilt, int idx,
693                                    uint8_t initop)
694 {
695         dma_addr_t      null_mapping;
696         int abs_idx = ilt->start_line + idx;
697
698
699         switch (initop) {
700         case INITOP_INIT:
701                 /* set in the init-value array */
702         case INITOP_SET:
703                 bnx2x_ilt_line_wr(bp, abs_idx, ilt->lines[idx].page_mapping);
704                 break;
705         case INITOP_CLEAR:
706                 null_mapping = 0;
707                 bnx2x_ilt_line_wr(bp, abs_idx, null_mapping);
708                 break;
709         }
710 }
711
712 static void bnx2x_ilt_boundry_init_op(struct bnx2x *bp,
713                                       struct ilt_client_info *ilt_cli,
714                                       uint32_t ilt_start, uint8_t initop)
715 {
716         uint32_t start_reg = 0;
717         uint32_t end_reg = 0;
718
719         /* The boundary is either SET or INIT,
720            CLEAR => SET and for now SET ~~ INIT */
721
722         /* find the appropriate regs */
723         if (CHIP_IS_E1(bp)) {
724                 switch (ilt_cli->client_num) {
725                 case ILT_CLIENT_CDU:
726                         start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
727                         break;
728                 case ILT_CLIENT_QM:
729                         start_reg = PXP2_REG_PSWRQ_QM0_L2P;
730                         break;
731                 case ILT_CLIENT_SRC:
732                         start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
733                         break;
734                 case ILT_CLIENT_TM:
735                         start_reg = PXP2_REG_PSWRQ_TM0_L2P;
736                         break;
737                 }
738                 REG_WR(bp, start_reg + BP_FUNC(bp)*4,
739                        ILT_RANGE((ilt_start + ilt_cli->start),
740                                  (ilt_start + ilt_cli->end)));
741         } else {
742                 switch (ilt_cli->client_num) {
743                 case ILT_CLIENT_CDU:
744                         start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
745                         end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
746                         break;
747                 case ILT_CLIENT_QM:
748                         start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
749                         end_reg = PXP2_REG_RQ_QM_LAST_ILT;
750                         break;
751                 case ILT_CLIENT_SRC:
752                         start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
753                         end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
754                         break;
755                 case ILT_CLIENT_TM:
756                         start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
757                         end_reg = PXP2_REG_RQ_TM_LAST_ILT;
758                         break;
759                 }
760                 REG_WR(bp, start_reg, (ilt_start + ilt_cli->start));
761                 REG_WR(bp, end_reg, (ilt_start + ilt_cli->end));
762         }
763 }
764
765 static void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp,
766                                          struct bnx2x_ilt *ilt,
767                                          struct ilt_client_info *ilt_cli,
768                                          uint8_t initop)
769 {
770         int i;
771
772         if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
773                 return;
774
775         for (i = ilt_cli->start; i <= ilt_cli->end; i++)
776                 bnx2x_ilt_line_init_op(bp, ilt, i, initop);
777
778         /* init/clear the ILT boundries */
779         bnx2x_ilt_boundry_init_op(bp, ilt_cli, ilt->start_line, initop);
780 }
781
782 static void bnx2x_ilt_client_init_op(struct bnx2x *bp,
783                                      struct ilt_client_info *ilt_cli,
784                                      uint8_t initop)
785 {
786         struct bnx2x_ilt *ilt = BP_ILT(bp);
787
788         bnx2x_ilt_client_init_op_ilt(bp, ilt, ilt_cli, initop);
789 }
790
791 static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp,
792                                         int cli_num, uint8_t initop)
793 {
794         struct bnx2x_ilt *ilt = BP_ILT(bp);
795         struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
796
797         bnx2x_ilt_client_init_op(bp, ilt_cli, initop);
798 }
799
800 static void bnx2x_ilt_init_op_cnic(struct bnx2x *bp, uint8_t initop)
801 {
802         if (CONFIGURE_NIC_MODE(bp))
803                 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
804         bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_TM, initop);
805 }
806
807 static void bnx2x_ilt_init_op(struct bnx2x *bp, uint8_t initop)
808 {
809         bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_CDU, initop);
810         bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_QM, initop);
811         if (CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp))
812                 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
813 }
814
815 static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num,
816                                       uint32_t psz_reg, uint8_t initop)
817 {
818         struct bnx2x_ilt *ilt = BP_ILT(bp);
819         struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
820
821         if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
822                 return;
823
824         switch (initop) {
825         case INITOP_INIT:
826                 /* set in the init-value array */
827         case INITOP_SET:
828                 REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12));
829                 break;
830         case INITOP_CLEAR:
831                 break;
832         }
833 }
834
835 /*
836  * called during init common stage, ilt clients should be initialized
837  * prioir to calling this function
838  */
839 static void bnx2x_ilt_init_page_size(struct bnx2x *bp, uint8_t initop)
840 {
841         bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_CDU,
842                                   PXP2_REG_RQ_CDU_P_SIZE, initop);
843         bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_QM,
844                                   PXP2_REG_RQ_QM_P_SIZE, initop);
845         bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_SRC,
846                                   PXP2_REG_RQ_SRC_P_SIZE, initop);
847         bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_TM,
848                                   PXP2_REG_RQ_TM_P_SIZE, initop);
849 }
850
851 /****************************************************************************
852 * QM initializations
853 ****************************************************************************/
854 #define QM_QUEUES_PER_FUNC      16 /* E1 has 32, but only 16 are used */
855 #define QM_INIT_MIN_CID_COUNT   31
856 #define QM_INIT(cid_cnt)        (cid_cnt > QM_INIT_MIN_CID_COUNT)
857
858 /* called during init port stage */
859 static void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count,
860                                     uint8_t initop)
861 {
862         int port = BP_PORT(bp);
863
864         if (QM_INIT(qm_cid_count)) {
865                 switch (initop) {
866                 case INITOP_INIT:
867                         /* set in the init-value array */
868                 case INITOP_SET:
869                         REG_WR(bp, QM_REG_CONNNUM_0 + port*4,
870                                qm_cid_count/16 - 1);
871                         break;
872                 case INITOP_CLEAR:
873                         break;
874                 }
875         }
876 }
877
878 static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count,
879                                    uint32_t base_reg, uint32_t reg)
880 {
881         int i;
882         uint32_t wb_data[2] = {0, 0};
883         for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
884                 REG_WR(bp, base_reg + i*4,
885                        qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
886                 bnx2x_init_wr_wb(bp, reg + i*8,  wb_data, 2);
887         }
888 }
889
890 /* called during init common stage */
891 static void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count,
892                                     uint8_t initop)
893 {
894         if (!QM_INIT(qm_cid_count))
895                 return;
896
897         switch (initop) {
898         case INITOP_INIT:
899                 /* set in the init-value array */
900         case INITOP_SET:
901                 bnx2x_qm_set_ptr_table(bp, qm_cid_count,
902                                        QM_REG_BASEADDR, QM_REG_PTRTBL);
903                 if (CHIP_IS_E1H(bp))
904                         bnx2x_qm_set_ptr_table(bp, qm_cid_count,
905                                                QM_REG_BASEADDR_EXT_A,
906                                                QM_REG_PTRTBL_EXT_A);
907                 break;
908         case INITOP_CLEAR:
909                 break;
910         }
911 }
912
913 /****************************************************************************
914 * SRC initializations
915 ****************************************************************************/
916 /* called during init func stage */
917 static void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2,
918                               dma_addr_t t2_mapping, int src_cid_count)
919 {
920         int i;
921         int port = BP_PORT(bp);
922
923         /* Initialize T2 */
924         for (i = 0; i < src_cid_count-1; i++)
925                 t2[i].next = (uint64_t)(t2_mapping +
926                              (i+1)*sizeof(struct src_ent));
927
928         /* tell the searcher where the T2 table is */
929         REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
930
931         bnx2x_wr_64(bp, SRC_REG_FIRSTFREE0 + port*16,
932                     U64_LO(t2_mapping), U64_HI(t2_mapping));
933
934         bnx2x_wr_64(bp, SRC_REG_LASTFREE0 + port*16,
935                     U64_LO((uint64_t)t2_mapping +
936                            (src_cid_count-1) * sizeof(struct src_ent)),
937                     U64_HI((uint64_t)t2_mapping +
938                            (src_cid_count-1) * sizeof(struct src_ent)));
939 }
940 #endif /* BNX2X_INIT_OPS_H */