Migrated Akaros code to use pragma once (XCC)
[akaros.git] / kern / drivers / net / bnx2x / bnx2x_init_ops.h
1 /* bnx2x_init_ops.h: Broadcom Everest network driver.
2  *               Static functions needed during the initialization.
3  *               This file is "included" in bnx2x_main.c.
4  *
5  * Copyright (c) 2007-2013 Broadcom Corporation
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation.
10  *
11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12  * Written by: Vladislav Zolotarov
13  */
14
15 #pragma once
16
17
18 #ifndef BP_ILT
19 #define BP_ILT(bp)      NULL
20 #endif
21
22 #ifndef BP_FUNC
23 #define BP_FUNC(bp)     0
24 #endif
25
26 #ifndef BP_PORT
27 #define BP_PORT(bp)     0
28 #endif
29
30 #ifndef BNX2X_ILT_FREE
31 #define BNX2X_ILT_FREE(x, y, sz)
32 #endif
33
34 #ifndef BNX2X_ILT_ZALLOC
35 #define BNX2X_ILT_ZALLOC(x, y, sz)
36 #endif
37
38 #ifndef ILOG2
39 #define ILOG2(x)        x
40 #endif
41
42 static int bnx2x_gunzip(struct bnx2x *bp, const uint8_t *zbuf, int len);
43 static void bnx2x_reg_wr_ind(struct bnx2x *bp, uint32_t addr, uint32_t val);
44 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp,
45                                       dma_addr_t phys_addr, uint32_t addr,
46                                       uint32_t len);
47
48 static void bnx2x_init_str_wr(struct bnx2x *bp, uint32_t addr,
49                               const uint32_t *data, uint32_t len)
50 {
51         uint32_t i;
52
53         for (i = 0; i < len; i++)
54                 REG_WR(bp, addr + i*4, data[i]);
55 }
56
57 static void bnx2x_init_ind_wr(struct bnx2x *bp, uint32_t addr,
58                               const uint32_t *data, uint32_t len)
59 {
60         uint32_t i;
61
62         for (i = 0; i < len; i++)
63                 bnx2x_reg_wr_ind(bp, addr + i*4, data[i]);
64 }
65
66 static void bnx2x_write_big_buf(struct bnx2x *bp, uint32_t addr,
67                                 uint32_t len,
68                                 uint8_t wb)
69 {
70         if (bp->dmae_ready)
71                 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
72
73         /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
74         else if (wb && CHIP_IS_E1(bp))
75                 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
76
77         /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
78         else
79                 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
80 }
81
82 static void bnx2x_init_fill(struct bnx2x *bp, uint32_t addr, int fill,
83                             uint32_t len, uint8_t wb)
84 {
85         uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
86         uint32_t buf_len32 = buf_len/4;
87         uint32_t i;
88
89         memset(GUNZIP_BUF(bp), (uint8_t)fill, buf_len);
90
91         for (i = 0; i < len; i += buf_len32) {
92                 uint32_t cur_len = MIN(buf_len32, len - i);
93
94                 bnx2x_write_big_buf(bp, addr + i*4, cur_len, wb);
95         }
96 }
97
98 static void bnx2x_write_big_buf_wb(struct bnx2x *bp, uint32_t addr,
99                                    uint32_t len)
100 {
101         if (bp->dmae_ready)
102                 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
103
104         /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
105         else if (CHIP_IS_E1(bp))
106                 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
107
108         /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
109         else
110                 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
111 }
112
113 static void bnx2x_init_wr_64(struct bnx2x *bp, uint32_t addr,
114                              const uint32_t *data, uint32_t len64)
115 {
116         uint32_t buf_len32 = FW_BUF_SIZE/4;
117         uint32_t len = len64*2;
118         uint64_t data64 = 0;
119         uint32_t i;
120
121         /* 64 bit value is in a blob: first low DWORD, then high DWORD */
122         data64 = HILO_U64((*(data + 1)), (*data));
123
124         len64 = MIN((uint32_t)(FW_BUF_SIZE / 8), len64);
125         for (i = 0; i < len64; i++) {
126                 uint64_t *pdata = ((uint64_t *)(GUNZIP_BUF(bp))) + i;
127
128                 *pdata = data64;
129         }
130
131         for (i = 0; i < len; i += buf_len32) {
132                 uint32_t cur_len = MIN(buf_len32, len - i);
133
134                 bnx2x_write_big_buf_wb(bp, addr + i*4, cur_len);
135         }
136 }
137
138 /*********************************************************
139    There are different blobs for each PRAM section.
140    In addition, each blob write operation is divided into a few operations
141    in order to decrease the amount of phys. contiguous buffer needed.
142    Thus, when we select a blob the address may be with some offset
143    from the beginning of PRAM section.
144    The same holds for the INT_TABLE sections.
145 **********************************************************/
146 #define IF_IS_INT_TABLE_ADDR(base, addr) \
147                         if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
148
149 #define IF_IS_PRAM_ADDR(base, addr) \
150                         if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
151
152 static const uint8_t *bnx2x_sel_blob(struct bnx2x *bp, uint32_t addr,
153                                 const uint8_t *data)
154 {
155         IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
156                 data = INIT_TSEM_INT_TABLE_DATA(bp);
157         else
158                 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
159                         data = INIT_CSEM_INT_TABLE_DATA(bp);
160         else
161                 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
162                         data = INIT_USEM_INT_TABLE_DATA(bp);
163         else
164                 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
165                         data = INIT_XSEM_INT_TABLE_DATA(bp);
166         else
167                 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
168                         data = INIT_TSEM_PRAM_DATA(bp);
169         else
170                 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
171                         data = INIT_CSEM_PRAM_DATA(bp);
172         else
173                 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
174                         data = INIT_USEM_PRAM_DATA(bp);
175         else
176                 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
177                         data = INIT_XSEM_PRAM_DATA(bp);
178
179         return data;
180 }
181
182 static void bnx2x_init_wr_wb(struct bnx2x *bp, uint32_t addr,
183                              const uint32_t *data, uint32_t len)
184 {
185         if (bp->dmae_ready)
186                 VIRT_WR_DMAE_LEN(bp, data, addr, len, 0);
187
188         /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
189         else if (CHIP_IS_E1(bp))
190                 bnx2x_init_ind_wr(bp, addr, data, len);
191
192         /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
193         else
194                 bnx2x_init_str_wr(bp, addr, data, len);
195 }
196
197 static void bnx2x_wr_64(struct bnx2x *bp, uint32_t reg, uint32_t val_lo,
198                         uint32_t val_hi)
199 {
200         uint32_t wb_write[2];
201
202         wb_write[0] = val_lo;
203         wb_write[1] = val_hi;
204         REG_WR_DMAE_LEN(bp, reg, wb_write, 2);
205 }
206 static void bnx2x_init_wr_zp(struct bnx2x *bp, uint32_t addr, uint32_t len,
207                              uint32_t blob_off)
208 {
209         const uint8_t *data = NULL;
210         int rc;
211         uint32_t i;
212
213         data = bnx2x_sel_blob(bp, addr, data) + blob_off*4;
214
215         rc = bnx2x_gunzip(bp, data, len);
216         if (rc)
217                 return;
218
219         /* gunzip_outlen is in dwords */
220         len = GUNZIP_OUTLEN(bp);
221         for (i = 0; i < len; i++)
222                 ((uint32_t *)GUNZIP_BUF(bp))[i] = (__force uint32_t)
223                                 cpu_to_le32(((uint32_t *)GUNZIP_BUF(bp))[i]);
224
225         bnx2x_write_big_buf_wb(bp, addr, len);
226 }
227
228 static void bnx2x_init_block(struct bnx2x *bp, uint32_t block,
229                              uint32_t stage)
230 {
231         uint16_t op_start =
232                 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
233                                                      STAGE_START)];
234         uint16_t op_end =
235                 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
236                                                      STAGE_END)];
237         const union init_op *op;
238         uint32_t op_idx, op_type, addr, len;
239         const uint32_t *data, *data_base;
240
241         /* If empty block */
242         if (op_start == op_end)
243                 return;
244
245         data_base = INIT_DATA(bp);
246
247         for (op_idx = op_start; op_idx < op_end; op_idx++) {
248
249                 op = (const union init_op *)&(INIT_OPS(bp)[op_idx]);
250                 /* Get generic data */
251                 op_type = op->raw.op;
252                 addr = op->raw.offset;
253                 /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
254                  * OP_WR64 (we assume that op_arr_write and op_write have the
255                  * same structure).
256                  */
257                 len = op->arr_wr.data_len;
258                 data = data_base + op->arr_wr.data_off;
259
260                 switch (op_type) {
261                 case OP_RD:
262                         REG_RD(bp, addr);
263                         break;
264                 case OP_WR:
265                         REG_WR(bp, addr, op->write.val);
266                         break;
267                 case OP_SW:
268                         bnx2x_init_str_wr(bp, addr, data, len);
269                         break;
270                 case OP_WB:
271                         bnx2x_init_wr_wb(bp, addr, data, len);
272                         break;
273                 case OP_ZR:
274                         bnx2x_init_fill(bp, addr, 0, op->zero.len, 0);
275                         break;
276                 case OP_WB_ZR:
277                         bnx2x_init_fill(bp, addr, 0, op->zero.len, 1);
278                         break;
279                 case OP_ZP:
280                         bnx2x_init_wr_zp(bp, addr, len,
281                                          op->arr_wr.data_off);
282                         break;
283                 case OP_WR_64:
284                         bnx2x_init_wr_64(bp, addr, data, len);
285                         break;
286                 case OP_IF_MODE_AND:
287                         /* if any of the flags doesn't match, skip the
288                          * conditional block.
289                          */
290                         if ((INIT_MODE_FLAGS(bp) &
291                                 op->if_mode.mode_bit_map) !=
292                                 op->if_mode.mode_bit_map)
293                                 op_idx += op->if_mode.cmd_offset;
294                         break;
295                 case OP_IF_MODE_OR:
296                         /* if all the flags don't match, skip the conditional
297                          * block.
298                          */
299                         if ((INIT_MODE_FLAGS(bp) &
300                                 op->if_mode.mode_bit_map) == 0)
301                                 op_idx += op->if_mode.cmd_offset;
302                         break;
303                 default:
304                         /* Should never get here! */
305
306                         break;
307                 }
308         }
309 }
310
311
312 /****************************************************************************
313 * PXP Arbiter
314 ****************************************************************************/
315 /*
316  * This code configures the PCI read/write arbiter
317  * which implements a weighted round robin
318  * between the virtual queues in the chip.
319  *
320  * The values were derived for each PCI max payload and max request size.
321  * since max payload and max request size are only known at run time,
322  * this is done as a separate init stage.
323  */
324
325 #define NUM_WR_Q                        13
326 #define NUM_RD_Q                        29
327 #define MAX_RD_ORD                      3
328 #define MAX_WR_ORD                      2
329
330 /* configuration for one arbiter queue */
331 struct arb_line {
332         int l;
333         int add;
334         int ubound;
335 };
336
337 /* derived configuration for each read queue for each max request size */
338 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
339 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
340         { {4, 8,  4},  {4,  8,  4},  {4,  8,  4},  {4,  8,  4}  },
341         { {4, 3,  3},  {4,  3,  3},  {4,  3,  3},  {4,  3,  3}  },
342         { {8, 3,  6},  {16, 3,  11}, {16, 3,  11}, {16, 3,  11} },
343         { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
344         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
345         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
346         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
347         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
348 /* 10 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
349         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
350         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
351         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
352         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
353         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
354         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
355         { {8, 64, 6},  {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
356         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
357         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
358 /* 20 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
359         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
360         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
361         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
362         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
363         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
364         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
365         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
366         { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
367         { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
368 };
369
370 /* derived configuration for each write queue for each max request size */
371 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
372 /* 1 */ { {4, 6,  3},  {4,  6,  3},  {4,  6,  3} },
373         { {4, 2,  3},  {4,  2,  3},  {4,  2,  3} },
374         { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
375         { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
376         { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
377         { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
378         { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
379         { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
380         { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
381 /* 10 */{ {8, 9,  6},  {16, 9,  11}, {32, 9,  21} },
382         { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
383         { {8, 9,  6},  {16, 9,  11}, {16, 9,  11} },
384         { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
385 };
386
387 /* register addresses for read queues */
388 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
389 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
390                 PXP2_REG_RQ_BW_RD_UBOUND0},
391         {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
392                 PXP2_REG_PSWRQ_BW_UB1},
393         {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
394                 PXP2_REG_PSWRQ_BW_UB2},
395         {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
396                 PXP2_REG_PSWRQ_BW_UB3},
397         {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
398                 PXP2_REG_RQ_BW_RD_UBOUND4},
399         {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
400                 PXP2_REG_RQ_BW_RD_UBOUND5},
401         {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
402                 PXP2_REG_PSWRQ_BW_UB6},
403         {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
404                 PXP2_REG_PSWRQ_BW_UB7},
405         {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
406                 PXP2_REG_PSWRQ_BW_UB8},
407 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
408                 PXP2_REG_PSWRQ_BW_UB9},
409         {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
410                 PXP2_REG_PSWRQ_BW_UB10},
411         {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
412                 PXP2_REG_PSWRQ_BW_UB11},
413         {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
414                 PXP2_REG_RQ_BW_RD_UBOUND12},
415         {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
416                 PXP2_REG_RQ_BW_RD_UBOUND13},
417         {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
418                 PXP2_REG_RQ_BW_RD_UBOUND14},
419         {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
420                 PXP2_REG_RQ_BW_RD_UBOUND15},
421         {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
422                 PXP2_REG_RQ_BW_RD_UBOUND16},
423         {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
424                 PXP2_REG_RQ_BW_RD_UBOUND17},
425         {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
426                 PXP2_REG_RQ_BW_RD_UBOUND18},
427 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
428                 PXP2_REG_RQ_BW_RD_UBOUND19},
429         {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
430                 PXP2_REG_RQ_BW_RD_UBOUND20},
431         {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
432                 PXP2_REG_RQ_BW_RD_UBOUND22},
433         {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
434                 PXP2_REG_RQ_BW_RD_UBOUND23},
435         {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
436                 PXP2_REG_RQ_BW_RD_UBOUND24},
437         {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
438                 PXP2_REG_RQ_BW_RD_UBOUND25},
439         {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
440                 PXP2_REG_RQ_BW_RD_UBOUND26},
441         {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
442                 PXP2_REG_RQ_BW_RD_UBOUND27},
443         {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
444                 PXP2_REG_PSWRQ_BW_UB28}
445 };
446
447 /* register addresses for write queues */
448 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
449 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
450                 PXP2_REG_PSWRQ_BW_UB1},
451         {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
452                 PXP2_REG_PSWRQ_BW_UB2},
453         {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
454                 PXP2_REG_PSWRQ_BW_UB3},
455         {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
456                 PXP2_REG_PSWRQ_BW_UB6},
457         {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
458                 PXP2_REG_PSWRQ_BW_UB7},
459         {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
460                 PXP2_REG_PSWRQ_BW_UB8},
461         {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
462                 PXP2_REG_PSWRQ_BW_UB9},
463         {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
464                 PXP2_REG_PSWRQ_BW_UB10},
465         {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
466                 PXP2_REG_PSWRQ_BW_UB11},
467 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
468                 PXP2_REG_PSWRQ_BW_UB28},
469         {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
470                 PXP2_REG_RQ_BW_WR_UBOUND29},
471         {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
472                 PXP2_REG_RQ_BW_WR_UBOUND30}
473 };
474
475 static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order,
476                                int w_order)
477 {
478         uint32_t val, i;
479
480         if (r_order > MAX_RD_ORD) {
481                 DP(NETIF_MSG_HW, "read order of %d  order adjusted to %d\n",
482                    r_order, MAX_RD_ORD);
483                 r_order = MAX_RD_ORD;
484         }
485         if (w_order > MAX_WR_ORD) {
486                 DP(NETIF_MSG_HW, "write order of %d  order adjusted to %d\n",
487                    w_order, MAX_WR_ORD);
488                 w_order = MAX_WR_ORD;
489         }
490         if (CHIP_REV_IS_FPGA(bp)) {
491                 DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
492                 w_order = 0;
493         }
494         DP(NETIF_MSG_HW, "read order %d  write order %d\n", r_order, w_order);
495
496         for (i = 0; i < NUM_RD_Q-1; i++) {
497                 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
498                 REG_WR(bp, read_arb_addr[i].add,
499                        read_arb_data[i][r_order].add);
500                 REG_WR(bp, read_arb_addr[i].ubound,
501                        read_arb_data[i][r_order].ubound);
502         }
503
504         for (i = 0; i < NUM_WR_Q-1; i++) {
505                 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
506                     (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
507
508                         REG_WR(bp, write_arb_addr[i].l,
509                                write_arb_data[i][w_order].l);
510
511                         REG_WR(bp, write_arb_addr[i].add,
512                                write_arb_data[i][w_order].add);
513
514                         REG_WR(bp, write_arb_addr[i].ubound,
515                                write_arb_data[i][w_order].ubound);
516                 } else {
517
518                         val = REG_RD(bp, write_arb_addr[i].l);
519                         REG_WR(bp, write_arb_addr[i].l,
520                                val | (write_arb_data[i][w_order].l << 10));
521
522                         val = REG_RD(bp, write_arb_addr[i].add);
523                         REG_WR(bp, write_arb_addr[i].add,
524                                val | (write_arb_data[i][w_order].add << 10));
525
526                         val = REG_RD(bp, write_arb_addr[i].ubound);
527                         REG_WR(bp, write_arb_addr[i].ubound,
528                                val | (write_arb_data[i][w_order].ubound << 7));
529                 }
530         }
531
532         val =  write_arb_data[NUM_WR_Q-1][w_order].add;
533         val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
534         val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
535         REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
536
537         val =  read_arb_data[NUM_RD_Q-1][r_order].add;
538         val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
539         val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
540         REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
541
542         REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
543         REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
544         REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
545         REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
546
547         if ((CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) && (r_order == MAX_RD_ORD))
548                 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
549
550         if (CHIP_IS_E3(bp))
551                 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
552         else if (CHIP_IS_E2(bp))
553                 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
554         else
555                 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
556
557         if (!CHIP_IS_E1(bp)) {
558                 /*    MPS      w_order     optimal TH      presently TH
559                  *    128         0             0               2
560                  *    256         1             1               3
561                  *    >=512       2             2               3
562                  */
563                 /* DMAE is special */
564                 if (!CHIP_IS_E1H(bp)) {
565                         /* E2 can use optimal TH */
566                         val = w_order;
567                         REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val);
568                 } else {
569                         val = ((w_order == 0) ? 2 : 3);
570                         REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2);
571                 }
572
573                 REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
574                 REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
575                 REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
576                 REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
577                 REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
578                 REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
579                 REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
580                 REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
581                 REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
582                 REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
583         }
584
585         /* Validate number of tags suppoted by device */
586 #define PCIE_REG_PCIER_TL_HDR_FC_ST             0x2980
587         val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST);
588         val &= 0xFF;
589         if (val <= 0x20)
590                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
591 }
592
593 /****************************************************************************
594 * ILT management
595 ****************************************************************************/
596 /*
597  * This codes hides the low level HW interaction for ILT management and
598  * configuration. The API consists of a shadow ILT table which is set by the
599  * driver and a set of routines to use it to configure the HW.
600  *
601  */
602
603 /* ILT HW init operations */
604
605 /* ILT memory management operations */
606 #define ILT_MEMOP_ALLOC         0
607 #define ILT_MEMOP_FREE          1
608
609 /* the phys address is shifted right 12 bits and has an added
610  * 1=valid bit added to the 53rd bit
611  * then since this is a wide register(TM)
612  * we split it into two 32 bit writes
613  */
614 #define ILT_ADDR1(x)            ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
615 #define ILT_ADDR2(x)            ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
616 #define ILT_RANGE(f, l)         (((l) << 10) | f)
617
618 static int bnx2x_ilt_line_mem_op(struct bnx2x *bp,
619                                  struct ilt_line *line, uint32_t size,
620                                  uint8_t memop)
621 {
622         if (memop == ILT_MEMOP_FREE) {
623                 BNX2X_ILT_FREE(line->page, line->page_mapping, line->size);
624                 return 0;
625         }
626         BNX2X_ILT_ZALLOC(line->page, &line->page_mapping, size);
627         if (!line->page)
628                 return -1;
629         line->size = size;
630         return 0;
631 }
632
633
634 static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num,
635                                    uint8_t memop)
636 {
637         int i, rc;
638         struct bnx2x_ilt *ilt = BP_ILT(bp);
639         struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
640
641         if (!ilt || !ilt->lines)
642                 return -1;
643
644         if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
645                 return 0;
646
647         for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
648                 rc = bnx2x_ilt_line_mem_op(bp, &ilt->lines[i],
649                                            ilt_cli->page_size, memop);
650         }
651         return rc;
652 }
653
654 static int bnx2x_ilt_mem_op_cnic(struct bnx2x *bp, uint8_t memop)
655 {
656         int rc = 0;
657
658         if (CONFIGURE_NIC_MODE(bp))
659                 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
660         if (!rc)
661                 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_TM, memop);
662
663         return rc;
664 }
665
666 static int bnx2x_ilt_mem_op(struct bnx2x *bp, uint8_t memop)
667 {
668         int rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_CDU, memop);
669         if (!rc)
670                 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_QM, memop);
671         if (!rc && CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp))
672                 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
673
674         return rc;
675 }
676
677 static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx,
678                               dma_addr_t page_mapping)
679 {
680         uint32_t reg;
681
682         if (CHIP_IS_E1(bp))
683                 reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
684         else
685                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
686
687         bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
688 }
689
690 static void bnx2x_ilt_line_init_op(struct bnx2x *bp,
691                                    struct bnx2x_ilt *ilt, int idx,
692                                    uint8_t initop)
693 {
694         dma_addr_t      null_mapping;
695         int abs_idx = ilt->start_line + idx;
696
697
698         switch (initop) {
699         case INITOP_INIT:
700                 /* set in the init-value array */
701         case INITOP_SET:
702                 bnx2x_ilt_line_wr(bp, abs_idx, ilt->lines[idx].page_mapping);
703                 break;
704         case INITOP_CLEAR:
705                 null_mapping = 0;
706                 bnx2x_ilt_line_wr(bp, abs_idx, null_mapping);
707                 break;
708         }
709 }
710
711 static void bnx2x_ilt_boundry_init_op(struct bnx2x *bp,
712                                       struct ilt_client_info *ilt_cli,
713                                       uint32_t ilt_start, uint8_t initop)
714 {
715         uint32_t start_reg = 0;
716         uint32_t end_reg = 0;
717
718         /* The boundary is either SET or INIT,
719            CLEAR => SET and for now SET ~~ INIT */
720
721         /* find the appropriate regs */
722         if (CHIP_IS_E1(bp)) {
723                 switch (ilt_cli->client_num) {
724                 case ILT_CLIENT_CDU:
725                         start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
726                         break;
727                 case ILT_CLIENT_QM:
728                         start_reg = PXP2_REG_PSWRQ_QM0_L2P;
729                         break;
730                 case ILT_CLIENT_SRC:
731                         start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
732                         break;
733                 case ILT_CLIENT_TM:
734                         start_reg = PXP2_REG_PSWRQ_TM0_L2P;
735                         break;
736                 }
737                 REG_WR(bp, start_reg + BP_FUNC(bp)*4,
738                        ILT_RANGE((ilt_start + ilt_cli->start),
739                                  (ilt_start + ilt_cli->end)));
740         } else {
741                 switch (ilt_cli->client_num) {
742                 case ILT_CLIENT_CDU:
743                         start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
744                         end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
745                         break;
746                 case ILT_CLIENT_QM:
747                         start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
748                         end_reg = PXP2_REG_RQ_QM_LAST_ILT;
749                         break;
750                 case ILT_CLIENT_SRC:
751                         start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
752                         end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
753                         break;
754                 case ILT_CLIENT_TM:
755                         start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
756                         end_reg = PXP2_REG_RQ_TM_LAST_ILT;
757                         break;
758                 }
759                 REG_WR(bp, start_reg, (ilt_start + ilt_cli->start));
760                 REG_WR(bp, end_reg, (ilt_start + ilt_cli->end));
761         }
762 }
763
764 static void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp,
765                                          struct bnx2x_ilt *ilt,
766                                          struct ilt_client_info *ilt_cli,
767                                          uint8_t initop)
768 {
769         int i;
770
771         if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
772                 return;
773
774         for (i = ilt_cli->start; i <= ilt_cli->end; i++)
775                 bnx2x_ilt_line_init_op(bp, ilt, i, initop);
776
777         /* init/clear the ILT boundries */
778         bnx2x_ilt_boundry_init_op(bp, ilt_cli, ilt->start_line, initop);
779 }
780
781 static void bnx2x_ilt_client_init_op(struct bnx2x *bp,
782                                      struct ilt_client_info *ilt_cli,
783                                      uint8_t initop)
784 {
785         struct bnx2x_ilt *ilt = BP_ILT(bp);
786
787         bnx2x_ilt_client_init_op_ilt(bp, ilt, ilt_cli, initop);
788 }
789
790 static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp,
791                                         int cli_num, uint8_t initop)
792 {
793         struct bnx2x_ilt *ilt = BP_ILT(bp);
794         struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
795
796         bnx2x_ilt_client_init_op(bp, ilt_cli, initop);
797 }
798
799 static void bnx2x_ilt_init_op_cnic(struct bnx2x *bp, uint8_t initop)
800 {
801         if (CONFIGURE_NIC_MODE(bp))
802                 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
803         bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_TM, initop);
804 }
805
806 static void bnx2x_ilt_init_op(struct bnx2x *bp, uint8_t initop)
807 {
808         bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_CDU, initop);
809         bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_QM, initop);
810         if (CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp))
811                 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
812 }
813
814 static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num,
815                                       uint32_t psz_reg, uint8_t initop)
816 {
817         struct bnx2x_ilt *ilt = BP_ILT(bp);
818         struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
819
820         if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
821                 return;
822
823         switch (initop) {
824         case INITOP_INIT:
825                 /* set in the init-value array */
826         case INITOP_SET:
827                 REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12));
828                 break;
829         case INITOP_CLEAR:
830                 break;
831         }
832 }
833
834 /*
835  * called during init common stage, ilt clients should be initialized
836  * prioir to calling this function
837  */
838 static void bnx2x_ilt_init_page_size(struct bnx2x *bp, uint8_t initop)
839 {
840         bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_CDU,
841                                   PXP2_REG_RQ_CDU_P_SIZE, initop);
842         bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_QM,
843                                   PXP2_REG_RQ_QM_P_SIZE, initop);
844         bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_SRC,
845                                   PXP2_REG_RQ_SRC_P_SIZE, initop);
846         bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_TM,
847                                   PXP2_REG_RQ_TM_P_SIZE, initop);
848 }
849
850 /****************************************************************************
851 * QM initializations
852 ****************************************************************************/
853 #define QM_QUEUES_PER_FUNC      16 /* E1 has 32, but only 16 are used */
854 #define QM_INIT_MIN_CID_COUNT   31
855 #define QM_INIT(cid_cnt)        (cid_cnt > QM_INIT_MIN_CID_COUNT)
856
857 /* called during init port stage */
858 static void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count,
859                                     uint8_t initop)
860 {
861         int port = BP_PORT(bp);
862
863         if (QM_INIT(qm_cid_count)) {
864                 switch (initop) {
865                 case INITOP_INIT:
866                         /* set in the init-value array */
867                 case INITOP_SET:
868                         REG_WR(bp, QM_REG_CONNNUM_0 + port*4,
869                                qm_cid_count/16 - 1);
870                         break;
871                 case INITOP_CLEAR:
872                         break;
873                 }
874         }
875 }
876
877 static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count,
878                                    uint32_t base_reg, uint32_t reg)
879 {
880         int i;
881         uint32_t wb_data[2] = {0, 0};
882         for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
883                 REG_WR(bp, base_reg + i*4,
884                        qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
885                 bnx2x_init_wr_wb(bp, reg + i*8,  wb_data, 2);
886         }
887 }
888
889 /* called during init common stage */
890 static void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count,
891                                     uint8_t initop)
892 {
893         if (!QM_INIT(qm_cid_count))
894                 return;
895
896         switch (initop) {
897         case INITOP_INIT:
898                 /* set in the init-value array */
899         case INITOP_SET:
900                 bnx2x_qm_set_ptr_table(bp, qm_cid_count,
901                                        QM_REG_BASEADDR, QM_REG_PTRTBL);
902                 if (CHIP_IS_E1H(bp))
903                         bnx2x_qm_set_ptr_table(bp, qm_cid_count,
904                                                QM_REG_BASEADDR_EXT_A,
905                                                QM_REG_PTRTBL_EXT_A);
906                 break;
907         case INITOP_CLEAR:
908                 break;
909         }
910 }
911
912 /****************************************************************************
913 * SRC initializations
914 ****************************************************************************/
915 /* called during init func stage */
916 static void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2,
917                               dma_addr_t t2_mapping, int src_cid_count)
918 {
919         int i;
920         int port = BP_PORT(bp);
921
922         /* Initialize T2 */
923         for (i = 0; i < src_cid_count-1; i++)
924                 t2[i].next = (uint64_t)(t2_mapping +
925                              (i+1)*sizeof(struct src_ent));
926
927         /* tell the searcher where the T2 table is */
928         REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
929
930         bnx2x_wr_64(bp, SRC_REG_FIRSTFREE0 + port*16,
931                     U64_LO(t2_mapping), U64_HI(t2_mapping));
932
933         bnx2x_wr_64(bp, SRC_REG_LASTFREE0 + port*16,
934                     U64_LO((uint64_t)t2_mapping +
935                            (src_cid_count-1) * sizeof(struct src_ent)),
936                     U64_HI((uint64_t)t2_mapping +
937                            (src_cid_count-1) * sizeof(struct src_ent)));
938 }