BNX2X: limit queues to 2
[akaros.git] / kern / drivers / net / bnx2x / bnx2x_hsi.h
1 /* bnx2x_hsi.h: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9 #ifndef BNX2X_HSI_H
10 #define BNX2X_HSI_H
11
12 #include "bnx2x_fw_defs.h"
13 #include "bnx2x_mfw_req.h"
14
15 #define FW_ENCODE_32BIT_PATTERN         0x1e1e1e1e
16
17 struct license_key {
18         uint32_t reserved[6];
19
20         uint32_t max_iscsi_conn;
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK  0xFFFF
22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK  0xFFFF0000
24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
25
26         uint32_t reserved_a;
27
28         uint32_t max_fcoe_conn;
29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK   0xFFFF
30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT  0
31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK   0xFFFF0000
32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT  16
33
34         uint32_t reserved_b[4];
35 };
36
37 /****************************************************************************
38  * Shared HW configuration                                                  *
39  ****************************************************************************/
40 #define PIN_CFG_NA                          0x00000000
41 #define PIN_CFG_GPIO0_P0                    0x00000001
42 #define PIN_CFG_GPIO1_P0                    0x00000002
43 #define PIN_CFG_GPIO2_P0                    0x00000003
44 #define PIN_CFG_GPIO3_P0                    0x00000004
45 #define PIN_CFG_GPIO0_P1                    0x00000005
46 #define PIN_CFG_GPIO1_P1                    0x00000006
47 #define PIN_CFG_GPIO2_P1                    0x00000007
48 #define PIN_CFG_GPIO3_P1                    0x00000008
49 #define PIN_CFG_EPIO0                       0x00000009
50 #define PIN_CFG_EPIO1                       0x0000000a
51 #define PIN_CFG_EPIO2                       0x0000000b
52 #define PIN_CFG_EPIO3                       0x0000000c
53 #define PIN_CFG_EPIO4                       0x0000000d
54 #define PIN_CFG_EPIO5                       0x0000000e
55 #define PIN_CFG_EPIO6                       0x0000000f
56 #define PIN_CFG_EPIO7                       0x00000010
57 #define PIN_CFG_EPIO8                       0x00000011
58 #define PIN_CFG_EPIO9                       0x00000012
59 #define PIN_CFG_EPIO10                      0x00000013
60 #define PIN_CFG_EPIO11                      0x00000014
61 #define PIN_CFG_EPIO12                      0x00000015
62 #define PIN_CFG_EPIO13                      0x00000016
63 #define PIN_CFG_EPIO14                      0x00000017
64 #define PIN_CFG_EPIO15                      0x00000018
65 #define PIN_CFG_EPIO16                      0x00000019
66 #define PIN_CFG_EPIO17                      0x0000001a
67 #define PIN_CFG_EPIO18                      0x0000001b
68 #define PIN_CFG_EPIO19                      0x0000001c
69 #define PIN_CFG_EPIO20                      0x0000001d
70 #define PIN_CFG_EPIO21                      0x0000001e
71 #define PIN_CFG_EPIO22                      0x0000001f
72 #define PIN_CFG_EPIO23                      0x00000020
73 #define PIN_CFG_EPIO24                      0x00000021
74 #define PIN_CFG_EPIO25                      0x00000022
75 #define PIN_CFG_EPIO26                      0x00000023
76 #define PIN_CFG_EPIO27                      0x00000024
77 #define PIN_CFG_EPIO28                      0x00000025
78 #define PIN_CFG_EPIO29                      0x00000026
79 #define PIN_CFG_EPIO30                      0x00000027
80 #define PIN_CFG_EPIO31                      0x00000028
81
82 /* EPIO definition */
83 #define EPIO_CFG_NA                         0x00000000
84 #define EPIO_CFG_EPIO0                      0x00000001
85 #define EPIO_CFG_EPIO1                      0x00000002
86 #define EPIO_CFG_EPIO2                      0x00000003
87 #define EPIO_CFG_EPIO3                      0x00000004
88 #define EPIO_CFG_EPIO4                      0x00000005
89 #define EPIO_CFG_EPIO5                      0x00000006
90 #define EPIO_CFG_EPIO6                      0x00000007
91 #define EPIO_CFG_EPIO7                      0x00000008
92 #define EPIO_CFG_EPIO8                      0x00000009
93 #define EPIO_CFG_EPIO9                      0x0000000a
94 #define EPIO_CFG_EPIO10                     0x0000000b
95 #define EPIO_CFG_EPIO11                     0x0000000c
96 #define EPIO_CFG_EPIO12                     0x0000000d
97 #define EPIO_CFG_EPIO13                     0x0000000e
98 #define EPIO_CFG_EPIO14                     0x0000000f
99 #define EPIO_CFG_EPIO15                     0x00000010
100 #define EPIO_CFG_EPIO16                     0x00000011
101 #define EPIO_CFG_EPIO17                     0x00000012
102 #define EPIO_CFG_EPIO18                     0x00000013
103 #define EPIO_CFG_EPIO19                     0x00000014
104 #define EPIO_CFG_EPIO20                     0x00000015
105 #define EPIO_CFG_EPIO21                     0x00000016
106 #define EPIO_CFG_EPIO22                     0x00000017
107 #define EPIO_CFG_EPIO23                     0x00000018
108 #define EPIO_CFG_EPIO24                     0x00000019
109 #define EPIO_CFG_EPIO25                     0x0000001a
110 #define EPIO_CFG_EPIO26                     0x0000001b
111 #define EPIO_CFG_EPIO27                     0x0000001c
112 #define EPIO_CFG_EPIO28                     0x0000001d
113 #define EPIO_CFG_EPIO29                     0x0000001e
114 #define EPIO_CFG_EPIO30                     0x0000001f
115 #define EPIO_CFG_EPIO31                     0x00000020
116
117 struct mac_addr {
118         uint32_t upper;
119         uint32_t lower;
120 };
121
122 struct shared_hw_cfg {                   /* NVRAM Offset */
123         /* Up to 16 bytes of NULL-terminated string */
124         uint8_t  part_num[16];              /* 0x104 */
125
126         uint32_t config;                        /* 0x114 */
127         #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
128                 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT             0
129                 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V              0x00000000
130                 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V              0x00000001
131         #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
132
133         #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
134
135         #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
136
137         #define SHARED_HW_CFG_PCIE_GEN3_DISABLED            0x00000000
138         #define SHARED_HW_CFG_PCIE_GEN3_ENABLED             0x00000010
139
140         #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
141                 #define SHARED_HW_CFG_MFW_SELECT_SHIFT               8
142         /* Whatever MFW found in NVM
143            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
144                 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT             0x00000000
145                 #define SHARED_HW_CFG_MFW_SELECT_NC_SI               0x00000100
146                 #define SHARED_HW_CFG_MFW_SELECT_UMP                 0x00000200
147                 #define SHARED_HW_CFG_MFW_SELECT_IPMI                0x00000300
148         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
149           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
150                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI    0x00000400
151         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
152           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
153                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI      0x00000500
154         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
155           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
156                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP     0x00000600
157
158         #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
159                 #define SHARED_HW_CFG_LED_MODE_SHIFT                 16
160                 #define SHARED_HW_CFG_LED_MAC1                       0x00000000
161                 #define SHARED_HW_CFG_LED_PHY1                       0x00010000
162                 #define SHARED_HW_CFG_LED_PHY2                       0x00020000
163                 #define SHARED_HW_CFG_LED_PHY3                       0x00030000
164                 #define SHARED_HW_CFG_LED_MAC2                       0x00040000
165                 #define SHARED_HW_CFG_LED_PHY4                       0x00050000
166                 #define SHARED_HW_CFG_LED_PHY5                       0x00060000
167                 #define SHARED_HW_CFG_LED_PHY6                       0x00070000
168                 #define SHARED_HW_CFG_LED_MAC3                       0x00080000
169                 #define SHARED_HW_CFG_LED_PHY7                       0x00090000
170                 #define SHARED_HW_CFG_LED_PHY9                       0x000a0000
171                 #define SHARED_HW_CFG_LED_PHY11                      0x000b0000
172                 #define SHARED_HW_CFG_LED_MAC4                       0x000c0000
173                 #define SHARED_HW_CFG_LED_PHY8                       0x000d0000
174                 #define SHARED_HW_CFG_LED_EXTPHY1                    0x000e0000
175                 #define SHARED_HW_CFG_LED_EXTPHY2                    0x000f0000
176
177
178         #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
179                 #define SHARED_HW_CFG_AN_ENABLE_SHIFT                24
180                 #define SHARED_HW_CFG_AN_ENABLE_CL37                 0x01000000
181                 #define SHARED_HW_CFG_AN_ENABLE_CL73                 0x02000000
182                 #define SHARED_HW_CFG_AN_ENABLE_BAM                  0x04000000
183                 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION   0x08000000
184                 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT  0x10000000
185                 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY           0x20000000
186
187         #define SHARED_HW_CFG_SRIOV_MASK                    0x40000000
188                 #define SHARED_HW_CFG_SRIOV_DISABLED                 0x00000000
189                 #define SHARED_HW_CFG_SRIOV_ENABLED                  0x40000000
190
191         #define SHARED_HW_CFG_ATC_MASK                      0x80000000
192                 #define SHARED_HW_CFG_ATC_DISABLED                   0x00000000
193                 #define SHARED_HW_CFG_ATC_ENABLED                    0x80000000
194
195         uint32_t config2;                           /* 0x118 */
196         /* one time auto detect grace period (in sec) */
197         #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
198         #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT                     0
199
200         #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
201         #define SHARED_HW_CFG_PCIE_GEN2_DISABLED            0x00000000
202
203         /* The default value for the core clock is 250MHz and it is
204            achieved by setting the clock change to 4 */
205         #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
206         #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT                     9
207
208         #define SHARED_HW_CFG_SMBUS_TIMING_MASK             0x00001000
209                 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ            0x00000000
210                 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ            0x00001000
211
212         #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
213
214         #define SHARED_HW_CFG_WOL_CAPABLE_MASK              0x00004000
215                 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED           0x00000000
216                 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED            0x00004000
217
218                 /* Output low when PERST is asserted */
219         #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK       0x00008000
220                 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED    0x00000000
221                 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED     0x00008000
222
223         #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK    0x00070000
224                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT    16
225                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW       0x00000000
226                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB      0x00010000
227                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB    0x00020000
228                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB    0x00030000
229
230         /*  The fan failure mechanism is usually related to the PHY type
231               since the power consumption of the board is determined by the PHY.
232               Currently, fan is required for most designs with SFX7101, BCM8727
233               and BCM8481. If a fan is not required for a board which uses one
234               of those PHYs, this field should be set to "Disabled". If a fan is
235               required for a different PHY type, this option should be set to
236               "Enabled". The fan failure indication is expected on SPIO5 */
237         #define SHARED_HW_CFG_FAN_FAILURE_MASK              0x00180000
238                 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT              19
239                 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE           0x00000000
240                 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED           0x00080000
241                 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED            0x00100000
242
243                 /* ASPM Power Management support */
244         #define SHARED_HW_CFG_ASPM_SUPPORT_MASK             0x00600000
245                 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT             21
246                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED    0x00000000
247                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED      0x00200000
248                 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED       0x00400000
249                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED   0x00600000
250
251         /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
252            tl_control_0 (register 0x2800) */
253         #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK         0x00800000
254                 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED      0x00000000
255                 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED       0x00800000
256
257         #define SHARED_HW_CFG_PORT_MODE_MASK                0x01000000
258                 #define SHARED_HW_CFG_PORT_MODE_2                    0x00000000
259                 #define SHARED_HW_CFG_PORT_MODE_4                    0x01000000
260
261         #define SHARED_HW_CFG_PATH_SWAP_MASK                0x02000000
262                 #define SHARED_HW_CFG_PATH_SWAP_DISABLED             0x00000000
263                 #define SHARED_HW_CFG_PATH_SWAP_ENABLED              0x02000000
264
265         /*  Set the MDC/MDIO access for the first external phy */
266         #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000
267                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT         26
268                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE      0x00000000
269                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0         0x04000000
270                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1         0x08000000
271                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH          0x0c000000
272                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED       0x10000000
273
274         /*  Set the MDC/MDIO access for the second external phy */
275         #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000
276                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT         29
277                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE      0x00000000
278                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0         0x20000000
279                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1         0x40000000
280                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH          0x60000000
281                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED       0x80000000
282
283         uint32_t config_3;                              /* 0x11C */
284         #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK         0x00000F00
285                 #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT              8
286                 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5        0x00000000
287                 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0        0x00000100
288
289         uint32_t ump_nc_si_config;                      /* 0x120 */
290         #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
291                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT       0
292                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC         0x00000000
293                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY         0x00000001
294                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII         0x00000000
295                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII        0x00000002
296
297         #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
298                 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT       8
299
300         #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
301                 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT   16
302                 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE    0x00000000
303                 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
304
305         uint32_t board;                 /* 0x124 */
306         #define SHARED_HW_CFG_E3_I2C_MUX0_MASK              0x0000003F
307         #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT                      0
308         #define SHARED_HW_CFG_E3_I2C_MUX1_MASK              0x00000FC0
309         #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT                      6
310         /* Use the PIN_CFG_XXX defines on top */
311         #define SHARED_HW_CFG_BOARD_REV_MASK                0x00ff0000
312         #define SHARED_HW_CFG_BOARD_REV_SHIFT                        16
313
314         #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0f000000
315         #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT                  24
316
317         #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xf0000000
318         #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT                  28
319
320         uint32_t wc_lane_config;                                    /* 0x128 */
321         #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK            0x0000FFFF
322                 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT            0
323                 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210         0x00001b1b
324                 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123         0x00001be4
325                 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210         0x0000e41b
326                 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123         0x0000e4e4
327         #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK         0x000000FF
328         #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                 0
329         #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK         0x0000FF00
330         #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                 8
331
332         /* TX lane Polarity swap */
333         #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED     0x00010000
334         #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED     0x00020000
335         #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED     0x00040000
336         #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED     0x00080000
337         /* TX lane Polarity swap */
338         #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED     0x00100000
339         #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED     0x00200000
340         #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED     0x00400000
341         #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED     0x00800000
342
343         /*  Selects the port layout of the board */
344         #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK           0x0F000000
345                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT           24
346                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01           0x00000000
347                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10           0x01000000
348                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123         0x02000000
349                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032         0x03000000
350                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301         0x04000000
351                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210         0x05000000
352 };
353
354
355 /****************************************************************************
356  * Port HW configuration                                                    *
357  ****************************************************************************/
358 struct port_hw_cfg {                /* port 0: 0x12c  port 1: 0x2bc */
359
360         uint32_t pci_id;
361         #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
362         #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
363
364         uint32_t pci_sub_id;
365         #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
366         #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
367
368         uint32_t power_dissipated;
369         #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
370         #define PORT_HW_CFG_POWER_DIS_D0_SHIFT                       0
371         #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
372         #define PORT_HW_CFG_POWER_DIS_D1_SHIFT                       8
373         #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
374         #define PORT_HW_CFG_POWER_DIS_D2_SHIFT                       16
375         #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
376         #define PORT_HW_CFG_POWER_DIS_D3_SHIFT                       24
377
378         uint32_t power_consumed;
379         #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
380         #define PORT_HW_CFG_POWER_CONS_D0_SHIFT                      0
381         #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
382         #define PORT_HW_CFG_POWER_CONS_D1_SHIFT                      8
383         #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
384         #define PORT_HW_CFG_POWER_CONS_D2_SHIFT                      16
385         #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
386         #define PORT_HW_CFG_POWER_CONS_D3_SHIFT                      24
387
388         uint32_t mac_upper;
389         #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
390         #define PORT_HW_CFG_UPPERMAC_SHIFT                           0
391         uint32_t mac_lower;
392
393         uint32_t iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
394         uint32_t iscsi_mac_lower;
395
396         uint32_t rdma_mac_upper;   /* Upper 16 bits are always zeroes */
397         uint32_t rdma_mac_lower;
398
399         uint32_t serdes_config;
400         #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
401         #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT         0
402
403         #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0xffff0000
404         #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT            16
405
406
407         /*  Default values: 2P-64, 4P-32 */
408         uint32_t pf_config;                                         /* 0x158 */
409         #define PORT_HW_CFG_PF_NUM_VF_MASK                  0x0000007F
410         #define PORT_HW_CFG_PF_NUM_VF_SHIFT                          0
411
412         /*  Default values: 17 */
413         #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK        0x00007F00
414         #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT                8
415
416         #define PORT_HW_CFG_ENABLE_FLR_MASK                 0x00010000
417         #define PORT_HW_CFG_FLR_ENABLED                     0x00010000
418
419         uint32_t vf_config;                                         /* 0x15C */
420         #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK        0x0000007F
421         #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT                0
422
423         #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK           0xFFFF0000
424         #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT                   16
425
426         uint32_t mf_pci_id;                                         /* 0x160 */
427         #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK           0x0000FFFF
428         #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT                   0
429
430         /*  Controls the TX laser of the SFP+ module */
431         uint32_t sfp_ctrl;                                          /* 0x164 */
432         #define PORT_HW_CFG_TX_LASER_MASK                   0x000000FF
433                 #define PORT_HW_CFG_TX_LASER_SHIFT                   0
434                 #define PORT_HW_CFG_TX_LASER_MDIO                    0x00000000
435                 #define PORT_HW_CFG_TX_LASER_GPIO0                   0x00000001
436                 #define PORT_HW_CFG_TX_LASER_GPIO1                   0x00000002
437                 #define PORT_HW_CFG_TX_LASER_GPIO2                   0x00000003
438                 #define PORT_HW_CFG_TX_LASER_GPIO3                   0x00000004
439
440         /*  Controls the fault module LED of the SFP+ */
441         #define PORT_HW_CFG_FAULT_MODULE_LED_MASK           0x0000FF00
442                 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT           8
443                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0           0x00000000
444                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1           0x00000100
445                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2           0x00000200
446                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3           0x00000300
447                 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED        0x00000400
448
449         /*  The output pin TX_DIS that controls the TX laser of the SFP+
450           module. Use the PIN_CFG_XXX defines on top */
451         uint32_t e3_sfp_ctrl;                               /* 0x168 */
452         #define PORT_HW_CFG_E3_TX_LASER_MASK                0x000000FF
453         #define PORT_HW_CFG_E3_TX_LASER_SHIFT                        0
454
455         /*  The output pin for SFPP_TYPE which turns on the Fault module LED */
456         #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK           0x0000FF00
457         #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT                   8
458
459         /*  The input pin MOD_ABS that indicates whether SFP+ module is
460           present or not. Use the PIN_CFG_XXX defines on top */
461         #define PORT_HW_CFG_E3_MOD_ABS_MASK                 0x00FF0000
462         #define PORT_HW_CFG_E3_MOD_ABS_SHIFT                         16
463
464         /*  The output pin PWRDIS_SFP_X which disable the power of the SFP+
465           module. Use the PIN_CFG_XXX defines on top */
466         #define PORT_HW_CFG_E3_PWR_DIS_MASK                 0xFF000000
467         #define PORT_HW_CFG_E3_PWR_DIS_SHIFT                         24
468
469         /*
470          * The input pin which signals module transmit fault. Use the
471          * PIN_CFG_XXX defines on top
472          */
473         uint32_t e3_cmn_pin_cfg;                                    /* 0x16C */
474         #define PORT_HW_CFG_E3_TX_FAULT_MASK                0x000000FF
475         #define PORT_HW_CFG_E3_TX_FAULT_SHIFT                        0
476
477         /*  The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
478          top */
479         #define PORT_HW_CFG_E3_PHY_RESET_MASK               0x0000FF00
480         #define PORT_HW_CFG_E3_PHY_RESET_SHIFT                       8
481
482         /*
483          * The output pin which powers down the PHY. Use the PIN_CFG_XXX
484          * defines on top
485          */
486         #define PORT_HW_CFG_E3_PWR_DOWN_MASK                0x00FF0000
487         #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT                        16
488
489         /*  The output pin values BSC_SEL which selects the I2C for this port
490           in the I2C Mux */
491         #define PORT_HW_CFG_E3_I2C_MUX0_MASK                0x01000000
492         #define PORT_HW_CFG_E3_I2C_MUX1_MASK                0x02000000
493
494
495         /*
496          * The input pin I_FAULT which indicate over-current has occurred.
497          * Use the PIN_CFG_XXX defines on top
498          */
499         uint32_t e3_cmn_pin_cfg1;                                   /* 0x170 */
500         #define PORT_HW_CFG_E3_OVER_CURRENT_MASK            0x000000FF
501         #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT                    0
502
503         /*  pause on host ring */
504         uint32_t generic_features;                               /* 0x174 */
505         #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK                   0x00000001
506         #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT                  0
507         #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED               0x00000000
508         #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED                0x00000001
509
510         /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
511          * LOM recommended and tested value is 0xBEB2. Using a different
512          * value means using a value not tested by BRCM
513          */
514         uint32_t sfi_tap_values;                                 /* 0x178 */
515         #define PORT_HW_CFG_TX_EQUALIZATION_MASK                      0x0000FFFF
516         #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT                     0
517
518         /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
519          * value is 0x2. LOM recommended and tested value is 0x2. Using a
520          * different value means using a value not tested by BRCM
521          */
522         #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK                     0x000F0000
523         #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT                    16
524
525         uint32_t reserved0[5];                              /* 0x17c */
526
527         uint32_t aeu_int_mask;                              /* 0x190 */
528
529         uint32_t media_type;                                        /* 0x194 */
530         #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK            0x000000FF
531         #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT                    0
532
533         #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK            0x0000FF00
534         #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT                    8
535
536         #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK            0x00FF0000
537         #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT                    16
538
539         /*  4 times 16 bits for all 4 lanes. In case external PHY is present
540               (not direct mode), those values will not take effect on the 4 XGXS
541               lanes. For some external PHYs (such as 8706 and 8726) the values
542               will be used to configure the external PHY  in those cases, not
543               all 4 values are needed. */
544         uint16_t xgxs_config_rx[4];                     /* 0x198 */
545         uint16_t xgxs_config_tx[4];                     /* 0x1A0 */
546
547         /* For storing FCOE mac on shared memory */
548         uint32_t fcoe_fip_mac_upper;
549         #define PORT_HW_CFG_FCOE_UPPERMAC_MASK              0x0000ffff
550         #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT                      0
551         uint32_t fcoe_fip_mac_lower;
552
553         uint32_t fcoe_wwn_port_name_upper;
554         uint32_t fcoe_wwn_port_name_lower;
555
556         uint32_t fcoe_wwn_node_name_upper;
557         uint32_t fcoe_wwn_node_name_lower;
558
559         uint32_t Reserved1[49];                             /* 0x1C0 */
560
561         /*  Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
562               84833 only */
563         uint32_t xgbt_phy_cfg;                              /* 0x284 */
564         #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK             0x000000FF
565         #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT                     0
566
567                 uint32_t default_cfg;                       /* 0x288 */
568         #define PORT_HW_CFG_GPIO0_CONFIG_MASK               0x00000003
569                 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT               0
570                 #define PORT_HW_CFG_GPIO0_CONFIG_NA                  0x00000000
571                 #define PORT_HW_CFG_GPIO0_CONFIG_LOW                 0x00000001
572                 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH                0x00000002
573                 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT               0x00000003
574
575         #define PORT_HW_CFG_GPIO1_CONFIG_MASK               0x0000000C
576                 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT               2
577                 #define PORT_HW_CFG_GPIO1_CONFIG_NA                  0x00000000
578                 #define PORT_HW_CFG_GPIO1_CONFIG_LOW                 0x00000004
579                 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH                0x00000008
580                 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT               0x0000000c
581
582         #define PORT_HW_CFG_GPIO2_CONFIG_MASK               0x00000030
583                 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT               4
584                 #define PORT_HW_CFG_GPIO2_CONFIG_NA                  0x00000000
585                 #define PORT_HW_CFG_GPIO2_CONFIG_LOW                 0x00000010
586                 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH                0x00000020
587                 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT               0x00000030
588
589         #define PORT_HW_CFG_GPIO3_CONFIG_MASK               0x000000C0
590                 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT               6
591                 #define PORT_HW_CFG_GPIO3_CONFIG_NA                  0x00000000
592                 #define PORT_HW_CFG_GPIO3_CONFIG_LOW                 0x00000040
593                 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH                0x00000080
594                 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT               0x000000c0
595
596         /*  When KR link is required to be set to force which is not
597               KR-compliant, this parameter determine what is the trigger for it.
598               When GPIO is selected, low input will force the speed. Currently
599               default speed is 1G. In the future, it may be widen to select the
600               forced speed in with another parameter. Note when force-1G is
601               enabled, it override option 56: Link Speed option. */
602         #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK           0x00000F00
603                 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT           8
604                 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED      0x00000000
605                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0        0x00000100
606                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0        0x00000200
607                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0        0x00000300
608                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0        0x00000400
609                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1        0x00000500
610                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1        0x00000600
611                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1        0x00000700
612                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1        0x00000800
613                 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED          0x00000900
614         /*  Enable to determine with which GPIO to reset the external phy */
615         #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK           0x000F0000
616                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT           16
617                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE        0x00000000
618                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0        0x00010000
619                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0        0x00020000
620                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0        0x00030000
621                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0        0x00040000
622                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1        0x00050000
623                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1        0x00060000
624                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1        0x00070000
625                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1        0x00080000
626
627         /*  Enable BAM on KR */
628         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK           0x00100000
629         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT                   20
630         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED                0x00000000
631         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED                 0x00100000
632
633         /*  Enable Common Mode Sense */
634         #define PORT_HW_CFG_ENABLE_CMS_MASK                 0x00200000
635         #define PORT_HW_CFG_ENABLE_CMS_SHIFT                         21
636         #define PORT_HW_CFG_ENABLE_CMS_DISABLED                      0x00000000
637         #define PORT_HW_CFG_ENABLE_CMS_ENABLED                       0x00200000
638
639         /*  Determine the Serdes electrical interface   */
640         #define PORT_HW_CFG_NET_SERDES_IF_MASK              0x0F000000
641         #define PORT_HW_CFG_NET_SERDES_IF_SHIFT                      24
642         #define PORT_HW_CFG_NET_SERDES_IF_SGMII                      0x00000000
643         #define PORT_HW_CFG_NET_SERDES_IF_XFI                        0x01000000
644         #define PORT_HW_CFG_NET_SERDES_IF_SFI                        0x02000000
645         #define PORT_HW_CFG_NET_SERDES_IF_KR                         0x03000000
646         #define PORT_HW_CFG_NET_SERDES_IF_DXGXS                      0x04000000
647         #define PORT_HW_CFG_NET_SERDES_IF_KR2                        0x05000000
648
649
650         uint32_t speed_capability_mask2;                            /* 0x28C */
651         #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK       0x0000FFFF
652                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT       0
653                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL    0x00000001
654                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__           0x00000002
655                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___          0x00000004
656                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL   0x00000008
657                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G          0x00000010
658                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G    0x00000020
659                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G         0x00000040
660                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G         0x00000080
661
662         #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK       0xFFFF0000
663                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT       16
664                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL    0x00010000
665                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__           0x00020000
666                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___          0x00040000
667                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL   0x00080000
668                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G          0x00100000
669                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G    0x00200000
670                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G         0x00400000
671                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G         0x00800000
672
673
674         /*  In the case where two media types (e.g. copper and fiber) are
675               present and electrically active at the same time, PHY Selection
676               will determine which of the two PHYs will be designated as the
677               Active PHY and used for a connection to the network.  */
678         uint32_t multi_phy_config;                                  /* 0x290 */
679         #define PORT_HW_CFG_PHY_SELECTION_MASK              0x00000007
680                 #define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
681                 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
682                 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001
683                 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002
684                 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
685                 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
686
687         /*  When enabled, all second phy nvram parameters will be swapped
688               with the first phy parameters */
689         #define PORT_HW_CFG_PHY_SWAPPED_MASK                0x00000008
690                 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3
691                 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000
692                 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008
693
694
695         /*  Address of the second external phy */
696         uint32_t external_phy_config2;                      /* 0x294 */
697         #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
698         #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT                 0
699
700         /*  The second XGXS external PHY type */
701         #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00
702                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT         8
703                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT        0x00000000
704                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071       0x00000100
705                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072       0x00000200
706                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073       0x00000300
707                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705       0x00000400
708                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706       0x00000500
709                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726       0x00000600
710                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481       0x00000700
711                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101       0x00000800
712                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727       0x00000900
713                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC   0x00000a00
714                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823      0x00000b00
715                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640      0x00000c00
716                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833      0x00000d00
717                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE    0x00000e00
718                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722       0x00000f00
719                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616      0x00001000
720                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834      0x00001100
721                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE       0x0000fd00
722                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN      0x0000ff00
723
724
725         /*  4 times 16 bits for all 4 lanes. For some external PHYs (such as
726               8706, 8726 and 8727) not all 4 values are needed. */
727         uint16_t xgxs_config2_rx[4];                                /* 0x296 */
728         uint16_t xgxs_config2_tx[4];                                /* 0x2A0 */
729
730         uint32_t lane_config;
731         #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
732                 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT              0
733                 /* AN and forced */
734                 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123           0x00001b1b
735                 /* forced only */
736                 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210           0x00001be4
737                 /* forced only */
738                 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120           0x0000d8d8
739                 /* forced only */
740                 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210           0x0000e4e4
741         #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
742         #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                   0
743         #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
744         #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                   8
745         #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
746         #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT               14
747
748         /*  Indicate whether to swap the external phy polarity */
749         #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK          0x00010000
750                 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED       0x00000000
751                 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED        0x00010000
752
753
754         uint32_t external_phy_config;
755         #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
756         #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT                  0
757
758         #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
759                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT          8
760                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT         0x00000000
761                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071        0x00000100
762                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072        0x00000200
763                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073        0x00000300
764                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705        0x00000400
765                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706        0x00000500
766                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726        0x00000600
767                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481        0x00000700
768                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101        0x00000800
769                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727        0x00000900
770                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC    0x00000a00
771                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823       0x00000b00
772                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640       0x00000c00
773                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833       0x00000d00
774                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE     0x00000e00
775                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722        0x00000f00
776                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616       0x00001000
777                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834       0x00001100
778                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC      0x0000fc00
779                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE        0x0000fd00
780                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN       0x0000ff00
781
782         #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
783         #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT                16
784
785         #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
786                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT        24
787                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT       0x00000000
788                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482      0x01000000
789                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD    0x02000000
790                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN     0xff000000
791
792         uint32_t speed_capability_mask;
793         #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
794                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT        0
795                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL     0x00000001
796                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF     0x00000002
797                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF    0x00000004
798                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL    0x00000008
799                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G           0x00000010
800                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G         0x00000020
801                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G          0x00000040
802                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G          0x00000080
803                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED     0x0000f000
804
805         #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
806                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT        16
807                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL     0x00010000
808                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF     0x00020000
809                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF    0x00040000
810                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL    0x00080000
811                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G           0x00100000
812                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G         0x00200000
813                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G          0x00400000
814                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G          0x00800000
815                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED     0xf0000000
816
817         /*  A place to hold the original MAC address as a backup */
818         uint32_t backup_mac_upper;                      /* 0x2B4 */
819         uint32_t backup_mac_lower;                      /* 0x2B8 */
820
821 };
822
823
824 /****************************************************************************
825  * Shared Feature configuration                                             *
826  ****************************************************************************/
827 struct shared_feat_cfg {                 /* NVRAM Offset */
828
829         uint32_t config;                        /* 0x450 */
830         #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
831
832         /* Use NVRAM values instead of HW default values */
833         #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
834                                                             0x00000002
835                 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
836                                                                      0x00000000
837                 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
838                                                                      0x00000002
839
840         #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK         0x00000008
841                 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO          0x00000000
842                 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM         0x00000008
843
844         #define SHARED_FEAT_CFG_NCSI_ID_MASK                0x00000030
845         #define SHARED_FEAT_CFG_NCSI_ID_SHIFT                        4
846
847         /*  Override the OTP back to single function mode. When using GPIO,
848               high means only SF, 0 is according to CLP configuration */
849         #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK          0x00000700
850                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT          8
851                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED     0x00000000
852                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF      0x00000100
853                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4          0x00000200
854                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT  0x00000300
855                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE      0x00000400
856                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE       0x00000600
857                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE  0x00000700
858
859         /* The interval in seconds between sending LLDP packets. Set to zero
860            to disable the feature */
861         #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK     0x00ff0000
862         #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT             16
863
864         /* The assigned device type ID for LLDP usage */
865         #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK    0xff000000
866         #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT            24
867
868 };
869
870
871 /****************************************************************************
872  * Port Feature configuration                                               *
873  ****************************************************************************/
874 struct port_feat_cfg {              /* port 0: 0x454  port 1: 0x4c8 */
875
876         uint32_t config;
877         #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
878                 #define PORT_FEATURE_BAR1_SIZE_SHIFT                 0
879                 #define PORT_FEATURE_BAR1_SIZE_DISABLED              0x00000000
880                 #define PORT_FEATURE_BAR1_SIZE_64K                   0x00000001
881                 #define PORT_FEATURE_BAR1_SIZE_128K                  0x00000002
882                 #define PORT_FEATURE_BAR1_SIZE_256K                  0x00000003
883                 #define PORT_FEATURE_BAR1_SIZE_512K                  0x00000004
884                 #define PORT_FEATURE_BAR1_SIZE_1M                    0x00000005
885                 #define PORT_FEATURE_BAR1_SIZE_2M                    0x00000006
886                 #define PORT_FEATURE_BAR1_SIZE_4M                    0x00000007
887                 #define PORT_FEATURE_BAR1_SIZE_8M                    0x00000008
888                 #define PORT_FEATURE_BAR1_SIZE_16M                   0x00000009
889                 #define PORT_FEATURE_BAR1_SIZE_32M                   0x0000000a
890                 #define PORT_FEATURE_BAR1_SIZE_64M                   0x0000000b
891                 #define PORT_FEATURE_BAR1_SIZE_128M                  0x0000000c
892                 #define PORT_FEATURE_BAR1_SIZE_256M                  0x0000000d
893                 #define PORT_FEATURE_BAR1_SIZE_512M                  0x0000000e
894                 #define PORT_FEATURE_BAR1_SIZE_1G                    0x0000000f
895         #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
896                 #define PORT_FEATURE_BAR2_SIZE_SHIFT                 4
897                 #define PORT_FEATURE_BAR2_SIZE_DISABLED              0x00000000
898                 #define PORT_FEATURE_BAR2_SIZE_64K                   0x00000010
899                 #define PORT_FEATURE_BAR2_SIZE_128K                  0x00000020
900                 #define PORT_FEATURE_BAR2_SIZE_256K                  0x00000030
901                 #define PORT_FEATURE_BAR2_SIZE_512K                  0x00000040
902                 #define PORT_FEATURE_BAR2_SIZE_1M                    0x00000050
903                 #define PORT_FEATURE_BAR2_SIZE_2M                    0x00000060
904                 #define PORT_FEATURE_BAR2_SIZE_4M                    0x00000070
905                 #define PORT_FEATURE_BAR2_SIZE_8M                    0x00000080
906                 #define PORT_FEATURE_BAR2_SIZE_16M                   0x00000090
907                 #define PORT_FEATURE_BAR2_SIZE_32M                   0x000000a0
908                 #define PORT_FEATURE_BAR2_SIZE_64M                   0x000000b0
909                 #define PORT_FEATURE_BAR2_SIZE_128M                  0x000000c0
910                 #define PORT_FEATURE_BAR2_SIZE_256M                  0x000000d0
911                 #define PORT_FEATURE_BAR2_SIZE_512M                  0x000000e0
912                 #define PORT_FEATURE_BAR2_SIZE_1G                    0x000000f0
913
914         #define PORT_FEAT_CFG_DCBX_MASK                     0x00000100
915                 #define PORT_FEAT_CFG_DCBX_DISABLED                  0x00000000
916                 #define PORT_FEAT_CFG_DCBX_ENABLED                   0x00000100
917
918                 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK        0x00000C00
919                 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE        0x00000400
920                 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI       0x00000800
921
922         #define PORT_FEATURE_EN_SIZE_MASK                   0x0f000000
923         #define PORT_FEATURE_EN_SIZE_SHIFT                           24
924         #define PORT_FEATURE_WOL_ENABLED                             0x01000000
925         #define PORT_FEATURE_MBA_ENABLED                             0x02000000
926         #define PORT_FEATURE_MFW_ENABLED                             0x04000000
927
928         /* Advertise expansion ROM even if MBA is disabled */
929         #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK        0x08000000
930                 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED     0x00000000
931                 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED      0x08000000
932
933         /* Check the optic vendor via i2c against a list of approved modules
934            in a separate nvram image */
935         #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK         0xe0000000
936                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT         29
937                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
938                                                                      0x00000000
939                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
940                                                                      0x20000000
941                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG   0x40000000
942                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN    0x60000000
943
944         uint32_t wol_config;
945         /* Default is used when driver sets to "auto" mode */
946         #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
947                 #define PORT_FEATURE_WOL_DEFAULT_SHIFT               0
948                 #define PORT_FEATURE_WOL_DEFAULT_DISABLE             0x00000000
949                 #define PORT_FEATURE_WOL_DEFAULT_MAGIC               0x00000001
950                 #define PORT_FEATURE_WOL_DEFAULT_ACPI                0x00000002
951                 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI      0x00000003
952         #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
953         #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
954         #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
955
956         uint32_t mba_config;
957         #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000007
958                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT       0
959                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0x00000000
960                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL         0x00000001
961                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP       0x00000002
962                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB      0x00000003
963                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT   0x00000004
964                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE        0x00000007
965
966         #define PORT_FEATURE_MBA_BOOT_RETRY_MASK            0x00000038
967         #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT                    3
968
969         #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
970         #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
971         #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
972         #define PORT_FEATURE_MBA_HOTKEY_MASK                0x00000800
973                 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S               0x00000000
974                 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B               0x00000800
975         #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
976                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT          12
977                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED       0x00000000
978                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K             0x00001000
979                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K             0x00002000
980                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K             0x00003000
981                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K            0x00004000
982                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K            0x00005000
983                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K            0x00006000
984                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K           0x00007000
985                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K           0x00008000
986                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K           0x00009000
987                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M             0x0000a000
988                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M             0x0000b000
989                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M             0x0000c000
990                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M             0x0000d000
991                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M            0x0000e000
992                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M            0x0000f000
993         #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
994         #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT                   20
995         #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
996                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT        24
997                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO         0x00000000
998                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS          0x01000000
999                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H       0x02000000
1000                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H       0x03000000
1001         #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
1002                 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT            26
1003                 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO             0x00000000
1004                 #define PORT_FEATURE_MBA_LINK_SPEED_10HD             0x04000000
1005                 #define PORT_FEATURE_MBA_LINK_SPEED_10FD             0x08000000
1006                 #define PORT_FEATURE_MBA_LINK_SPEED_100HD            0x0c000000
1007                 #define PORT_FEATURE_MBA_LINK_SPEED_100FD            0x10000000
1008                 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS            0x14000000
1009                 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS          0x18000000
1010                 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4       0x1c000000
1011                 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS           0x20000000
1012         uint32_t bmc_config;
1013         #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK         0x00000001
1014                 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT       0x00000000
1015                 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN            0x00000001
1016
1017         uint32_t mba_vlan_cfg;
1018         #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
1019         #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT                      0
1020         #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
1021
1022         uint32_t resource_cfg;
1023         #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
1024         #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
1025         #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
1026         #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
1027         #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
1028
1029         uint32_t smbus_config;
1030         #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
1031         #define PORT_FEATURE_SMBUS_ADDR_SHIFT                        1
1032
1033         uint32_t vf_config;
1034         #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK             0x0000000f
1035                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT             0
1036                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED          0x00000000
1037                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K                0x00000001
1038                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K                0x00000002
1039                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K               0x00000003
1040                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K               0x00000004
1041                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K               0x00000005
1042                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K              0x00000006
1043                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K              0x00000007
1044                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K              0x00000008
1045                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M                0x00000009
1046                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M                0x0000000a
1047                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M                0x0000000b
1048                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M                0x0000000c
1049                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M               0x0000000d
1050                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M               0x0000000e
1051                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M               0x0000000f
1052
1053         uint32_t link_config;    /* Used as HW defaults for the driver */
1054         #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
1055                 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT          24
1056                 /* (forced) low speed switch (< 10G) */
1057                 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH            0x00000000
1058                 /* (forced) high speed switch (>= 10G) */
1059                 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH           0x01000000
1060                 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT          0x02000000
1061                 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT      0x03000000
1062
1063         #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
1064                 #define PORT_FEATURE_LINK_SPEED_SHIFT                16
1065                 #define PORT_FEATURE_LINK_SPEED_AUTO                 0x00000000
1066                 #define PORT_FEATURE_LINK_SPEED_10M_FULL             0x00010000
1067                 #define PORT_FEATURE_LINK_SPEED_10M_HALF             0x00020000
1068                 #define PORT_FEATURE_LINK_SPEED_100M_HALF            0x00030000
1069                 #define PORT_FEATURE_LINK_SPEED_100M_FULL            0x00040000
1070                 #define PORT_FEATURE_LINK_SPEED_1G                   0x00050000
1071                 #define PORT_FEATURE_LINK_SPEED_2_5G                 0x00060000
1072                 #define PORT_FEATURE_LINK_SPEED_10G_CX4              0x00070000
1073                 #define PORT_FEATURE_LINK_SPEED_20G                  0x00080000
1074
1075         #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
1076                 #define PORT_FEATURE_FLOW_CONTROL_SHIFT              8
1077                 #define PORT_FEATURE_FLOW_CONTROL_AUTO               0x00000000
1078                 #define PORT_FEATURE_FLOW_CONTROL_TX                 0x00000100
1079                 #define PORT_FEATURE_FLOW_CONTROL_RX                 0x00000200
1080                 #define PORT_FEATURE_FLOW_CONTROL_BOTH               0x00000300
1081                 #define PORT_FEATURE_FLOW_CONTROL_NONE               0x00000400
1082
1083         /* The default for MCP link configuration,
1084            uses the same defines as link_config */
1085         uint32_t mfw_wol_link_cfg;
1086
1087         /* The default for the driver of the second external phy,
1088            uses the same defines as link_config */
1089         uint32_t link_config2;                              /* 0x47C */
1090
1091         /* The default for MCP of the second external phy,
1092            uses the same defines as link_config */
1093         uint32_t mfw_wol_link_cfg2;                                 /* 0x480 */
1094
1095
1096         /*  EEE power saving mode */
1097         uint32_t eee_power_mode;                                 /* 0x484 */
1098         #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK                     0x000000FF
1099         #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT                    0
1100         #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED                 0x00000000
1101         #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED                 0x00000001
1102         #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE               0x00000002
1103         #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY              0x00000003
1104
1105
1106         uint32_t Reserved2[16];                                  /* 0x488 */
1107 };
1108
1109
1110 /****************************************************************************
1111  * Device Information                                                       *
1112  ****************************************************************************/
1113 struct shm_dev_info {                           /* size */
1114
1115         uint32_t    bc_rev; /* 8 bits each: major, minor, build */             /* 4 */
1116
1117         struct shared_hw_cfg     shared_hw_config;            /* 40 */
1118
1119         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
1120
1121         struct shared_feat_cfg   shared_feature_config;            /* 4 */
1122
1123         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
1124
1125 };
1126
1127
1128 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1129         #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1130 #endif
1131
1132 #define FUNC_0              0
1133 #define FUNC_1              1
1134 #define FUNC_2              2
1135 #define FUNC_3              3
1136 #define FUNC_4              4
1137 #define FUNC_5              5
1138 #define FUNC_6              6
1139 #define FUNC_7              7
1140 #define E1_FUNC_MAX         2
1141 #define E1H_FUNC_MAX            8
1142 #define E2_FUNC_MAX         4   /* per path */
1143
1144 #define VN_0                0
1145 #define VN_1                1
1146 #define VN_2                2
1147 #define VN_3                3
1148 #define E1VN_MAX            1
1149 #define E1HVN_MAX           4
1150
1151 #define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */
1152 /* This value (in milliseconds) determines the frequency of the driver
1153  * issuing the PULSE message code.  The firmware monitors this periodic
1154  * pulse to determine when to switch to an OS-absent mode. */
1155 #define DRV_PULSE_PERIOD_MS     250
1156
1157 /* This value (in milliseconds) determines how long the driver should
1158  * wait for an acknowledgement from the firmware before timing out.  Once
1159  * the firmware has timed out, the driver will assume there is no firmware
1160  * running and there won't be any firmware-driver synchronization during a
1161  * driver reset. */
1162 #define FW_ACK_TIME_OUT_MS      5000
1163
1164 #define FW_ACK_POLL_TIME_MS     1
1165
1166 #define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1167
1168 #define MFW_TRACE_SIGNATURE     0x54524342
1169
1170 /****************************************************************************
1171  * Driver <-> FW Mailbox                                                    *
1172  ****************************************************************************/
1173 struct drv_port_mb {
1174
1175         uint32_t link_status;
1176         /* Driver should update this field on any link change event */
1177
1178         #define LINK_STATUS_NONE                                (0<<0)
1179         #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
1180         #define LINK_STATUS_LINK_UP                             0x00000001
1181         #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
1182         #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
1183         #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
1184         #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
1185         #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
1186         #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
1187         #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
1188         #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
1189         #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
1190         #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
1191         #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
1192         #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
1193         #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
1194         #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
1195         #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
1196         #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD             (11<<1)
1197         #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD             (11<<1)
1198
1199         #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
1200         #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
1201
1202         #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
1203         #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
1204         #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
1205
1206         #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
1207         #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
1208         #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
1209         #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
1210         #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
1211         #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
1212         #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
1213
1214         #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
1215         #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
1216
1217         #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
1218         #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
1219
1220         #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
1221         #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
1222         #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
1223         #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
1224         #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
1225
1226         #define LINK_STATUS_SERDES_LINK                         0x00100000
1227
1228         #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
1229         #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
1230         #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
1231         #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE         0x10000000
1232
1233         #define LINK_STATUS_PFC_ENABLED                         0x20000000
1234
1235         #define LINK_STATUS_PHYSICAL_LINK_FLAG                  0x40000000
1236         #define LINK_STATUS_SFP_TX_FAULT                        0x80000000
1237
1238         uint32_t port_stx;
1239
1240         uint32_t stat_nig_timer;
1241
1242         /* MCP firmware does not use this field */
1243         uint32_t ext_phy_fw_version;
1244
1245 };
1246
1247
1248 struct drv_func_mb {
1249
1250         uint32_t drv_mb_header;
1251         #define DRV_MSG_CODE_MASK                       0xffff0000
1252         #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
1253         #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
1254         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
1255         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
1256         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
1257         #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
1258         #define DRV_MSG_CODE_DCC_OK                     0x30000000
1259         #define DRV_MSG_CODE_DCC_FAILURE                0x31000000
1260         #define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
1261         #define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
1262         #define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
1263         #define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
1264         #define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
1265         #define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
1266         #define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
1267         #define DRV_MSG_CODE_OEM_OK                     0x00010000
1268         #define DRV_MSG_CODE_OEM_FAILURE                0x00020000
1269         #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK         0x00030000
1270         #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE    0x00040000
1271         /*
1272          * The optic module verification command requires bootcode
1273          * v5.0.6 or later, te specific optic module verification command
1274          * requires bootcode v5.2.12 or later
1275          */
1276         #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
1277         #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
1278         #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa1000000
1279         #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x00050234
1280         #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED        0xa2000000
1281         #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED        0x00070002
1282         #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x00070014
1283         #define REQ_BC_VER_4_MT_SUPPORTED               0x00070201
1284         #define REQ_BC_VER_4_PFC_STATS_SUPPORTED        0x00070201
1285         #define REQ_BC_VER_4_FCOE_FEATURES              0x00070209
1286
1287         #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb0000000
1288         #define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb2000000
1289         #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF     0x00070401
1290
1291         #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
1292
1293         #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC         0xd0000000
1294         #define DRV_MSG_CODE_AFEX_LISTGET_ACK           0xd1000000
1295         #define DRV_MSG_CODE_AFEX_LISTSET_ACK           0xd2000000
1296         #define DRV_MSG_CODE_AFEX_STATSGET_ACK          0xd3000000
1297         #define DRV_MSG_CODE_AFEX_VIFSET_ACK            0xd4000000
1298
1299         #define DRV_MSG_CODE_DRV_INFO_ACK               0xd8000000
1300         #define DRV_MSG_CODE_DRV_INFO_NACK              0xd9000000
1301
1302         #define DRV_MSG_CODE_EEE_RESULTS_ACK            0xda000000
1303
1304         #define DRV_MSG_CODE_RMMOD                      0xdb000000
1305         #define REQ_BC_VER_4_RMMOD_CMD                  0x0007080f
1306
1307         #define DRV_MSG_CODE_SET_MF_BW                  0xe0000000
1308         #define REQ_BC_VER_4_SET_MF_BW                  0x00060202
1309         #define DRV_MSG_CODE_SET_MF_BW_ACK              0xe1000000
1310
1311         #define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x01000000
1312
1313         #define DRV_MSG_CODE_INITIATE_FLR               0x02000000
1314         #define REQ_BC_VER_4_INITIATE_FLR               0x00070213
1315
1316         #define BIOS_MSG_CODE_LIC_CHALLENGE             0xff010000
1317         #define BIOS_MSG_CODE_LIC_RESPONSE              0xff020000
1318         #define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff030000
1319         #define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff040000
1320
1321         #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
1322
1323         uint32_t drv_mb_param;
1324         #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
1325         #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000
1326
1327         #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET     0x00000002
1328
1329         #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA          0x0000100a
1330         #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA         0x00002000
1331
1332         uint32_t fw_mb_header;
1333         #define FW_MSG_CODE_MASK                        0xffff0000
1334         #define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
1335         #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
1336         #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
1337         /* Load common chip is supported from bc 6.0.0  */
1338         #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
1339         #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
1340
1341         #define FW_MSG_CODE_DRV_LOAD_REFUSED            0x10200000
1342         #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
1343         #define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x20100000
1344         #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20110000
1345         #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20120000
1346         #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
1347         #define FW_MSG_CODE_DCC_DONE                    0x30100000
1348         #define FW_MSG_CODE_LLDP_DONE                   0x40100000
1349         #define FW_MSG_CODE_DIAG_ENTER_DONE             0x50100000
1350         #define FW_MSG_CODE_DIAG_REFUSE                 0x50200000
1351         #define FW_MSG_CODE_DIAG_EXIT_DONE              0x60100000
1352         #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70100000
1353         #define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x70200000
1354         #define FW_MSG_CODE_GET_KEY_DONE                0x80100000
1355         #define FW_MSG_CODE_NO_KEY                      0x80f00000
1356         #define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f80000
1357         #define FW_MSG_CODE_L2B_PRAM_LOADED             0x90100000
1358         #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x90210000
1359         #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x90220000
1360         #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x90230000
1361         #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x90240000
1362         #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa0100000
1363         #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa0200000
1364         #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa0300000
1365         #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
1366         #define FW_MSG_CODE_HW_SET_INVALID_IMAGE        0xb0100000
1367
1368         #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE     0xd0100000
1369         #define FW_MSG_CODE_AFEX_LISTGET_ACK            0xd1100000
1370         #define FW_MSG_CODE_AFEX_LISTSET_ACK            0xd2100000
1371         #define FW_MSG_CODE_AFEX_STATSGET_ACK           0xd3100000
1372         #define FW_MSG_CODE_AFEX_VIFSET_ACK             0xd4100000
1373
1374         #define FW_MSG_CODE_DRV_INFO_ACK                0xd8100000
1375         #define FW_MSG_CODE_DRV_INFO_NACK               0xd9100000
1376
1377         #define FW_MSG_CODE_EEE_RESULS_ACK              0xda100000
1378
1379         #define FW_MSG_CODE_RMMOD_ACK                   0xdb100000
1380
1381         #define FW_MSG_CODE_SET_MF_BW_SENT              0xe0000000
1382         #define FW_MSG_CODE_SET_MF_BW_DONE              0xe1000000
1383
1384         #define FW_MSG_CODE_LINK_CHANGED_ACK            0x01100000
1385
1386         #define FW_MSG_CODE_LIC_CHALLENGE               0xff010000
1387         #define FW_MSG_CODE_LIC_RESPONSE                0xff020000
1388         #define FW_MSG_CODE_VIRT_MAC_PRIM               0xff030000
1389         #define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff040000
1390
1391         #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
1392
1393         uint32_t fw_mb_param;
1394
1395         uint32_t drv_pulse_mb;
1396         #define DRV_PULSE_SEQ_MASK                      0x00007fff
1397         #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
1398         /*
1399          * The system time is in the format of
1400          * (year-2001)*12*32 + month*32 + day.
1401          */
1402         #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
1403         /*
1404          * Indicate to the firmware not to go into the
1405          * OS-absent when it is not getting driver pulse.
1406          * This is used for debugging as well for PXE(MBA).
1407          */
1408
1409         uint32_t mcp_pulse_mb;
1410         #define MCP_PULSE_SEQ_MASK                      0x00007fff
1411         #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
1412         /* Indicates to the driver not to assert due to lack
1413          * of MCP response */
1414         #define MCP_EVENT_MASK                          0xffff0000
1415         #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
1416
1417         uint32_t iscsi_boot_signature;
1418         uint32_t iscsi_boot_block_offset;
1419
1420         uint32_t drv_status;
1421         #define DRV_STATUS_PMF                          0x00000001
1422         #define DRV_STATUS_VF_DISABLED                  0x00000002
1423         #define DRV_STATUS_SET_MF_BW                    0x00000004
1424         #define DRV_STATUS_LINK_EVENT                   0x00000008
1425
1426         #define DRV_STATUS_OEM_EVENT_MASK               0x00000070
1427         #define DRV_STATUS_OEM_DISABLE_ENABLE_PF        0x00000010
1428         #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION     0x00000020
1429
1430         #define DRV_STATUS_OEM_UPDATE_SVID              0x00000080
1431
1432         #define DRV_STATUS_DCC_EVENT_MASK               0x0000ff00
1433         #define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x00000100
1434         #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x00000200
1435         #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x00000400
1436         #define DRV_STATUS_DCC_RESERVED1                0x00000800
1437         #define DRV_STATUS_DCC_SET_PROTOCOL             0x00001000
1438         #define DRV_STATUS_DCC_SET_PRIORITY             0x00002000
1439
1440         #define DRV_STATUS_DCBX_EVENT_MASK              0x000f0000
1441         #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x00010000
1442         #define DRV_STATUS_AFEX_EVENT_MASK              0x03f00000
1443         #define DRV_STATUS_AFEX_LISTGET_REQ             0x00100000
1444         #define DRV_STATUS_AFEX_LISTSET_REQ             0x00200000
1445         #define DRV_STATUS_AFEX_STATSGET_REQ            0x00400000
1446         #define DRV_STATUS_AFEX_VIFSET_REQ              0x00800000
1447
1448         #define DRV_STATUS_DRV_INFO_REQ                 0x04000000
1449
1450         #define DRV_STATUS_EEE_NEGOTIATION_RESULTS      0x08000000
1451
1452         uint32_t virt_mac_upper;
1453         #define VIRT_MAC_SIGN_MASK                      0xffff0000
1454         #define VIRT_MAC_SIGNATURE                      0x564d0000
1455         uint32_t virt_mac_lower;
1456
1457 };
1458
1459
1460 /****************************************************************************
1461  * Management firmware state                                                *
1462  ****************************************************************************/
1463 /* Allocate 440 bytes for management firmware */
1464 #define MGMTFW_STATE_WORD_SIZE                          110
1465
1466 struct mgmtfw_state {
1467         uint32_t opaque[MGMTFW_STATE_WORD_SIZE];
1468 };
1469
1470
1471 /****************************************************************************
1472  * Multi-Function configuration                                             *
1473  ****************************************************************************/
1474 struct shared_mf_cfg {
1475
1476         uint32_t clp_mb;
1477         #define SHARED_MF_CLP_SET_DEFAULT               0x00000000
1478         /* set by CLP */
1479         #define SHARED_MF_CLP_EXIT                      0x00000001
1480         /* set by MCP */
1481         #define SHARED_MF_CLP_EXIT_DONE                 0x00010000
1482
1483 };
1484
1485 struct port_mf_cfg {
1486
1487         uint32_t dynamic_cfg;    /* device control channel */
1488         #define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1489         #define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
1490         #define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK
1491
1492         uint32_t reserved[1];
1493
1494 };
1495
1496 struct func_mf_cfg {
1497
1498         uint32_t config;
1499         /* E/R/I/D */
1500         /* function 0 of each port cannot be hidden */
1501         #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
1502
1503         #define FUNC_MF_CFG_PROTOCOL_MASK               0x00000006
1504         #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000000
1505         #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000002
1506         #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1507         #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000006
1508         #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1509                                 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1510
1511         #define FUNC_MF_CFG_FUNC_DISABLED               0x00000008
1512         #define FUNC_MF_CFG_FUNC_DELETED                0x00000010
1513
1514         /* PRI */
1515         /* 0 - low priority, 3 - high priority */
1516         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x00000300
1517         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     8
1518         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x00000000
1519
1520         /* MINBW, MAXBW */
1521         /* value range - 0..100, increments in 100Mbps */
1522         #define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff0000
1523         #define FUNC_MF_CFG_MIN_BW_SHIFT                16
1524         #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
1525         #define FUNC_MF_CFG_MAX_BW_MASK                 0xff000000
1526         #define FUNC_MF_CFG_MAX_BW_SHIFT                24
1527         #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000
1528
1529         uint32_t mac_upper;         /* MAC */
1530         #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
1531         #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
1532         #define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
1533         uint32_t mac_lower;
1534         #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
1535
1536         uint32_t e1hov_tag;     /* VNI */
1537         #define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1538         #define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
1539         #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK
1540
1541         /* afex default VLAN ID - 12 bits */
1542         #define FUNC_MF_CFG_AFEX_VLAN_MASK              0x0fff0000
1543         #define FUNC_MF_CFG_AFEX_VLAN_SHIFT             16
1544
1545         uint32_t afex_config;
1546         #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK                     0x000000ff
1547         #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT                    0
1548         #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK                    0x0000ff00
1549         #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT                   8
1550         #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL                     0x00000100
1551         #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK                      0x000f0000
1552         #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT                     16
1553
1554         uint32_t reserved;
1555 };
1556
1557 enum mf_cfg_afex_vlan_mode {
1558         FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1559         FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1560         FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1561 };
1562
1563 /* This structure is not applicable and should not be accessed on 57711 */
1564 struct func_ext_cfg {
1565         uint32_t func_cfg;
1566         #define MACP_FUNC_CFG_FLAGS_MASK                0x0000007F
1567         #define MACP_FUNC_CFG_FLAGS_SHIFT               0
1568         #define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
1569         #define MACP_FUNC_CFG_FLAGS_ETHERNET            0x00000002
1570         #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x00000004
1571         #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
1572         #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING        0x00000080
1573
1574         uint32_t iscsi_mac_addr_upper;
1575         uint32_t iscsi_mac_addr_lower;
1576
1577         uint32_t fcoe_mac_addr_upper;
1578         uint32_t fcoe_mac_addr_lower;
1579
1580         uint32_t fcoe_wwn_port_name_upper;
1581         uint32_t fcoe_wwn_port_name_lower;
1582
1583         uint32_t fcoe_wwn_node_name_upper;
1584         uint32_t fcoe_wwn_node_name_lower;
1585
1586         uint32_t preserve_data;
1587         #define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
1588         #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
1589         #define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
1590         #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)
1591         #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)
1592         #define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)
1593 };
1594
1595 struct mf_cfg {
1596
1597         struct shared_mf_cfg    shared_mf_config;       /* 0x4 */
1598                                                         /* 0x8*2*2=0x20 */
1599         struct port_mf_cfg  port_mf_config[NVM_PATH_MAX][PORT_MAX];
1600         /* for all chips, there are 8 mf functions */
1601         struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1602         /*
1603          * Extended configuration per function  - this array does not exist and
1604          * should not be accessed on 57711
1605          */
1606         struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1607 }; /* 0x224 */
1608
1609 /****************************************************************************
1610  * Shared Memory Region                                                     *
1611  ****************************************************************************/
1612 struct shmem_region {                  /*   SharedMem Offset (size) */
1613
1614         uint32_t         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
1615         #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
1616         #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
1617         /* validity bits */
1618         #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
1619         #define SHR_MEM_VALIDITY_MB                         0x00200000
1620         #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
1621         #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
1622         /* One licensing bit should be set */
1623         #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
1624         #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
1625         #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
1626         #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
1627         /* Active MFW */
1628         #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
1629         #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
1630         #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
1631         #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
1632         #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
1633         #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
1634
1635         struct shm_dev_info dev_info;        /* 0x8     (0x438) */
1636
1637         struct license_key       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1638
1639         /* FW information (for internal FW use) */
1640         uint32_t         fw_info_fio_offset;            /* 0x4a8       (0x4) */
1641         struct mgmtfw_state mgmtfw_state;       /* 0x4ac     (0x1b8) */
1642
1643         struct drv_port_mb  port_mb[PORT_MAX];  /* 0x664 (16*2=0x20) */
1644
1645 #ifdef BMAPI
1646         /* This is a variable length array */
1647         /* the number of function depends on the chip type */
1648         struct drv_func_mb func_mb[1];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1649 #else
1650         /* the number of function depends on the chip type */
1651         struct drv_func_mb  func_mb[];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1652 #endif /* BMAPI */
1653
1654 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1655
1656 /****************************************************************************
1657  * Shared Memory 2 Region                                                   *
1658  ****************************************************************************/
1659 /* The fw_flr_ack is actually built in the following way:                   */
1660 /* 8 bit:  PF ack                                                           */
1661 /* 64 bit: VF ack                                                           */
1662 /* 8 bit:  ios_dis_ack                                                      */
1663 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1664 /* u32. The fw must have the VF right after the PF since this is how it     */
1665 /* access arrays(it expects always the VF to reside after the PF, and that  */
1666 /* makes the calculation much easier for it. )                              */
1667 /* In order to answer both limitations, and keep the struct small, the code */
1668 /* will abuse the structure defined here to achieve the actual partition    */
1669 /* above                                                                    */
1670 /****************************************************************************/
1671 struct fw_flr_ack {
1672         uint32_t         pf_ack;
1673         uint32_t         vf_ack[1];
1674         uint32_t         iov_dis_ack;
1675 };
1676
1677 struct fw_flr_mb {
1678         uint32_t         aggint;
1679         uint32_t         opgen_addr;
1680         struct fw_flr_ack ack;
1681 };
1682
1683 struct eee_remote_vals {
1684         uint32_t         tx_tw;
1685         uint32_t         rx_tw;
1686 };
1687
1688 /**** SUPPORT FOR SHMEM ARRRAYS ***
1689  * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1690  * define arrays with storage types smaller then unsigned dwords.
1691  * The macros below add generic support for SHMEM arrays with numeric elements
1692  * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1693  * array with individual bit-filed elements accessed using shifts and masks.
1694  *
1695  */
1696
1697 /* eb is the bitwidth of a single element */
1698 #define SHMEM_ARRAY_MASK(eb)            ((1<<(eb))-1)
1699 #define SHMEM_ARRAY_ENTRY(i, eb)        ((i)/(32/(eb)))
1700
1701 /* the bit-position macro allows the used to flip the order of the arrays
1702  * elements on a per byte or word boundary.
1703  *
1704  * example: an array with 8 entries each 4 bit wide. This array will fit into
1705  * a single dword. The diagrmas below show the array order of the nibbles.
1706  *
1707  * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1708  *
1709  *                |                |                |               |
1710  *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |
1711  *                |                |                |               |
1712  *
1713  * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1714  *
1715  *                |                |                |               |
1716  *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |
1717  *                |                |                |               |
1718  *
1719  * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1720  *
1721  *                |                |                |               |
1722  *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |
1723  *                |                |                |               |
1724  */
1725 #define SHMEM_ARRAY_BITPOS(i, eb, fb)   \
1726         ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1727         (((i)%((fb)/(eb))) * (eb)))
1728
1729 #define SHMEM_ARRAY_GET(a, i, eb, fb)                                   \
1730         ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
1731         SHMEM_ARRAY_MASK(eb))
1732
1733 #define SHMEM_ARRAY_SET(a, i, eb, fb, val)                              \
1734 do {                                                                       \
1735         a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<           \
1736         SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
1737         a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
1738         SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
1739 } while (0)
1740
1741
1742 /****START OF DCBX STRUCTURES DECLARATIONS****/
1743 #define DCBX_MAX_NUM_PRI_PG_ENTRIES     8
1744 #define DCBX_PRI_PG_BITWIDTH            4
1745 #define DCBX_PRI_PG_FBITS               8
1746 #define DCBX_PRI_PG_GET(a, i)           \
1747         SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1748 #define DCBX_PRI_PG_SET(a, i, val)      \
1749         SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1750 #define DCBX_MAX_NUM_PG_BW_ENTRIES      8
1751 #define DCBX_BW_PG_BITWIDTH             8
1752 #define DCBX_PG_BW_GET(a, i)            \
1753         SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1754 #define DCBX_PG_BW_SET(a, i, val)       \
1755         SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1756 #define DCBX_STRICT_PRI_PG              15
1757 #define DCBX_MAX_APP_PROTOCOL           16
1758 #define FCOE_APP_IDX                    0
1759 #define ISCSI_APP_IDX                   1
1760 #define PREDEFINED_APP_IDX_MAX          2
1761
1762
1763 /* Big/Little endian have the same representation. */
1764 struct dcbx_ets_feature {
1765         /*
1766          * For Admin MIB - is this feature supported by the
1767          * driver | For Local MIB - should this feature be enabled.
1768          */
1769         uint32_t enabled;
1770         uint32_t  pg_bw_tbl[2];
1771         uint32_t  pri_pg_tbl[1];
1772 };
1773
1774 /* Driver structure in LE */
1775 struct dcbx_pfc_feature {
1776 #ifdef __BIG_ENDIAN
1777         uint8_t pri_en_bitmap;
1778         #define DCBX_PFC_PRI_0 0x01
1779         #define DCBX_PFC_PRI_1 0x02
1780         #define DCBX_PFC_PRI_2 0x04
1781         #define DCBX_PFC_PRI_3 0x08
1782         #define DCBX_PFC_PRI_4 0x10
1783         #define DCBX_PFC_PRI_5 0x20
1784         #define DCBX_PFC_PRI_6 0x40
1785         #define DCBX_PFC_PRI_7 0x80
1786         uint8_t pfc_caps;
1787         uint8_t reserved;
1788         uint8_t enabled;
1789 #elif defined(__LITTLE_ENDIAN)
1790         uint8_t enabled;
1791         uint8_t reserved;
1792         uint8_t pfc_caps;
1793         uint8_t pri_en_bitmap;
1794         #define DCBX_PFC_PRI_0 0x01
1795         #define DCBX_PFC_PRI_1 0x02
1796         #define DCBX_PFC_PRI_2 0x04
1797         #define DCBX_PFC_PRI_3 0x08
1798         #define DCBX_PFC_PRI_4 0x10
1799         #define DCBX_PFC_PRI_5 0x20
1800         #define DCBX_PFC_PRI_6 0x40
1801         #define DCBX_PFC_PRI_7 0x80
1802 #endif
1803 };
1804
1805 struct dcbx_app_priority_entry {
1806 #ifdef __BIG_ENDIAN
1807         uint16_t  app_id;
1808         uint8_t  pri_bitmap;
1809         uint8_t  appBitfield;
1810         #define DCBX_APP_ENTRY_VALID         0x01
1811         #define DCBX_APP_ENTRY_SF_MASK       0x30
1812         #define DCBX_APP_ENTRY_SF_SHIFT      4
1813         #define DCBX_APP_SF_ETH_TYPE         0x10
1814         #define DCBX_APP_SF_PORT             0x20
1815 #elif defined(__LITTLE_ENDIAN)
1816         uint8_t appBitfield;
1817         #define DCBX_APP_ENTRY_VALID         0x01
1818         #define DCBX_APP_ENTRY_SF_MASK       0x30
1819         #define DCBX_APP_ENTRY_SF_SHIFT      4
1820         #define DCBX_APP_SF_ETH_TYPE         0x10
1821         #define DCBX_APP_SF_PORT             0x20
1822         uint8_t  pri_bitmap;
1823         uint16_t  app_id;
1824 #endif
1825 };
1826
1827
1828 /* FW structure in BE */
1829 struct dcbx_app_priority_feature {
1830 #ifdef __BIG_ENDIAN
1831         uint8_t reserved;
1832         uint8_t default_pri;
1833         uint8_t tc_supported;
1834         uint8_t enabled;
1835 #elif defined(__LITTLE_ENDIAN)
1836         uint8_t enabled;
1837         uint8_t tc_supported;
1838         uint8_t default_pri;
1839         uint8_t reserved;
1840 #endif
1841         struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1842 };
1843
1844 /* FW structure in BE */
1845 struct dcbx_features {
1846         /* PG feature */
1847         struct dcbx_ets_feature ets;
1848         /* PFC feature */
1849         struct dcbx_pfc_feature pfc;
1850         /* APP feature */
1851         struct dcbx_app_priority_feature app;
1852 };
1853
1854 /* LLDP protocol parameters */
1855 /* FW structure in BE */
1856 struct lldp_params {
1857 #ifdef __BIG_ENDIAN
1858         uint8_t  msg_fast_tx_interval;
1859         uint8_t  msg_tx_hold;
1860         uint8_t  msg_tx_interval;
1861         uint8_t  admin_status;
1862         #define LLDP_TX_ONLY  0x01
1863         #define LLDP_RX_ONLY  0x02
1864         #define LLDP_TX_RX    0x03
1865         #define LLDP_DISABLED 0x04
1866         uint8_t  reserved1;
1867         uint8_t  tx_fast;
1868         uint8_t  tx_crd_max;
1869         uint8_t  tx_crd;
1870 #elif defined(__LITTLE_ENDIAN)
1871         uint8_t  admin_status;
1872         #define LLDP_TX_ONLY  0x01
1873         #define LLDP_RX_ONLY  0x02
1874         #define LLDP_TX_RX    0x03
1875         #define LLDP_DISABLED 0x04
1876         uint8_t  msg_tx_interval;
1877         uint8_t  msg_tx_hold;
1878         uint8_t  msg_fast_tx_interval;
1879         uint8_t  tx_crd;
1880         uint8_t  tx_crd_max;
1881         uint8_t  tx_fast;
1882         uint8_t  reserved1;
1883 #endif
1884         #define REM_CHASSIS_ID_STAT_LEN 4
1885         #define REM_PORT_ID_STAT_LEN 4
1886         /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1887         uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1888         /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1889         uint32_t peer_port_id[REM_PORT_ID_STAT_LEN];
1890 };
1891
1892 struct lldp_dcbx_stat {
1893         #define LOCAL_CHASSIS_ID_STAT_LEN 2
1894         #define LOCAL_PORT_ID_STAT_LEN 2
1895         /* Holds local Chassis ID 8B payload of constant subtype 4. */
1896         uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1897         /* Holds local Port ID 8B payload of constant subtype 3. */
1898         uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN];
1899         /* Number of DCBX frames transmitted. */
1900         uint32_t num_tx_dcbx_pkts;
1901         /* Number of DCBX frames received. */
1902         uint32_t num_rx_dcbx_pkts;
1903 };
1904
1905 /* ADMIN MIB - DCBX local machine default configuration. */
1906 struct lldp_admin_mib {
1907         uint32_t     ver_cfg_flags;
1908         #define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
1909         #define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
1910         #define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
1911         #define DCBX_ETS_RECO_TX_ENABLED         0x00000008
1912         #define DCBX_ETS_RECO_VALID              0x00000010
1913         #define DCBX_ETS_WILLING                 0x00000020
1914         #define DCBX_PFC_WILLING                 0x00000040
1915         #define DCBX_APP_WILLING                 0x00000080
1916         #define DCBX_VERSION_CEE                 0x00000100
1917         #define DCBX_VERSION_IEEE                0x00000200
1918         #define DCBX_DCBX_ENABLED                0x00000400
1919         #define DCBX_CEE_VERSION_MASK            0x0000f000
1920         #define DCBX_CEE_VERSION_SHIFT           12
1921         #define DCBX_CEE_MAX_VERSION_MASK        0x000f0000
1922         #define DCBX_CEE_MAX_VERSION_SHIFT       16
1923         struct dcbx_features     features;
1924 };
1925
1926 /* REMOTE MIB - remote machine DCBX configuration. */
1927 struct lldp_remote_mib {
1928         uint32_t prefix_seq_num;
1929         uint32_t flags;
1930         #define DCBX_ETS_TLV_RX                  0x00000001
1931         #define DCBX_PFC_TLV_RX                  0x00000002
1932         #define DCBX_APP_TLV_RX                  0x00000004
1933         #define DCBX_ETS_RX_ERROR                0x00000010
1934         #define DCBX_PFC_RX_ERROR                0x00000020
1935         #define DCBX_APP_RX_ERROR                0x00000040
1936         #define DCBX_ETS_REM_WILLING             0x00000100
1937         #define DCBX_PFC_REM_WILLING             0x00000200
1938         #define DCBX_APP_REM_WILLING             0x00000400
1939         #define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
1940         #define DCBX_REMOTE_MIB_VALID            0x00002000
1941         struct dcbx_features features;
1942         uint32_t suffix_seq_num;
1943 };
1944
1945 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1946 struct lldp_local_mib {
1947         uint32_t prefix_seq_num;
1948         /* Indicates if there is mismatch with negotiation results. */
1949         uint32_t error;
1950         #define DCBX_LOCAL_ETS_ERROR             0x00000001
1951         #define DCBX_LOCAL_PFC_ERROR             0x00000002
1952         #define DCBX_LOCAL_APP_ERROR             0x00000004
1953         #define DCBX_LOCAL_PFC_MISMATCH          0x00000010
1954         #define DCBX_LOCAL_APP_MISMATCH          0x00000020
1955         #define DCBX_REMOTE_MIB_ERROR            0x00000040
1956         #define DCBX_REMOTE_ETS_TLV_NOT_FOUND    0x00000080
1957         #define DCBX_REMOTE_PFC_TLV_NOT_FOUND    0x00000100
1958         #define DCBX_REMOTE_APP_TLV_NOT_FOUND    0x00000200
1959         struct dcbx_features   features;
1960         uint32_t suffix_seq_num;
1961 };
1962 /***END OF DCBX STRUCTURES DECLARATIONS***/
1963
1964 /***********************************************************/
1965 /*                         Elink section                   */
1966 /***********************************************************/
1967 #define SHMEM_LINK_CONFIG_SIZE 2
1968 struct shmem_lfa {
1969         uint32_t req_duplex;
1970         #define REQ_DUPLEX_PHY0_MASK        0x0000ffff
1971         #define REQ_DUPLEX_PHY0_SHIFT       0
1972         #define REQ_DUPLEX_PHY1_MASK        0xffff0000
1973         #define REQ_DUPLEX_PHY1_SHIFT       16
1974         uint32_t req_flow_ctrl;
1975         #define REQ_FLOW_CTRL_PHY0_MASK     0x0000ffff
1976         #define REQ_FLOW_CTRL_PHY0_SHIFT    0
1977         #define REQ_FLOW_CTRL_PHY1_MASK     0xffff0000
1978         #define REQ_FLOW_CTRL_PHY1_SHIFT    16
1979         uint32_t req_line_speed; /* Also determine AutoNeg */
1980         #define REQ_LINE_SPD_PHY0_MASK      0x0000ffff
1981         #define REQ_LINE_SPD_PHY0_SHIFT     0
1982         #define REQ_LINE_SPD_PHY1_MASK      0xffff0000
1983         #define REQ_LINE_SPD_PHY1_SHIFT     16
1984         uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
1985         uint32_t additional_config;
1986         #define REQ_FC_AUTO_ADV_MASK        0x0000ffff
1987         #define REQ_FC_AUTO_ADV0_SHIFT      0
1988         #define NO_LFA_DUE_TO_DCC_MASK      0x00010000
1989         uint32_t lfa_sts;
1990         #define LFA_LINK_FLAP_REASON_OFFSET             0
1991         #define LFA_LINK_FLAP_REASON_MASK               0x000000ff
1992                 #define LFA_LINK_DOWN                       0x1
1993                 #define LFA_LOOPBACK_ENABLED            0x2
1994                 #define LFA_DUPLEX_MISMATCH                 0x3
1995                 #define LFA_MFW_IS_TOO_OLD                  0x4
1996                 #define LFA_LINK_SPEED_MISMATCH         0x5
1997                 #define LFA_FLOW_CTRL_MISMATCH          0x6
1998                 #define LFA_SPEED_CAP_MISMATCH          0x7
1999                 #define LFA_DCC_LFA_DISABLED            0x8
2000                 #define LFA_EEE_MISMATCH                0x9
2001
2002         #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET        8
2003         #define LINK_FLAP_AVOIDANCE_COUNT_MASK          0x0000ff00
2004
2005         #define LINK_FLAP_COUNT_OFFSET                  16
2006         #define LINK_FLAP_COUNT_MASK                    0x00ff0000
2007
2008         #define LFA_FLAGS_MASK                          0xff000000
2009         #define SHMEM_LFA_DONT_CLEAR_STAT               (1<<24)
2010 };
2011
2012 /* Used to support NSCI get OS driver version
2013  * on driver load the version value will be set
2014  * on driver unload driver value of 0x0 will be set.
2015  */
2016 struct os_drv_ver {
2017 #define DRV_VER_NOT_LOADED                      0
2018
2019         /* personalties order is important */
2020 #define DRV_PERS_ETHERNET                       0
2021 #define DRV_PERS_ISCSI                          1
2022 #define DRV_PERS_FCOE                           2
2023
2024         /* shmem2 struct is constant can't add more personalties here */
2025 #define MAX_DRV_PERS                            3
2026         uint32_t versions[MAX_DRV_PERS];
2027 };
2028
2029 struct ncsi_oem_fcoe_features {
2030         uint32_t fcoe_features1;
2031         #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK          0x0000FFFF
2032         #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET        0
2033
2034         #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK             0xFFFF0000
2035         #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET           16
2036
2037         uint32_t fcoe_features2;
2038         #define FCOE_FEATURES2_EXCHANGES_MASK                   0x0000FFFF
2039         #define FCOE_FEATURES2_EXCHANGES_OFFSET                 0
2040
2041         #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK           0xFFFF0000
2042         #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET         16
2043
2044         uint32_t fcoe_features3;
2045         #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK           0x0000FFFF
2046         #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET         0
2047
2048         #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK        0xFFFF0000
2049         #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET      16
2050
2051         uint32_t fcoe_features4;
2052         #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK            0x0000000F
2053         #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET          0
2054 };
2055
2056 struct ncsi_oem_data {
2057         uint32_t driver_version[4];
2058         struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
2059 };
2060
2061 struct shmem2_region {
2062
2063         uint32_t size;                                  /* 0x0000 */
2064
2065         uint32_t dcc_support;                           /* 0x0004 */
2066         #define SHMEM_DCC_SUPPORT_NONE                      0x00000000
2067         #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
2068         #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
2069         #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
2070         #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
2071         #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
2072
2073         uint32_t ext_phy_fw_version2[PORT_MAX];         /* 0x0008 */
2074         /*
2075          * For backwards compatibility, if the mf_cfg_addr does not exist
2076          * (the size filed is smaller than 0xc) the mf_cfg resides at the
2077          * end of struct shmem_region
2078          */
2079         uint32_t mf_cfg_addr;                           /* 0x0010 */
2080         #define SHMEM_MF_CFG_ADDR_NONE                  0x00000000
2081
2082         struct fw_flr_mb flr_mb;                        /* 0x0014 */
2083         uint32_t dcbx_lldp_params_offset;                       /* 0x0028 */
2084         #define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
2085         uint32_t dcbx_neg_res_offset;                   /* 0x002c */
2086         #define SHMEM_DCBX_NEG_RES_NONE                 0x00000000
2087         uint32_t dcbx_remote_mib_offset;                        /* 0x0030 */
2088         #define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
2089         /*
2090          * The other shmemX_base_addr holds the other path's shmem address
2091          * required for example in case of common phy init, or for path1 to know
2092          * the address of mcp debug trace which is located in offset from shmem
2093          * of path0
2094          */
2095         uint32_t other_shmem_base_addr;                 /* 0x0034 */
2096         uint32_t other_shmem2_base_addr;                        /* 0x0038 */
2097         /*
2098          * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2099          * which were disabled/flred
2100          */
2101         uint32_t mcp_vf_disabled[E2_VF_MAX / 32];               /* 0x003c */
2102
2103         /*
2104          * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2105          * VFs
2106          */
2107         uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2108
2109         uint32_t dcbx_lldp_dcbx_stat_offset;                    /* 0x0064 */
2110         #define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000
2111
2112         /*
2113          * edebug_driver_if field is used to transfer messages between edebug
2114          * app to the driver through shmem2.
2115          *
2116          * message format:
2117          * bits 0-2 -  function number / instance of driver to perform request
2118          * bits 3-5 -  op code / is_ack?
2119          * bits 6-63 - data
2120          */
2121         uint32_t edebug_driver_if[2];                   /* 0x0068 */
2122         #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
2123         #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
2124         #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3
2125
2126         uint32_t nvm_retain_bitmap_addr;                        /* 0x0070 */
2127
2128         /* afex support of that driver */
2129         uint32_t afex_driver_support;                   /* 0x0074 */
2130         #define SHMEM_AFEX_VERSION_MASK                  0x100f
2131         #define SHMEM_AFEX_SUPPORTED_VERSION_ONE         0x1001
2132         #define SHMEM_AFEX_REDUCED_DRV_LOADED            0x8000
2133
2134         /* driver receives addr in scratchpad to which it should respond */
2135         uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2136
2137         /* generic params from MCP to driver (value depends on the msg sent
2138          * to driver
2139          */
2140         uint32_t afex_param1_to_driver[E2_FUNC_MAX];            /* 0x0088 */
2141         uint32_t afex_param2_to_driver[E2_FUNC_MAX];            /* 0x0098 */
2142
2143         uint32_t swim_base_addr;                                /* 0x0108 */
2144         uint32_t swim_funcs;
2145         uint32_t swim_main_cb;
2146
2147         /* bitmap notifying which VIF profiles stored in nvram are enabled by
2148          * switch
2149          */
2150         uint32_t afex_profiles_enabled[2];
2151
2152         /* generic flags controlled by the driver */
2153         uint32_t drv_flags;
2154         #define DRV_FLAGS_DCB_CONFIGURED                0x0
2155         #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED     0x1
2156         #define DRV_FLAGS_DCB_MFW_CONFIGURED    0x2
2157
2158         #define DRV_FLAGS_PORT_MASK     ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2159                         (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2160                         (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2161         /* pointer to extended dev_info shared data copied from nvm image */
2162         uint32_t extended_dev_info_shared_addr;
2163         uint32_t ncsi_oem_data_addr;
2164
2165         uint32_t ocsd_host_addr; /* initialized by option ROM */
2166         uint32_t ocbb_host_addr; /* initialized by option ROM */
2167         uint32_t ocsd_req_update_interval; /* initialized by option ROM */
2168         uint32_t temperature_in_half_celsius;
2169         uint32_t glob_struct_in_host;
2170
2171         uint32_t dcbx_neg_res_ext_offset;
2172 #define SHMEM_DCBX_NEG_RES_EXT_NONE                     0x00000000
2173
2174         uint32_t drv_capabilities_flag[E2_FUNC_MAX];
2175 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2176 #define DRV_FLAGS_CAPABILITIES_LOADED_L2        0x00000002
2177 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE      0x00000004
2178 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI     0x00000008
2179
2180         uint32_t extended_dev_info_shared_cfg_size;
2181
2182         uint32_t dcbx_en[PORT_MAX];
2183
2184         /* The offset points to the multi threaded meta structure */
2185         uint32_t multi_thread_data_offset;
2186
2187         /* address of DMAable host address holding values from the drivers */
2188         uint32_t drv_info_host_addr_lo;
2189         uint32_t drv_info_host_addr_hi;
2190
2191         /* general values written by the MFW (such as current version) */
2192         uint32_t drv_info_control;
2193 #define DRV_INFO_CONTROL_VER_MASK          0x000000ff
2194 #define DRV_INFO_CONTROL_VER_SHIFT         0
2195 #define DRV_INFO_CONTROL_OP_CODE_MASK      0x0000ff00
2196 #define DRV_INFO_CONTROL_OP_CODE_SHIFT     8
2197         uint32_t ibft_host_addr; /* initialized by option ROM */
2198         struct eee_remote_vals eee_remote_vals[PORT_MAX];
2199         uint32_t reserved[E2_FUNC_MAX];
2200
2201
2202         /* the status of EEE auto-negotiation
2203          * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2204          * bits 19:16 the supported modes for EEE.
2205          * bits 23:20 the speeds advertised for EEE.
2206          * bits 27:24 the speeds the Link partner advertised for EEE.
2207          * The supported/adv. modes in bits 27:19 originate from the
2208          * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2209          * bit 28 when 1'b1 EEE was requested.
2210          * bit 29 when 1'b1 tx lpi was requested.
2211          * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2212          * 30:29 are 2'b11.
2213          * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2214          * value. When 1'b1 those bits contains a value times 16 microseconds.
2215          */
2216         uint32_t eee_status[PORT_MAX];
2217         #define SHMEM_EEE_TIMER_MASK               0x0000ffff
2218         #define SHMEM_EEE_SUPPORTED_MASK           0x000f0000
2219         #define SHMEM_EEE_SUPPORTED_SHIFT          16
2220         #define SHMEM_EEE_ADV_STATUS_MASK          0x00f00000
2221                 #define SHMEM_EEE_100M_ADV         (1<<0)
2222                 #define SHMEM_EEE_1G_ADV           (1<<1)
2223                 #define SHMEM_EEE_10G_ADV          (1<<2)
2224         #define SHMEM_EEE_ADV_STATUS_SHIFT         20
2225         #define SHMEM_EEE_LP_ADV_STATUS_MASK       0x0f000000
2226         #define SHMEM_EEE_LP_ADV_STATUS_SHIFT      24
2227         #define SHMEM_EEE_REQUESTED_BIT            0x10000000
2228         #define SHMEM_EEE_LPI_REQUESTED_BIT        0x20000000
2229         #define SHMEM_EEE_ACTIVE_BIT               0x40000000
2230         #define SHMEM_EEE_TIME_OUTPUT_BIT          0x80000000
2231
2232         uint32_t sizeof_port_stats;
2233
2234         /* Link Flap Avoidance */
2235         uint32_t lfa_host_addr[PORT_MAX];
2236         uint32_t reserved1;
2237
2238         uint32_t reserved2;                             /* Offset 0x148 */
2239         uint32_t reserved3;                             /* Offset 0x14C */
2240         uint32_t reserved4;                             /* Offset 0x150 */
2241         uint32_t link_attr_sync[PORT_MAX];              /* Offset 0x154 */
2242         #define LINK_ATTR_SYNC_KR2_ENABLE       0x00000001
2243         #define LINK_SFP_EEPROM_COMP_CODE_MASK  0x0000ff00
2244         #define LINK_SFP_EEPROM_COMP_CODE_SHIFT          8
2245         #define LINK_SFP_EEPROM_COMP_CODE_SR    0x00001000
2246         #define LINK_SFP_EEPROM_COMP_CODE_LR    0x00002000
2247         #define LINK_SFP_EEPROM_COMP_CODE_LRM   0x00004000
2248
2249         uint32_t reserved5[2];
2250         uint32_t reserved6[PORT_MAX];
2251
2252         /* driver version for each personality */
2253         struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
2254
2255         /* Flag to the driver that PF's drv_info_host_addr buffer was read  */
2256         uint32_t mfw_drv_indication;
2257
2258         /* We use indication for each PF (0..3) */
2259 #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
2260 };
2261
2262
2263 struct emac_stats {
2264         uint32_t     rx_stat_ifhcinoctets;
2265         uint32_t     rx_stat_ifhcinbadoctets;
2266         uint32_t     rx_stat_etherstatsfragments;
2267         uint32_t     rx_stat_ifhcinucastpkts;
2268         uint32_t     rx_stat_ifhcinmulticastpkts;
2269         uint32_t     rx_stat_ifhcinbroadcastpkts;
2270         uint32_t     rx_stat_dot3statsfcserrors;
2271         uint32_t     rx_stat_dot3statsalignmenterrors;
2272         uint32_t     rx_stat_dot3statscarriersenseerrors;
2273         uint32_t     rx_stat_xonpauseframesreceived;
2274         uint32_t     rx_stat_xoffpauseframesreceived;
2275         uint32_t     rx_stat_maccontrolframesreceived;
2276         uint32_t     rx_stat_xoffstateentered;
2277         uint32_t     rx_stat_dot3statsframestoolong;
2278         uint32_t     rx_stat_etherstatsjabbers;
2279         uint32_t     rx_stat_etherstatsundersizepkts;
2280         uint32_t     rx_stat_etherstatspkts64octets;
2281         uint32_t     rx_stat_etherstatspkts65octetsto127octets;
2282         uint32_t     rx_stat_etherstatspkts128octetsto255octets;
2283         uint32_t     rx_stat_etherstatspkts256octetsto511octets;
2284         uint32_t     rx_stat_etherstatspkts512octetsto1023octets;
2285         uint32_t     rx_stat_etherstatspkts1024octetsto1522octets;
2286         uint32_t     rx_stat_etherstatspktsover1522octets;
2287
2288         uint32_t     rx_stat_falsecarriererrors;
2289
2290         uint32_t     tx_stat_ifhcoutoctets;
2291         uint32_t     tx_stat_ifhcoutbadoctets;
2292         uint32_t     tx_stat_etherstatscollisions;
2293         uint32_t     tx_stat_outxonsent;
2294         uint32_t     tx_stat_outxoffsent;
2295         uint32_t     tx_stat_flowcontroldone;
2296         uint32_t     tx_stat_dot3statssinglecollisionframes;
2297         uint32_t     tx_stat_dot3statsmultiplecollisionframes;
2298         uint32_t     tx_stat_dot3statsdeferredtransmissions;
2299         uint32_t     tx_stat_dot3statsexcessivecollisions;
2300         uint32_t     tx_stat_dot3statslatecollisions;
2301         uint32_t     tx_stat_ifhcoutucastpkts;
2302         uint32_t     tx_stat_ifhcoutmulticastpkts;
2303         uint32_t     tx_stat_ifhcoutbroadcastpkts;
2304         uint32_t     tx_stat_etherstatspkts64octets;
2305         uint32_t     tx_stat_etherstatspkts65octetsto127octets;
2306         uint32_t     tx_stat_etherstatspkts128octetsto255octets;
2307         uint32_t     tx_stat_etherstatspkts256octetsto511octets;
2308         uint32_t     tx_stat_etherstatspkts512octetsto1023octets;
2309         uint32_t     tx_stat_etherstatspkts1024octetsto1522octets;
2310         uint32_t     tx_stat_etherstatspktsover1522octets;
2311         uint32_t     tx_stat_dot3statsinternalmactransmiterrors;
2312 };
2313
2314
2315 struct bmac1_stats {
2316         uint32_t        tx_stat_gtpkt_lo;
2317         uint32_t        tx_stat_gtpkt_hi;
2318         uint32_t        tx_stat_gtxpf_lo;
2319         uint32_t        tx_stat_gtxpf_hi;
2320         uint32_t        tx_stat_gtfcs_lo;
2321         uint32_t        tx_stat_gtfcs_hi;
2322         uint32_t        tx_stat_gtmca_lo;
2323         uint32_t        tx_stat_gtmca_hi;
2324         uint32_t        tx_stat_gtbca_lo;
2325         uint32_t        tx_stat_gtbca_hi;
2326         uint32_t        tx_stat_gtfrg_lo;
2327         uint32_t        tx_stat_gtfrg_hi;
2328         uint32_t        tx_stat_gtovr_lo;
2329         uint32_t        tx_stat_gtovr_hi;
2330         uint32_t        tx_stat_gt64_lo;
2331         uint32_t        tx_stat_gt64_hi;
2332         uint32_t        tx_stat_gt127_lo;
2333         uint32_t        tx_stat_gt127_hi;
2334         uint32_t        tx_stat_gt255_lo;
2335         uint32_t        tx_stat_gt255_hi;
2336         uint32_t        tx_stat_gt511_lo;
2337         uint32_t        tx_stat_gt511_hi;
2338         uint32_t        tx_stat_gt1023_lo;
2339         uint32_t        tx_stat_gt1023_hi;
2340         uint32_t        tx_stat_gt1518_lo;
2341         uint32_t        tx_stat_gt1518_hi;
2342         uint32_t        tx_stat_gt2047_lo;
2343         uint32_t        tx_stat_gt2047_hi;
2344         uint32_t        tx_stat_gt4095_lo;
2345         uint32_t        tx_stat_gt4095_hi;
2346         uint32_t        tx_stat_gt9216_lo;
2347         uint32_t        tx_stat_gt9216_hi;
2348         uint32_t        tx_stat_gt16383_lo;
2349         uint32_t        tx_stat_gt16383_hi;
2350         uint32_t        tx_stat_gtmax_lo;
2351         uint32_t        tx_stat_gtmax_hi;
2352         uint32_t        tx_stat_gtufl_lo;
2353         uint32_t        tx_stat_gtufl_hi;
2354         uint32_t        tx_stat_gterr_lo;
2355         uint32_t        tx_stat_gterr_hi;
2356         uint32_t        tx_stat_gtbyt_lo;
2357         uint32_t        tx_stat_gtbyt_hi;
2358
2359         uint32_t        rx_stat_gr64_lo;
2360         uint32_t        rx_stat_gr64_hi;
2361         uint32_t        rx_stat_gr127_lo;
2362         uint32_t        rx_stat_gr127_hi;
2363         uint32_t        rx_stat_gr255_lo;
2364         uint32_t        rx_stat_gr255_hi;
2365         uint32_t        rx_stat_gr511_lo;
2366         uint32_t        rx_stat_gr511_hi;
2367         uint32_t        rx_stat_gr1023_lo;
2368         uint32_t        rx_stat_gr1023_hi;
2369         uint32_t        rx_stat_gr1518_lo;
2370         uint32_t        rx_stat_gr1518_hi;
2371         uint32_t        rx_stat_gr2047_lo;
2372         uint32_t        rx_stat_gr2047_hi;
2373         uint32_t        rx_stat_gr4095_lo;
2374         uint32_t        rx_stat_gr4095_hi;
2375         uint32_t        rx_stat_gr9216_lo;
2376         uint32_t        rx_stat_gr9216_hi;
2377         uint32_t        rx_stat_gr16383_lo;
2378         uint32_t        rx_stat_gr16383_hi;
2379         uint32_t        rx_stat_grmax_lo;
2380         uint32_t        rx_stat_grmax_hi;
2381         uint32_t        rx_stat_grpkt_lo;
2382         uint32_t        rx_stat_grpkt_hi;
2383         uint32_t        rx_stat_grfcs_lo;
2384         uint32_t        rx_stat_grfcs_hi;
2385         uint32_t        rx_stat_grmca_lo;
2386         uint32_t        rx_stat_grmca_hi;
2387         uint32_t        rx_stat_grbca_lo;
2388         uint32_t        rx_stat_grbca_hi;
2389         uint32_t        rx_stat_grxcf_lo;
2390         uint32_t        rx_stat_grxcf_hi;
2391         uint32_t        rx_stat_grxpf_lo;
2392         uint32_t        rx_stat_grxpf_hi;
2393         uint32_t        rx_stat_grxuo_lo;
2394         uint32_t        rx_stat_grxuo_hi;
2395         uint32_t        rx_stat_grjbr_lo;
2396         uint32_t        rx_stat_grjbr_hi;
2397         uint32_t        rx_stat_grovr_lo;
2398         uint32_t        rx_stat_grovr_hi;
2399         uint32_t        rx_stat_grflr_lo;
2400         uint32_t        rx_stat_grflr_hi;
2401         uint32_t        rx_stat_grmeg_lo;
2402         uint32_t        rx_stat_grmeg_hi;
2403         uint32_t        rx_stat_grmeb_lo;
2404         uint32_t        rx_stat_grmeb_hi;
2405         uint32_t        rx_stat_grbyt_lo;
2406         uint32_t        rx_stat_grbyt_hi;
2407         uint32_t        rx_stat_grund_lo;
2408         uint32_t        rx_stat_grund_hi;
2409         uint32_t        rx_stat_grfrg_lo;
2410         uint32_t        rx_stat_grfrg_hi;
2411         uint32_t        rx_stat_grerb_lo;
2412         uint32_t        rx_stat_grerb_hi;
2413         uint32_t        rx_stat_grfre_lo;
2414         uint32_t        rx_stat_grfre_hi;
2415         uint32_t        rx_stat_gripj_lo;
2416         uint32_t        rx_stat_gripj_hi;
2417 };
2418
2419 struct bmac2_stats {
2420         uint32_t        tx_stat_gtpk_lo; /* gtpok */
2421         uint32_t        tx_stat_gtpk_hi; /* gtpok */
2422         uint32_t        tx_stat_gtxpf_lo; /* gtpf */
2423         uint32_t        tx_stat_gtxpf_hi; /* gtpf */
2424         uint32_t        tx_stat_gtpp_lo; /* NEW BMAC2 */
2425         uint32_t        tx_stat_gtpp_hi; /* NEW BMAC2 */
2426         uint32_t        tx_stat_gtfcs_lo;
2427         uint32_t        tx_stat_gtfcs_hi;
2428         uint32_t        tx_stat_gtuca_lo; /* NEW BMAC2 */
2429         uint32_t        tx_stat_gtuca_hi; /* NEW BMAC2 */
2430         uint32_t        tx_stat_gtmca_lo;
2431         uint32_t        tx_stat_gtmca_hi;
2432         uint32_t        tx_stat_gtbca_lo;
2433         uint32_t        tx_stat_gtbca_hi;
2434         uint32_t        tx_stat_gtovr_lo;
2435         uint32_t        tx_stat_gtovr_hi;
2436         uint32_t        tx_stat_gtfrg_lo;
2437         uint32_t        tx_stat_gtfrg_hi;
2438         uint32_t        tx_stat_gtpkt1_lo; /* gtpkt */
2439         uint32_t        tx_stat_gtpkt1_hi; /* gtpkt */
2440         uint32_t        tx_stat_gt64_lo;
2441         uint32_t        tx_stat_gt64_hi;
2442         uint32_t        tx_stat_gt127_lo;
2443         uint32_t        tx_stat_gt127_hi;
2444         uint32_t        tx_stat_gt255_lo;
2445         uint32_t        tx_stat_gt255_hi;
2446         uint32_t        tx_stat_gt511_lo;
2447         uint32_t        tx_stat_gt511_hi;
2448         uint32_t        tx_stat_gt1023_lo;
2449         uint32_t        tx_stat_gt1023_hi;
2450         uint32_t        tx_stat_gt1518_lo;
2451         uint32_t        tx_stat_gt1518_hi;
2452         uint32_t        tx_stat_gt2047_lo;
2453         uint32_t        tx_stat_gt2047_hi;
2454         uint32_t        tx_stat_gt4095_lo;
2455         uint32_t        tx_stat_gt4095_hi;
2456         uint32_t        tx_stat_gt9216_lo;
2457         uint32_t        tx_stat_gt9216_hi;
2458         uint32_t        tx_stat_gt16383_lo;
2459         uint32_t        tx_stat_gt16383_hi;
2460         uint32_t        tx_stat_gtmax_lo;
2461         uint32_t        tx_stat_gtmax_hi;
2462         uint32_t        tx_stat_gtufl_lo;
2463         uint32_t        tx_stat_gtufl_hi;
2464         uint32_t        tx_stat_gterr_lo;
2465         uint32_t        tx_stat_gterr_hi;
2466         uint32_t        tx_stat_gtbyt_lo;
2467         uint32_t        tx_stat_gtbyt_hi;
2468
2469         uint32_t        rx_stat_gr64_lo;
2470         uint32_t        rx_stat_gr64_hi;
2471         uint32_t        rx_stat_gr127_lo;
2472         uint32_t        rx_stat_gr127_hi;
2473         uint32_t        rx_stat_gr255_lo;
2474         uint32_t        rx_stat_gr255_hi;
2475         uint32_t        rx_stat_gr511_lo;
2476         uint32_t        rx_stat_gr511_hi;
2477         uint32_t        rx_stat_gr1023_lo;
2478         uint32_t        rx_stat_gr1023_hi;
2479         uint32_t        rx_stat_gr1518_lo;
2480         uint32_t        rx_stat_gr1518_hi;
2481         uint32_t        rx_stat_gr2047_lo;
2482         uint32_t        rx_stat_gr2047_hi;
2483         uint32_t        rx_stat_gr4095_lo;
2484         uint32_t        rx_stat_gr4095_hi;
2485         uint32_t        rx_stat_gr9216_lo;
2486         uint32_t        rx_stat_gr9216_hi;
2487         uint32_t        rx_stat_gr16383_lo;
2488         uint32_t        rx_stat_gr16383_hi;
2489         uint32_t        rx_stat_grmax_lo;
2490         uint32_t        rx_stat_grmax_hi;
2491         uint32_t        rx_stat_grpkt_lo;
2492         uint32_t        rx_stat_grpkt_hi;
2493         uint32_t        rx_stat_grfcs_lo;
2494         uint32_t        rx_stat_grfcs_hi;
2495         uint32_t        rx_stat_gruca_lo;
2496         uint32_t        rx_stat_gruca_hi;
2497         uint32_t        rx_stat_grmca_lo;
2498         uint32_t        rx_stat_grmca_hi;
2499         uint32_t        rx_stat_grbca_lo;
2500         uint32_t        rx_stat_grbca_hi;
2501         uint32_t        rx_stat_grxpf_lo; /* grpf */
2502         uint32_t        rx_stat_grxpf_hi; /* grpf */
2503         uint32_t        rx_stat_grpp_lo;
2504         uint32_t        rx_stat_grpp_hi;
2505         uint32_t        rx_stat_grxuo_lo; /* gruo */
2506         uint32_t        rx_stat_grxuo_hi; /* gruo */
2507         uint32_t        rx_stat_grjbr_lo;
2508         uint32_t        rx_stat_grjbr_hi;
2509         uint32_t        rx_stat_grovr_lo;
2510         uint32_t        rx_stat_grovr_hi;
2511         uint32_t        rx_stat_grxcf_lo; /* grcf */
2512         uint32_t        rx_stat_grxcf_hi; /* grcf */
2513         uint32_t        rx_stat_grflr_lo;
2514         uint32_t        rx_stat_grflr_hi;
2515         uint32_t        rx_stat_grpok_lo;
2516         uint32_t        rx_stat_grpok_hi;
2517         uint32_t        rx_stat_grmeg_lo;
2518         uint32_t        rx_stat_grmeg_hi;
2519         uint32_t        rx_stat_grmeb_lo;
2520         uint32_t        rx_stat_grmeb_hi;
2521         uint32_t        rx_stat_grbyt_lo;
2522         uint32_t        rx_stat_grbyt_hi;
2523         uint32_t        rx_stat_grund_lo;
2524         uint32_t        rx_stat_grund_hi;
2525         uint32_t        rx_stat_grfrg_lo;
2526         uint32_t        rx_stat_grfrg_hi;
2527         uint32_t        rx_stat_grerb_lo; /* grerrbyt */
2528         uint32_t        rx_stat_grerb_hi; /* grerrbyt */
2529         uint32_t        rx_stat_grfre_lo; /* grfrerr */
2530         uint32_t        rx_stat_grfre_hi; /* grfrerr */
2531         uint32_t        rx_stat_gripj_lo;
2532         uint32_t        rx_stat_gripj_hi;
2533 };
2534
2535 struct mstat_stats {
2536         struct {
2537                 /* OTE MSTAT on E3 has a bug where this register's contents are
2538                  * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2539                  */
2540                 uint32_t tx_gtxpok_lo;
2541                 uint32_t tx_gtxpok_hi;
2542                 uint32_t tx_gtxpf_lo;
2543                 uint32_t tx_gtxpf_hi;
2544                 uint32_t tx_gtxpp_lo;
2545                 uint32_t tx_gtxpp_hi;
2546                 uint32_t tx_gtfcs_lo;
2547                 uint32_t tx_gtfcs_hi;
2548                 uint32_t tx_gtuca_lo;
2549                 uint32_t tx_gtuca_hi;
2550                 uint32_t tx_gtmca_lo;
2551                 uint32_t tx_gtmca_hi;
2552                 uint32_t tx_gtgca_lo;
2553                 uint32_t tx_gtgca_hi;
2554                 uint32_t tx_gtpkt_lo;
2555                 uint32_t tx_gtpkt_hi;
2556                 uint32_t tx_gt64_lo;
2557                 uint32_t tx_gt64_hi;
2558                 uint32_t tx_gt127_lo;
2559                 uint32_t tx_gt127_hi;
2560                 uint32_t tx_gt255_lo;
2561                 uint32_t tx_gt255_hi;
2562                 uint32_t tx_gt511_lo;
2563                 uint32_t tx_gt511_hi;
2564                 uint32_t tx_gt1023_lo;
2565                 uint32_t tx_gt1023_hi;
2566                 uint32_t tx_gt1518_lo;
2567                 uint32_t tx_gt1518_hi;
2568                 uint32_t tx_gt2047_lo;
2569                 uint32_t tx_gt2047_hi;
2570                 uint32_t tx_gt4095_lo;
2571                 uint32_t tx_gt4095_hi;
2572                 uint32_t tx_gt9216_lo;
2573                 uint32_t tx_gt9216_hi;
2574                 uint32_t tx_gt16383_lo;
2575                 uint32_t tx_gt16383_hi;
2576                 uint32_t tx_gtufl_lo;
2577                 uint32_t tx_gtufl_hi;
2578                 uint32_t tx_gterr_lo;
2579                 uint32_t tx_gterr_hi;
2580                 uint32_t tx_gtbyt_lo;
2581                 uint32_t tx_gtbyt_hi;
2582                 uint32_t tx_collisions_lo;
2583                 uint32_t tx_collisions_hi;
2584                 uint32_t tx_singlecollision_lo;
2585                 uint32_t tx_singlecollision_hi;
2586                 uint32_t tx_multiplecollisions_lo;
2587                 uint32_t tx_multiplecollisions_hi;
2588                 uint32_t tx_deferred_lo;
2589                 uint32_t tx_deferred_hi;
2590                 uint32_t tx_excessivecollisions_lo;
2591                 uint32_t tx_excessivecollisions_hi;
2592                 uint32_t tx_latecollisions_lo;
2593                 uint32_t tx_latecollisions_hi;
2594         } stats_tx;
2595
2596         struct {
2597                 uint32_t rx_gr64_lo;
2598                 uint32_t rx_gr64_hi;
2599                 uint32_t rx_gr127_lo;
2600                 uint32_t rx_gr127_hi;
2601                 uint32_t rx_gr255_lo;
2602                 uint32_t rx_gr255_hi;
2603                 uint32_t rx_gr511_lo;
2604                 uint32_t rx_gr511_hi;
2605                 uint32_t rx_gr1023_lo;
2606                 uint32_t rx_gr1023_hi;
2607                 uint32_t rx_gr1518_lo;
2608                 uint32_t rx_gr1518_hi;
2609                 uint32_t rx_gr2047_lo;
2610                 uint32_t rx_gr2047_hi;
2611                 uint32_t rx_gr4095_lo;
2612                 uint32_t rx_gr4095_hi;
2613                 uint32_t rx_gr9216_lo;
2614                 uint32_t rx_gr9216_hi;
2615                 uint32_t rx_gr16383_lo;
2616                 uint32_t rx_gr16383_hi;
2617                 uint32_t rx_grpkt_lo;
2618                 uint32_t rx_grpkt_hi;
2619                 uint32_t rx_grfcs_lo;
2620                 uint32_t rx_grfcs_hi;
2621                 uint32_t rx_gruca_lo;
2622                 uint32_t rx_gruca_hi;
2623                 uint32_t rx_grmca_lo;
2624                 uint32_t rx_grmca_hi;
2625                 uint32_t rx_grbca_lo;
2626                 uint32_t rx_grbca_hi;
2627                 uint32_t rx_grxpf_lo;
2628                 uint32_t rx_grxpf_hi;
2629                 uint32_t rx_grxpp_lo;
2630                 uint32_t rx_grxpp_hi;
2631                 uint32_t rx_grxuo_lo;
2632                 uint32_t rx_grxuo_hi;
2633                 uint32_t rx_grovr_lo;
2634                 uint32_t rx_grovr_hi;
2635                 uint32_t rx_grxcf_lo;
2636                 uint32_t rx_grxcf_hi;
2637                 uint32_t rx_grflr_lo;
2638                 uint32_t rx_grflr_hi;
2639                 uint32_t rx_grpok_lo;
2640                 uint32_t rx_grpok_hi;
2641                 uint32_t rx_grbyt_lo;
2642                 uint32_t rx_grbyt_hi;
2643                 uint32_t rx_grund_lo;
2644                 uint32_t rx_grund_hi;
2645                 uint32_t rx_grfrg_lo;
2646                 uint32_t rx_grfrg_hi;
2647                 uint32_t rx_grerb_lo;
2648                 uint32_t rx_grerb_hi;
2649                 uint32_t rx_grfre_lo;
2650                 uint32_t rx_grfre_hi;
2651
2652                 uint32_t rx_alignmenterrors_lo;
2653                 uint32_t rx_alignmenterrors_hi;
2654                 uint32_t rx_falsecarrier_lo;
2655                 uint32_t rx_falsecarrier_hi;
2656                 uint32_t rx_llfcmsgcnt_lo;
2657                 uint32_t rx_llfcmsgcnt_hi;
2658         } stats_rx;
2659 };
2660
2661 union mac_stats {
2662         struct emac_stats       emac_stats;
2663         struct bmac1_stats      bmac1_stats;
2664         struct bmac2_stats      bmac2_stats;
2665         struct mstat_stats      mstat_stats;
2666 };
2667
2668
2669 struct mac_stx {
2670         /* in_bad_octets */
2671         uint32_t     rx_stat_ifhcinbadoctets_hi;
2672         uint32_t     rx_stat_ifhcinbadoctets_lo;
2673
2674         /* out_bad_octets */
2675         uint32_t     tx_stat_ifhcoutbadoctets_hi;
2676         uint32_t     tx_stat_ifhcoutbadoctets_lo;
2677
2678         /* crc_receive_errors */
2679         uint32_t     rx_stat_dot3statsfcserrors_hi;
2680         uint32_t     rx_stat_dot3statsfcserrors_lo;
2681         /* alignment_errors */
2682         uint32_t     rx_stat_dot3statsalignmenterrors_hi;
2683         uint32_t     rx_stat_dot3statsalignmenterrors_lo;
2684         /* carrier_sense_errors */
2685         uint32_t     rx_stat_dot3statscarriersenseerrors_hi;
2686         uint32_t     rx_stat_dot3statscarriersenseerrors_lo;
2687         /* false_carrier_detections */
2688         uint32_t     rx_stat_falsecarriererrors_hi;
2689         uint32_t     rx_stat_falsecarriererrors_lo;
2690
2691         /* runt_packets_received */
2692         uint32_t     rx_stat_etherstatsundersizepkts_hi;
2693         uint32_t     rx_stat_etherstatsundersizepkts_lo;
2694         /* jabber_packets_received */
2695         uint32_t     rx_stat_dot3statsframestoolong_hi;
2696         uint32_t     rx_stat_dot3statsframestoolong_lo;
2697
2698         /* error_runt_packets_received */
2699         uint32_t     rx_stat_etherstatsfragments_hi;
2700         uint32_t     rx_stat_etherstatsfragments_lo;
2701         /* error_jabber_packets_received */
2702         uint32_t     rx_stat_etherstatsjabbers_hi;
2703         uint32_t     rx_stat_etherstatsjabbers_lo;
2704
2705         /* control_frames_received */
2706         uint32_t     rx_stat_maccontrolframesreceived_hi;
2707         uint32_t     rx_stat_maccontrolframesreceived_lo;
2708         uint32_t     rx_stat_mac_xpf_hi;
2709         uint32_t     rx_stat_mac_xpf_lo;
2710         uint32_t     rx_stat_mac_xcf_hi;
2711         uint32_t     rx_stat_mac_xcf_lo;
2712
2713         /* xoff_state_entered */
2714         uint32_t     rx_stat_xoffstateentered_hi;
2715         uint32_t     rx_stat_xoffstateentered_lo;
2716         /* pause_xon_frames_received */
2717         uint32_t     rx_stat_xonpauseframesreceived_hi;
2718         uint32_t     rx_stat_xonpauseframesreceived_lo;
2719         /* pause_xoff_frames_received */
2720         uint32_t     rx_stat_xoffpauseframesreceived_hi;
2721         uint32_t     rx_stat_xoffpauseframesreceived_lo;
2722         /* pause_xon_frames_transmitted */
2723         uint32_t     tx_stat_outxonsent_hi;
2724         uint32_t     tx_stat_outxonsent_lo;
2725         /* pause_xoff_frames_transmitted */
2726         uint32_t     tx_stat_outxoffsent_hi;
2727         uint32_t     tx_stat_outxoffsent_lo;
2728         /* flow_control_done */
2729         uint32_t     tx_stat_flowcontroldone_hi;
2730         uint32_t     tx_stat_flowcontroldone_lo;
2731
2732         /* ether_stats_collisions */
2733         uint32_t     tx_stat_etherstatscollisions_hi;
2734         uint32_t     tx_stat_etherstatscollisions_lo;
2735         /* single_collision_transmit_frames */
2736         uint32_t     tx_stat_dot3statssinglecollisionframes_hi;
2737         uint32_t     tx_stat_dot3statssinglecollisionframes_lo;
2738         /* multiple_collision_transmit_frames */
2739         uint32_t     tx_stat_dot3statsmultiplecollisionframes_hi;
2740         uint32_t     tx_stat_dot3statsmultiplecollisionframes_lo;
2741         /* deferred_transmissions */
2742         uint32_t     tx_stat_dot3statsdeferredtransmissions_hi;
2743         uint32_t     tx_stat_dot3statsdeferredtransmissions_lo;
2744         /* excessive_collision_frames */
2745         uint32_t     tx_stat_dot3statsexcessivecollisions_hi;
2746         uint32_t     tx_stat_dot3statsexcessivecollisions_lo;
2747         /* late_collision_frames */
2748         uint32_t     tx_stat_dot3statslatecollisions_hi;
2749         uint32_t     tx_stat_dot3statslatecollisions_lo;
2750
2751         /* frames_transmitted_64_bytes */
2752         uint32_t     tx_stat_etherstatspkts64octets_hi;
2753         uint32_t     tx_stat_etherstatspkts64octets_lo;
2754         /* frames_transmitted_65_127_bytes */
2755         uint32_t     tx_stat_etherstatspkts65octetsto127octets_hi;
2756         uint32_t     tx_stat_etherstatspkts65octetsto127octets_lo;
2757         /* frames_transmitted_128_255_bytes */
2758         uint32_t     tx_stat_etherstatspkts128octetsto255octets_hi;
2759         uint32_t     tx_stat_etherstatspkts128octetsto255octets_lo;
2760         /* frames_transmitted_256_511_bytes */
2761         uint32_t     tx_stat_etherstatspkts256octetsto511octets_hi;
2762         uint32_t     tx_stat_etherstatspkts256octetsto511octets_lo;
2763         /* frames_transmitted_512_1023_bytes */
2764         uint32_t     tx_stat_etherstatspkts512octetsto1023octets_hi;
2765         uint32_t     tx_stat_etherstatspkts512octetsto1023octets_lo;
2766         /* frames_transmitted_1024_1522_bytes */
2767         uint32_t     tx_stat_etherstatspkts1024octetsto1522octets_hi;
2768         uint32_t     tx_stat_etherstatspkts1024octetsto1522octets_lo;
2769         /* frames_transmitted_1523_9022_bytes */
2770         uint32_t     tx_stat_etherstatspktsover1522octets_hi;
2771         uint32_t     tx_stat_etherstatspktsover1522octets_lo;
2772         uint32_t     tx_stat_mac_2047_hi;
2773         uint32_t     tx_stat_mac_2047_lo;
2774         uint32_t     tx_stat_mac_4095_hi;
2775         uint32_t     tx_stat_mac_4095_lo;
2776         uint32_t     tx_stat_mac_9216_hi;
2777         uint32_t     tx_stat_mac_9216_lo;
2778         uint32_t     tx_stat_mac_16383_hi;
2779         uint32_t     tx_stat_mac_16383_lo;
2780
2781         /* internal_mac_transmit_errors */
2782         uint32_t     tx_stat_dot3statsinternalmactransmiterrors_hi;
2783         uint32_t     tx_stat_dot3statsinternalmactransmiterrors_lo;
2784
2785         /* if_out_discards */
2786         uint32_t     tx_stat_mac_ufl_hi;
2787         uint32_t     tx_stat_mac_ufl_lo;
2788 };
2789
2790
2791 #define MAC_STX_IDX_MAX                     2
2792
2793 struct host_port_stats {
2794         uint32_t            host_port_stats_counter;
2795
2796         struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2797
2798         uint32_t            brb_drop_hi;
2799         uint32_t            brb_drop_lo;
2800
2801         uint32_t            not_used; /* obsolete */
2802         uint32_t            pfc_frames_tx_hi;
2803         uint32_t            pfc_frames_tx_lo;
2804         uint32_t            pfc_frames_rx_hi;
2805         uint32_t            pfc_frames_rx_lo;
2806
2807         uint32_t            eee_lpi_count_hi;
2808         uint32_t            eee_lpi_count_lo;
2809 };
2810
2811
2812 struct host_func_stats {
2813         uint32_t     host_func_stats_start;
2814
2815         uint32_t     total_bytes_received_hi;
2816         uint32_t     total_bytes_received_lo;
2817
2818         uint32_t     total_bytes_transmitted_hi;
2819         uint32_t     total_bytes_transmitted_lo;
2820
2821         uint32_t     total_unicast_packets_received_hi;
2822         uint32_t     total_unicast_packets_received_lo;
2823
2824         uint32_t     total_multicast_packets_received_hi;
2825         uint32_t     total_multicast_packets_received_lo;
2826
2827         uint32_t     total_broadcast_packets_received_hi;
2828         uint32_t     total_broadcast_packets_received_lo;
2829
2830         uint32_t     total_unicast_packets_transmitted_hi;
2831         uint32_t     total_unicast_packets_transmitted_lo;
2832
2833         uint32_t     total_multicast_packets_transmitted_hi;
2834         uint32_t     total_multicast_packets_transmitted_lo;
2835
2836         uint32_t     total_broadcast_packets_transmitted_hi;
2837         uint32_t     total_broadcast_packets_transmitted_lo;
2838
2839         uint32_t     valid_bytes_received_hi;
2840         uint32_t     valid_bytes_received_lo;
2841
2842         uint32_t     host_func_stats_end;
2843 };
2844
2845 /* VIC definitions */
2846 #define VICSTATST_UIF_INDEX 2
2847
2848
2849 /* stats collected for afex.
2850  * NOTE: structure is exactly as expected to be received by the switch.
2851  *       order must remain exactly as is unless protocol changes !
2852  */
2853 struct afex_stats {
2854         uint32_t tx_unicast_frames_hi;
2855         uint32_t tx_unicast_frames_lo;
2856         uint32_t tx_unicast_bytes_hi;
2857         uint32_t tx_unicast_bytes_lo;
2858         uint32_t tx_multicast_frames_hi;
2859         uint32_t tx_multicast_frames_lo;
2860         uint32_t tx_multicast_bytes_hi;
2861         uint32_t tx_multicast_bytes_lo;
2862         uint32_t tx_broadcast_frames_hi;
2863         uint32_t tx_broadcast_frames_lo;
2864         uint32_t tx_broadcast_bytes_hi;
2865         uint32_t tx_broadcast_bytes_lo;
2866         uint32_t tx_frames_discarded_hi;
2867         uint32_t tx_frames_discarded_lo;
2868         uint32_t tx_frames_dropped_hi;
2869         uint32_t tx_frames_dropped_lo;
2870
2871         uint32_t rx_unicast_frames_hi;
2872         uint32_t rx_unicast_frames_lo;
2873         uint32_t rx_unicast_bytes_hi;
2874         uint32_t rx_unicast_bytes_lo;
2875         uint32_t rx_multicast_frames_hi;
2876         uint32_t rx_multicast_frames_lo;
2877         uint32_t rx_multicast_bytes_hi;
2878         uint32_t rx_multicast_bytes_lo;
2879         uint32_t rx_broadcast_frames_hi;
2880         uint32_t rx_broadcast_frames_lo;
2881         uint32_t rx_broadcast_bytes_hi;
2882         uint32_t rx_broadcast_bytes_lo;
2883         uint32_t rx_frames_discarded_hi;
2884         uint32_t rx_frames_discarded_lo;
2885         uint32_t rx_frames_dropped_hi;
2886         uint32_t rx_frames_dropped_lo;
2887 };
2888
2889 #define BCM_5710_FW_MAJOR_VERSION                       7
2890 #define BCM_5710_FW_MINOR_VERSION                       10
2891 #define BCM_5710_FW_REVISION_VERSION            51
2892 #define BCM_5710_FW_ENGINEERING_VERSION         0
2893 #define BCM_5710_FW_COMPILE_FLAGS                       1
2894
2895
2896 /*
2897  * attention bits
2898  */
2899 struct atten_sp_status_block {
2900         __le32 attn_bits;
2901         __le32 attn_bits_ack;
2902         uint8_t status_block_id;
2903         uint8_t reserved0;
2904         __le16 attn_bits_index;
2905         __le32 reserved1;
2906 };
2907
2908
2909 /*
2910  * The eth aggregative context of Cstorm
2911  */
2912 struct cstorm_eth_ag_context {
2913         uint32_t __reserved0[10];
2914 };
2915
2916
2917 /*
2918  * dmae command structure