Migrated Akaros code to use pragma once (XCC)
[akaros.git] / kern / drivers / net / bnx2x / bnx2x_ethtool.c
1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath and fastpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include <linux_compat.h>
19
20 #include "bnx2x.h"
21 #include "bnx2x_cmn.h"
22 #include "bnx2x_dump.h"
23 #include "bnx2x_init.h"
24
25 /* Note: in the format strings below %s is replaced by the queue-name which is
26  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
27  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
28  */
29 #define MAX_QUEUE_NAME_LEN      4
30 static const struct {
31         long offset;
32         int size;
33         char string[ETH_GSTRING_LEN];
34 } bnx2x_q_stats_arr[] = {
35 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
36         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
37                                                 8, "[%s]: rx_ucast_packets" },
38         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
39                                                 8, "[%s]: rx_mcast_packets" },
40         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
41                                                 8, "[%s]: rx_bcast_packets" },
42         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
43         { Q_STATS_OFFSET32(rx_err_discard_pkt),
44                                          4, "[%s]: rx_phy_ip_err_discards"},
45         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
46                                          4, "[%s]: rx_skb_alloc_discard" },
47         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
48
49         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
50 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
51                                                 8, "[%s]: tx_ucast_packets" },
52         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
53                                                 8, "[%s]: tx_mcast_packets" },
54         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
55                                                 8, "[%s]: tx_bcast_packets" },
56         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
57                                                 8, "[%s]: tpa_aggregations" },
58         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
59                                         8, "[%s]: tpa_aggregated_frames"},
60         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
61         { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
62                                         4, "[%s]: driver_filtered_tx_pkt" }
63 };
64
65 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
66
67 static const struct {
68         long offset;
69         int size;
70         uint32_t flags;
71 #define STATS_FLAGS_PORT                1
72 #define STATS_FLAGS_FUNC                2
73 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
74         char string[ETH_GSTRING_LEN];
75 } bnx2x_stats_arr[] = {
76 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
77                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
78         { STATS_OFFSET32(error_bytes_received_hi),
79                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
80         { STATS_OFFSET32(total_unicast_packets_received_hi),
81                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
82         { STATS_OFFSET32(total_multicast_packets_received_hi),
83                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
84         { STATS_OFFSET32(total_broadcast_packets_received_hi),
85                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
86         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
87                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
88         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
89                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
90         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
91                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
92         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
93                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
94 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
95                                 8, STATS_FLAGS_PORT, "rx_fragments" },
96         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
97                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
98         { STATS_OFFSET32(no_buff_discard_hi),
99                                 8, STATS_FLAGS_BOTH, "rx_discards" },
100         { STATS_OFFSET32(mac_filter_discard),
101                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
102         { STATS_OFFSET32(mf_tag_discard),
103                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
104         { STATS_OFFSET32(pfc_frames_received_hi),
105                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
106         { STATS_OFFSET32(pfc_frames_sent_hi),
107                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
108         { STATS_OFFSET32(brb_drop_hi),
109                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
110         { STATS_OFFSET32(brb_truncate_hi),
111                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
112         { STATS_OFFSET32(pause_frames_received_hi),
113                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
114         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
115                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
116         { STATS_OFFSET32(nig_timer_max),
117                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
118 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
119                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
120         { STATS_OFFSET32(rx_skb_alloc_failed),
121                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
122         { STATS_OFFSET32(hw_csum_err),
123                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
124
125         { STATS_OFFSET32(total_bytes_transmitted_hi),
126                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
127         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
128                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
129         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
130                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
131         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
132                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
133         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
134                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
135         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
136                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
137         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
138                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
139 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
140                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
141         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
142                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
143         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
144                                 8, STATS_FLAGS_PORT, "tx_deferred" },
145         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
146                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
147         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
148                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
149         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
150                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
151         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
152                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
153         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
154                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
155         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
156                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
157         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
158                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
159 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
160                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
161         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
162                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
163         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
164                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
165         { STATS_OFFSET32(pause_frames_sent_hi),
166                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
167         { STATS_OFFSET32(total_tpa_aggregations_hi),
168                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
169         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
170                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
171         { STATS_OFFSET32(total_tpa_bytes_hi),
172                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
173         { STATS_OFFSET32(recoverable_error),
174                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
175         { STATS_OFFSET32(unrecoverable_error),
176                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
177         { STATS_OFFSET32(driver_filtered_tx_pkt),
178                         4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
179         { STATS_OFFSET32(eee_tx_lpi),
180                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
181 };
182
183 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
184
185 static int bnx2x_get_port_type(struct bnx2x *bp)
186 {
187         int port_type;
188         uint32_t phy_idx = bnx2x_get_cur_phy_idx(bp);
189         switch (bp->link_params.phy[phy_idx].media_type) {
190         case ETH_PHY_SFPP_10G_FIBER:
191         case ETH_PHY_SFP_1G_FIBER:
192         case ETH_PHY_XFP_FIBER:
193         case ETH_PHY_KR:
194         case ETH_PHY_CX4:
195                 port_type = PORT_FIBRE;
196                 break;
197         case ETH_PHY_DA_TWINAX:
198                 port_type = PORT_DA;
199                 break;
200         case ETH_PHY_BASE_T:
201                 port_type = PORT_TP;
202                 break;
203         case ETH_PHY_NOT_PRESENT:
204                 port_type = PORT_NONE;
205                 break;
206         case ETH_PHY_UNSPECIFIED:
207         default:
208                 port_type = PORT_OTHER;
209                 break;
210         }
211         return port_type;
212 }
213
214 static int bnx2x_get_vf_settings(struct ether *dev,
215                                  struct ethtool_cmd *cmd)
216 {
217         struct bnx2x *bp = netdev_priv(dev);
218
219         if (bp->state == BNX2X_STATE_OPEN) {
220                 if (test_bit(BNX2X_LINK_REPORT_FD,
221                              &bp->vf_link_vars.link_report_flags))
222                         cmd->duplex = DUPLEX_FULL;
223                 else
224                         cmd->duplex = DUPLEX_HALF;
225
226                 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
227         } else {
228                 cmd->duplex = DUPLEX_UNKNOWN;
229                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
230         }
231
232         cmd->port               = PORT_OTHER;
233         cmd->phy_address        = 0;
234         cmd->transceiver        = XCVR_INTERNAL;
235         cmd->autoneg            = AUTONEG_DISABLE;
236         cmd->maxtxpkt           = 0;
237         cmd->maxrxpkt           = 0;
238
239         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
240            "  supported 0x%x  advertising 0x%x  speed %u\n"
241            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
242            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
243            cmd->cmd, cmd->supported, cmd->advertising,
244            ethtool_cmd_speed(cmd),
245            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
246            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
247
248         return 0;
249 }
250
251 static int bnx2x_get_settings(struct ether *dev, struct ethtool_cmd *cmd)
252 {
253         struct bnx2x *bp = netdev_priv(dev);
254         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
255
256         /* Dual Media boards present all available port types */
257         cmd->supported = bp->port.supported[cfg_idx] |
258                 (bp->port.supported[cfg_idx ^ 1] &
259                  (SUPPORTED_TP | SUPPORTED_FIBRE));
260         cmd->advertising = bp->port.advertising[cfg_idx];
261         if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
262             ETH_PHY_SFP_1G_FIBER) {
263                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
264                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
265         }
266
267         if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
268             !(bp->flags & MF_FUNC_DIS)) {
269                 cmd->duplex = bp->link_vars.duplex;
270
271                 if (IS_MF(bp) && !BP_NOMCP(bp))
272                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
273                 else
274                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
275         } else {
276                 cmd->duplex = DUPLEX_UNKNOWN;
277                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
278         }
279
280         cmd->port = bnx2x_get_port_type(bp);
281
282         cmd->phy_address = bp->mdio.prtad;
283         cmd->transceiver = XCVR_INTERNAL;
284
285         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
286                 cmd->autoneg = AUTONEG_ENABLE;
287         else
288                 cmd->autoneg = AUTONEG_DISABLE;
289
290         /* Publish LP advertised speeds and FC */
291         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
292                 uint32_t status = bp->link_vars.link_status;
293
294                 cmd->lp_advertising |= ADVERTISED_Autoneg;
295                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
296                         cmd->lp_advertising |= ADVERTISED_Pause;
297                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
298                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
299
300                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
301                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
302                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
303                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
304                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
305                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
306                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
307                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
308                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
309                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
310                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
311                         cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
312                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
313                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
314                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
315                         cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
316                 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
317                         cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
318         }
319
320         cmd->maxtxpkt = 0;
321         cmd->maxrxpkt = 0;
322
323         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
324            "  supported 0x%x  advertising 0x%x  speed %u\n"
325            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
326            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
327            cmd->cmd, cmd->supported, cmd->advertising,
328            ethtool_cmd_speed(cmd),
329            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
330            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
331
332         return 0;
333 }
334
335 static int bnx2x_set_settings(struct ether *dev, struct ethtool_cmd *cmd)
336 {
337         struct bnx2x *bp = netdev_priv(dev);
338         uint32_t advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
339         uint32_t speed, phy_idx;
340
341         if (IS_MF_SD(bp))
342                 return 0;
343
344         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
345            "  supported 0x%x  advertising 0x%x  speed %u\n"
346            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
347            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
348            cmd->cmd, cmd->supported, cmd->advertising,
349            ethtool_cmd_speed(cmd),
350            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
351            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
352
353         speed = ethtool_cmd_speed(cmd);
354
355         /* If received a request for an unknown duplex, assume full*/
356         if (cmd->duplex == DUPLEX_UNKNOWN)
357                 cmd->duplex = DUPLEX_FULL;
358
359         if (IS_MF_SI(bp)) {
360                 uint32_t part;
361                 uint32_t line_speed = bp->link_vars.line_speed;
362
363                 /* use 10G if no link detected */
364                 if (!line_speed)
365                         line_speed = 10000;
366
367                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
368                         DP(BNX2X_MSG_ETHTOOL,
369                            "To set speed BC %X or higher is required, please upgrade BC\n",
370                            REQ_BC_VER_4_SET_MF_BW);
371                         return -EINVAL;
372                 }
373
374                 part = (speed * 100) / line_speed;
375
376                 if (line_speed < speed || !part) {
377                         DP(BNX2X_MSG_ETHTOOL,
378                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
379                         return -EINVAL;
380                 }
381
382                 if (bp->state != BNX2X_STATE_OPEN)
383                         /* store value for following "load" */
384                         bp->pending_max = part;
385                 else
386                         bnx2x_update_max_mf_config(bp, part);
387
388                 return 0;
389         }
390
391         cfg_idx = bnx2x_get_link_cfg_idx(bp);
392         old_multi_phy_config = bp->link_params.multi_phy_config;
393         if (cmd->port != bnx2x_get_port_type(bp)) {
394                 switch (cmd->port) {
395                 case PORT_TP:
396                         if (!(bp->port.supported[0] & SUPPORTED_TP ||
397                               bp->port.supported[1] & SUPPORTED_TP)) {
398                                 DP(BNX2X_MSG_ETHTOOL,
399                                    "Unsupported port type\n");
400                                 return -EINVAL;
401                         }
402                         bp->link_params.multi_phy_config &=
403                                 ~PORT_HW_CFG_PHY_SELECTION_MASK;
404                         if (bp->link_params.multi_phy_config &
405                             PORT_HW_CFG_PHY_SWAPPED_ENABLED)
406                                 bp->link_params.multi_phy_config |=
407                                 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
408                         else
409                                 bp->link_params.multi_phy_config |=
410                                 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
411                         break;
412                 case PORT_FIBRE:
413                 case PORT_DA:
414                 case PORT_NONE:
415                         if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
416                               bp->port.supported[1] & SUPPORTED_FIBRE)) {
417                                 DP(BNX2X_MSG_ETHTOOL,
418                                    "Unsupported port type\n");
419                                 return -EINVAL;
420                         }
421                         bp->link_params.multi_phy_config &=
422                                 ~PORT_HW_CFG_PHY_SELECTION_MASK;
423                         if (bp->link_params.multi_phy_config &
424                             PORT_HW_CFG_PHY_SWAPPED_ENABLED)
425                                 bp->link_params.multi_phy_config |=
426                                 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
427                         else
428                                 bp->link_params.multi_phy_config |=
429                                 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
430                         break;
431                 default:
432                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
433                         return -EINVAL;
434                 }
435         }
436         /* Save new config in case command complete successfully */
437         new_multi_phy_config = bp->link_params.multi_phy_config;
438         /* Get the new cfg_idx */
439         cfg_idx = bnx2x_get_link_cfg_idx(bp);
440         /* Restore old config in case command failed */
441         bp->link_params.multi_phy_config = old_multi_phy_config;
442         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
443
444         if (cmd->autoneg == AUTONEG_ENABLE) {
445                 uint32_t an_supported_speed = bp->port.supported[cfg_idx];
446                 if (bp->link_params.phy[EXT_PHY1].type ==
447                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
448                         an_supported_speed |= (SUPPORTED_100baseT_Half |
449                                                SUPPORTED_100baseT_Full);
450                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
451                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
452                         return -EINVAL;
453                 }
454
455                 /* advertise the requested speed and duplex if supported */
456                 if (cmd->advertising & ~an_supported_speed) {
457                         DP(BNX2X_MSG_ETHTOOL,
458                            "Advertisement parameters are not supported\n");
459                         return -EINVAL;
460                 }
461
462                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
463                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
464                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
465                                          cmd->advertising);
466                 if (cmd->advertising) {
467
468                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
469                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
470                                 bp->link_params.speed_cap_mask[cfg_idx] |=
471                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
472                         }
473                         if (cmd->advertising & ADVERTISED_10baseT_Full)
474                                 bp->link_params.speed_cap_mask[cfg_idx] |=
475                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
476
477                         if (cmd->advertising & ADVERTISED_100baseT_Full)
478                                 bp->link_params.speed_cap_mask[cfg_idx] |=
479                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
480
481                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
482                                 bp->link_params.speed_cap_mask[cfg_idx] |=
483                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
484                         }
485                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
486                                 bp->link_params.speed_cap_mask[cfg_idx] |=
487                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
488                         }
489                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
490                                                 ADVERTISED_1000baseKX_Full))
491                                 bp->link_params.speed_cap_mask[cfg_idx] |=
492                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
493
494                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
495                                                 ADVERTISED_10000baseKX4_Full |
496                                                 ADVERTISED_10000baseKR_Full))
497                                 bp->link_params.speed_cap_mask[cfg_idx] |=
498                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
499
500                         if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
501                                 bp->link_params.speed_cap_mask[cfg_idx] |=
502                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
503                 }
504         } else { /* forced speed */
505                 /* advertise the requested speed and duplex if supported */
506                 switch (speed) {
507                 case SPEED_10:
508                         if (cmd->duplex == DUPLEX_FULL) {
509                                 if (!(bp->port.supported[cfg_idx] &
510                                       SUPPORTED_10baseT_Full)) {
511                                         DP(BNX2X_MSG_ETHTOOL,
512                                            "10M full not supported\n");
513                                         return -EINVAL;
514                                 }
515
516                                 advertising = (ADVERTISED_10baseT_Full |
517                                                ADVERTISED_TP);
518                         } else {
519                                 if (!(bp->port.supported[cfg_idx] &
520                                       SUPPORTED_10baseT_Half)) {
521                                         DP(BNX2X_MSG_ETHTOOL,
522                                            "10M half not supported\n");
523                                         return -EINVAL;
524                                 }
525
526                                 advertising = (ADVERTISED_10baseT_Half |
527                                                ADVERTISED_TP);
528                         }
529                         break;
530
531                 case SPEED_100:
532                         if (cmd->duplex == DUPLEX_FULL) {
533                                 if (!(bp->port.supported[cfg_idx] &
534                                                 SUPPORTED_100baseT_Full)) {
535                                         DP(BNX2X_MSG_ETHTOOL,
536                                            "100M full not supported\n");
537                                         return -EINVAL;
538                                 }
539
540                                 advertising = (ADVERTISED_100baseT_Full |
541                                                ADVERTISED_TP);
542                         } else {
543                                 if (!(bp->port.supported[cfg_idx] &
544                                                 SUPPORTED_100baseT_Half)) {
545                                         DP(BNX2X_MSG_ETHTOOL,
546                                            "100M half not supported\n");
547                                         return -EINVAL;
548                                 }
549
550                                 advertising = (ADVERTISED_100baseT_Half |
551                                                ADVERTISED_TP);
552                         }
553                         break;
554
555                 case SPEED_1000:
556                         if (cmd->duplex != DUPLEX_FULL) {
557                                 DP(BNX2X_MSG_ETHTOOL,
558                                    "1G half not supported\n");
559                                 return -EINVAL;
560                         }
561
562                         if (!(bp->port.supported[cfg_idx] &
563                               SUPPORTED_1000baseT_Full)) {
564                                 DP(BNX2X_MSG_ETHTOOL,
565                                    "1G full not supported\n");
566                                 return -EINVAL;
567                         }
568
569                         advertising = (ADVERTISED_1000baseT_Full |
570                                        ADVERTISED_TP);
571                         break;
572
573                 case SPEED_2500:
574                         if (cmd->duplex != DUPLEX_FULL) {
575                                 DP(BNX2X_MSG_ETHTOOL,
576                                    "2.5G half not supported\n");
577                                 return -EINVAL;
578                         }
579
580                         if (!(bp->port.supported[cfg_idx]
581                               & SUPPORTED_2500baseX_Full)) {
582                                 DP(BNX2X_MSG_ETHTOOL,
583                                    "2.5G full not supported\n");
584                                 return -EINVAL;
585                         }
586
587                         advertising = (ADVERTISED_2500baseX_Full |
588                                        ADVERTISED_TP);
589                         break;
590
591                 case SPEED_10000:
592                         if (cmd->duplex != DUPLEX_FULL) {
593                                 DP(BNX2X_MSG_ETHTOOL,
594                                    "10G half not supported\n");
595                                 return -EINVAL;
596                         }
597                         phy_idx = bnx2x_get_cur_phy_idx(bp);
598                         if (!(bp->port.supported[cfg_idx]
599                               & SUPPORTED_10000baseT_Full) ||
600                             (bp->link_params.phy[phy_idx].media_type ==
601                              ETH_PHY_SFP_1G_FIBER)) {
602                                 DP(BNX2X_MSG_ETHTOOL,
603                                    "10G full not supported\n");
604                                 return -EINVAL;
605                         }
606
607                         advertising = (ADVERTISED_10000baseT_Full |
608                                        ADVERTISED_FIBRE);
609                         break;
610
611                 default:
612                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
613                         return -EINVAL;
614                 }
615
616                 bp->link_params.req_line_speed[cfg_idx] = speed;
617                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
618                 bp->port.advertising[cfg_idx] = advertising;
619         }
620
621         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
622            "  req_duplex %d  advertising 0x%x\n",
623            bp->link_params.req_line_speed[cfg_idx],
624            bp->link_params.req_duplex[cfg_idx],
625            bp->port.advertising[cfg_idx]);
626
627         /* Set new config */
628         bp->link_params.multi_phy_config = new_multi_phy_config;
629         if (netif_running(dev)) {
630                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
631                 bnx2x_link_set(bp);
632         }
633
634         return 0;
635 }
636
637 #define DUMP_ALL_PRESETS                0x1FFF
638 #define DUMP_MAX_PRESETS                13
639
640 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, uint32_t preset)
641 {
642         if (CHIP_IS_E1(bp))
643                 return dump_num_registers[0][preset-1];
644         else if (CHIP_IS_E1H(bp))
645                 return dump_num_registers[1][preset-1];
646         else if (CHIP_IS_E2(bp))
647                 return dump_num_registers[2][preset-1];
648         else if (CHIP_IS_E3A0(bp))
649                 return dump_num_registers[3][preset-1];
650         else if (CHIP_IS_E3B0(bp))
651                 return dump_num_registers[4][preset-1];
652         else
653                 return 0;
654 }
655
656 static int __bnx2x_get_regs_len(struct bnx2x *bp)
657 {
658         uint32_t preset_idx;
659         int regdump_len = 0;
660
661         /* Calculate the total preset regs length */
662         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
663                 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
664
665         return regdump_len;
666 }
667
668 static int bnx2x_get_regs_len(struct ether *dev)
669 {
670         struct bnx2x *bp = netdev_priv(dev);
671         int regdump_len = 0;
672
673         if (IS_VF(bp))
674                 return 0;
675
676         regdump_len = __bnx2x_get_regs_len(bp);
677         regdump_len *= 4;
678         regdump_len += sizeof(struct dump_header);
679
680         return regdump_len;
681 }
682
683 #define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
684 #define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
685 #define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
686 #define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
687 #define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
688
689 #define IS_REG_IN_PRESET(presets, idx)  \
690                 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
691
692 /******* Paged registers info selectors ********/
693 static const uint32_t *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
694 {
695         if (CHIP_IS_E2(bp))
696                 return page_vals_e2;
697         else if (CHIP_IS_E3(bp))
698                 return page_vals_e3;
699         else
700                 return NULL;
701 }
702
703 static uint32_t __bnx2x_get_page_reg_num(struct bnx2x *bp)
704 {
705         if (CHIP_IS_E2(bp))
706                 return PAGE_MODE_VALUES_E2;
707         else if (CHIP_IS_E3(bp))
708                 return PAGE_MODE_VALUES_E3;
709         else
710                 return 0;
711 }
712
713 static const uint32_t *__bnx2x_get_page_write_ar(struct bnx2x *bp)
714 {
715         if (CHIP_IS_E2(bp))
716                 return page_write_regs_e2;
717         else if (CHIP_IS_E3(bp))
718                 return page_write_regs_e3;
719         else
720                 return NULL;
721 }
722
723 static uint32_t __bnx2x_get_page_write_num(struct bnx2x *bp)
724 {
725         if (CHIP_IS_E2(bp))
726                 return PAGE_WRITE_REGS_E2;
727         else if (CHIP_IS_E3(bp))
728                 return PAGE_WRITE_REGS_E3;
729         else
730                 return 0;
731 }
732
733 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
734 {
735         if (CHIP_IS_E2(bp))
736                 return page_read_regs_e2;
737         else if (CHIP_IS_E3(bp))
738                 return page_read_regs_e3;
739         else
740                 return NULL;
741 }
742
743 static uint32_t __bnx2x_get_page_read_num(struct bnx2x *bp)
744 {
745         if (CHIP_IS_E2(bp))
746                 return PAGE_READ_REGS_E2;
747         else if (CHIP_IS_E3(bp))
748                 return PAGE_READ_REGS_E3;
749         else
750                 return 0;
751 }
752
753 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
754                                        const struct reg_addr *reg_info)
755 {
756         if (CHIP_IS_E1(bp))
757                 return IS_E1_REG(reg_info->chips);
758         else if (CHIP_IS_E1H(bp))
759                 return IS_E1H_REG(reg_info->chips);
760         else if (CHIP_IS_E2(bp))
761                 return IS_E2_REG(reg_info->chips);
762         else if (CHIP_IS_E3A0(bp))
763                 return IS_E3A0_REG(reg_info->chips);
764         else if (CHIP_IS_E3B0(bp))
765                 return IS_E3B0_REG(reg_info->chips);
766         else
767                 return false;
768 }
769
770 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
771         const struct wreg_addr *wreg_info)
772 {
773         if (CHIP_IS_E1(bp))
774                 return IS_E1_REG(wreg_info->chips);
775         else if (CHIP_IS_E1H(bp))
776                 return IS_E1H_REG(wreg_info->chips);
777         else if (CHIP_IS_E2(bp))
778                 return IS_E2_REG(wreg_info->chips);
779         else if (CHIP_IS_E3A0(bp))
780                 return IS_E3A0_REG(wreg_info->chips);
781         else if (CHIP_IS_E3B0(bp))
782                 return IS_E3B0_REG(wreg_info->chips);
783         else
784                 return false;
785 }
786
787 /**
788  * bnx2x_read_pages_regs - read "paged" registers
789  *
790  * @bp          device handle
791  * @p           output buffer
792  *
793  * Reads "paged" memories: memories that may only be read by first writing to a
794  * specific address ("write address") and then reading from a specific address
795  * ("read address"). There may be more than one write address per "page" and
796  * more than one read address per write address.
797  */
798 static void bnx2x_read_pages_regs(struct bnx2x *bp, uint32_t *p,
799                                   uint32_t preset)
800 {
801         uint32_t i, j, k, n;
802
803         /* addresses of the paged registers */
804         const uint32_t *page_addr = __bnx2x_get_page_addr_ar(bp);
805         /* number of paged registers */
806         int num_pages = __bnx2x_get_page_reg_num(bp);
807         /* write addresses */
808         const uint32_t *write_addr = __bnx2x_get_page_write_ar(bp);
809         /* number of write addresses */
810         int write_num = __bnx2x_get_page_write_num(bp);
811         /* read addresses info */
812         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
813         /* number of read addresses */
814         int read_num = __bnx2x_get_page_read_num(bp);
815         uint32_t addr, size;
816
817         for (i = 0; i < num_pages; i++) {
818                 for (j = 0; j < write_num; j++) {
819                         REG_WR(bp, write_addr[j], page_addr[i]);
820
821                         for (k = 0; k < read_num; k++) {
822                                 if (IS_REG_IN_PRESET(read_addr[k].presets,
823                                                      preset)) {
824                                         size = read_addr[k].size;
825                                         for (n = 0; n < size; n++) {
826                                                 addr = read_addr[k].addr + n*4;
827                                                 *p++ = REG_RD(bp, addr);
828                                         }
829                                 }
830                         }
831                 }
832         }
833 }
834
835 static int __bnx2x_get_preset_regs(struct bnx2x *bp, uint32_t *p,
836                                    uint32_t preset)
837 {
838         uint32_t i, j, addr;
839         const struct wreg_addr *wreg_addr_p = NULL;
840
841         if (CHIP_IS_E1(bp))
842                 wreg_addr_p = &wreg_addr_e1;
843         else if (CHIP_IS_E1H(bp))
844                 wreg_addr_p = &wreg_addr_e1h;
845         else if (CHIP_IS_E2(bp))
846                 wreg_addr_p = &wreg_addr_e2;
847         else if (CHIP_IS_E3A0(bp))
848                 wreg_addr_p = &wreg_addr_e3;
849         else if (CHIP_IS_E3B0(bp))
850                 wreg_addr_p = &wreg_addr_e3b0;
851
852         /* Read the idle_chk registers */
853         for (i = 0; i < IDLE_REGS_COUNT; i++) {
854                 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
855                     IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
856                         for (j = 0; j < idle_reg_addrs[i].size; j++)
857                                 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
858                 }
859         }
860
861         /* Read the regular registers */
862         for (i = 0; i < REGS_COUNT; i++) {
863                 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
864                     IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
865                         for (j = 0; j < reg_addrs[i].size; j++)
866                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
867                 }
868         }
869
870         /* Read the CAM registers */
871         if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
872             IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
873                 for (i = 0; i < wreg_addr_p->size; i++) {
874                         *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
875
876                         /* In case of wreg_addr register, read additional
877                            registers from read_regs array
878                         */
879                         for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
880                                 addr = *(wreg_addr_p->read_regs);
881                                 *p++ = REG_RD(bp, addr + j*4);
882                         }
883                 }
884         }
885
886         /* Paged registers are supported in E2 & E3 only */
887         if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
888                 /* Read "paged" registers */
889                 bnx2x_read_pages_regs(bp, p, preset);
890         }
891
892         return 0;
893 }
894
895 static void __bnx2x_get_regs(struct bnx2x *bp, uint32_t *p)
896 {
897         uint32_t preset_idx;
898
899         /* Read all registers, by reading all preset registers */
900         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
901                 /* Skip presets with IOR */
902                 if ((preset_idx == 2) ||
903                     (preset_idx == 5) ||
904                     (preset_idx == 8) ||
905                     (preset_idx == 11))
906                         continue;
907                 __bnx2x_get_preset_regs(bp, p, preset_idx);
908                 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
909         }
910 }
911
912 static void bnx2x_get_regs(struct ether *dev,
913                            struct ethtool_regs *regs, void *_p)
914 {
915         uint32_t *p = _p;
916         struct bnx2x *bp = netdev_priv(dev);
917         struct dump_header dump_hdr = {0};
918
919         regs->version = 2;
920         memset(p, 0, regs->len);
921
922         if (!netif_running(bp->dev))
923                 return;
924
925         /* Disable parity attentions as long as following dump may
926          * cause false alarms by reading never written registers. We
927          * will re-enable parity attentions right after the dump.
928          */
929
930         bnx2x_disable_blocks_parity(bp);
931
932         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
933         dump_hdr.preset = DUMP_ALL_PRESETS;
934         dump_hdr.version = BNX2X_DUMP_VERSION;
935
936         /* dump_meta_data presents OR of CHIP and PATH. */
937         if (CHIP_IS_E1(bp)) {
938                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
939         } else if (CHIP_IS_E1H(bp)) {
940                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
941         } else if (CHIP_IS_E2(bp)) {
942                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
943                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
944         } else if (CHIP_IS_E3A0(bp)) {
945                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
946                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
947         } else if (CHIP_IS_E3B0(bp)) {
948                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
949                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
950         }
951
952         memcpy(p, &dump_hdr, sizeof(struct dump_header));
953         p += dump_hdr.header_size + 1;
954
955         /* Actually read the registers */
956         __bnx2x_get_regs(bp, p);
957
958         /* Re-enable parity attentions */
959         bnx2x_clear_blocks_parity(bp);
960         bnx2x_enable_blocks_parity(bp);
961 }
962
963 static int bnx2x_get_preset_regs_len(struct ether *dev, uint32_t preset)
964 {
965         struct bnx2x *bp = netdev_priv(dev);
966         int regdump_len = 0;
967
968         regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
969         regdump_len *= 4;
970         regdump_len += sizeof(struct dump_header);
971
972         return regdump_len;
973 }
974
975 static int bnx2x_set_dump(struct ether *dev, struct ethtool_dump *val)
976 {
977         struct bnx2x *bp = netdev_priv(dev);
978
979         /* Use the ethtool_dump "flag" field as the dump preset index */
980         if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
981                 return -EINVAL;
982
983         bp->dump_preset_idx = val->flag;
984         return 0;
985 }
986
987 static int bnx2x_get_dump_flag(struct ether *dev,
988                                struct ethtool_dump *dump)
989 {
990         struct bnx2x *bp = netdev_priv(dev);
991
992         dump->version = BNX2X_DUMP_VERSION;
993         dump->flag = bp->dump_preset_idx;
994         /* Calculate the requested preset idx length */
995         dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
996         DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
997            bp->dump_preset_idx, dump->len);
998         return 0;
999 }
1000
1001 static int bnx2x_get_dump_data(struct ether *dev,
1002                                struct ethtool_dump *dump,
1003                                void *buffer)
1004 {
1005         uint32_t *p = buffer;
1006         struct bnx2x *bp = netdev_priv(dev);
1007         struct dump_header dump_hdr = {0};
1008
1009         /* Disable parity attentions as long as following dump may
1010          * cause false alarms by reading never written registers. We
1011          * will re-enable parity attentions right after the dump.
1012          */
1013
1014         bnx2x_disable_blocks_parity(bp);
1015
1016         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1017         dump_hdr.preset = bp->dump_preset_idx;
1018         dump_hdr.version = BNX2X_DUMP_VERSION;
1019
1020         DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1021
1022         /* dump_meta_data presents OR of CHIP and PATH. */
1023         if (CHIP_IS_E1(bp)) {
1024                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1025         } else if (CHIP_IS_E1H(bp)) {
1026                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1027         } else if (CHIP_IS_E2(bp)) {
1028                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1029                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1030         } else if (CHIP_IS_E3A0(bp)) {
1031                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1032                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1033         } else if (CHIP_IS_E3B0(bp)) {
1034                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1035                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1036         }
1037
1038         memcpy(p, &dump_hdr, sizeof(struct dump_header));
1039         p += dump_hdr.header_size + 1;
1040
1041         /* Actually read the registers */
1042         __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1043
1044         /* Re-enable parity attentions */
1045         bnx2x_clear_blocks_parity(bp);
1046         bnx2x_enable_blocks_parity(bp);
1047
1048         return 0;
1049 }
1050
1051 static void bnx2x_get_drvinfo(struct ether *dev,
1052                               struct ethtool_drvinfo *info)
1053 {
1054 panic("Not implemented");
1055 #if 0 // AKAROS_PORT
1056         struct bnx2x *bp = netdev_priv(dev);
1057
1058         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1059         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1060
1061         bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1062
1063         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1064         info->n_stats = BNX2X_NUM_STATS;
1065         info->testinfo_len = BNX2X_NUM_TESTS(bp);
1066         info->eedump_len = bp->common.flash_size;
1067         info->regdump_len = bnx2x_get_regs_len(dev);
1068 #endif
1069 }
1070
1071 static void bnx2x_get_wol(struct ether *dev, struct ethtool_wolinfo *wol)
1072 {
1073         struct bnx2x *bp = netdev_priv(dev);
1074
1075         if (bp->flags & NO_WOL_FLAG) {
1076                 wol->supported = 0;
1077                 wol->wolopts = 0;
1078         } else {
1079                 wol->supported = WAKE_MAGIC;
1080                 if (bp->wol)
1081                         wol->wolopts = WAKE_MAGIC;
1082                 else
1083                         wol->wolopts = 0;
1084         }
1085         memset(&wol->sopass, 0, sizeof(wol->sopass));
1086 }
1087
1088 static int bnx2x_set_wol(struct ether *dev, struct ethtool_wolinfo *wol)
1089 {
1090         struct bnx2x *bp = netdev_priv(dev);
1091
1092         if (wol->wolopts & ~WAKE_MAGIC) {
1093                 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1094                 return -EINVAL;
1095         }
1096
1097         if (wol->wolopts & WAKE_MAGIC) {
1098                 if (bp->flags & NO_WOL_FLAG) {
1099                         DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1100                         return -EINVAL;
1101                 }
1102                 bp->wol = 1;
1103         } else
1104                 bp->wol = 0;
1105
1106         return 0;
1107 }
1108
1109 static uint32_t bnx2x_get_msglevel(struct ether *dev)
1110 {
1111         struct bnx2x *bp = netdev_priv(dev);
1112
1113         return bp->msg_enable;
1114 }
1115
1116 static void bnx2x_set_msglevel(struct ether *dev, uint32_t level)
1117 {
1118         struct bnx2x *bp = netdev_priv(dev);
1119
1120         if (capable(CAP_NET_ADMIN)) {
1121                 /* dump MCP trace */
1122                 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1123                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
1124                 bp->msg_enable = level;
1125         }
1126 }
1127
1128 static int bnx2x_nway_reset(struct ether *dev)
1129 {
1130         struct bnx2x *bp = netdev_priv(dev);
1131
1132         if (!bp->port.pmf)
1133                 return 0;
1134
1135         if (netif_running(dev)) {
1136                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1137                 bnx2x_force_link_reset(bp);
1138                 bnx2x_link_set(bp);
1139         }
1140
1141         return 0;
1142 }
1143
1144 static uint32_t bnx2x_get_link(struct ether *dev)
1145 {
1146         struct bnx2x *bp = netdev_priv(dev);
1147
1148         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1149                 return 0;
1150
1151         if (IS_VF(bp))
1152                 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1153                                  &bp->vf_link_vars.link_report_flags);
1154
1155         return bp->link_vars.link_up;
1156 }
1157
1158 static int bnx2x_get_eeprom_len(struct ether *dev)
1159 {
1160         struct bnx2x *bp = netdev_priv(dev);
1161
1162         return bp->common.flash_size;
1163 }
1164
1165 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1166  * had we done things the other way around, if two pfs from the same port would
1167  * attempt to access nvram at the same time, we could run into a scenario such
1168  * as:
1169  * pf A takes the port lock.
1170  * pf B succeeds in taking the same lock since they are from the same port.
1171  * pf A takes the per pf misc lock. Performs eeprom access.
1172  * pf A finishes. Unlocks the per pf misc lock.
1173  * Pf B takes the lock and proceeds to perform it's own access.
1174  * pf A unlocks the per port lock, while pf B is still working (!).
1175  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1176  * access corrupted by pf B)
1177  */
1178 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1179 {
1180         int port = BP_PORT(bp);
1181         int count, i;
1182         uint32_t val;
1183
1184         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1185         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1186
1187         /* adjust timeout for emulation/FPGA */
1188         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1189         if (CHIP_REV_IS_SLOW(bp))
1190                 count *= 100;
1191
1192         /* request access to nvram interface */
1193         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1194                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1195
1196         for (i = 0; i < count*10; i++) {
1197                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1198                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1199                         break;
1200
1201                 udelay(5);
1202         }
1203
1204         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1205                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1206                    "cannot get access to nvram interface\n");
1207                 return -EBUSY;
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1214 {
1215         int port = BP_PORT(bp);
1216         int count, i;
1217         uint32_t val;
1218
1219         /* adjust timeout for emulation/FPGA */
1220         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1221         if (CHIP_REV_IS_SLOW(bp))
1222                 count *= 100;
1223
1224         /* relinquish nvram interface */
1225         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1226                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1227
1228         for (i = 0; i < count*10; i++) {
1229                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1230                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1231                         break;
1232
1233                 udelay(5);
1234         }
1235
1236         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1237                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1238                    "cannot free access to nvram interface\n");
1239                 return -EBUSY;
1240         }
1241
1242         /* release HW lock: protect against other PFs in PF Direct Assignment */
1243         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1244         return 0;
1245 }
1246
1247 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1248 {
1249         uint32_t val;
1250
1251         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1252
1253         /* enable both bits, even on read */
1254         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1255                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1256                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1257 }
1258
1259 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1260 {
1261         uint32_t val;
1262
1263         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1264
1265         /* disable both bits, even after read */
1266         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1267                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1268                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1269 }
1270
1271 static int bnx2x_nvram_read_dword(struct bnx2x *bp, uint32_t offset,
1272                                   __be32 *ret_val,
1273                                   uint32_t cmd_flags)
1274 {
1275         int count, i, rc;
1276         uint32_t val;
1277
1278         /* build the command word */
1279         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1280
1281         /* need to clear DONE bit separately */
1282         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1283
1284         /* address of the NVRAM to read from */
1285         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1286                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1287
1288         /* issue a read command */
1289         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1290
1291         /* adjust timeout for emulation/FPGA */
1292         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1293         if (CHIP_REV_IS_SLOW(bp))
1294                 count *= 100;
1295
1296         /* wait for completion */
1297         *ret_val = 0;
1298         rc = -EBUSY;
1299         for (i = 0; i < count; i++) {
1300                 udelay(5);
1301                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1302
1303                 if (val & MCPR_NVM_COMMAND_DONE) {
1304                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1305                         /* we read nvram data in cpu order
1306                          * but ethtool sees it as an array of bytes
1307                          * converting to big-endian will do the work
1308                          */
1309                         *ret_val = cpu_to_be32(val);
1310                         rc = 0;
1311                         break;
1312                 }
1313         }
1314         if (rc == -EBUSY)
1315                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1316                    "nvram read timeout expired\n");
1317         return rc;
1318 }
1319
1320 static int bnx2x_nvram_read(struct bnx2x *bp, uint32_t offset,
1321                             uint8_t *ret_buf,
1322                             int buf_size)
1323 {
1324         int rc;
1325         uint32_t cmd_flags;
1326         __be32 val;
1327
1328         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1329                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1330                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1331                    offset, buf_size);
1332                 return -EINVAL;
1333         }
1334
1335         if (offset + buf_size > bp->common.flash_size) {
1336                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1337                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1338                    offset, buf_size, bp->common.flash_size);
1339                 return -EINVAL;
1340         }
1341
1342         /* request access to nvram interface */
1343         rc = bnx2x_acquire_nvram_lock(bp);
1344         if (rc)
1345                 return rc;
1346
1347         /* enable access to nvram interface */
1348         bnx2x_enable_nvram_access(bp);
1349
1350         /* read the first word(s) */
1351         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1352         while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
1353                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1354                 memcpy(ret_buf, &val, 4);
1355
1356                 /* advance to the next dword */
1357                 offset += sizeof(uint32_t);
1358                 ret_buf += sizeof(uint32_t);
1359                 buf_size -= sizeof(uint32_t);
1360                 cmd_flags = 0;
1361         }
1362
1363         if (rc == 0) {
1364                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1365                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1366                 memcpy(ret_buf, &val, 4);
1367         }
1368
1369         /* disable access to nvram interface */
1370         bnx2x_disable_nvram_access(bp);
1371         bnx2x_release_nvram_lock(bp);
1372
1373         return rc;
1374 }
1375
1376 static int bnx2x_nvram_read32(struct bnx2x *bp, uint32_t offset,
1377                               uint32_t *buf,
1378                               int buf_size)
1379 {
1380         int rc;
1381
1382         rc = bnx2x_nvram_read(bp, offset, (uint8_t *)buf, buf_size);
1383
1384         if (!rc) {
1385                 __be32 *be = (__be32 *)buf;
1386
1387                 while ((buf_size -= 4) >= 0)
1388                         *buf++ = be32_to_cpu(*be++);
1389         }
1390
1391         return rc;
1392 }
1393
1394 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1395 {
1396 panic("Not implemented");
1397 #if 0 // AKAROS_PORT
1398         int rc = 1;
1399         uint16_t pm = 0;
1400         struct ether *dev = pci_get_drvdata(bp->pdev);
1401
1402         if (bp->pdev->pm_cap)
1403                 rc = pci_read_config_word(bp->pdev,
1404                                           bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1405
1406         if ((rc && !netif_running(dev)) ||
1407             (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force uint16_t)PCI_D0)))
1408                 return false;
1409
1410         return true;
1411 #endif
1412 }
1413
1414 static int bnx2x_get_eeprom(struct ether *dev,
1415                             struct ethtool_eeprom *eeprom, uint8_t *eebuf)
1416 {
1417         struct bnx2x *bp = netdev_priv(dev);
1418
1419         if (!bnx2x_is_nvm_accessible(bp)) {
1420                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1421                    "cannot access eeprom when the interface is down\n");
1422                 return -EAGAIN;
1423         }
1424
1425         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1426            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1427            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1428            eeprom->len, eeprom->len);
1429
1430         /* parameters already validated in ethtool_get_eeprom */
1431
1432         return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1433 }
1434
1435 static int bnx2x_get_module_eeprom(struct ether *dev,
1436                                    struct ethtool_eeprom *ee,
1437                                    uint8_t *data)
1438 {
1439         struct bnx2x *bp = netdev_priv(dev);
1440         int rc = -EINVAL, phy_idx;
1441         uint8_t *user_data = data;
1442         unsigned int start_addr = ee->offset, xfer_size = 0;
1443
1444         if (!bnx2x_is_nvm_accessible(bp)) {
1445                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1446                    "cannot access eeprom when the interface is down\n");
1447                 return -EAGAIN;
1448         }
1449
1450         phy_idx = bnx2x_get_cur_phy_idx(bp);
1451
1452         /* Read A0 section */
1453         if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1454                 /* Limit transfer size to the A0 section boundary */
1455                 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1456                         xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1457                 else
1458                         xfer_size = ee->len;
1459                 bnx2x_acquire_phy_lock(bp);
1460                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1461                                                   &bp->link_params,
1462                                                   I2C_DEV_ADDR_A0,
1463                                                   start_addr,
1464                                                   xfer_size,
1465                                                   user_data);
1466                 bnx2x_release_phy_lock(bp);
1467                 if (rc) {
1468                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1469
1470                         return -EINVAL;
1471                 }
1472                 user_data += xfer_size;
1473                 start_addr += xfer_size;
1474         }
1475
1476         /* Read A2 section */
1477         if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1478             (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1479                 xfer_size = ee->len - xfer_size;
1480                 /* Limit transfer size to the A2 section boundary */
1481                 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1482                         xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1483                 start_addr -= ETH_MODULE_SFF_8079_LEN;
1484                 bnx2x_acquire_phy_lock(bp);
1485                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1486                                                   &bp->link_params,
1487                                                   I2C_DEV_ADDR_A2,
1488                                                   start_addr,
1489                                                   xfer_size,
1490                                                   user_data);
1491                 bnx2x_release_phy_lock(bp);
1492                 if (rc) {
1493                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1494                         return -EINVAL;
1495                 }
1496         }
1497         return rc;
1498 }
1499
1500 static int bnx2x_get_module_info(struct ether *dev,
1501                                  struct ethtool_modinfo *modinfo)
1502 {
1503         struct bnx2x *bp = netdev_priv(dev);
1504         int phy_idx, rc;
1505         uint8_t sff8472_comp, diag_type;
1506
1507         if (!bnx2x_is_nvm_accessible(bp)) {
1508                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1509                    "cannot access eeprom when the interface is down\n");
1510                 return -EAGAIN;
1511         }
1512         phy_idx = bnx2x_get_cur_phy_idx(bp);
1513         bnx2x_acquire_phy_lock(bp);
1514         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1515                                           &bp->link_params,
1516                                           I2C_DEV_ADDR_A0,
1517                                           SFP_EEPROM_SFF_8472_COMP_ADDR,
1518                                           SFP_EEPROM_SFF_8472_COMP_SIZE,
1519                                           &sff8472_comp);
1520         bnx2x_release_phy_lock(bp);
1521         if (rc) {
1522                 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1523                 return -EINVAL;
1524         }
1525
1526         bnx2x_acquire_phy_lock(bp);
1527         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1528                                           &bp->link_params,
1529                                           I2C_DEV_ADDR_A0,
1530                                           SFP_EEPROM_DIAG_TYPE_ADDR,
1531                                           SFP_EEPROM_DIAG_TYPE_SIZE,
1532                                           &diag_type);
1533         bnx2x_release_phy_lock(bp);
1534         if (rc) {
1535                 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1536                 return -EINVAL;
1537         }
1538
1539         if (!sff8472_comp ||
1540             (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1541                 modinfo->type = ETH_MODULE_SFF_8079;
1542                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1543         } else {
1544                 modinfo->type = ETH_MODULE_SFF_8472;
1545                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1546         }
1547         return 0;
1548 }
1549
1550 static int bnx2x_nvram_write_dword(struct bnx2x *bp, uint32_t offset,
1551                                    uint32_t val,
1552                                    uint32_t cmd_flags)
1553 {
1554         int count, i, rc;
1555
1556         /* build the command word */
1557         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1558
1559         /* need to clear DONE bit separately */
1560         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1561
1562         /* write the data */
1563         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1564
1565         /* address of the NVRAM to write to */
1566         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1567                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1568
1569         /* issue the write command */
1570         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1571
1572         /* adjust timeout for emulation/FPGA */
1573         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1574         if (CHIP_REV_IS_SLOW(bp))
1575                 count *= 100;
1576
1577         /* wait for completion */
1578         rc = -EBUSY;
1579         for (i = 0; i < count; i++) {
1580                 udelay(5);
1581                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1582                 if (val & MCPR_NVM_COMMAND_DONE) {
1583                         rc = 0;
1584                         break;
1585                 }
1586         }
1587
1588         if (rc == -EBUSY)
1589                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1590                    "nvram write timeout expired\n");
1591         return rc;
1592 }
1593
1594 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1595
1596 static int bnx2x_nvram_write1(struct bnx2x *bp, uint32_t offset,
1597                               uint8_t *data_buf,
1598                               int buf_size)
1599 {
1600         int rc;
1601         uint32_t cmd_flags, align_offset, val;
1602         __be32 val_be;
1603
1604         if (offset + buf_size > bp->common.flash_size) {
1605                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1606                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1607                    offset, buf_size, bp->common.flash_size);
1608                 return -EINVAL;
1609         }
1610
1611         /* request access to nvram interface */
1612         rc = bnx2x_acquire_nvram_lock(bp);
1613         if (rc)
1614                 return rc;
1615
1616         /* enable access to nvram interface */
1617         bnx2x_enable_nvram_access(bp);
1618
1619         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1620         align_offset = (offset & ~0x03);
1621         rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1622
1623         if (rc == 0) {
1624                 /* nvram data is returned as an array of bytes
1625                  * convert it back to cpu order
1626                  */
1627                 val = be32_to_cpu(val_be);
1628
1629                 val &= ~le32_to_cpu((__force __le32)
1630                                     (0xff << BYTE_OFFSET(offset)));
1631                 val |= le32_to_cpu((__force __le32)
1632                                    (*data_buf << BYTE_OFFSET(offset)));
1633
1634                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1635                                              cmd_flags);
1636         }
1637
1638         /* disable access to nvram interface */
1639         bnx2x_disable_nvram_access(bp);
1640         bnx2x_release_nvram_lock(bp);
1641
1642         return rc;
1643 }
1644
1645 static int bnx2x_nvram_write(struct bnx2x *bp, uint32_t offset,
1646                              uint8_t *data_buf,
1647                              int buf_size)
1648 {
1649         int rc;
1650         uint32_t cmd_flags;
1651         uint32_t val;
1652         uint32_t written_so_far;
1653
1654         if (buf_size == 1)      /* ethtool */
1655                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1656
1657         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1658                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1659                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1660                    offset, buf_size);
1661                 return -EINVAL;
1662         }
1663
1664         if (offset + buf_size > bp->common.flash_size) {
1665                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1666                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1667                    offset, buf_size, bp->common.flash_size);
1668                 return -EINVAL;
1669         }
1670
1671         /* request access to nvram interface */
1672         rc = bnx2x_acquire_nvram_lock(bp);
1673         if (rc)
1674                 return rc;
1675
1676         /* enable access to nvram interface */
1677         bnx2x_enable_nvram_access(bp);
1678
1679         written_so_far = 0;
1680         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1681         while ((written_so_far < buf_size) && (rc == 0)) {
1682                 if (written_so_far == (buf_size - sizeof(uint32_t)))
1683                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1684                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1685                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1686                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1687                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1688
1689                 memcpy(&val, data_buf, 4);
1690
1691                 /* Notice unlike bnx2x_nvram_read_dword() this will not
1692                  * change val using be32_to_cpu(), which causes data to flip
1693                  * if the eeprom is read and then written back. This is due
1694                  * to tools utilizing this functionality that would break
1695                  * if this would be resolved.
1696                  */
1697                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1698
1699                 /* advance to the next dword */
1700                 offset += sizeof(uint32_t);
1701                 data_buf += sizeof(uint32_t);
1702                 written_so_far += sizeof(uint32_t);
1703                 cmd_flags = 0;
1704         }
1705
1706         /* disable access to nvram interface */
1707         bnx2x_disable_nvram_access(bp);
1708         bnx2x_release_nvram_lock(bp);
1709
1710         return rc;
1711 }
1712
1713 static int bnx2x_set_eeprom(struct ether *dev,
1714                             struct ethtool_eeprom *eeprom, uint8_t *eebuf)
1715 {
1716         struct bnx2x *bp = netdev_priv(dev);
1717         int port = BP_PORT(bp);
1718         int rc = 0;
1719         uint32_t ext_phy_config;
1720
1721         if (!bnx2x_is_nvm_accessible(bp)) {
1722                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1723                    "cannot access eeprom when the interface is down\n");
1724                 return -EAGAIN;
1725         }
1726
1727         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1728            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1729            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1730            eeprom->len, eeprom->len);
1731
1732         /* parameters already validated in ethtool_set_eeprom */
1733
1734         /* PHY eeprom can be accessed only by the PMF */
1735         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1736             !bp->port.pmf) {
1737                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1738                    "wrong magic or interface is not pmf\n");
1739                 return -EINVAL;
1740         }
1741
1742         ext_phy_config =
1743                 SHMEM_RD(bp,
1744                          dev_info.port_hw_config[port].external_phy_config);
1745
1746         if (eeprom->magic == 0x50485950) {
1747                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1748                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1749
1750                 bnx2x_acquire_phy_lock(bp);
1751                 rc |= bnx2x_link_reset(&bp->link_params,
1752                                        &bp->link_vars, 0);
1753                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1754                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1755                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1756                                        MISC_REGISTERS_GPIO_HIGH, port);
1757                 bnx2x_release_phy_lock(bp);
1758                 bnx2x_link_report(bp);
1759
1760         } else if (eeprom->magic == 0x50485952) {
1761                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1762                 if (bp->state == BNX2X_STATE_OPEN) {
1763                         bnx2x_acquire_phy_lock(bp);
1764                         rc |= bnx2x_link_reset(&bp->link_params,
1765                                                &bp->link_vars, 1);
1766
1767                         rc |= bnx2x_phy_init(&bp->link_params,
1768                                              &bp->link_vars);
1769                         bnx2x_release_phy_lock(bp);
1770                         bnx2x_calc_fc_adv(bp);
1771                 }
1772         } else if (eeprom->magic == 0x53985943) {
1773                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1774                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1775                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1776
1777                         /* DSP Remove Download Mode */
1778                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1779                                        MISC_REGISTERS_GPIO_LOW, port);
1780
1781                         bnx2x_acquire_phy_lock(bp);
1782
1783                         bnx2x_sfx7101_sp_sw_reset(bp,
1784                                                 &bp->link_params.phy[EXT_PHY1]);
1785
1786                         /* wait 0.5 sec to allow it to run */
1787                         kthread_usleep(1000 * 500);
1788                         bnx2x_ext_phy_hw_reset(bp, port);
1789                         kthread_usleep(1000 * 500);
1790                         bnx2x_release_phy_lock(bp);
1791                 }
1792         } else
1793                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1794
1795         return rc;
1796 }
1797
1798 static int bnx2x_get_coalesce(struct ether *dev,
1799                               struct ethtool_coalesce *coal)
1800 {
1801         struct bnx2x *bp = netdev_priv(dev);
1802
1803         memset(coal, 0, sizeof(struct ethtool_coalesce));
1804
1805         coal->rx_coalesce_usecs = bp->rx_ticks;
1806         coal->tx_coalesce_usecs = bp->tx_ticks;
1807
1808         return 0;
1809 }
1810
1811 static int bnx2x_set_coalesce(struct ether *dev,
1812                               struct ethtool_coalesce *coal)
1813 {
1814         struct bnx2x *bp = netdev_priv(dev);
1815
1816         bp->rx_ticks = (uint16_t)coal->rx_coalesce_usecs;
1817         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1818                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1819
1820         bp->tx_ticks = (uint16_t)coal->tx_coalesce_usecs;
1821         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1822                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1823
1824         if (netif_running(dev))
1825                 bnx2x_update_coalesce(bp);
1826
1827         return 0;
1828 }
1829
1830 static void bnx2x_get_ringparam(struct ether *dev,
1831                                 struct ethtool_ringparam *ering)
1832 {
1833         struct bnx2x *bp = netdev_priv(dev);
1834
1835         ering->rx_max_pending = MAX_RX_AVAIL;
1836
1837         if (bp->rx_ring_size)
1838                 ering->rx_pending = bp->rx_ring_size;
1839         else
1840                 ering->rx_pending = MAX_RX_AVAIL;
1841
1842         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1843         ering->tx_pending = bp->tx_ring_size;
1844 }
1845
1846 static int bnx2x_set_ringparam(struct ether *dev,
1847                                struct ethtool_ringparam *ering)
1848 {
1849         struct bnx2x *bp = netdev_priv(dev);
1850
1851         DP(BNX2X_MSG_ETHTOOL,
1852            "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1853            ering->rx_pending, ering->tx_pending);
1854
1855         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1856                 DP(BNX2X_MSG_ETHTOOL,
1857                    "Handling parity error recovery. Try again later\n");
1858                 return -EAGAIN;
1859         }
1860
1861         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1862             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1863                                                     MIN_RX_SIZE_TPA)) ||
1864             (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1865             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1866                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1867                 return -EINVAL;
1868         }
1869
1870         bp->rx_ring_size = ering->rx_pending;
1871         bp->tx_ring_size = ering->tx_pending;
1872
1873         return bnx2x_reload_if_running(dev);
1874 }
1875
1876 static void bnx2x_get_pauseparam(struct ether *dev,
1877                                  struct ethtool_pauseparam *epause)
1878 {
1879         struct bnx2x *bp = netdev_priv(dev);
1880         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1881         int cfg_reg;
1882
1883         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1884                            BNX2X_FLOW_CTRL_AUTO);
1885
1886         if (!epause->autoneg)
1887                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1888         else
1889                 cfg_reg = bp->link_params.req_fc_auto_adv;
1890
1891         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1892                             BNX2X_FLOW_CTRL_RX);
1893         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1894                             BNX2X_FLOW_CTRL_TX);
1895
1896         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1897            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1898            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1899 }
1900
1901 static int bnx2x_set_pauseparam(struct ether *dev,
1902                                 struct ethtool_pauseparam *epause)
1903 {
1904         struct bnx2x *bp = netdev_priv(dev);
1905         uint32_t cfg_idx = bnx2x_get_link_cfg_idx(bp);
1906         if (IS_MF(bp))
1907                 return 0;
1908
1909         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1910            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1911            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1912
1913         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1914
1915         if (epause->rx_pause)
1916                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1917
1918         if (epause->tx_pause)
1919                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1920
1921         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1922                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1923
1924         if (epause->autoneg) {
1925                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1926                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1927                         return -EINVAL;
1928                 }
1929
1930                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1931                         bp->link_params.req_flow_ctrl[cfg_idx] =
1932                                 BNX2X_FLOW_CTRL_AUTO;
1933                 }
1934                 bp->link_params.req_fc_auto_adv = 0;
1935                 if (epause->rx_pause)
1936                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1937
1938                 if (epause->tx_pause)
1939                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1940
1941                 if (!bp->link_params.req_fc_auto_adv)
1942                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1943         }
1944
1945         DP(BNX2X_MSG_ETHTOOL,
1946            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1947
1948         if (netif_running(dev)) {
1949                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1950                 bnx2x_link_set(bp);
1951         }
1952
1953         return 0;
1954 }
1955
1956 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1957         "register_test (offline)    ",
1958         "memory_test (offline)      ",
1959         "int_loopback_test (offline)",
1960         "ext_loopback_test (offline)",
1961         "nvram_test (online)        ",
1962         "interrupt_test (online)    ",
1963         "link_test (online)         "
1964 };
1965
1966 enum {
1967         BNX2X_PRI_FLAG_ISCSI,
1968         BNX2X_PRI_FLAG_FCOE,
1969         BNX2X_PRI_FLAG_STORAGE,
1970         BNX2X_PRI_FLAG_LEN,
1971 };
1972
1973 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
1974         "iSCSI offload support",
1975         "FCoE offload support",
1976         "Storage only interface"
1977 };
1978
1979 static uint32_t bnx2x_eee_to_adv(uint32_t eee_adv)
1980 {
1981         uint32_t modes = 0;
1982
1983         if (eee_adv & SHMEM_EEE_100M_ADV)
1984                 modes |= ADVERTISED_100baseT_Full;
1985         if (eee_adv & SHMEM_EEE_1G_ADV)
1986                 modes |= ADVERTISED_1000baseT_Full;
1987         if (eee_adv & SHMEM_EEE_10G_ADV)
1988                 modes |= ADVERTISED_10000baseT_Full;
1989
1990         return modes;
1991 }
1992
1993 static uint32_t bnx2x_adv_to_eee(uint32_t modes, uint32_t shift)
1994 {
1995         uint32_t eee_adv = 0;
1996         if (modes & ADVERTISED_100baseT_Full)
1997                 eee_adv |= SHMEM_EEE_100M_ADV;
1998         if (modes & ADVERTISED_1000baseT_Full)
1999                 eee_adv |= SHMEM_EEE_1G_ADV;
2000         if (modes & ADVERTISED_10000baseT_Full)
2001                 eee_adv |= SHMEM_EEE_10G_ADV;
2002
2003         return eee_adv << shift;
2004 }
2005
2006 static int bnx2x_get_eee(struct ether *dev, struct ethtool_eee *edata)
2007 {
2008         struct bnx2x *bp = netdev_priv(dev);
2009         uint32_t eee_cfg;
2010
2011         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2012                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2013                 return -EOPNOTSUPP;
2014         }
2015
2016         eee_cfg = bp->link_vars.eee_status;
2017
2018         edata->supported =
2019                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2020                                  SHMEM_EEE_SUPPORTED_SHIFT);
2021
2022         edata->advertised =
2023                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2024                                  SHMEM_EEE_ADV_STATUS_SHIFT);
2025         edata->lp_advertised =
2026                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2027                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2028
2029         /* SHMEM value is in 16u units --> Convert to 1u units. */
2030         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2031
2032         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
2033         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
2034         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2035
2036         return 0;
2037 }
2038
2039 static int bnx2x_set_eee(struct ether *dev, struct ethtool_eee *edata)
2040 {
2041         struct bnx2x *bp = netdev_priv(dev);
2042         uint32_t eee_cfg;
2043         uint32_t advertised;
2044
2045         if (IS_MF(bp))
2046                 return 0;
2047
2048         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2049                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2050                 return -EOPNOTSUPP;
2051         }
2052
2053         eee_cfg = bp->link_vars.eee_status;
2054
2055         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2056                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2057                 return -EOPNOTSUPP;
2058         }
2059
2060         advertised = bnx2x_adv_to_eee(edata->advertised,
2061                                       SHMEM_EEE_ADV_STATUS_SHIFT);
2062         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2063                 DP(BNX2X_MSG_ETHTOOL,
2064                    "Direct manipulation of EEE advertisement is not supported\n");
2065                 return -EINVAL;
2066         }
2067
2068         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2069                 DP(BNX2X_MSG_ETHTOOL,
2070                    "Maximal Tx Lpi timer supported is %x(u)\n",
2071                    EEE_MODE_TIMER_MASK);
2072                 return -EINVAL;
2073         }
2074         if (edata->tx_lpi_enabled &&
2075             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2076                 DP(BNX2X_MSG_ETHTOOL,
2077                    "Minimal Tx Lpi timer supported is %d(u)\n",
2078                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2079                 return -EINVAL;
2080         }
2081
2082         /* All is well; Apply changes*/
2083         if (edata->eee_enabled)
2084                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2085         else
2086                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2087
2088         if (edata->tx_lpi_enabled)
2089                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2090         else
2091                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2092
2093         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2094         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2095                                     EEE_MODE_TIMER_MASK) |
2096                                     EEE_MODE_OVERRIDE_NVRAM |
2097                                     EEE_MODE_OUTPUT_TIME;
2098
2099         /* Restart link to propagate changes */
2100         if (netif_running(dev)) {
2101                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2102                 bnx2x_force_link_reset(bp);
2103                 bnx2x_link_set(bp);
2104         }
2105
2106         return 0;
2107 }
2108
2109 enum {
2110         BNX2X_CHIP_E1_OFST = 0,
2111         BNX2X_CHIP_E1H_OFST,
2112         BNX2X_CHIP_E2_OFST,
2113         BNX2X_CHIP_E3_OFST,
2114         BNX2X_CHIP_E3B0_OFST,
2115         BNX2X_CHIP_MAX_OFST
2116 };
2117
2118 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
2119 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
2120 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
2121 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
2122 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
2123
2124 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2125 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2126
2127 static int bnx2x_test_registers(struct bnx2x *bp)
2128 {
2129         int idx, i, rc = -ENODEV;
2130         uint32_t wr_val = 0, hw;
2131         int port = BP_PORT(bp);
2132         static const struct {
2133                 uint32_t hw;
2134                 uint32_t offset0;
2135                 uint32_t offset1;
2136                 uint32_t mask;
2137         } reg_tbl[] = {
2138 /* 0 */         { BNX2X_CHIP_MASK_ALL,
2139                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2140                 { BNX2X_CHIP_MASK_ALL,
2141                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2142                 { BNX2X_CHIP_MASK_E1X,
2143                         HC_REG_AGG_INT_0,               4, 0x000003ff },
2144                 { BNX2X_CHIP_MASK_ALL,
2145                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2146                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2147                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2148                 { BNX2X_CHIP_MASK_E3B0,
2149                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2150                 { BNX2X_CHIP_MASK_ALL,
2151                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2152                 { BNX2X_CHIP_MASK_ALL,
2153                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2154                 { BNX2X_CHIP_MASK_ALL,
2155                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2156                 { BNX2X_CHIP_MASK_ALL,
2157                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2158 /* 10 */        { BNX2X_CHIP_MASK_ALL,
2159                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2160                 { BNX2X_CHIP_MASK_ALL,
2161                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2162                 { BNX2X_CHIP_MASK_ALL,
2163                         QM_REG_CONNNUM_0,               4, 0x000fffff },
2164                 { BNX2X_CHIP_MASK_ALL,
2165                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2166                 { BNX2X_CHIP_MASK_ALL,
2167                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2168                 { BNX2X_CHIP_MASK_ALL,
2169                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2170                 { BNX2X_CHIP_MASK_ALL,
2171                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2172                 { BNX2X_CHIP_MASK_ALL,
2173                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2174                 { BNX2X_CHIP_MASK_ALL,
2175                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2176                 { BNX2X_CHIP_MASK_ALL,
2177                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2178 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2179                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2180                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2181                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2182                 { BNX2X_CHIP_MASK_ALL,
2183                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2184                 { BNX2X_CHIP_MASK_ALL,
2185                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2186                 { BNX2X_CHIP_MASK_ALL,
2187                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2188                 { BNX2X_CHIP_MASK_ALL,
2189                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2190                 { BNX2X_CHIP_MASK_ALL,
2191                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2192                 { BNX2X_CHIP_MASK_ALL,
2193                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2194                 { BNX2X_CHIP_MASK_ALL,
2195                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2196                 { BNX2X_CHIP_MASK_ALL,
2197                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2198 /* 30 */        { BNX2X_CHIP_MASK_ALL,
2199                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2200                 { BNX2X_CHIP_MASK_ALL,
2201                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2202                 { BNX2X_CHIP_MASK_ALL,
2203                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2204                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2205                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2206                 { BNX2X_CHIP_MASK_ALL,
2207                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2208                 { BNX2X_CHIP_MASK_ALL,
2209                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2210                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2211                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2212                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2213                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2214
2215                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2216         };
2217
2218         if (!bnx2x_is_nvm_accessible(bp)) {
2219                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2220                    "cannot access eeprom when the interface is down\n");
2221                 return rc;
2222         }
2223
2224         if (CHIP_IS_E1(bp))
2225                 hw = BNX2X_CHIP_MASK_E1;
2226         else if (CHIP_IS_E1H(bp))
2227                 hw = BNX2X_CHIP_MASK_E1H;
2228         else if (CHIP_IS_E2(bp))
2229                 hw = BNX2X_CHIP_MASK_E2;
2230         else if (CHIP_IS_E3B0(bp))
2231                 hw = BNX2X_CHIP_MASK_E3B0;
2232         else /* e3 A0 */
2233                 hw = BNX2X_CHIP_MASK_E3;
2234
2235         /* Repeat the test twice:
2236          * First by writing 0x00000000, second by writing 0xffffffff
2237          */
2238         for (idx = 0; idx < 2; idx++) {
2239
2240                 switch (idx) {
2241                 case 0:
2242                         wr_val = 0;
2243                         break;
2244                 case 1:
2245                         wr_val = 0xffffffff;
2246                         break;
2247                 }
2248
2249                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2250                         uint32_t offset, mask, save_val, val;
2251                         if (!(hw & reg_tbl[i].hw))
2252                                 continue;
2253
2254                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2255                         mask = reg_tbl[i].mask;
2256
2257                         save_val = REG_RD(bp, offset);
2258
2259                         REG_WR(bp, offset, wr_val & mask);
2260
2261                         val = REG_RD(bp, offset);
2262
2263                         /* Restore the original register's value */
2264                         REG_WR(bp, offset, save_val);
2265
2266                         /* verify value is as expected */
2267                         if ((val & mask) != (wr_val & mask)) {
2268                                 DP(BNX2X_MSG_ETHTOOL,
2269                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2270                                    offset, val, wr_val, mask);
2271                                 goto test_reg_exit;
2272                         }
2273                 }
2274         }
2275
2276         rc = 0;
2277
2278 test_reg_exit:
2279         return rc;
2280 }
2281
2282 static int bnx2x_test_memory(struct bnx2x *bp)
2283 {
2284         int i, j, rc = -ENODEV;
2285         uint32_t val, index;
2286         static const struct {
2287                 uint32_t offset;
2288                 int size;
2289         } mem_tbl[] = {
2290                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2291                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2292                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2293                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2294                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2295                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2296                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2297
2298                 { 0xffffffff, 0 }
2299         };
2300
2301         static const struct {
2302                 char *name;
2303                 uint32_t offset;
2304                 uint32_t hw_mask[BNX2X_CHIP_MAX_OFST];
2305         } prty_tbl[] = {
2306                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2307                         {0x3ffc0, 0,   0, 0} },
2308                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2309                         {0x2,     0x2, 0, 0} },
2310                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2311                         {0,       0,   0, 0} },
2312                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2313                         {0x3ffc0, 0,   0, 0} },
2314                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2315                         {0x3ffc0, 0,   0, 0} },
2316                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2317                         {0x3ffc1, 0,   0, 0} },
2318
2319                 { NULL, 0xffffffff, {0, 0, 0, 0} }
2320         };
2321
2322         if (!bnx2x_is_nvm_accessible(bp)) {
2323                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2324                    "cannot access eeprom when the interface is down\n");
2325                 return rc;
2326         }
2327
2328         if (CHIP_IS_E1(bp))
2329                 index = BNX2X_CHIP_E1_OFST;
2330         else if (CHIP_IS_E1H(bp))
2331                 index = BNX2X_CHIP_E1H_OFST;
2332         else if (CHIP_IS_E2(bp))
2333                 index = BNX2X_CHIP_E2_OFST;
2334         else /* e3 */
2335                 index = BNX2X_CHIP_E3_OFST;
2336
2337         /* pre-Check the parity status */
2338         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2339                 val = REG_RD(bp, prty_tbl[i].offset);
2340                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2341                         DP(BNX2X_MSG_ETHTOOL,
2342                            "%s is 0x%x\n", prty_tbl[i].name, val);
2343                         goto test_mem_exit;
2344                 }
2345         }
2346
2347         /* Go through all the memories */
2348         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2349                 for (j = 0; j < mem_tbl[i].size; j++)
2350                         REG_RD(bp, mem_tbl[i].offset + j*4);
2351
2352         /* Check the parity status */
2353         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2354                 val = REG_RD(bp, prty_tbl[i].offset);
2355                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2356                         DP(BNX2X_MSG_ETHTOOL,
2357                            "%s is 0x%x\n", prty_tbl[i].name, val);
2358                         goto test_mem_exit;
2359                 }
2360         }
2361
2362         rc = 0;
2363
2364 test_mem_exit:
2365         return rc;
2366 }
2367
2368 static void bnx2x_wait_for_link(struct bnx2x *bp, uint8_t link_up,
2369                                 uint8_t is_serdes)
2370 {
2371         int cnt = 1400;
2372
2373         if (link_up) {
2374                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2375                         kthread_usleep(1000 * 20);
2376
2377                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2378                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2379
2380                 cnt = 1400;
2381                 while (!bp->link_vars.link_up && cnt--)
2382                         kthread_usleep(1000 * 20);
2383
2384                 if (cnt <= 0 && !bp->link_vars.link_up)
2385                         DP(BNX2X_MSG_ETHTOOL,
2386                            "Timeout waiting for link init\n");
2387         }
2388 }
2389
2390 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2391 {
2392 panic("Not implemented");
2393 #if 0 // AKAROS_PORT
2394         unsigned int pkt_size, num_pkts, i;
2395         struct sk_buff *skb;
2396         unsigned char *packet;
2397         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2398         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2399         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2400         uint16_t tx_start_idx, tx_idx;
2401         uint16_t rx_start_idx, rx_idx;
2402         uint16_t pkt_prod, bd_prod;
2403         struct sw_tx_bd *tx_buf;
2404         struct eth_tx_start_bd *tx_start_bd;
2405         dma_addr_t mapping;
2406         union eth_rx_cqe *cqe;
2407         uint8_t cqe_fp_flags, cqe_fp_type;
2408         struct sw_rx_bd *rx_buf;
2409         uint16_t len;
2410         int rc = -ENODEV;
2411         uint8_t *data;
2412         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2413                                                        txdata->txq_index);
2414
2415         /* check the loopback mode */
2416         switch (loopback_mode) {
2417         case BNX2X_PHY_LOOPBACK:
2418                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2419                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2420                         return -EINVAL;
2421                 }
2422                 break;
2423         case BNX2X_MAC_LOOPBACK:
2424                 if (CHIP_IS_E3(bp)) {
2425                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2426                         if (bp->port.supported[cfg_idx] &
2427                             (SUPPORTED_10000baseT_Full |
2428                              SUPPORTED_20000baseMLD2_Full |
2429                              SUPPORTED_20000baseKR2_Full))
2430                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2431                         else
2432                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2433                 } else
2434                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2435
2436                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2437                 break;
2438         case BNX2X_EXT_LOOPBACK:
2439                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2440                         DP(BNX2X_MSG_ETHTOOL,
2441                            "Can't configure external loopback\n");
2442                         return -EINVAL;
2443                 }
2444                 break;
2445         default:
2446                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2447                 return -EINVAL;
2448         }
2449
2450         /* prepare the loopback packet */
2451         pkt_size = (((bp->dev->maxmtu < ETH_MAX_PACKET_SIZE) ?
2452                      bp->dev->maxmtu : ETH_MAX_PACKET_SIZE) + ETHERHDRSIZE);
2453         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2454         if (!skb) {
2455                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2456                 rc = -ENOMEM;
2457                 goto test_loopback_exit;
2458         }
2459         packet = skb_put(skb, pkt_size);
2460         memcpy(packet, bp->dev->dev_addr, Eaddrlen);
2461         memset(packet + Eaddrlen, 0, Eaddrlen);
2462         memset(packet + 2*Eaddrlen, 0x77, (ETHERHDRSIZE - 2*Eaddrlen));
2463         for (i = ETHERHDRSIZE; i < pkt_size; i++)
2464                 packet[i] = (unsigned char) (i & 0xff);
2465         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2466                                  skb_headlen(skb), DMA_TO_DEVICE);
2467         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2468                 rc = -ENOMEM;
2469                 dev_kfree_skb(skb);
2470                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2471                 goto test_loopback_exit;
2472         }
2473
2474         /* send the loopback packet */
2475         num_pkts = 0;
2476         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2477         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2478
2479         netdev_tx_sent_queue(txq, skb->len);
2480
2481         pkt_prod = txdata->tx_pkt_prod++;
2482         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2483         tx_buf->first_bd = txdata->tx_bd_prod;
2484         tx_buf->skb = skb;
2485         tx_buf->flags = 0;
2486
2487         bd_prod = TX_BD(txdata->tx_bd_prod);
2488         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2489         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2490         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2491         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2492         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2493         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2494         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2495         SET_FLAG(tx_start_bd->general_data,
2496                  ETH_TX_START_BD_HDR_NBDS,
2497                  1);
2498         SET_FLAG(tx_start_bd->general_data,
2499                  ETH_TX_START_BD_PARSE_NBDS,
2500                  0);
2501
2502         /* turn on parsing and get a BD */
2503         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2504
2505         if (CHIP_IS_E1x(bp)) {
2506                 uint16_t global_data = 0;
2507                 struct eth_tx_parse_bd_e1x  *pbd_e1x =
2508                         &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2509                 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2510                 SET_FLAG(global_data,
2511                          ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2512                 pbd_e1x->global_data = cpu_to_le16(global_data);
2513         } else {
2514                 uint32_t parsing_data = 0;
2515                 struct eth_tx_parse_bd_e2  *pbd_e2 =
2516                         &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2517                 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2518                 SET_FLAG(parsing_data,
2519                          ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2520                 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2521         }
2522         wmb();
2523
2524         txdata->tx_db.data.prod += 2;
2525         cmb();
2526         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2527
2528         bus_wmb();
2529         cmb();
2530
2531         num_pkts++;
2532         txdata->tx_bd_prod += 2; /* start + pbd */
2533
2534         udelay(100);
2535
2536         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2537         if (tx_idx != tx_start_idx + num_pkts)
2538                 goto test_loopback_exit;
2539
2540         /* Unlike HC IGU won't generate an interrupt for status block
2541          * updates that have been performed while interrupts were
2542          * disabled.
2543          */
2544         if (bp->common.int_block == INT_BLOCK_IGU) {
2545                 /* Disable local BHes to prevent a dead-lock situation between
2546                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2547                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2548                  */
2549                 local_bh_disable();
2550                 bnx2x_tx_int(bp, txdata);
2551                 local_bh_enable();
2552         }
2553
2554         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2555         if (rx_idx != rx_start_idx + num_pkts)
2556                 goto test_loopback_exit;
2557
2558         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2559         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2560         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2561         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2562                 goto test_loopback_rx_exit;
2563
2564         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2565         if (len != pkt_size)
2566                 goto test_loopback_rx_exit;
2567
2568         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2569         dma_sync_single_for_cpu(&bp->pdev->dev,
2570                                    dma_unmap_addr(rx_buf, mapping),
2571                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2572         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2573         for (i = ETHERHDRSIZE; i < pkt_size; i++)
2574                 if (*(data + i) != (unsigned char) (i & 0xff))
2575                         goto test_loopback_rx_exit;
2576
2577         rc = 0;
2578
2579 test_loopback_rx_exit:
2580
2581         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2582         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2583         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2584         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2585
2586         /* Update producers */
2587         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2588                              fp_rx->rx_sge_prod);
2589
2590 test_loopback_exit:
2591         bp->link_params.loopback_mode = LOOPBACK_NONE;
2592
2593         return rc;
2594 #endif
2595 }
2596
2597 static int bnx2x_test_loopback(struct bnx2x *bp)
2598 {
2599         int rc = 0, res;
2600
2601         if (BP_NOMCP(bp))
2602                 return rc;
2603
2604         if (!netif_running(bp->dev))
2605                 return BNX2X_LOOPBACK_FAILED;
2606
2607         bnx2x_netif_stop(bp, 1);
2608         bnx2x_acquire_phy_lock(bp);
2609
2610         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2611         if (res) {
2612                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2613                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2614         }
2615
2616         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2617         if (res) {
2618                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2619                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2620         }
2621
2622         bnx2x_release_phy_lock(bp);
2623         bnx2x_netif_start(bp);
2624
2625         return rc;
2626 }
2627
2628 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2629 {
2630         int rc;
2631         uint8_t is_serdes =
2632                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2633
2634         if (BP_NOMCP(bp))
2635                 return -ENODEV;
2636
2637         if (!netif_running(bp->dev))
2638                 return BNX2X_EXT_LOOPBACK_FAILED;
2639
2640         bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2641         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2642         if (rc) {
2643                 DP(BNX2X_MSG_ETHTOOL,
2644                    "Can't perform self-test, nic_load (for external lb) failed\n");
2645                 return -ENODEV;
2646         }
2647         bnx2x_wait_for_link(bp, 1, is_serdes);
2648
2649         bnx2x_netif_stop(bp, 1);
2650
2651         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2652         if (rc)
2653                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2654
2655         bnx2x_netif_start(bp);
2656
2657         return rc;
2658 }
2659
2660 struct code_entry {
2661         uint32_t sram_start_addr;
2662         uint32_t code_attribute;
2663 #define CODE_IMAGE_TYPE_MASK                    0xf0800003
2664 #define CODE_IMAGE_VNTAG_PROFILES_DATA          0xd0000003
2665 #define CODE_IMAGE_LENGTH_MASK                  0x007ffffc
2666 #define CODE_IMAGE_TYPE_EXTENDED_DIR            0xe0000000
2667         uint32_t nvm_start_addr;
2668 };
2669
2670 #define CODE_ENTRY_MAX                  16
2671 #define CODE_ENTRY_EXTENDED_DIR_IDX     15
2672 #define MAX_IMAGES_IN_EXTENDED_DIR      64
2673 #define NVRAM_DIR_OFFSET                0x14
2674
2675 #define EXTENDED_DIR_EXISTS(code)                                         \
2676         ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2677          (code & CODE_IMAGE_LENGTH_MASK) != 0)
2678
2679 #define CRC32_RESIDUAL                  0xdebb20e3
2680 #define CRC_BUFF_SIZE                   256
2681
2682 static int bnx2x_nvram_crc(struct bnx2x *bp,
2683                            int offset,
2684                            int size,
2685                            uint8_t *buff)
2686 {
2687         uint32_t crc = ~0;
2688         int rc = 0, done = 0;
2689
2690         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2691            "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2692
2693         while (done < size) {
2694                 int count = MIN_T(int, size - done, CRC_BUFF_SIZE);
2695
2696                 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2697
2698                 if (rc)
2699                         return rc;
2700
2701                 crc = crc32_le(crc, buff, count);
2702                 done += count;
2703         }
2704
2705         if (crc != CRC32_RESIDUAL)
2706                 rc = -EINVAL;
2707
2708         return rc;
2709 }
2710
2711 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2712                                 struct code_entry *entry,
2713                                 uint8_t *buff)
2714 {
2715         size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2716         uint32_t type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2717         int rc;
2718
2719         /* Zero-length images and AFEX profiles do not have CRC */
2720         if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2721                 return 0;
2722
2723         rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2724         if (rc)
2725                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2726                    "image %x has failed crc test (rc %d)\n", type, rc);
2727
2728         return rc;
2729 }
2730
2731 static int bnx2x_test_dir_entry(struct bnx2x *bp, uint32_t addr,
2732                                 uint8_t *buff)
2733 {
2734         int rc;
2735         struct code_entry entry;
2736
2737         rc = bnx2x_nvram_read32(bp, addr, (uint32_t *)&entry, sizeof(entry));
2738         if (rc)
2739                 return rc;
2740
2741         return bnx2x_test_nvram_dir(bp, &entry, buff);
2742 }
2743
2744 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, uint8_t *buff)
2745 {
2746         uint32_t rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2747         struct code_entry entry;
2748         int i;
2749
2750         rc = bnx2x_nvram_read32(bp,
2751                                 dir_offset +
2752                                 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2753                                 (uint32_t *)&entry, sizeof(entry));
2754         if (rc)
2755                 return rc;
2756
2757         if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2758                 return 0;
2759
2760         rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2761                                 &cnt, sizeof(uint32_t));
2762         if (rc)
2763                 return rc;
2764
2765         dir_offset = entry.nvm_start_addr + 8;
2766
2767         for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2768                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2769                                               sizeof(struct code_entry) * i,
2770                                           buff);
2771                 if (rc)
2772                         return rc;
2773         }
2774
2775         return 0;
2776 }
2777
2778 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, uint8_t *buff)
2779 {
2780         uint32_t rc, dir_offset = NVRAM_DIR_OFFSET;
2781         int i;
2782
2783         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2784
2785         for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2786                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2787                                               sizeof(struct code_entry) * i,
2788                                           buff);
2789                 if (rc)
2790                         return rc;
2791         }
2792
2793         return bnx2x_test_nvram_ext_dirs(bp, buff);
2794 }
2795
2796 struct crc_pair {
2797         int offset;
2798         int size;
2799 };
2800
2801 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2802                                 const struct crc_pair *nvram_tbl,
2803                                 uint8_t *buf)
2804 {
2805         int i;
2806
2807         for (i = 0; nvram_tbl[i].size; i++) {
2808                 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2809                                          nvram_tbl[i].size, buf);
2810                 if (rc) {
2811                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2812                            "nvram_tbl[%d] has failed crc test (rc %d)\n",
2813                            i, rc);
2814                         return rc;
2815                 }
2816         }
2817
2818         return 0;
2819 }
2820
2821 static int bnx2x_test_nvram(struct bnx2x *bp)
2822 {
2823         const struct crc_pair nvram_tbl[] = {
2824                 {     0,  0x14 }, /* bootstrap */
2825                 {  0x14,  0xec }, /* dir */
2826                 { 0x100, 0x350 }, /* manuf_info */
2827                 { 0x450,  0xf0 }, /* feature_info */
2828                 { 0x640,  0x64 }, /* upgrade_key_info */
2829                 { 0x708,  0x70 }, /* manuf_key_info */
2830                 {     0,     0 }
2831         };
2832         const struct crc_pair nvram_tbl2[] = {
2833                 { 0x7e8, 0x350 }, /* manuf_info2 */
2834                 { 0xb38,  0xf0 }, /* feature_info */
2835                 {     0,     0 }
2836         };
2837
2838         uint8_t *buf;
2839         int rc;
2840         uint32_t magic;
2841
2842         if (BP_NOMCP(bp))
2843                 return 0;
2844
2845         buf = kmalloc(CRC_BUFF_SIZE, KMALLOC_WAIT);
2846         if (!buf) {
2847                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2848                 rc = -ENOMEM;
2849                 goto test_nvram_exit;
2850         }
2851
2852         rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2853         if (rc) {
2854                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2855                    "magic value read (rc %d)\n", rc);
2856                 goto test_nvram_exit;
2857         }
2858
2859         if (magic != 0x669955aa) {
2860                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2861                    "wrong magic value (0x%08x)\n", magic);
2862                 rc = -ENODEV;
2863                 goto test_nvram_exit;
2864         }
2865
2866         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2867         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2868         if (rc)
2869                 goto test_nvram_exit;
2870
2871         if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2872                 uint32_t hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2873                            SHARED_HW_CFG_HIDE_PORT1;
2874
2875                 if (!hide) {
2876                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2877                            "Port 1 CRC test-set\n");
2878                         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2879                         if (rc)
2880                                 goto test_nvram_exit;
2881                 }
2882         }
2883
2884         rc = bnx2x_test_nvram_dirs(bp, buf);
2885
2886 test_nvram_exit:
2887         kfree(buf);
2888         return rc;
2889 }
2890
2891 /* Send an EMPTY ramrod on the first queue */
2892 static int bnx2x_test_intr(struct bnx2x *bp)
2893 {
2894         struct bnx2x_queue_state_params params = {NULL};
2895
2896         if (!netif_running(bp->dev)) {
2897                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2898                    "cannot access eeprom when the interface is down\n");
2899                 return -ENODEV;
2900         }
2901
2902         params.q_obj = &bp->sp_objs->q_obj;
2903         params.cmd = BNX2X_Q_CMD_EMPTY;
2904
2905         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2906
2907         return bnx2x_queue_state_change(bp, &params);
2908 }
2909
2910 static void bnx2x_self_test(struct ether *dev,
2911                             struct ethtool_test *etest, uint64_t *buf)
2912 {
2913         struct bnx2x *bp = netdev_priv(dev);
2914         uint8_t is_serdes, link_up;
2915         int rc, cnt = 0;
2916
2917         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2918                 netdev_err(bp->dev,
2919                            "Handling parity error recovery. Try again later\n");
2920                 etest->flags |= ETH_TEST_FL_FAILED;
2921                 return;
2922         }
2923
2924         DP(BNX2X_MSG_ETHTOOL,
2925            "Self-test command parameters: offline = %d, external_lb = %d\n",
2926            (etest->flags & ETH_TEST_FL_OFFLINE),
2927            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2928
2929         memset(buf, 0, sizeof(uint64_t) * BNX2X_NUM_TESTS(bp));
2930
2931         if (bnx2x_test_nvram(bp) != 0) {
2932                 if (!IS_MF(bp))
2933                         buf[4] = 1;
2934                 else
2935                         buf[0] = 1;
2936                 etest->flags |= ETH_TEST_FL_FAILED;
2937         }
2938
2939         if (!netif_running(dev)) {
2940                 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2941                 return;
2942         }
2943
2944         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2945         link_up = bp->link_vars.link_up;
2946         /* offline tests are not supported in MF mode */
2947         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2948                 int port = BP_PORT(bp);
2949                 uint32_t val;
2950
2951                 /* save current value of input enable for TX port IF */
2952                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2953                 /* disable input for TX port IF */
2954                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2955
2956                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2957                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2958                 if (rc) {
2959                         etest->flags |= ETH_TEST_FL_FAILED;
2960                         DP(BNX2X_MSG_ETHTOOL,
2961                            "Can't perform self-test, nic_load (for offline) failed\n");
2962                         return;
2963                 }
2964
2965                 /* wait until link state is restored */
2966                 bnx2x_wait_for_link(bp, 1, is_serdes);
2967
2968                 if (bnx2x_test_registers(bp) != 0) {
2969                         buf[0] = 1;
2970                         etest->flags |= ETH_TEST_FL_FAILED;
2971                 }
2972                 if (bnx2x_test_memory(bp) != 0) {
2973                         buf[1] = 1;
2974                         etest->flags |= ETH_TEST_FL_FAILED;
2975                 }
2976
2977                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2978                 if (buf[2] != 0)
2979                         etest->flags |= ETH_TEST_FL_FAILED;
2980
2981                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2982                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2983                         if (buf[3] != 0)
2984                                 etest->flags |= ETH_TEST_FL_FAILED;
2985                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2986                 }
2987
2988                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2989
2990                 /* restore input for TX port IF */
2991                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2992                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2993                 if (rc) {
2994                         etest->flags |= ETH_TEST_FL_FAILED;
2995                         DP(BNX2X_MSG_ETHTOOL,
2996                            "Can't perform self-test, nic_load (for online) failed\n");
2997                         return;
2998                 }
2999                 /* wait until link state is restored */
3000                 bnx2x_wait_for_link(bp, link_up, is_serdes);
3001         }
3002
3003         if (bnx2x_test_intr(bp) != 0) {
3004                 if (!IS_MF(bp))
3005                         buf[5] = 1;
3006                 else
3007                         buf[1] = 1;
3008                 etest->flags |= ETH_TEST_FL_FAILED;
3009         }
3010
3011         if (link_up) {
3012                 cnt = 100;
3013                 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3014                         kthread_usleep(1000 * 20);
3015         }
3016
3017         if (!cnt) {
3018                 if (!IS_MF(bp))
3019                         buf[6] = 1;
3020                 else
3021                         buf[2] = 1;
3022                 etest->flags |= ETH_TEST_FL_FAILED;
3023         }
3024 }
3025
3026 #define IS_PORT_STAT(i) \
3027         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
3028 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
3029 #define HIDE_PORT_STAT(bp) \
3030                 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \
3031                  IS_VF(bp))
3032
3033 /* ethtool statistics are displayed for all regular ethernet queues and the
3034  * fcoe L2 queue if not disabled
3035  */
3036 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3037 {
3038         return BNX2X_NUM_ETH_QUEUES(bp);
3039 }
3040
3041 static int bnx2x_get_sset_count(struct ether *dev, int stringset)
3042 {
3043         struct bnx2x *bp = netdev_priv(dev);
3044         int i, num_strings = 0;
3045
3046         switch (stringset) {
3047         case ETH_SS_STATS:
3048                 if (is_multi(bp)) {
3049                         num_strings = bnx2x_num_stat_queues(bp) *
3050                                       BNX2X_NUM_Q_STATS;
3051                 } else
3052                         num_strings = 0;
3053                 if (HIDE_PORT_STAT(bp)) {
3054                         for (i = 0; i < BNX2X_NUM_STATS; i++)
3055                                 if (IS_FUNC_STAT(i))
3056                                         num_strings++;
3057                 } else
3058                         num_strings += BNX2X_NUM_STATS;
3059
3060                 return num_strings;
3061
3062         case ETH_SS_TEST:
3063                 return BNX2X_NUM_TESTS(bp);
3064
3065         case ETH_SS_PRIV_FLAGS:
3066                 return BNX2X_PRI_FLAG_LEN;
3067
3068         default:
3069                 return -EINVAL;
3070         }
3071 }
3072