BNX2X: spatch ether->mtu -> ether->maxmtu
[akaros.git] / kern / drivers / net / bnx2x / bnx2x_ethtool.c
1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath and fastpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include "akaros_compat.h"
19
20 #include "bnx2x.h"
21 #include "bnx2x_cmn.h"
22 #include "bnx2x_dump.h"
23 #include "bnx2x_init.h"
24
25 /* Note: in the format strings below %s is replaced by the queue-name which is
26  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
27  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
28  */
29 #define MAX_QUEUE_NAME_LEN      4
30 static const struct {
31         long offset;
32         int size;
33         char string[ETH_GSTRING_LEN];
34 } bnx2x_q_stats_arr[] = {
35 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
36         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
37                                                 8, "[%s]: rx_ucast_packets" },
38         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
39                                                 8, "[%s]: rx_mcast_packets" },
40         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
41                                                 8, "[%s]: rx_bcast_packets" },
42         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
43         { Q_STATS_OFFSET32(rx_err_discard_pkt),
44                                          4, "[%s]: rx_phy_ip_err_discards"},
45         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
46                                          4, "[%s]: rx_skb_alloc_discard" },
47         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
48
49         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
50 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
51                                                 8, "[%s]: tx_ucast_packets" },
52         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
53                                                 8, "[%s]: tx_mcast_packets" },
54         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
55                                                 8, "[%s]: tx_bcast_packets" },
56         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
57                                                 8, "[%s]: tpa_aggregations" },
58         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
59                                         8, "[%s]: tpa_aggregated_frames"},
60         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
61         { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
62                                         4, "[%s]: driver_filtered_tx_pkt" }
63 };
64
65 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
66
67 static const struct {
68         long offset;
69         int size;
70         uint32_t flags;
71 #define STATS_FLAGS_PORT                1
72 #define STATS_FLAGS_FUNC                2
73 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
74         char string[ETH_GSTRING_LEN];
75 } bnx2x_stats_arr[] = {
76 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
77                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
78         { STATS_OFFSET32(error_bytes_received_hi),
79                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
80         { STATS_OFFSET32(total_unicast_packets_received_hi),
81                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
82         { STATS_OFFSET32(total_multicast_packets_received_hi),
83                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
84         { STATS_OFFSET32(total_broadcast_packets_received_hi),
85                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
86         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
87                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
88         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
89                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
90         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
91                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
92         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
93                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
94 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
95                                 8, STATS_FLAGS_PORT, "rx_fragments" },
96         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
97                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
98         { STATS_OFFSET32(no_buff_discard_hi),
99                                 8, STATS_FLAGS_BOTH, "rx_discards" },
100         { STATS_OFFSET32(mac_filter_discard),
101                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
102         { STATS_OFFSET32(mf_tag_discard),
103                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
104         { STATS_OFFSET32(pfc_frames_received_hi),
105                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
106         { STATS_OFFSET32(pfc_frames_sent_hi),
107                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
108         { STATS_OFFSET32(brb_drop_hi),
109                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
110         { STATS_OFFSET32(brb_truncate_hi),
111                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
112         { STATS_OFFSET32(pause_frames_received_hi),
113                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
114         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
115                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
116         { STATS_OFFSET32(nig_timer_max),
117                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
118 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
119                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
120         { STATS_OFFSET32(rx_skb_alloc_failed),
121                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
122         { STATS_OFFSET32(hw_csum_err),
123                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
124
125         { STATS_OFFSET32(total_bytes_transmitted_hi),
126                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
127         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
128                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
129         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
130                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
131         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
132                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
133         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
134                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
135         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
136                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
137         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
138                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
139 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
140                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
141         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
142                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
143         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
144                                 8, STATS_FLAGS_PORT, "tx_deferred" },
145         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
146                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
147         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
148                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
149         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
150                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
151         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
152                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
153         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
154                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
155         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
156                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
157         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
158                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
159 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
160                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
161         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
162                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
163         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
164                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
165         { STATS_OFFSET32(pause_frames_sent_hi),
166                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
167         { STATS_OFFSET32(total_tpa_aggregations_hi),
168                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
169         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
170                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
171         { STATS_OFFSET32(total_tpa_bytes_hi),
172                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
173         { STATS_OFFSET32(recoverable_error),
174                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
175         { STATS_OFFSET32(unrecoverable_error),
176                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
177         { STATS_OFFSET32(driver_filtered_tx_pkt),
178                         4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
179         { STATS_OFFSET32(eee_tx_lpi),
180                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
181 };
182
183 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
184
185 static int bnx2x_get_port_type(struct bnx2x *bp)
186 {
187         int port_type;
188         uint32_t phy_idx = bnx2x_get_cur_phy_idx(bp);
189         switch (bp->link_params.phy[phy_idx].media_type) {
190         case ETH_PHY_SFPP_10G_FIBER:
191         case ETH_PHY_SFP_1G_FIBER:
192         case ETH_PHY_XFP_FIBER:
193         case ETH_PHY_KR:
194         case ETH_PHY_CX4:
195                 port_type = PORT_FIBRE;
196                 break;
197         case ETH_PHY_DA_TWINAX:
198                 port_type = PORT_DA;
199                 break;
200         case ETH_PHY_BASE_T:
201                 port_type = PORT_TP;
202                 break;
203         case ETH_PHY_NOT_PRESENT:
204                 port_type = PORT_NONE;
205                 break;
206         case ETH_PHY_UNSPECIFIED:
207         default:
208                 port_type = PORT_OTHER;
209                 break;
210         }
211         return port_type;
212 }
213
214 static int bnx2x_get_vf_settings(struct ether *dev,
215                                  struct ethtool_cmd *cmd)
216 {
217         struct bnx2x *bp = netdev_priv(dev);
218
219         if (bp->state == BNX2X_STATE_OPEN) {
220                 if (test_bit(BNX2X_LINK_REPORT_FD,
221                              &bp->vf_link_vars.link_report_flags))
222                         cmd->duplex = DUPLEX_FULL;
223                 else
224                         cmd->duplex = DUPLEX_HALF;
225
226                 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
227         } else {
228                 cmd->duplex = DUPLEX_UNKNOWN;
229                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
230         }
231
232         cmd->port               = PORT_OTHER;
233         cmd->phy_address        = 0;
234         cmd->transceiver        = XCVR_INTERNAL;
235         cmd->autoneg            = AUTONEG_DISABLE;
236         cmd->maxtxpkt           = 0;
237         cmd->maxrxpkt           = 0;
238
239         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
240            "  supported 0x%x  advertising 0x%x  speed %u\n"
241            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
242            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
243            cmd->cmd, cmd->supported, cmd->advertising,
244            ethtool_cmd_speed(cmd),
245            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
246            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
247
248         return 0;
249 }
250
251 static int bnx2x_get_settings(struct ether *dev, struct ethtool_cmd *cmd)
252 {
253         struct bnx2x *bp = netdev_priv(dev);
254         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
255
256         /* Dual Media boards present all available port types */
257         cmd->supported = bp->port.supported[cfg_idx] |
258                 (bp->port.supported[cfg_idx ^ 1] &
259                  (SUPPORTED_TP | SUPPORTED_FIBRE));
260         cmd->advertising = bp->port.advertising[cfg_idx];
261         if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
262             ETH_PHY_SFP_1G_FIBER) {
263                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
264                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
265         }
266
267         if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
268             !(bp->flags & MF_FUNC_DIS)) {
269                 cmd->duplex = bp->link_vars.duplex;
270
271                 if (IS_MF(bp) && !BP_NOMCP(bp))
272                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
273                 else
274                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
275         } else {
276                 cmd->duplex = DUPLEX_UNKNOWN;
277                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
278         }
279
280         cmd->port = bnx2x_get_port_type(bp);
281
282         cmd->phy_address = bp->mdio.prtad;
283         cmd->transceiver = XCVR_INTERNAL;
284
285         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
286                 cmd->autoneg = AUTONEG_ENABLE;
287         else
288                 cmd->autoneg = AUTONEG_DISABLE;
289
290         /* Publish LP advertised speeds and FC */
291         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
292                 uint32_t status = bp->link_vars.link_status;
293
294                 cmd->lp_advertising |= ADVERTISED_Autoneg;
295                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
296                         cmd->lp_advertising |= ADVERTISED_Pause;
297                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
298                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
299
300                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
301                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
302                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
303                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
304                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
305                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
306                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
307                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
308                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
309                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
310                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
311                         cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
312                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
313                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
314                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
315                         cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
316                 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
317                         cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
318         }
319
320         cmd->maxtxpkt = 0;
321         cmd->maxrxpkt = 0;
322
323         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
324            "  supported 0x%x  advertising 0x%x  speed %u\n"
325            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
326            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
327            cmd->cmd, cmd->supported, cmd->advertising,
328            ethtool_cmd_speed(cmd),
329            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
330            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
331
332         return 0;
333 }
334
335 static int bnx2x_set_settings(struct ether *dev, struct ethtool_cmd *cmd)
336 {
337         struct bnx2x *bp = netdev_priv(dev);
338         uint32_t advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
339         uint32_t speed, phy_idx;
340
341         if (IS_MF_SD(bp))
342                 return 0;
343
344         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
345            "  supported 0x%x  advertising 0x%x  speed %u\n"
346            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
347            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
348            cmd->cmd, cmd->supported, cmd->advertising,
349            ethtool_cmd_speed(cmd),
350            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
351            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
352
353         speed = ethtool_cmd_speed(cmd);
354
355         /* If received a request for an unknown duplex, assume full*/
356         if (cmd->duplex == DUPLEX_UNKNOWN)
357                 cmd->duplex = DUPLEX_FULL;
358
359         if (IS_MF_SI(bp)) {
360                 uint32_t part;
361                 uint32_t line_speed = bp->link_vars.line_speed;
362
363                 /* use 10G if no link detected */
364                 if (!line_speed)
365                         line_speed = 10000;
366
367                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
368                         DP(BNX2X_MSG_ETHTOOL,
369                            "To set speed BC %X or higher is required, please upgrade BC\n",
370                            REQ_BC_VER_4_SET_MF_BW);
371                         return -EINVAL;
372                 }
373
374                 part = (speed * 100) / line_speed;
375
376                 if (line_speed < speed || !part) {
377                         DP(BNX2X_MSG_ETHTOOL,
378                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
379                         return -EINVAL;
380                 }
381
382                 if (bp->state != BNX2X_STATE_OPEN)
383                         /* store value for following "load" */
384                         bp->pending_max = part;
385                 else
386                         bnx2x_update_max_mf_config(bp, part);
387
388                 return 0;
389         }
390
391         cfg_idx = bnx2x_get_link_cfg_idx(bp);
392         old_multi_phy_config = bp->link_params.multi_phy_config;
393         if (cmd->port != bnx2x_get_port_type(bp)) {
394                 switch (cmd->port) {
395                 case PORT_TP:
396                         if (!(bp->port.supported[0] & SUPPORTED_TP ||
397                               bp->port.supported[1] & SUPPORTED_TP)) {
398                                 DP(BNX2X_MSG_ETHTOOL,
399                                    "Unsupported port type\n");
400                                 return -EINVAL;
401                         }
402                         bp->link_params.multi_phy_config &=
403                                 ~PORT_HW_CFG_PHY_SELECTION_MASK;
404                         if (bp->link_params.multi_phy_config &
405                             PORT_HW_CFG_PHY_SWAPPED_ENABLED)
406                                 bp->link_params.multi_phy_config |=
407                                 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
408                         else
409                                 bp->link_params.multi_phy_config |=
410                                 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
411                         break;
412                 case PORT_FIBRE:
413                 case PORT_DA:
414                 case PORT_NONE:
415                         if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
416                               bp->port.supported[1] & SUPPORTED_FIBRE)) {
417                                 DP(BNX2X_MSG_ETHTOOL,
418                                    "Unsupported port type\n");
419                                 return -EINVAL;
420                         }
421                         bp->link_params.multi_phy_config &=
422                                 ~PORT_HW_CFG_PHY_SELECTION_MASK;
423                         if (bp->link_params.multi_phy_config &
424                             PORT_HW_CFG_PHY_SWAPPED_ENABLED)
425                                 bp->link_params.multi_phy_config |=
426                                 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
427                         else
428                                 bp->link_params.multi_phy_config |=
429                                 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
430                         break;
431                 default:
432                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
433                         return -EINVAL;
434                 }
435         }
436         /* Save new config in case command complete successfully */
437         new_multi_phy_config = bp->link_params.multi_phy_config;
438         /* Get the new cfg_idx */
439         cfg_idx = bnx2x_get_link_cfg_idx(bp);
440         /* Restore old config in case command failed */
441         bp->link_params.multi_phy_config = old_multi_phy_config;
442         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
443
444         if (cmd->autoneg == AUTONEG_ENABLE) {
445                 uint32_t an_supported_speed = bp->port.supported[cfg_idx];
446                 if (bp->link_params.phy[EXT_PHY1].type ==
447                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
448                         an_supported_speed |= (SUPPORTED_100baseT_Half |
449                                                SUPPORTED_100baseT_Full);
450                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
451                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
452                         return -EINVAL;
453                 }
454
455                 /* advertise the requested speed and duplex if supported */
456                 if (cmd->advertising & ~an_supported_speed) {
457                         DP(BNX2X_MSG_ETHTOOL,
458                            "Advertisement parameters are not supported\n");
459                         return -EINVAL;
460                 }
461
462                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
463                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
464                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
465                                          cmd->advertising);
466                 if (cmd->advertising) {
467
468                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
469                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
470                                 bp->link_params.speed_cap_mask[cfg_idx] |=
471                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
472                         }
473                         if (cmd->advertising & ADVERTISED_10baseT_Full)
474                                 bp->link_params.speed_cap_mask[cfg_idx] |=
475                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
476
477                         if (cmd->advertising & ADVERTISED_100baseT_Full)
478                                 bp->link_params.speed_cap_mask[cfg_idx] |=
479                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
480
481                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
482                                 bp->link_params.speed_cap_mask[cfg_idx] |=
483                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
484                         }
485                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
486                                 bp->link_params.speed_cap_mask[cfg_idx] |=
487                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
488                         }
489                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
490                                                 ADVERTISED_1000baseKX_Full))
491                                 bp->link_params.speed_cap_mask[cfg_idx] |=
492                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
493
494                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
495                                                 ADVERTISED_10000baseKX4_Full |
496                                                 ADVERTISED_10000baseKR_Full))
497                                 bp->link_params.speed_cap_mask[cfg_idx] |=
498                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
499
500                         if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
501                                 bp->link_params.speed_cap_mask[cfg_idx] |=
502                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
503                 }
504         } else { /* forced speed */
505                 /* advertise the requested speed and duplex if supported */
506                 switch (speed) {
507                 case SPEED_10:
508                         if (cmd->duplex == DUPLEX_FULL) {
509                                 if (!(bp->port.supported[cfg_idx] &
510                                       SUPPORTED_10baseT_Full)) {
511                                         DP(BNX2X_MSG_ETHTOOL,
512                                            "10M full not supported\n");
513                                         return -EINVAL;
514                                 }
515
516                                 advertising = (ADVERTISED_10baseT_Full |
517                                                ADVERTISED_TP);
518                         } else {
519                                 if (!(bp->port.supported[cfg_idx] &
520                                       SUPPORTED_10baseT_Half)) {
521                                         DP(BNX2X_MSG_ETHTOOL,
522                                            "10M half not supported\n");
523                                         return -EINVAL;
524                                 }
525
526                                 advertising = (ADVERTISED_10baseT_Half |
527                                                ADVERTISED_TP);
528                         }
529                         break;
530
531                 case SPEED_100:
532                         if (cmd->duplex == DUPLEX_FULL) {
533                                 if (!(bp->port.supported[cfg_idx] &
534                                                 SUPPORTED_100baseT_Full)) {
535                                         DP(BNX2X_MSG_ETHTOOL,
536                                            "100M full not supported\n");
537                                         return -EINVAL;
538                                 }
539
540                                 advertising = (ADVERTISED_100baseT_Full |
541                                                ADVERTISED_TP);
542                         } else {
543                                 if (!(bp->port.supported[cfg_idx] &
544                                                 SUPPORTED_100baseT_Half)) {
545                                         DP(BNX2X_MSG_ETHTOOL,
546                                            "100M half not supported\n");
547                                         return -EINVAL;
548                                 }
549
550                                 advertising = (ADVERTISED_100baseT_Half |
551                                                ADVERTISED_TP);
552                         }
553                         break;
554
555                 case SPEED_1000:
556                         if (cmd->duplex != DUPLEX_FULL) {
557                                 DP(BNX2X_MSG_ETHTOOL,
558                                    "1G half not supported\n");
559                                 return -EINVAL;
560                         }
561
562                         if (!(bp->port.supported[cfg_idx] &
563                               SUPPORTED_1000baseT_Full)) {
564                                 DP(BNX2X_MSG_ETHTOOL,
565                                    "1G full not supported\n");
566                                 return -EINVAL;
567                         }
568
569                         advertising = (ADVERTISED_1000baseT_Full |
570                                        ADVERTISED_TP);
571                         break;
572
573                 case SPEED_2500:
574                         if (cmd->duplex != DUPLEX_FULL) {
575                                 DP(BNX2X_MSG_ETHTOOL,
576                                    "2.5G half not supported\n");
577                                 return -EINVAL;
578                         }
579
580                         if (!(bp->port.supported[cfg_idx]
581                               & SUPPORTED_2500baseX_Full)) {
582                                 DP(BNX2X_MSG_ETHTOOL,
583                                    "2.5G full not supported\n");
584                                 return -EINVAL;
585                         }
586
587                         advertising = (ADVERTISED_2500baseX_Full |
588                                        ADVERTISED_TP);
589                         break;
590
591                 case SPEED_10000:
592                         if (cmd->duplex != DUPLEX_FULL) {
593                                 DP(BNX2X_MSG_ETHTOOL,
594                                    "10G half not supported\n");
595                                 return -EINVAL;
596                         }
597                         phy_idx = bnx2x_get_cur_phy_idx(bp);
598                         if (!(bp->port.supported[cfg_idx]
599                               & SUPPORTED_10000baseT_Full) ||
600                             (bp->link_params.phy[phy_idx].media_type ==
601                              ETH_PHY_SFP_1G_FIBER)) {
602                                 DP(BNX2X_MSG_ETHTOOL,
603                                    "10G full not supported\n");
604                                 return -EINVAL;
605                         }
606
607                         advertising = (ADVERTISED_10000baseT_Full |
608                                        ADVERTISED_FIBRE);
609                         break;
610
611                 default:
612                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
613                         return -EINVAL;
614                 }
615
616                 bp->link_params.req_line_speed[cfg_idx] = speed;
617                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
618                 bp->port.advertising[cfg_idx] = advertising;
619         }
620
621         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
622            "  req_duplex %d  advertising 0x%x\n",
623            bp->link_params.req_line_speed[cfg_idx],
624            bp->link_params.req_duplex[cfg_idx],
625            bp->port.advertising[cfg_idx]);
626
627         /* Set new config */
628         bp->link_params.multi_phy_config = new_multi_phy_config;
629         if (netif_running(dev)) {
630                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
631                 bnx2x_link_set(bp);
632         }
633
634         return 0;
635 }
636
637 #define DUMP_ALL_PRESETS                0x1FFF
638 #define DUMP_MAX_PRESETS                13
639
640 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, uint32_t preset)
641 {
642         if (CHIP_IS_E1(bp))
643                 return dump_num_registers[0][preset-1];
644         else if (CHIP_IS_E1H(bp))
645                 return dump_num_registers[1][preset-1];
646         else if (CHIP_IS_E2(bp))
647                 return dump_num_registers[2][preset-1];
648         else if (CHIP_IS_E3A0(bp))
649                 return dump_num_registers[3][preset-1];
650         else if (CHIP_IS_E3B0(bp))
651                 return dump_num_registers[4][preset-1];
652         else
653                 return 0;
654 }
655
656 static int __bnx2x_get_regs_len(struct bnx2x *bp)
657 {
658         uint32_t preset_idx;
659         int regdump_len = 0;
660
661         /* Calculate the total preset regs length */
662         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
663                 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
664
665         return regdump_len;
666 }
667
668 static int bnx2x_get_regs_len(struct ether *dev)
669 {
670         struct bnx2x *bp = netdev_priv(dev);
671         int regdump_len = 0;
672
673         if (IS_VF(bp))
674                 return 0;
675
676         regdump_len = __bnx2x_get_regs_len(bp);
677         regdump_len *= 4;
678         regdump_len += sizeof(struct dump_header);
679
680         return regdump_len;
681 }
682
683 #define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
684 #define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
685 #define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
686 #define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
687 #define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
688
689 #define IS_REG_IN_PRESET(presets, idx)  \
690                 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
691
692 /******* Paged registers info selectors ********/
693 static const uint32_t *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
694 {
695         if (CHIP_IS_E2(bp))
696                 return page_vals_e2;
697         else if (CHIP_IS_E3(bp))
698                 return page_vals_e3;
699         else
700                 return NULL;
701 }
702
703 static uint32_t __bnx2x_get_page_reg_num(struct bnx2x *bp)
704 {
705         if (CHIP_IS_E2(bp))
706                 return PAGE_MODE_VALUES_E2;
707         else if (CHIP_IS_E3(bp))
708                 return PAGE_MODE_VALUES_E3;
709         else
710                 return 0;
711 }
712
713 static const uint32_t *__bnx2x_get_page_write_ar(struct bnx2x *bp)
714 {
715         if (CHIP_IS_E2(bp))
716                 return page_write_regs_e2;
717         else if (CHIP_IS_E3(bp))
718                 return page_write_regs_e3;
719         else
720                 return NULL;
721 }
722
723 static uint32_t __bnx2x_get_page_write_num(struct bnx2x *bp)
724 {
725         if (CHIP_IS_E2(bp))
726                 return PAGE_WRITE_REGS_E2;
727         else if (CHIP_IS_E3(bp))
728                 return PAGE_WRITE_REGS_E3;
729         else
730                 return 0;
731 }
732
733 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
734 {
735         if (CHIP_IS_E2(bp))
736                 return page_read_regs_e2;
737         else if (CHIP_IS_E3(bp))
738                 return page_read_regs_e3;
739         else
740                 return NULL;
741 }
742
743 static uint32_t __bnx2x_get_page_read_num(struct bnx2x *bp)
744 {
745         if (CHIP_IS_E2(bp))
746                 return PAGE_READ_REGS_E2;
747         else if (CHIP_IS_E3(bp))
748                 return PAGE_READ_REGS_E3;
749         else
750                 return 0;
751 }
752
753 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
754                                        const struct reg_addr *reg_info)
755 {
756         if (CHIP_IS_E1(bp))
757                 return IS_E1_REG(reg_info->chips);
758         else if (CHIP_IS_E1H(bp))
759                 return IS_E1H_REG(reg_info->chips);
760         else if (CHIP_IS_E2(bp))
761                 return IS_E2_REG(reg_info->chips);
762         else if (CHIP_IS_E3A0(bp))
763                 return IS_E3A0_REG(reg_info->chips);
764         else if (CHIP_IS_E3B0(bp))
765                 return IS_E3B0_REG(reg_info->chips);
766         else
767                 return false;
768 }
769
770 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
771         const struct wreg_addr *wreg_info)
772 {
773         if (CHIP_IS_E1(bp))
774                 return IS_E1_REG(wreg_info->chips);
775         else if (CHIP_IS_E1H(bp))
776                 return IS_E1H_REG(wreg_info->chips);
777         else if (CHIP_IS_E2(bp))
778                 return IS_E2_REG(wreg_info->chips);
779         else if (CHIP_IS_E3A0(bp))
780                 return IS_E3A0_REG(wreg_info->chips);
781         else if (CHIP_IS_E3B0(bp))
782                 return IS_E3B0_REG(wreg_info->chips);
783         else
784                 return false;
785 }
786
787 /**
788  * bnx2x_read_pages_regs - read "paged" registers
789  *
790  * @bp          device handle
791  * @p           output buffer
792  *
793  * Reads "paged" memories: memories that may only be read by first writing to a
794  * specific address ("write address") and then reading from a specific address
795  * ("read address"). There may be more than one write address per "page" and
796  * more than one read address per write address.
797  */
798 static void bnx2x_read_pages_regs(struct bnx2x *bp, uint32_t *p,
799                                   uint32_t preset)
800 {
801         uint32_t i, j, k, n;
802
803         /* addresses of the paged registers */
804         const uint32_t *page_addr = __bnx2x_get_page_addr_ar(bp);
805         /* number of paged registers */
806         int num_pages = __bnx2x_get_page_reg_num(bp);
807         /* write addresses */
808         const uint32_t *write_addr = __bnx2x_get_page_write_ar(bp);
809         /* number of write addresses */
810         int write_num = __bnx2x_get_page_write_num(bp);
811         /* read addresses info */
812         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
813         /* number of read addresses */
814         int read_num = __bnx2x_get_page_read_num(bp);
815         uint32_t addr, size;
816
817         for (i = 0; i < num_pages; i++) {
818                 for (j = 0; j < write_num; j++) {
819                         REG_WR(bp, write_addr[j], page_addr[i]);
820
821                         for (k = 0; k < read_num; k++) {
822                                 if (IS_REG_IN_PRESET(read_addr[k].presets,
823                                                      preset)) {
824                                         size = read_addr[k].size;
825                                         for (n = 0; n < size; n++) {
826                                                 addr = read_addr[k].addr + n*4;
827                                                 *p++ = REG_RD(bp, addr);
828                                         }
829                                 }
830                         }
831                 }
832         }
833 }
834
835 static int __bnx2x_get_preset_regs(struct bnx2x *bp, uint32_t *p,
836                                    uint32_t preset)
837 {
838         uint32_t i, j, addr;
839         const struct wreg_addr *wreg_addr_p = NULL;
840
841         if (CHIP_IS_E1(bp))
842                 wreg_addr_p = &wreg_addr_e1;
843         else if (CHIP_IS_E1H(bp))
844                 wreg_addr_p = &wreg_addr_e1h;
845         else if (CHIP_IS_E2(bp))
846                 wreg_addr_p = &wreg_addr_e2;
847         else if (CHIP_IS_E3A0(bp))
848                 wreg_addr_p = &wreg_addr_e3;
849         else if (CHIP_IS_E3B0(bp))
850                 wreg_addr_p = &wreg_addr_e3b0;
851
852         /* Read the idle_chk registers */
853         for (i = 0; i < IDLE_REGS_COUNT; i++) {
854                 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
855                     IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
856                         for (j = 0; j < idle_reg_addrs[i].size; j++)
857                                 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
858                 }
859         }
860
861         /* Read the regular registers */
862         for (i = 0; i < REGS_COUNT; i++) {
863                 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
864                     IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
865                         for (j = 0; j < reg_addrs[i].size; j++)
866                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
867                 }
868         }
869
870         /* Read the CAM registers */
871         if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
872             IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
873                 for (i = 0; i < wreg_addr_p->size; i++) {
874                         *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
875
876                         /* In case of wreg_addr register, read additional
877                            registers from read_regs array
878                         */
879                         for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
880                                 addr = *(wreg_addr_p->read_regs);
881                                 *p++ = REG_RD(bp, addr + j*4);
882                         }
883                 }
884         }
885
886         /* Paged registers are supported in E2 & E3 only */
887         if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
888                 /* Read "paged" registers */
889                 bnx2x_read_pages_regs(bp, p, preset);
890         }
891
892         return 0;
893 }
894
895 static void __bnx2x_get_regs(struct bnx2x *bp, uint32_t *p)
896 {
897         uint32_t preset_idx;
898
899         /* Read all registers, by reading all preset registers */
900         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
901                 /* Skip presets with IOR */
902                 if ((preset_idx == 2) ||
903                     (preset_idx == 5) ||
904                     (preset_idx == 8) ||
905                     (preset_idx == 11))
906                         continue;
907                 __bnx2x_get_preset_regs(bp, p, preset_idx);
908                 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
909         }
910 }
911
912 static void bnx2x_get_regs(struct ether *dev,
913                            struct ethtool_regs *regs, void *_p)
914 {
915         uint32_t *p = _p;
916         struct bnx2x *bp = netdev_priv(dev);
917         struct dump_header dump_hdr = {0};
918
919         regs->version = 2;
920         memset(p, 0, regs->len);
921
922         if (!netif_running(bp->dev))
923                 return;
924
925         /* Disable parity attentions as long as following dump may
926          * cause false alarms by reading never written registers. We
927          * will re-enable parity attentions right after the dump.
928          */
929
930         bnx2x_disable_blocks_parity(bp);
931
932         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
933         dump_hdr.preset = DUMP_ALL_PRESETS;
934         dump_hdr.version = BNX2X_DUMP_VERSION;
935
936         /* dump_meta_data presents OR of CHIP and PATH. */
937         if (CHIP_IS_E1(bp)) {
938                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
939         } else if (CHIP_IS_E1H(bp)) {
940                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
941         } else if (CHIP_IS_E2(bp)) {
942                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
943                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
944         } else if (CHIP_IS_E3A0(bp)) {
945                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
946                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
947         } else if (CHIP_IS_E3B0(bp)) {
948                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
949                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
950         }
951
952         memcpy(p, &dump_hdr, sizeof(struct dump_header));
953         p += dump_hdr.header_size + 1;
954
955         /* Actually read the registers */
956         __bnx2x_get_regs(bp, p);
957
958         /* Re-enable parity attentions */
959         bnx2x_clear_blocks_parity(bp);
960         bnx2x_enable_blocks_parity(bp);
961 }
962
963 static int bnx2x_get_preset_regs_len(struct ether *dev, uint32_t preset)
964 {
965         struct bnx2x *bp = netdev_priv(dev);
966         int regdump_len = 0;
967
968         regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
969         regdump_len *= 4;
970         regdump_len += sizeof(struct dump_header);
971
972         return regdump_len;
973 }
974
975 static int bnx2x_set_dump(struct ether *dev, struct ethtool_dump *val)
976 {
977         struct bnx2x *bp = netdev_priv(dev);
978
979         /* Use the ethtool_dump "flag" field as the dump preset index */
980         if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
981                 return -EINVAL;
982
983         bp->dump_preset_idx = val->flag;
984         return 0;
985 }
986
987 static int bnx2x_get_dump_flag(struct ether *dev,
988                                struct ethtool_dump *dump)
989 {
990         struct bnx2x *bp = netdev_priv(dev);
991
992         dump->version = BNX2X_DUMP_VERSION;
993         dump->flag = bp->dump_preset_idx;
994         /* Calculate the requested preset idx length */
995         dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
996         DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
997            bp->dump_preset_idx, dump->len);
998         return 0;
999 }
1000
1001 static int bnx2x_get_dump_data(struct ether *dev,
1002                                struct ethtool_dump *dump,
1003                                void *buffer)
1004 {
1005         uint32_t *p = buffer;
1006         struct bnx2x *bp = netdev_priv(dev);
1007         struct dump_header dump_hdr = {0};
1008
1009         /* Disable parity attentions as long as following dump may
1010          * cause false alarms by reading never written registers. We
1011          * will re-enable parity attentions right after the dump.
1012          */
1013
1014         bnx2x_disable_blocks_parity(bp);
1015
1016         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1017         dump_hdr.preset = bp->dump_preset_idx;
1018         dump_hdr.version = BNX2X_DUMP_VERSION;
1019
1020         DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1021
1022         /* dump_meta_data presents OR of CHIP and PATH. */
1023         if (CHIP_IS_E1(bp)) {
1024                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1025         } else if (CHIP_IS_E1H(bp)) {
1026                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1027         } else if (CHIP_IS_E2(bp)) {
1028                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1029                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1030         } else if (CHIP_IS_E3A0(bp)) {
1031                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1032                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1033         } else if (CHIP_IS_E3B0(bp)) {
1034                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1035                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1036         }
1037
1038         memcpy(p, &dump_hdr, sizeof(struct dump_header));
1039         p += dump_hdr.header_size + 1;
1040
1041         /* Actually read the registers */
1042         __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1043
1044         /* Re-enable parity attentions */
1045         bnx2x_clear_blocks_parity(bp);
1046         bnx2x_enable_blocks_parity(bp);
1047
1048         return 0;
1049 }
1050
1051 static void bnx2x_get_drvinfo(struct ether *dev,
1052                               struct ethtool_drvinfo *info)
1053 {
1054         struct bnx2x *bp = netdev_priv(dev);
1055
1056         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1057         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1058
1059         bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1060
1061         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1062         info->n_stats = BNX2X_NUM_STATS;
1063         info->testinfo_len = BNX2X_NUM_TESTS(bp);
1064         info->eedump_len = bp->common.flash_size;
1065         info->regdump_len = bnx2x_get_regs_len(dev);
1066 }
1067
1068 static void bnx2x_get_wol(struct ether *dev, struct ethtool_wolinfo *wol)
1069 {
1070         struct bnx2x *bp = netdev_priv(dev);
1071
1072         if (bp->flags & NO_WOL_FLAG) {
1073                 wol->supported = 0;
1074                 wol->wolopts = 0;
1075         } else {
1076                 wol->supported = WAKE_MAGIC;
1077                 if (bp->wol)
1078                         wol->wolopts = WAKE_MAGIC;
1079                 else
1080                         wol->wolopts = 0;
1081         }
1082         memset(&wol->sopass, 0, sizeof(wol->sopass));
1083 }
1084
1085 static int bnx2x_set_wol(struct ether *dev, struct ethtool_wolinfo *wol)
1086 {
1087         struct bnx2x *bp = netdev_priv(dev);
1088
1089         if (wol->wolopts & ~WAKE_MAGIC) {
1090                 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1091                 return -EINVAL;
1092         }
1093
1094         if (wol->wolopts & WAKE_MAGIC) {
1095                 if (bp->flags & NO_WOL_FLAG) {
1096                         DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1097                         return -EINVAL;
1098                 }
1099                 bp->wol = 1;
1100         } else
1101                 bp->wol = 0;
1102
1103         return 0;
1104 }
1105
1106 static uint32_t bnx2x_get_msglevel(struct ether *dev)
1107 {
1108         struct bnx2x *bp = netdev_priv(dev);
1109
1110         return bp->msg_enable;
1111 }
1112
1113 static void bnx2x_set_msglevel(struct ether *dev, uint32_t level)
1114 {
1115         struct bnx2x *bp = netdev_priv(dev);
1116
1117         if (capable(CAP_NET_ADMIN)) {
1118                 /* dump MCP trace */
1119                 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1120                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
1121                 bp->msg_enable = level;
1122         }
1123 }
1124
1125 static int bnx2x_nway_reset(struct ether *dev)
1126 {
1127         struct bnx2x *bp = netdev_priv(dev);
1128
1129         if (!bp->port.pmf)
1130                 return 0;
1131
1132         if (netif_running(dev)) {
1133                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1134                 bnx2x_force_link_reset(bp);
1135                 bnx2x_link_set(bp);
1136         }
1137
1138         return 0;
1139 }
1140
1141 static uint32_t bnx2x_get_link(struct ether *dev)
1142 {
1143         struct bnx2x *bp = netdev_priv(dev);
1144
1145         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1146                 return 0;
1147
1148         if (IS_VF(bp))
1149                 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1150                                  &bp->vf_link_vars.link_report_flags);
1151
1152         return bp->link_vars.link_up;
1153 }
1154
1155 static int bnx2x_get_eeprom_len(struct ether *dev)
1156 {
1157         struct bnx2x *bp = netdev_priv(dev);
1158
1159         return bp->common.flash_size;
1160 }
1161
1162 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1163  * had we done things the other way around, if two pfs from the same port would
1164  * attempt to access nvram at the same time, we could run into a scenario such
1165  * as:
1166  * pf A takes the port lock.
1167  * pf B succeeds in taking the same lock since they are from the same port.
1168  * pf A takes the per pf misc lock. Performs eeprom access.
1169  * pf A finishes. Unlocks the per pf misc lock.
1170  * Pf B takes the lock and proceeds to perform it's own access.
1171  * pf A unlocks the per port lock, while pf B is still working (!).
1172  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1173  * access corrupted by pf B)
1174  */
1175 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1176 {
1177         int port = BP_PORT(bp);
1178         int count, i;
1179         uint32_t val;
1180
1181         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1182         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1183
1184         /* adjust timeout for emulation/FPGA */
1185         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1186         if (CHIP_REV_IS_SLOW(bp))
1187                 count *= 100;
1188
1189         /* request access to nvram interface */
1190         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1191                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1192
1193         for (i = 0; i < count*10; i++) {
1194                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1195                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1196                         break;
1197
1198                 udelay(5);
1199         }
1200
1201         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1202                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1203                    "cannot get access to nvram interface\n");
1204                 return -EBUSY;
1205         }
1206
1207         return 0;
1208 }
1209
1210 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1211 {
1212         int port = BP_PORT(bp);
1213         int count, i;
1214         uint32_t val;
1215
1216         /* adjust timeout for emulation/FPGA */
1217         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1218         if (CHIP_REV_IS_SLOW(bp))
1219                 count *= 100;
1220
1221         /* relinquish nvram interface */
1222         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1223                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1224
1225         for (i = 0; i < count*10; i++) {
1226                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1227                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1228                         break;
1229
1230                 udelay(5);
1231         }
1232
1233         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1234                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1235                    "cannot free access to nvram interface\n");
1236                 return -EBUSY;
1237         }
1238
1239         /* release HW lock: protect against other PFs in PF Direct Assignment */
1240         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1241         return 0;
1242 }
1243
1244 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1245 {
1246         uint32_t val;
1247
1248         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1249
1250         /* enable both bits, even on read */
1251         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1252                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1253                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1254 }
1255
1256 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1257 {
1258         uint32_t val;
1259
1260         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1261
1262         /* disable both bits, even after read */
1263         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1264                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1265                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1266 }
1267
1268 static int bnx2x_nvram_read_dword(struct bnx2x *bp, uint32_t offset,
1269                                   __be32 *ret_val,
1270                                   uint32_t cmd_flags)
1271 {
1272         int count, i, rc;
1273         uint32_t val;
1274
1275         /* build the command word */
1276         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1277
1278         /* need to clear DONE bit separately */
1279         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1280
1281         /* address of the NVRAM to read from */
1282         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1283                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1284
1285         /* issue a read command */
1286         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1287
1288         /* adjust timeout for emulation/FPGA */
1289         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1290         if (CHIP_REV_IS_SLOW(bp))
1291                 count *= 100;
1292
1293         /* wait for completion */
1294         *ret_val = 0;
1295         rc = -EBUSY;
1296         for (i = 0; i < count; i++) {
1297                 udelay(5);
1298                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1299
1300                 if (val & MCPR_NVM_COMMAND_DONE) {
1301                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1302                         /* we read nvram data in cpu order
1303                          * but ethtool sees it as an array of bytes
1304                          * converting to big-endian will do the work
1305                          */
1306                         *ret_val = cpu_to_be32(val);
1307                         rc = 0;
1308                         break;
1309                 }
1310         }
1311         if (rc == -EBUSY)
1312                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1313                    "nvram read timeout expired\n");
1314         return rc;
1315 }
1316
1317 static int bnx2x_nvram_read(struct bnx2x *bp, uint32_t offset,
1318                             uint8_t *ret_buf,
1319                             int buf_size)
1320 {
1321         int rc;
1322         uint32_t cmd_flags;
1323         __be32 val;
1324
1325         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1326                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1327                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1328                    offset, buf_size);
1329                 return -EINVAL;
1330         }
1331
1332         if (offset + buf_size > bp->common.flash_size) {
1333                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1334                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1335                    offset, buf_size, bp->common.flash_size);
1336                 return -EINVAL;
1337         }
1338
1339         /* request access to nvram interface */
1340         rc = bnx2x_acquire_nvram_lock(bp);
1341         if (rc)
1342                 return rc;
1343
1344         /* enable access to nvram interface */
1345         bnx2x_enable_nvram_access(bp);
1346
1347         /* read the first word(s) */
1348         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1349         while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
1350                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1351                 memcpy(ret_buf, &val, 4);
1352
1353                 /* advance to the next dword */
1354                 offset += sizeof(uint32_t);
1355                 ret_buf += sizeof(uint32_t);
1356                 buf_size -= sizeof(uint32_t);
1357                 cmd_flags = 0;
1358         }
1359
1360         if (rc == 0) {
1361                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1362                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1363                 memcpy(ret_buf, &val, 4);
1364         }
1365
1366         /* disable access to nvram interface */
1367         bnx2x_disable_nvram_access(bp);
1368         bnx2x_release_nvram_lock(bp);
1369
1370         return rc;
1371 }
1372
1373 static int bnx2x_nvram_read32(struct bnx2x *bp, uint32_t offset,
1374                               uint32_t *buf,
1375                               int buf_size)
1376 {
1377         int rc;
1378
1379         rc = bnx2x_nvram_read(bp, offset, (uint8_t *)buf, buf_size);
1380
1381         if (!rc) {
1382                 __be32 *be = (__be32 *)buf;
1383
1384                 while ((buf_size -= 4) >= 0)
1385                         *buf++ = be32_to_cpu(*be++);
1386         }
1387
1388         return rc;
1389 }
1390
1391 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1392 {
1393         int rc = 1;
1394         uint16_t pm = 0;
1395         struct ether *dev = pci_get_drvdata(bp->pdev);
1396
1397         if (bp->pdev->pm_cap)
1398                 rc = pci_read_config_word(bp->pdev,
1399                                           bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1400
1401         if ((rc && !netif_running(dev)) ||
1402             (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force uint16_t)PCI_D0)))
1403                 return false;
1404
1405         return true;
1406 }
1407
1408 static int bnx2x_get_eeprom(struct ether *dev,
1409                             struct ethtool_eeprom *eeprom, uint8_t *eebuf)
1410 {
1411         struct bnx2x *bp = netdev_priv(dev);
1412
1413         if (!bnx2x_is_nvm_accessible(bp)) {
1414                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1415                    "cannot access eeprom when the interface is down\n");
1416                 return -EAGAIN;
1417         }
1418
1419         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1420            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1421            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1422            eeprom->len, eeprom->len);
1423
1424         /* parameters already validated in ethtool_get_eeprom */
1425
1426         return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1427 }
1428
1429 static int bnx2x_get_module_eeprom(struct ether *dev,
1430                                    struct ethtool_eeprom *ee,
1431                                    uint8_t *data)
1432 {
1433         struct bnx2x *bp = netdev_priv(dev);
1434         int rc = -EINVAL, phy_idx;
1435         uint8_t *user_data = data;
1436         unsigned int start_addr = ee->offset, xfer_size = 0;
1437
1438         if (!bnx2x_is_nvm_accessible(bp)) {
1439                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1440                    "cannot access eeprom when the interface is down\n");
1441                 return -EAGAIN;
1442         }
1443
1444         phy_idx = bnx2x_get_cur_phy_idx(bp);
1445
1446         /* Read A0 section */
1447         if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1448                 /* Limit transfer size to the A0 section boundary */
1449                 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1450                         xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1451                 else
1452                         xfer_size = ee->len;
1453                 bnx2x_acquire_phy_lock(bp);
1454                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1455                                                   &bp->link_params,
1456                                                   I2C_DEV_ADDR_A0,
1457                                                   start_addr,
1458                                                   xfer_size,
1459                                                   user_data);
1460                 bnx2x_release_phy_lock(bp);
1461                 if (rc) {
1462                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1463
1464                         return -EINVAL;
1465                 }
1466                 user_data += xfer_size;
1467                 start_addr += xfer_size;
1468         }
1469
1470         /* Read A2 section */
1471         if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1472             (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1473                 xfer_size = ee->len - xfer_size;
1474                 /* Limit transfer size to the A2 section boundary */
1475                 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1476                         xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1477                 start_addr -= ETH_MODULE_SFF_8079_LEN;
1478                 bnx2x_acquire_phy_lock(bp);
1479                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1480                                                   &bp->link_params,
1481                                                   I2C_DEV_ADDR_A2,
1482                                                   start_addr,
1483                                                   xfer_size,
1484                                                   user_data);
1485                 bnx2x_release_phy_lock(bp);
1486                 if (rc) {
1487                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1488                         return -EINVAL;
1489                 }
1490         }
1491         return rc;
1492 }
1493
1494 static int bnx2x_get_module_info(struct ether *dev,
1495                                  struct ethtool_modinfo *modinfo)
1496 {
1497         struct bnx2x *bp = netdev_priv(dev);
1498         int phy_idx, rc;
1499         uint8_t sff8472_comp, diag_type;
1500
1501         if (!bnx2x_is_nvm_accessible(bp)) {
1502                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1503                    "cannot access eeprom when the interface is down\n");
1504                 return -EAGAIN;
1505         }
1506         phy_idx = bnx2x_get_cur_phy_idx(bp);
1507         bnx2x_acquire_phy_lock(bp);
1508         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1509                                           &bp->link_params,
1510                                           I2C_DEV_ADDR_A0,
1511                                           SFP_EEPROM_SFF_8472_COMP_ADDR,
1512                                           SFP_EEPROM_SFF_8472_COMP_SIZE,
1513                                           &sff8472_comp);
1514         bnx2x_release_phy_lock(bp);
1515         if (rc) {
1516                 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1517                 return -EINVAL;
1518         }
1519
1520         bnx2x_acquire_phy_lock(bp);
1521         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1522                                           &bp->link_params,
1523                                           I2C_DEV_ADDR_A0,
1524                                           SFP_EEPROM_DIAG_TYPE_ADDR,
1525                                           SFP_EEPROM_DIAG_TYPE_SIZE,
1526                                           &diag_type);
1527         bnx2x_release_phy_lock(bp);
1528         if (rc) {
1529                 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1530                 return -EINVAL;
1531         }
1532
1533         if (!sff8472_comp ||
1534             (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1535                 modinfo->type = ETH_MODULE_SFF_8079;
1536                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1537         } else {
1538                 modinfo->type = ETH_MODULE_SFF_8472;
1539                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1540         }
1541         return 0;
1542 }
1543
1544 static int bnx2x_nvram_write_dword(struct bnx2x *bp, uint32_t offset,
1545                                    uint32_t val,
1546                                    uint32_t cmd_flags)
1547 {
1548         int count, i, rc;
1549
1550         /* build the command word */
1551         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1552
1553         /* need to clear DONE bit separately */
1554         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1555
1556         /* write the data */
1557         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1558
1559         /* address of the NVRAM to write to */
1560         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1561                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1562
1563         /* issue the write command */
1564         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1565
1566         /* adjust timeout for emulation/FPGA */
1567         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1568         if (CHIP_REV_IS_SLOW(bp))
1569                 count *= 100;
1570
1571         /* wait for completion */
1572         rc = -EBUSY;
1573         for (i = 0; i < count; i++) {
1574                 udelay(5);
1575                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1576                 if (val & MCPR_NVM_COMMAND_DONE) {
1577                         rc = 0;
1578                         break;
1579                 }
1580         }
1581
1582         if (rc == -EBUSY)
1583                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1584                    "nvram write timeout expired\n");
1585         return rc;
1586 }
1587
1588 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1589
1590 static int bnx2x_nvram_write1(struct bnx2x *bp, uint32_t offset,
1591                               uint8_t *data_buf,
1592                               int buf_size)
1593 {
1594         int rc;
1595         uint32_t cmd_flags, align_offset, val;
1596         __be32 val_be;
1597
1598         if (offset + buf_size > bp->common.flash_size) {
1599                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1600                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1601                    offset, buf_size, bp->common.flash_size);
1602                 return -EINVAL;
1603         }
1604
1605         /* request access to nvram interface */
1606         rc = bnx2x_acquire_nvram_lock(bp);
1607         if (rc)
1608                 return rc;
1609
1610         /* enable access to nvram interface */
1611         bnx2x_enable_nvram_access(bp);
1612
1613         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1614         align_offset = (offset & ~0x03);
1615         rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1616
1617         if (rc == 0) {
1618                 /* nvram data is returned as an array of bytes
1619                  * convert it back to cpu order
1620                  */
1621                 val = be32_to_cpu(val_be);
1622
1623                 val &= ~le32_to_cpu((__force __le32)
1624                                     (0xff << BYTE_OFFSET(offset)));
1625                 val |= le32_to_cpu((__force __le32)
1626                                    (*data_buf << BYTE_OFFSET(offset)));
1627
1628                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1629                                              cmd_flags);
1630         }
1631
1632         /* disable access to nvram interface */
1633         bnx2x_disable_nvram_access(bp);
1634         bnx2x_release_nvram_lock(bp);
1635
1636         return rc;
1637 }
1638
1639 static int bnx2x_nvram_write(struct bnx2x *bp, uint32_t offset,
1640                              uint8_t *data_buf,
1641                              int buf_size)
1642 {
1643         int rc;
1644         uint32_t cmd_flags;
1645         uint32_t val;
1646         uint32_t written_so_far;
1647
1648         if (buf_size == 1)      /* ethtool */
1649                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1650
1651         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1652                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1653                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1654                    offset, buf_size);
1655                 return -EINVAL;
1656         }
1657
1658         if (offset + buf_size > bp->common.flash_size) {
1659                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1660                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1661                    offset, buf_size, bp->common.flash_size);
1662                 return -EINVAL;
1663         }
1664
1665         /* request access to nvram interface */
1666         rc = bnx2x_acquire_nvram_lock(bp);
1667         if (rc)
1668                 return rc;
1669
1670         /* enable access to nvram interface */
1671         bnx2x_enable_nvram_access(bp);
1672
1673         written_so_far = 0;
1674         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1675         while ((written_so_far < buf_size) && (rc == 0)) {
1676                 if (written_so_far == (buf_size - sizeof(uint32_t)))
1677                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1678                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1679                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1680                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1681                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1682
1683                 memcpy(&val, data_buf, 4);
1684
1685                 /* Notice unlike bnx2x_nvram_read_dword() this will not
1686                  * change val using be32_to_cpu(), which causes data to flip
1687                  * if the eeprom is read and then written back. This is due
1688                  * to tools utilizing this functionality that would break
1689                  * if this would be resolved.
1690                  */
1691                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1692
1693                 /* advance to the next dword */
1694                 offset += sizeof(uint32_t);
1695                 data_buf += sizeof(uint32_t);
1696                 written_so_far += sizeof(uint32_t);
1697                 cmd_flags = 0;
1698         }
1699
1700         /* disable access to nvram interface */
1701         bnx2x_disable_nvram_access(bp);
1702         bnx2x_release_nvram_lock(bp);
1703
1704         return rc;
1705 }
1706
1707 static int bnx2x_set_eeprom(struct ether *dev,
1708                             struct ethtool_eeprom *eeprom, uint8_t *eebuf)
1709 {
1710         struct bnx2x *bp = netdev_priv(dev);
1711         int port = BP_PORT(bp);
1712         int rc = 0;
1713         uint32_t ext_phy_config;
1714
1715         if (!bnx2x_is_nvm_accessible(bp)) {
1716                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1717                    "cannot access eeprom when the interface is down\n");
1718                 return -EAGAIN;
1719         }
1720
1721         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1722            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1723            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1724            eeprom->len, eeprom->len);
1725
1726         /* parameters already validated in ethtool_set_eeprom */
1727
1728         /* PHY eeprom can be accessed only by the PMF */
1729         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1730             !bp->port.pmf) {
1731                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1732                    "wrong magic or interface is not pmf\n");
1733                 return -EINVAL;
1734         }
1735
1736         ext_phy_config =
1737                 SHMEM_RD(bp,
1738                          dev_info.port_hw_config[port].external_phy_config);
1739
1740         if (eeprom->magic == 0x50485950) {
1741                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1742                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1743
1744                 bnx2x_acquire_phy_lock(bp);
1745                 rc |= bnx2x_link_reset(&bp->link_params,
1746                                        &bp->link_vars, 0);
1747                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1748                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1749                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1750                                        MISC_REGISTERS_GPIO_HIGH, port);
1751                 bnx2x_release_phy_lock(bp);
1752                 bnx2x_link_report(bp);
1753
1754         } else if (eeprom->magic == 0x50485952) {
1755                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1756                 if (bp->state == BNX2X_STATE_OPEN) {
1757                         bnx2x_acquire_phy_lock(bp);
1758                         rc |= bnx2x_link_reset(&bp->link_params,
1759                                                &bp->link_vars, 1);
1760
1761                         rc |= bnx2x_phy_init(&bp->link_params,
1762                                              &bp->link_vars);
1763                         bnx2x_release_phy_lock(bp);
1764                         bnx2x_calc_fc_adv(bp);
1765                 }
1766         } else if (eeprom->magic == 0x53985943) {
1767                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1768                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1769                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1770
1771                         /* DSP Remove Download Mode */
1772                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1773                                        MISC_REGISTERS_GPIO_LOW, port);
1774
1775                         bnx2x_acquire_phy_lock(bp);
1776
1777                         bnx2x_sfx7101_sp_sw_reset(bp,
1778                                                 &bp->link_params.phy[EXT_PHY1]);
1779
1780                         /* wait 0.5 sec to allow it to run */
1781                         kthread_usleep(1000 * 500);
1782                         bnx2x_ext_phy_hw_reset(bp, port);
1783                         kthread_usleep(1000 * 500);
1784                         bnx2x_release_phy_lock(bp);
1785                 }
1786         } else
1787                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1788
1789         return rc;
1790 }
1791
1792 static int bnx2x_get_coalesce(struct ether *dev,
1793                               struct ethtool_coalesce *coal)
1794 {
1795         struct bnx2x *bp = netdev_priv(dev);
1796
1797         memset(coal, 0, sizeof(struct ethtool_coalesce));
1798
1799         coal->rx_coalesce_usecs = bp->rx_ticks;
1800         coal->tx_coalesce_usecs = bp->tx_ticks;
1801
1802         return 0;
1803 }
1804
1805 static int bnx2x_set_coalesce(struct ether *dev,
1806                               struct ethtool_coalesce *coal)
1807 {
1808         struct bnx2x *bp = netdev_priv(dev);
1809
1810         bp->rx_ticks = (uint16_t)coal->rx_coalesce_usecs;
1811         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1812                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1813
1814         bp->tx_ticks = (uint16_t)coal->tx_coalesce_usecs;
1815         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1816                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1817
1818         if (netif_running(dev))
1819                 bnx2x_update_coalesce(bp);
1820
1821         return 0;
1822 }
1823
1824 static void bnx2x_get_ringparam(struct ether *dev,
1825                                 struct ethtool_ringparam *ering)
1826 {
1827         struct bnx2x *bp = netdev_priv(dev);
1828
1829         ering->rx_max_pending = MAX_RX_AVAIL;
1830
1831         if (bp->rx_ring_size)
1832                 ering->rx_pending = bp->rx_ring_size;
1833         else
1834                 ering->rx_pending = MAX_RX_AVAIL;
1835
1836         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1837         ering->tx_pending = bp->tx_ring_size;
1838 }
1839
1840 static int bnx2x_set_ringparam(struct ether *dev,
1841                                struct ethtool_ringparam *ering)
1842 {
1843         struct bnx2x *bp = netdev_priv(dev);
1844
1845         DP(BNX2X_MSG_ETHTOOL,
1846            "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1847            ering->rx_pending, ering->tx_pending);
1848
1849         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1850                 DP(BNX2X_MSG_ETHTOOL,
1851                    "Handling parity error recovery. Try again later\n");
1852                 return -EAGAIN;
1853         }
1854
1855         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1856             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1857                                                     MIN_RX_SIZE_TPA)) ||
1858             (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1859             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1860                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1861                 return -EINVAL;
1862         }
1863
1864         bp->rx_ring_size = ering->rx_pending;
1865         bp->tx_ring_size = ering->tx_pending;
1866
1867         return bnx2x_reload_if_running(dev);
1868 }
1869
1870 static void bnx2x_get_pauseparam(struct ether *dev,
1871                                  struct ethtool_pauseparam *epause)
1872 {
1873         struct bnx2x *bp = netdev_priv(dev);
1874         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1875         int cfg_reg;
1876
1877         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1878                            BNX2X_FLOW_CTRL_AUTO);
1879
1880         if (!epause->autoneg)
1881                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1882         else
1883                 cfg_reg = bp->link_params.req_fc_auto_adv;
1884
1885         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1886                             BNX2X_FLOW_CTRL_RX);
1887         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1888                             BNX2X_FLOW_CTRL_TX);
1889
1890         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1891            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1892            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1893 }
1894
1895 static int bnx2x_set_pauseparam(struct ether *dev,
1896                                 struct ethtool_pauseparam *epause)
1897 {
1898         struct bnx2x *bp = netdev_priv(dev);
1899         uint32_t cfg_idx = bnx2x_get_link_cfg_idx(bp);
1900         if (IS_MF(bp))
1901                 return 0;
1902
1903         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1904            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1905            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1906
1907         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1908
1909         if (epause->rx_pause)
1910                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1911
1912         if (epause->tx_pause)
1913                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1914
1915         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1916                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1917
1918         if (epause->autoneg) {
1919                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1920                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1921                         return -EINVAL;
1922                 }
1923
1924                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1925                         bp->link_params.req_flow_ctrl[cfg_idx] =
1926                                 BNX2X_FLOW_CTRL_AUTO;
1927                 }
1928                 bp->link_params.req_fc_auto_adv = 0;
1929                 if (epause->rx_pause)
1930                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1931
1932                 if (epause->tx_pause)
1933                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1934
1935                 if (!bp->link_params.req_fc_auto_adv)
1936                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1937         }
1938
1939         DP(BNX2X_MSG_ETHTOOL,
1940            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1941
1942         if (netif_running(dev)) {
1943                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1944                 bnx2x_link_set(bp);
1945         }
1946
1947         return 0;
1948 }
1949
1950 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1951         "register_test (offline)    ",
1952         "memory_test (offline)      ",
1953         "int_loopback_test (offline)",
1954         "ext_loopback_test (offline)",
1955         "nvram_test (online)        ",
1956         "interrupt_test (online)    ",
1957         "link_test (online)         "
1958 };
1959
1960 enum {
1961         BNX2X_PRI_FLAG_ISCSI,
1962         BNX2X_PRI_FLAG_FCOE,
1963         BNX2X_PRI_FLAG_STORAGE,
1964         BNX2X_PRI_FLAG_LEN,
1965 };
1966
1967 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
1968         "iSCSI offload support",
1969         "FCoE offload support",
1970         "Storage only interface"
1971 };
1972
1973 static uint32_t bnx2x_eee_to_adv(uint32_t eee_adv)
1974 {
1975         uint32_t modes = 0;
1976
1977         if (eee_adv & SHMEM_EEE_100M_ADV)
1978                 modes |= ADVERTISED_100baseT_Full;
1979         if (eee_adv & SHMEM_EEE_1G_ADV)
1980                 modes |= ADVERTISED_1000baseT_Full;
1981         if (eee_adv & SHMEM_EEE_10G_ADV)
1982                 modes |= ADVERTISED_10000baseT_Full;
1983
1984         return modes;
1985 }
1986
1987 static uint32_t bnx2x_adv_to_eee(uint32_t modes, uint32_t shift)
1988 {
1989         uint32_t eee_adv = 0;
1990         if (modes & ADVERTISED_100baseT_Full)
1991                 eee_adv |= SHMEM_EEE_100M_ADV;
1992         if (modes & ADVERTISED_1000baseT_Full)
1993                 eee_adv |= SHMEM_EEE_1G_ADV;
1994         if (modes & ADVERTISED_10000baseT_Full)
1995                 eee_adv |= SHMEM_EEE_10G_ADV;
1996
1997         return eee_adv << shift;
1998 }
1999
2000 static int bnx2x_get_eee(struct ether *dev, struct ethtool_eee *edata)
2001 {
2002         struct bnx2x *bp = netdev_priv(dev);
2003         uint32_t eee_cfg;
2004
2005         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2006                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2007                 return -EOPNOTSUPP;
2008         }
2009
2010         eee_cfg = bp->link_vars.eee_status;
2011
2012         edata->supported =
2013                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2014                                  SHMEM_EEE_SUPPORTED_SHIFT);
2015
2016         edata->advertised =
2017                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2018                                  SHMEM_EEE_ADV_STATUS_SHIFT);
2019         edata->lp_advertised =
2020                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2021                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2022
2023         /* SHMEM value is in 16u units --> Convert to 1u units. */
2024         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2025
2026         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
2027         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
2028         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2029
2030         return 0;
2031 }
2032
2033 static int bnx2x_set_eee(struct ether *dev, struct ethtool_eee *edata)
2034 {
2035         struct bnx2x *bp = netdev_priv(dev);
2036         uint32_t eee_cfg;
2037         uint32_t advertised;
2038
2039         if (IS_MF(bp))
2040                 return 0;
2041
2042         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2043                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2044                 return -EOPNOTSUPP;
2045         }
2046
2047         eee_cfg = bp->link_vars.eee_status;
2048
2049         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2050                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2051                 return -EOPNOTSUPP;
2052         }
2053
2054         advertised = bnx2x_adv_to_eee(edata->advertised,
2055                                       SHMEM_EEE_ADV_STATUS_SHIFT);
2056         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2057                 DP(BNX2X_MSG_ETHTOOL,
2058                    "Direct manipulation of EEE advertisement is not supported\n");
2059                 return -EINVAL;
2060         }
2061
2062         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2063                 DP(BNX2X_MSG_ETHTOOL,
2064                    "Maximal Tx Lpi timer supported is %x(u)\n",
2065                    EEE_MODE_TIMER_MASK);
2066                 return -EINVAL;
2067         }
2068         if (edata->tx_lpi_enabled &&
2069             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2070                 DP(BNX2X_MSG_ETHTOOL,
2071                    "Minimal Tx Lpi timer supported is %d(u)\n",
2072                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2073                 return -EINVAL;
2074         }
2075
2076         /* All is well; Apply changes*/
2077         if (edata->eee_enabled)
2078                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2079         else
2080                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2081
2082         if (edata->tx_lpi_enabled)
2083                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2084         else
2085                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2086
2087         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2088         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2089                                     EEE_MODE_TIMER_MASK) |
2090                                     EEE_MODE_OVERRIDE_NVRAM |
2091                                     EEE_MODE_OUTPUT_TIME;
2092
2093         /* Restart link to propagate changes */
2094         if (netif_running(dev)) {
2095                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2096                 bnx2x_force_link_reset(bp);
2097                 bnx2x_link_set(bp);
2098         }
2099
2100         return 0;
2101 }
2102
2103 enum {
2104         BNX2X_CHIP_E1_OFST = 0,
2105         BNX2X_CHIP_E1H_OFST,
2106         BNX2X_CHIP_E2_OFST,
2107         BNX2X_CHIP_E3_OFST,
2108         BNX2X_CHIP_E3B0_OFST,
2109         BNX2X_CHIP_MAX_OFST
2110 };
2111
2112 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
2113 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
2114 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
2115 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
2116 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
2117
2118 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2119 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2120
2121 static int bnx2x_test_registers(struct bnx2x *bp)
2122 {
2123         int idx, i, rc = -ENODEV;
2124         uint32_t wr_val = 0, hw;
2125         int port = BP_PORT(bp);
2126         static const struct {
2127                 uint32_t hw;
2128                 uint32_t offset0;
2129                 uint32_t offset1;
2130                 uint32_t mask;
2131         } reg_tbl[] = {
2132 /* 0 */         { BNX2X_CHIP_MASK_ALL,
2133                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2134                 { BNX2X_CHIP_MASK_ALL,
2135                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2136                 { BNX2X_CHIP_MASK_E1X,
2137                         HC_REG_AGG_INT_0,               4, 0x000003ff },
2138                 { BNX2X_CHIP_MASK_ALL,
2139                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2140                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2141                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2142                 { BNX2X_CHIP_MASK_E3B0,
2143                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2144                 { BNX2X_CHIP_MASK_ALL,
2145                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2146                 { BNX2X_CHIP_MASK_ALL,
2147                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2148                 { BNX2X_CHIP_MASK_ALL,
2149                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2150                 { BNX2X_CHIP_MASK_ALL,
2151                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2152 /* 10 */        { BNX2X_CHIP_MASK_ALL,
2153                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2154                 { BNX2X_CHIP_MASK_ALL,
2155                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2156                 { BNX2X_CHIP_MASK_ALL,
2157                         QM_REG_CONNNUM_0,               4, 0x000fffff },
2158                 { BNX2X_CHIP_MASK_ALL,
2159                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2160                 { BNX2X_CHIP_MASK_ALL,
2161                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2162                 { BNX2X_CHIP_MASK_ALL,
2163                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2164                 { BNX2X_CHIP_MASK_ALL,
2165                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2166                 { BNX2X_CHIP_MASK_ALL,
2167                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2168                 { BNX2X_CHIP_MASK_ALL,
2169                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2170                 { BNX2X_CHIP_MASK_ALL,
2171                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2172 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2173                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2174                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2175                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2176                 { BNX2X_CHIP_MASK_ALL,
2177                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2178                 { BNX2X_CHIP_MASK_ALL,
2179                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2180                 { BNX2X_CHIP_MASK_ALL,
2181                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2182                 { BNX2X_CHIP_MASK_ALL,
2183                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2184                 { BNX2X_CHIP_MASK_ALL,
2185                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2186                 { BNX2X_CHIP_MASK_ALL,
2187                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2188                 { BNX2X_CHIP_MASK_ALL,
2189                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2190                 { BNX2X_CHIP_MASK_ALL,
2191                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2192 /* 30 */        { BNX2X_CHIP_MASK_ALL,
2193                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2194                 { BNX2X_CHIP_MASK_ALL,
2195                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2196                 { BNX2X_CHIP_MASK_ALL,
2197                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2198                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2199                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2200                 { BNX2X_CHIP_MASK_ALL,
2201                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2202                 { BNX2X_CHIP_MASK_ALL,
2203                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2204                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2205                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2206                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2207                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2208
2209                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2210         };
2211
2212         if (!bnx2x_is_nvm_accessible(bp)) {
2213                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2214                    "cannot access eeprom when the interface is down\n");
2215                 return rc;
2216         }
2217
2218         if (CHIP_IS_E1(bp))
2219                 hw = BNX2X_CHIP_MASK_E1;
2220         else if (CHIP_IS_E1H(bp))
2221                 hw = BNX2X_CHIP_MASK_E1H;
2222         else if (CHIP_IS_E2(bp))
2223                 hw = BNX2X_CHIP_MASK_E2;
2224         else if (CHIP_IS_E3B0(bp))
2225                 hw = BNX2X_CHIP_MASK_E3B0;
2226         else /* e3 A0 */
2227                 hw = BNX2X_CHIP_MASK_E3;
2228
2229         /* Repeat the test twice:
2230          * First by writing 0x00000000, second by writing 0xffffffff
2231          */
2232         for (idx = 0; idx < 2; idx++) {
2233
2234                 switch (idx) {
2235                 case 0:
2236                         wr_val = 0;
2237                         break;
2238                 case 1:
2239                         wr_val = 0xffffffff;
2240                         break;
2241                 }
2242
2243                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2244                         uint32_t offset, mask, save_val, val;
2245                         if (!(hw & reg_tbl[i].hw))
2246                                 continue;
2247
2248                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2249                         mask = reg_tbl[i].mask;
2250
2251                         save_val = REG_RD(bp, offset);
2252
2253                         REG_WR(bp, offset, wr_val & mask);
2254
2255                         val = REG_RD(bp, offset);
2256
2257                         /* Restore the original register's value */
2258                         REG_WR(bp, offset, save_val);
2259
2260                         /* verify value is as expected */
2261                         if ((val & mask) != (wr_val & mask)) {
2262                                 DP(BNX2X_MSG_ETHTOOL,
2263                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2264                                    offset, val, wr_val, mask);
2265                                 goto test_reg_exit;
2266                         }
2267                 }
2268         }
2269
2270         rc = 0;
2271
2272 test_reg_exit:
2273         return rc;
2274 }
2275
2276 static int bnx2x_test_memory(struct bnx2x *bp)
2277 {
2278         int i, j, rc = -ENODEV;
2279         uint32_t val, index;
2280         static const struct {
2281                 uint32_t offset;
2282                 int size;
2283         } mem_tbl[] = {
2284                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2285                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2286                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2287                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2288                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2289                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2290                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2291
2292                 { 0xffffffff, 0 }
2293         };
2294
2295         static const struct {
2296                 char *name;
2297                 uint32_t offset;
2298                 uint32_t hw_mask[BNX2X_CHIP_MAX_OFST];
2299         } prty_tbl[] = {
2300                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2301                         {0x3ffc0, 0,   0, 0} },
2302                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2303                         {0x2,     0x2, 0, 0} },
2304                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2305                         {0,       0,   0, 0} },
2306                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2307                         {0x3ffc0, 0,   0, 0} },
2308                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2309                         {0x3ffc0, 0,   0, 0} },
2310                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2311                         {0x3ffc1, 0,   0, 0} },
2312
2313                 { NULL, 0xffffffff, {0, 0, 0, 0} }
2314         };
2315
2316         if (!bnx2x_is_nvm_accessible(bp)) {
2317                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2318                    "cannot access eeprom when the interface is down\n");
2319                 return rc;
2320         }
2321
2322         if (CHIP_IS_E1(bp))
2323                 index = BNX2X_CHIP_E1_OFST;
2324         else if (CHIP_IS_E1H(bp))
2325                 index = BNX2X_CHIP_E1H_OFST;
2326         else if (CHIP_IS_E2(bp))
2327                 index = BNX2X_CHIP_E2_OFST;
2328         else /* e3 */
2329                 index = BNX2X_CHIP_E3_OFST;
2330
2331         /* pre-Check the parity status */
2332         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2333                 val = REG_RD(bp, prty_tbl[i].offset);
2334                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2335                         DP(BNX2X_MSG_ETHTOOL,
2336                            "%s is 0x%x\n", prty_tbl[i].name, val);
2337                         goto test_mem_exit;
2338                 }
2339         }
2340
2341         /* Go through all the memories */
2342         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2343                 for (j = 0; j < mem_tbl[i].size; j++)
2344                         REG_RD(bp, mem_tbl[i].offset + j*4);
2345
2346         /* Check the parity status */
2347         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2348                 val = REG_RD(bp, prty_tbl[i].offset);
2349                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2350                         DP(BNX2X_MSG_ETHTOOL,
2351                            "%s is 0x%x\n", prty_tbl[i].name, val);
2352                         goto test_mem_exit;
2353                 }
2354         }
2355
2356         rc = 0;
2357
2358 test_mem_exit:
2359         return rc;
2360 }
2361
2362 static void bnx2x_wait_for_link(struct bnx2x *bp, uint8_t link_up,
2363                                 uint8_t is_serdes)
2364 {
2365         int cnt = 1400;
2366
2367         if (link_up) {
2368                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2369                         kthread_usleep(1000 * 20);
2370
2371                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2372                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2373
2374                 cnt = 1400;
2375                 while (!bp->link_vars.link_up && cnt--)
2376                         kthread_usleep(1000 * 20);
2377
2378                 if (cnt <= 0 && !bp->link_vars.link_up)
2379                         DP(BNX2X_MSG_ETHTOOL,
2380                            "Timeout waiting for link init\n");
2381         }
2382 }
2383
2384 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2385 {
2386         unsigned int pkt_size, num_pkts, i;
2387         struct sk_buff *skb;
2388         unsigned char *packet;
2389         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2390         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2391         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2392         uint16_t tx_start_idx, tx_idx;
2393         uint16_t rx_start_idx, rx_idx;
2394         uint16_t pkt_prod, bd_prod;
2395         struct sw_tx_bd *tx_buf;
2396         struct eth_tx_start_bd *tx_start_bd;
2397         dma_addr_t mapping;
2398         union eth_rx_cqe *cqe;
2399         uint8_t cqe_fp_flags, cqe_fp_type;
2400         struct sw_rx_bd *rx_buf;
2401         uint16_t len;
2402         int rc = -ENODEV;
2403         uint8_t *data;
2404         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2405                                                        txdata->txq_index);
2406
2407         /* check the loopback mode */
2408         switch (loopback_mode) {
2409         case BNX2X_PHY_LOOPBACK:
2410                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2411                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2412                         return -EINVAL;
2413                 }
2414                 break;
2415         case BNX2X_MAC_LOOPBACK:
2416                 if (CHIP_IS_E3(bp)) {
2417                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2418                         if (bp->port.supported[cfg_idx] &
2419                             (SUPPORTED_10000baseT_Full |
2420                              SUPPORTED_20000baseMLD2_Full |
2421                              SUPPORTED_20000baseKR2_Full))
2422                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2423                         else
2424                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2425                 } else
2426                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2427
2428                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2429                 break;
2430         case BNX2X_EXT_LOOPBACK:
2431                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2432                         DP(BNX2X_MSG_ETHTOOL,
2433                            "Can't configure external loopback\n");
2434                         return -EINVAL;
2435                 }
2436                 break;
2437         default:
2438                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2439                 return -EINVAL;
2440         }
2441
2442         /* prepare the loopback packet */
2443         pkt_size = (((bp->dev->maxmtu < ETH_MAX_PACKET_SIZE) ?
2444                      bp->dev->maxmtu : ETH_MAX_PACKET_SIZE) + ETHERHDRSIZE);
2445         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2446         if (!skb) {
2447                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2448                 rc = -ENOMEM;
2449                 goto test_loopback_exit;
2450         }
2451         packet = skb_put(skb, pkt_size);
2452         memcpy(packet, bp->dev->dev_addr, Eaddrlen);
2453         memset(packet + Eaddrlen, 0, Eaddrlen);
2454         memset(packet + 2*Eaddrlen, 0x77, (ETHERHDRSIZE - 2*Eaddrlen));
2455         for (i = ETHERHDRSIZE; i < pkt_size; i++)
2456                 packet[i] = (unsigned char) (i & 0xff);
2457         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2458                                  skb_headlen(skb), DMA_TO_DEVICE);
2459         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2460                 rc = -ENOMEM;
2461                 dev_kfree_skb(skb);
2462                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2463                 goto test_loopback_exit;
2464         }
2465
2466         /* send the loopback packet */
2467         num_pkts = 0;
2468         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2469         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2470
2471         netdev_tx_sent_queue(txq, skb->len);
2472
2473         pkt_prod = txdata->tx_pkt_prod++;
2474         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2475         tx_buf->first_bd = txdata->tx_bd_prod;
2476         tx_buf->skb = skb;
2477         tx_buf->flags = 0;
2478
2479         bd_prod = TX_BD(txdata->tx_bd_prod);
2480         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2481         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2482         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2483         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2484         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2485         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2486         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2487         SET_FLAG(tx_start_bd->general_data,
2488                  ETH_TX_START_BD_HDR_NBDS,
2489                  1);
2490         SET_FLAG(tx_start_bd->general_data,
2491                  ETH_TX_START_BD_PARSE_NBDS,
2492                  0);
2493
2494         /* turn on parsing and get a BD */
2495         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2496
2497         if (CHIP_IS_E1x(bp)) {
2498                 uint16_t global_data = 0;
2499                 struct eth_tx_parse_bd_e1x  *pbd_e1x =
2500                         &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2501                 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2502                 SET_FLAG(global_data,
2503                          ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2504                 pbd_e1x->global_data = cpu_to_le16(global_data);
2505         } else {
2506                 uint32_t parsing_data = 0;
2507                 struct eth_tx_parse_bd_e2  *pbd_e2 =
2508                         &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2509                 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2510                 SET_FLAG(parsing_data,
2511                          ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2512                 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2513         }
2514         wmb();
2515
2516         txdata->tx_db.data.prod += 2;
2517         cmb();
2518         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2519
2520         bus_wmb();
2521         cmb();
2522
2523         num_pkts++;
2524         txdata->tx_bd_prod += 2; /* start + pbd */
2525
2526         udelay(100);
2527
2528         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2529         if (tx_idx != tx_start_idx + num_pkts)
2530                 goto test_loopback_exit;
2531
2532         /* Unlike HC IGU won't generate an interrupt for status block
2533          * updates that have been performed while interrupts were
2534          * disabled.
2535          */
2536         if (bp->common.int_block == INT_BLOCK_IGU) {
2537                 /* Disable local BHes to prevent a dead-lock situation between
2538                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2539                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2540                  */
2541                 local_bh_disable();
2542                 bnx2x_tx_int(bp, txdata);
2543                 local_bh_enable();
2544         }
2545
2546         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2547         if (rx_idx != rx_start_idx + num_pkts)
2548                 goto test_loopback_exit;
2549
2550         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2551         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2552         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2553         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2554                 goto test_loopback_rx_exit;
2555
2556         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2557         if (len != pkt_size)
2558                 goto test_loopback_rx_exit;
2559
2560         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2561         dma_sync_single_for_cpu(&bp->pdev->dev,
2562                                    dma_unmap_addr(rx_buf, mapping),
2563                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2564         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2565         for (i = ETHERHDRSIZE; i < pkt_size; i++)
2566                 if (*(data + i) != (unsigned char) (i & 0xff))
2567                         goto test_loopback_rx_exit;
2568
2569         rc = 0;
2570
2571 test_loopback_rx_exit:
2572
2573         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2574         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2575         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2576         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2577
2578         /* Update producers */
2579         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2580                              fp_rx->rx_sge_prod);
2581
2582 test_loopback_exit:
2583         bp->link_params.loopback_mode = LOOPBACK_NONE;
2584
2585         return rc;
2586 }
2587
2588 static int bnx2x_test_loopback(struct bnx2x *bp)
2589 {
2590         int rc = 0, res;
2591
2592         if (BP_NOMCP(bp))
2593                 return rc;
2594
2595         if (!netif_running(bp->dev))
2596                 return BNX2X_LOOPBACK_FAILED;
2597
2598         bnx2x_netif_stop(bp, 1);
2599         bnx2x_acquire_phy_lock(bp);
2600
2601         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2602         if (res) {
2603                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2604                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2605         }
2606
2607         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2608         if (res) {
2609                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2610                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2611         }
2612
2613         bnx2x_release_phy_lock(bp);
2614         bnx2x_netif_start(bp);
2615
2616         return rc;
2617 }
2618
2619 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2620 {
2621         int rc;
2622         uint8_t is_serdes =
2623                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2624
2625         if (BP_NOMCP(bp))
2626                 return -ENODEV;
2627
2628         if (!netif_running(bp->dev))
2629                 return BNX2X_EXT_LOOPBACK_FAILED;
2630
2631         bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2632         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2633         if (rc) {
2634                 DP(BNX2X_MSG_ETHTOOL,
2635                    "Can't perform self-test, nic_load (for external lb) failed\n");
2636                 return -ENODEV;
2637         }
2638         bnx2x_wait_for_link(bp, 1, is_serdes);
2639
2640         bnx2x_netif_stop(bp, 1);
2641
2642         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2643         if (rc)
2644                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2645
2646         bnx2x_netif_start(bp);
2647
2648         return rc;
2649 }
2650
2651 struct code_entry {
2652         uint32_t sram_start_addr;
2653         uint32_t code_attribute;
2654 #define CODE_IMAGE_TYPE_MASK                    0xf0800003
2655 #define CODE_IMAGE_VNTAG_PROFILES_DATA          0xd0000003
2656 #define CODE_IMAGE_LENGTH_MASK                  0x007ffffc
2657 #define CODE_IMAGE_TYPE_EXTENDED_DIR            0xe0000000
2658         uint32_t nvm_start_addr;
2659 };
2660
2661 #define CODE_ENTRY_MAX                  16
2662 #define CODE_ENTRY_EXTENDED_DIR_IDX     15
2663 #define MAX_IMAGES_IN_EXTENDED_DIR      64
2664 #define NVRAM_DIR_OFFSET                0x14
2665
2666 #define EXTENDED_DIR_EXISTS(code)                                         \
2667         ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2668          (code & CODE_IMAGE_LENGTH_MASK) != 0)
2669
2670 #define CRC32_RESIDUAL                  0xdebb20e3
2671 #define CRC_BUFF_SIZE                   256
2672
2673 static int bnx2x_nvram_crc(struct bnx2x *bp,
2674                            int offset,
2675                            int size,
2676                            uint8_t *buff)
2677 {
2678         uint32_t crc = ~0;
2679         int rc = 0, done = 0;
2680
2681         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2682            "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2683
2684         while (done < size) {
2685                 int count = MIN_T(int, size - done, CRC_BUFF_SIZE);
2686
2687                 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2688
2689                 if (rc)
2690                         return rc;
2691
2692                 crc = crc32_le(crc, buff, count);
2693                 done += count;
2694         }
2695
2696         if (crc != CRC32_RESIDUAL)
2697                 rc = -EINVAL;
2698
2699         return rc;
2700 }
2701
2702 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2703                                 struct code_entry *entry,
2704                                 uint8_t *buff)
2705 {
2706         size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2707         uint32_t type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2708         int rc;
2709
2710         /* Zero-length images and AFEX profiles do not have CRC */
2711         if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2712                 return 0;
2713
2714         rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2715         if (rc)
2716                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2717                    "image %x has failed crc test (rc %d)\n", type, rc);
2718
2719         return rc;
2720 }
2721
2722 static int bnx2x_test_dir_entry(struct bnx2x *bp, uint32_t addr,
2723                                 uint8_t *buff)
2724 {
2725         int rc;
2726         struct code_entry entry;
2727
2728         rc = bnx2x_nvram_read32(bp, addr, (uint32_t *)&entry, sizeof(entry));
2729         if (rc)
2730                 return rc;
2731
2732         return bnx2x_test_nvram_dir(bp, &entry, buff);
2733 }
2734
2735 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, uint8_t *buff)
2736 {
2737         uint32_t rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2738         struct code_entry entry;
2739         int i;
2740
2741         rc = bnx2x_nvram_read32(bp,
2742                                 dir_offset +
2743                                 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2744                                 (uint32_t *)&entry, sizeof(entry));
2745         if (rc)
2746                 return rc;
2747
2748         if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2749                 return 0;
2750
2751         rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2752                                 &cnt, sizeof(uint32_t));
2753         if (rc)
2754                 return rc;
2755
2756         dir_offset = entry.nvm_start_addr + 8;
2757
2758         for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2759                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2760                                               sizeof(struct code_entry) * i,
2761                                           buff);
2762                 if (rc)
2763                         return rc;
2764         }
2765
2766         return 0;
2767 }
2768
2769 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, uint8_t *buff)
2770 {
2771         uint32_t rc, dir_offset = NVRAM_DIR_OFFSET;
2772         int i;
2773
2774         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2775
2776         for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2777                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2778                                               sizeof(struct code_entry) * i,
2779                                           buff);
2780                 if (rc)
2781                         return rc;
2782         }
2783
2784         return bnx2x_test_nvram_ext_dirs(bp, buff);
2785 }
2786
2787 struct crc_pair {
2788         int offset;
2789         int size;
2790 };
2791
2792 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2793                                 const struct crc_pair *nvram_tbl,
2794                                 uint8_t *buf)
2795 {
2796         int i;
2797
2798         for (i = 0; nvram_tbl[i].size; i++) {
2799                 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2800                                          nvram_tbl[i].size, buf);
2801                 if (rc) {
2802                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2803                            "nvram_tbl[%d] has failed crc test (rc %d)\n",
2804                            i, rc);
2805                         return rc;
2806                 }
2807         }
2808
2809         return 0;
2810 }
2811
2812 static int bnx2x_test_nvram(struct bnx2x *bp)
2813 {
2814         const struct crc_pair nvram_tbl[] = {
2815                 {     0,  0x14 }, /* bootstrap */
2816                 {  0x14,  0xec }, /* dir */
2817                 { 0x100, 0x350 }, /* manuf_info */
2818                 { 0x450,  0xf0 }, /* feature_info */
2819                 { 0x640,  0x64 }, /* upgrade_key_info */
2820                 { 0x708,  0x70 }, /* manuf_key_info */
2821                 {     0,     0 }
2822         };
2823         const struct crc_pair nvram_tbl2[] = {
2824                 { 0x7e8, 0x350 }, /* manuf_info2 */
2825                 { 0xb38,  0xf0 }, /* feature_info */
2826                 {     0,     0 }
2827         };
2828
2829         uint8_t *buf;
2830         int rc;
2831         uint32_t magic;
2832
2833         if (BP_NOMCP(bp))
2834                 return 0;
2835
2836         buf = kmalloc(CRC_BUFF_SIZE, KMALLOC_WAIT);
2837         if (!buf) {
2838                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2839                 rc = -ENOMEM;
2840                 goto test_nvram_exit;
2841         }
2842
2843         rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2844         if (rc) {
2845                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2846                    "magic value read (rc %d)\n", rc);
2847                 goto test_nvram_exit;
2848         }
2849
2850         if (magic != 0x669955aa) {
2851                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2852                    "wrong magic value (0x%08x)\n", magic);
2853                 rc = -ENODEV;
2854                 goto test_nvram_exit;
2855         }
2856
2857         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2858         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2859         if (rc)
2860                 goto test_nvram_exit;
2861
2862         if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2863                 uint32_t hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2864                            SHARED_HW_CFG_HIDE_PORT1;
2865
2866                 if (!hide) {
2867                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2868                            "Port 1 CRC test-set\n");
2869                         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2870                         if (rc)
2871                                 goto test_nvram_exit;
2872                 }
2873         }
2874
2875         rc = bnx2x_test_nvram_dirs(bp, buf);
2876
2877 test_nvram_exit:
2878         kfree(buf);
2879         return rc;
2880 }
2881
2882 /* Send an EMPTY ramrod on the first queue */
2883 static int bnx2x_test_intr(struct bnx2x *bp)
2884 {
2885         struct bnx2x_queue_state_params params = {NULL};
2886
2887         if (!netif_running(bp->dev)) {
2888                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2889                    "cannot access eeprom when the interface is down\n");
2890                 return -ENODEV;
2891         }
2892
2893         params.q_obj = &bp->sp_objs->q_obj;
2894         params.cmd = BNX2X_Q_CMD_EMPTY;
2895
2896         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2897
2898         return bnx2x_queue_state_change(bp, &params);
2899 }
2900
2901 static void bnx2x_self_test(struct ether *dev,
2902                             struct ethtool_test *etest, uint64_t *buf)
2903 {
2904         struct bnx2x *bp = netdev_priv(dev);
2905         uint8_t is_serdes, link_up;
2906         int rc, cnt = 0;
2907
2908         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2909                 netdev_err(bp->dev,
2910                            "Handling parity error recovery. Try again later\n");
2911                 etest->flags |= ETH_TEST_FL_FAILED;
2912                 return;
2913         }
2914
2915         DP(BNX2X_MSG_ETHTOOL,
2916            "Self-test command parameters: offline = %d, external_lb = %d\n",
2917            (etest->flags & ETH_TEST_FL_OFFLINE),
2918            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2919
2920         memset(buf, 0, sizeof(uint64_t) * BNX2X_NUM_TESTS(bp));
2921
2922         if (bnx2x_test_nvram(bp) != 0) {
2923                 if (!IS_MF(bp))
2924                         buf[4] = 1;
2925                 else
2926                         buf[0] = 1;
2927                 etest->flags |= ETH_TEST_FL_FAILED;
2928         }
2929
2930         if (!netif_running(dev)) {
2931                 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2932                 return;
2933         }
2934
2935         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2936         link_up = bp->link_vars.link_up;
2937         /* offline tests are not supported in MF mode */
2938         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2939                 int port = BP_PORT(bp);
2940                 uint32_t val;
2941
2942                 /* save current value of input enable for TX port IF */
2943                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2944                 /* disable input for TX port IF */
2945                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2946
2947                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2948                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2949                 if (rc) {
2950                         etest->flags |= ETH_TEST_FL_FAILED;
2951                         DP(BNX2X_MSG_ETHTOOL,
2952                            "Can't perform self-test, nic_load (for offline) failed\n");
2953                         return;
2954                 }
2955
2956                 /* wait until link state is restored */
2957                 bnx2x_wait_for_link(bp, 1, is_serdes);
2958
2959                 if (bnx2x_test_registers(bp) != 0) {
2960                         buf[0] = 1;
2961                         etest->flags |= ETH_TEST_FL_FAILED;
2962                 }
2963                 if (bnx2x_test_memory(bp) != 0) {
2964                         buf[1] = 1;
2965                         etest->flags |= ETH_TEST_FL_FAILED;
2966                 }
2967
2968                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2969                 if (buf[2] != 0)
2970                         etest->flags |= ETH_TEST_FL_FAILED;
2971
2972                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2973                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2974                         if (buf[3] != 0)
2975                                 etest->flags |= ETH_TEST_FL_FAILED;
2976                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2977                 }
2978
2979                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2980
2981                 /* restore input for TX port IF */
2982                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2983                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2984                 if (rc) {
2985                         etest->flags |= ETH_TEST_FL_FAILED;
2986                         DP(BNX2X_MSG_ETHTOOL,
2987                            "Can't perform self-test, nic_load (for online) failed\n");
2988                         return;
2989                 }
2990                 /* wait until link state is restored */
2991                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2992         }
2993
2994         if (bnx2x_test_intr(bp) != 0) {
2995                 if (!IS_MF(bp))
2996                         buf[5] = 1;
2997                 else
2998                         buf[1] = 1;
2999                 etest->flags |= ETH_TEST_FL_FAILED;
3000         }
3001
3002         if (link_up) {
3003                 cnt = 100;
3004                 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3005                         kthread_usleep(1000 * 20);
3006         }
3007
3008         if (!cnt) {
3009                 if (!IS_MF(bp))
3010                         buf[6] = 1;
3011                 else
3012                         buf[2] = 1;
3013                 etest->flags |= ETH_TEST_FL_FAILED;
3014         }
3015 }
3016
3017 #define IS_PORT_STAT(i) \
3018         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
3019 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
3020 #define HIDE_PORT_STAT(bp) \
3021                 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \
3022                  IS_VF(bp))
3023
3024 /* ethtool statistics are displayed for all regular ethernet queues and the
3025  * fcoe L2 queue if not disabled
3026  */
3027 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3028 {
3029         return BNX2X_NUM_ETH_QUEUES(bp);
3030 }
3031
3032 static int bnx2x_get_sset_count(struct ether *dev, int stringset)
3033 {
3034         struct bnx2x *bp = netdev_priv(dev);
3035         int i, num_strings = 0;
3036
3037         switch (stringset) {
3038         case ETH_SS_STATS:
3039                 if (is_multi(bp)) {
3040                         num_strings = bnx2x_num_stat_queues(bp) *
3041                                       BNX2X_NUM_Q_STATS;
3042                 } else
3043                         num_strings = 0;
3044                 if (HIDE_PORT_STAT(bp)) {
3045                         for (i = 0; i < BNX2X_NUM_STATS; i++)
3046                                 if (IS_FUNC_STAT(i))
3047                                         num_strings++;
3048                 } else
3049                         num_strings += BNX2X_NUM_STATS;
3050
3051                 return num_strings;
3052
3053         case ETH_SS_TEST:
3054                 return BNX2X_NUM_TESTS(bp);
3055
3056         case ETH_SS_PRIV_FLAGS:
3057                 return BNX2X_PRI_FLAG_LEN;
3058
3059         default:
3060                 return -EINVAL;
3061         }
3062 }
3063
3064 static uint32_t bnx2x_get_private_flags(struct ether *dev)
3065 {
3066         struct bnx2x *bp = netdev_priv(dev);
3067         uint32_t flags = 0;
3068
3069         flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3070         flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3071         flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3072
3073         return flags;
3074 }
3075
3076 static void bnx2x_get_strings(struct ether *dev, uint32_t stringset,
3077                               uint8_t *buf)
3078 {
3079         struct bnx2x *bp = netdev_priv(dev);
3080         int i, j, k, start;
3081         char queue_name[MAX_QUEUE_NAME_LEN+1];
3082
3083         switch (stringset) {
3084         case ETH_SS_STATS:
3085                 k = 0;
3086                 if (is_multi(bp)) {
3087                         for_each_eth_queue(bp, i) {
3088                                 memset(queue_name, 0, sizeof(queue_name));
3089                                 sprintf(queue_name, "%d", i);
3090                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3091                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3092                                                 ETH_GSTRING_LEN,
3093                                                 bnx2x_q_stats_arr[j].string,
3094                                                 queue_name);
3095                                 k += BNX2X_NUM_Q_STATS;
3096                         }
3097                 }
3098
3099                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3100                         if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3101                                 continue;
3102                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3103                                    bnx2x_stats_arr[i].string);
3104                         j++;
3105                 }
3106
3107                 break;
3108
3109         case ETH_SS_TEST:
3110                 /* First 4 tests cannot be done in MF mode */
3111                 if (!IS_MF(bp))
3112                         start = 0;
3113                 else
3114                         start = 4;
3115                 memcpy(buf, bnx2x_tests_str_arr + start,
3116                        ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3117                 break;
3118
3119         case ETH_SS_PRIV_FLAGS:
3120                 memcpy(buf, bnx2x_private_arr,
3121                        ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3122                 break;
3123         }
3124 }
3125
3126 static void bnx2x_get_ethtool_stats(struct ether *dev,
3127                                     struct ethtool_stats *stats,
3128                                     uint64_t *buf)
3129 {
3130         struct bnx2x *bp = netdev_priv(dev);
3131         uint32_t *hw_stats, *offset;
3132         int i, j, k = 0;
3133
3134         if (is_multi(bp)) {
3135                 for_each_eth_queue(bp, i) {
3136                         hw_stats = (uint32_t *)&bp->fp_stats[i].eth_q_stats;
3137                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3138                                 if (bnx2x_q_stats_arr[j].size == 0) {
3139                                         /* skip this counter */
3140                                         buf[k + j] = 0;
3141                                         continue;
3142                                 }
3143                                 offset = (hw_stats +
3144                                           bnx2x_q_stats_arr[j].offset);
3145                                 if (bnx2x_q_stats_arr[j].size == 4) {
3146                                         /* 4-byte counter */
3147                                         buf[k + j] = (uint64_t) *offset;
3148                                         continue;
3149                                 }
3150                                 /* 8-byte counter */
3151                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3152                         }
3153                         k += BNX2X_NUM_Q_STATS;
3154                 }
3155         }
3156
3157         hw_stats = (uint32_t *)&bp->eth_stats;
3158         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3159                 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3160                         continue;
3161                 if (bnx2x_stats_arr[i].size == 0) {
3162                         /* skip this counter */
3163                         buf[k + j] = 0;
3164                         j++;
3165                         continue;
3166                 }
3167                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3168                 if (bnx2x_stats_arr[i].size == 4) {
3169                         /* 4-byte counter */
3170                         buf[k + j] = (uint64_t) *offset;
3171                         j++;
3172                         continue;
3173                 }
3174                 /* 8-byte counter */
3175                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3176                 j++;
3177         }
3178 }
3179
3180 static int bnx2x_set_phys_id(struct ether *dev,
3181                              enum ethtool_phys_id_state state)
3182 {
3183         struct bnx2x *bp = netdev_priv(dev);
3184
3185         if (!bnx2x_is_nvm_accessible(bp)) {
3186                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3187                    "cannot access eeprom when the interface is down\n");
3188                 return -EAGAIN;
3189         }
3190
3191         switch (state) {
3192         case ETHTOOL_ID_ACTIVE:
3193                 return 1;       /* cycle on/off once per second */
3194
3195         case ETHTOOL_ID_ON:
3196                 bnx2x_acquire_phy_lock(bp);
3197                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3198                               LED_MODE_ON, SPEED_1000);
3199                 bnx2x_release_phy_lock(bp);
3200                 break;
3201
3202         case ETHTOOL_ID_OFF:
3203                 bnx2x_acquire_phy_lock(bp);
3204                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3205                               LED_MODE_FRONT_PANEL_OFF, 0);
3206                 bnx2x_release_phy_lock(bp);
3207                 break;
3208
3209         case ETHTOOL_ID_INACTIVE:
3210                 bnx2x_acquire_phy_lock(bp);
3211                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3212                               LED_MODE_OPER,
3213                               bp->link_vars.line_speed);
3214                 bnx2x_release_phy_lock(bp);
3215         }
3216
3217         return 0;
3218 }
3219
3220 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3221 {
3222         switch (info->flow_type) {
3223         case TCP_V4_FLOW:
3224         case TCP_V6_FLOW:
3225                 info->data = RXH_IP_SRC | RXH_IP_DST |
3226                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3227                 break;
3228         case UDP_V4_FLOW:
3229                 if (bp->rss_conf_obj.udp_rss_v4)
3230                         info->data = RXH_IP_SRC | RXH_IP_DST |
3231                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3232                 else
3233                         info->data = RXH_IP_SRC | RXH_IP_DST;
3234                 break;
3235         case UDP_V6_FLOW:
3236                 if (bp->rss_conf_obj.udp_rss_v6)
3237                         info->data = RXH_IP_SRC | RXH_IP_DST |
3238                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3239                 else
3240                         info->data = RXH_IP_SRC | RXH_IP_DST;
3241                 break;
3242         case IPV4_FLOW:
3243         case IPV6_FLOW:
3244                 info->data = RXH_IP_SRC | RXH_IP_DST;
3245                 break;
3246         default:
3247                 info->data = 0;
3248                 break;
3249         }
3250
3251         return 0;
3252 }
3253
3254 static int bnx2x_get_rxnfc(struct ether *dev, struct ethtool_rxnfc *info,
3255                            uint32_t *rules __always_unused)
3256 {
3257         struct bnx2x *bp = netdev_priv(dev);
3258
3259         switch (info->cmd) {
3260         case ETHTOOL_GRXRINGS:
3261                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3262                 return 0;
3263         case ETHTOOL_GRXFH:
3264                 return bnx2x_get_rss_flags(bp, info);
3265         default:
3266                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3267                 return -EOPNOTSUPP;
3268         }
3269 }
3270
3271 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3272 {
3273         int udp_rss_requested;
3274
3275         DP(BNX2X_MSG_ETHTOOL,
3276            "Set rss flags command parameters: flow type = %d, data = %llu\n",
3277            info->flow_type, info->data);
3278
3279         switch (info->flow_type) {
3280         case TCP_V4_FLOW:
3281         case TCP_V6_FLOW:
3282                 /* For TCP only 4-tupple hash is supported */
3283                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3284                                   RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3285                         DP(BNX2X_MSG_ETHTOOL,
3286                            "Command parameters not supported\n");
3287                         return -EINVAL;
3288                 }
3289                 return 0;
3290
3291         case UDP_V4_FLOW:
3292         case UDP_V6_FLOW:
3293                 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3294                 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3295                                    RXH_L4_B_0_1 | RXH_L4_B_2_3))
3296                         udp_rss_requested = 1;
3297                 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3298                         udp_rss_requested = 0;
3299                 else
3300                         return -EINVAL;
3301                 if ((info->flow_type == UDP_V4_FLOW) &&
3302                     (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3303                         bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3304                         DP(BNX2X_MSG_ETHTOOL,
3305                            "rss re-configured, UDP 4-tupple %s\n",
3306                            udp_rss_requested ? "enabled" : "disabled");
3307                         return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3308                 } else if ((info->flow_type == UDP_V6_FLOW) &&
3309                            (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3310                         bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3311                         DP(BNX2X_MSG_ETHTOOL,
3312                            "rss re-configured, UDP 4-tupple %s\n",
3313                            udp_rss_requested ? "enabled" : "disabled");
3314                         return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3315                 }
3316                 return 0;
3317
3318         case IPV4_FLOW:
3319         case IPV6_FLOW:
3320                 /* For IP only 2-tupple hash is supported */
3321                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3322                         DP(BNX2X_MSG_ETHTOOL,
3323                            "Command parameters not supported\n");
3324                         return -EINVAL;
3325                 }
3326                 return 0;
3327
3328         case SCTP_V4_FLOW:
3329         case AH_ESP_V4_FLOW:
3330         case AH_V4_FLOW:
3331         case ESP_V4_FLOW:
3332         case SCTP_V6_FLOW: