BNX2X: spatch endian converters
[akaros.git] / kern / drivers / net / bnx2x / bnx2x_cmn.c
1 /* bnx2x_cmn.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath and fastpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include "akaros_compat.h"
19
20 #include "bnx2x_cmn.h"
21 #include "bnx2x_init.h"
22 #include "bnx2x_sp.h"
23
24 static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp);
25 static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp);
26 static int bnx2x_alloc_fp_mem(struct bnx2x *bp);
27 static int bnx2x_poll(struct napi_struct *napi, int budget);
28
29 static void bnx2x_add_all_napi_cnic(struct bnx2x *bp)
30 {
31         int i;
32
33         /* Add NAPI objects */
34         for_each_rx_queue_cnic(bp, i) {
35                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
36                                bnx2x_poll, NAPI_POLL_WEIGHT);
37                 napi_hash_add(&bnx2x_fp(bp, i, napi));
38         }
39 }
40
41 static void bnx2x_add_all_napi(struct bnx2x *bp)
42 {
43         int i;
44
45         /* Add NAPI objects */
46         for_each_eth_queue(bp, i) {
47                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
48                                bnx2x_poll, NAPI_POLL_WEIGHT);
49                 napi_hash_add(&bnx2x_fp(bp, i, napi));
50         }
51 }
52
53 static int bnx2x_calc_num_queues(struct bnx2x *bp)
54 {
55         int nq = bnx2x_num_queues ? : netif_get_num_default_rss_queues();
56
57         /* Reduce memory usage in kdump environment by using only one queue */
58         if (is_kdump_kernel())
59                 nq = 1;
60
61         nq = CLAMP(nq, 1, BNX2X_MAX_QUEUES(bp));
62         return nq;
63 }
64
65 /**
66  * bnx2x_move_fp - move content of the fastpath structure.
67  *
68  * @bp:         driver handle
69  * @from:       source FP index
70  * @to:         destination FP index
71  *
72  * Makes sure the contents of the bp->fp[to].napi is kept
73  * intact. This is done by first copying the napi struct from
74  * the target to the source, and then mem copying the entire
75  * source onto the target. Update txdata pointers and related
76  * content.
77  */
78 static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
79 {
80         struct bnx2x_fastpath *from_fp = &bp->fp[from];
81         struct bnx2x_fastpath *to_fp = &bp->fp[to];
82         struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from];
83         struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to];
84         struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from];
85         struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to];
86         int old_max_eth_txqs, new_max_eth_txqs;
87         int old_txdata_index = 0, new_txdata_index = 0;
88         struct bnx2x_agg_info *old_tpa_info = to_fp->tpa_info;
89
90         /* Copy the NAPI object as it has been already initialized */
91         from_fp->napi = to_fp->napi;
92
93         /* Move bnx2x_fastpath contents */
94         memcpy(to_fp, from_fp, sizeof(*to_fp));
95         to_fp->index = to;
96
97         /* Retain the tpa_info of the original `to' version as we don't want
98          * 2 FPs to contain the same tpa_info pointer.
99          */
100         to_fp->tpa_info = old_tpa_info;
101
102         /* move sp_objs contents as well, as their indices match fp ones */
103         memcpy(to_sp_objs, from_sp_objs, sizeof(*to_sp_objs));
104
105         /* move fp_stats contents as well, as their indices match fp ones */
106         memcpy(to_fp_stats, from_fp_stats, sizeof(*to_fp_stats));
107
108         /* Update txdata pointers in fp and move txdata content accordingly:
109          * Each fp consumes 'max_cos' txdata structures, so the index should be
110          * decremented by max_cos x delta.
111          */
112
113         old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos;
114         new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) *
115                                 (bp)->max_cos;
116         if (from == FCOE_IDX(bp)) {
117                 old_txdata_index = old_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
118                 new_txdata_index = new_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
119         }
120
121         memcpy(&bp->bnx2x_txq[new_txdata_index],
122                &bp->bnx2x_txq[old_txdata_index],
123                sizeof(struct bnx2x_fp_txdata));
124         to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index];
125 }
126
127 /**
128  * bnx2x_fill_fw_str - Fill buffer with FW version string.
129  *
130  * @bp:        driver handle
131  * @buf:       character buffer to fill with the fw name
132  * @buf_len:   length of the above buffer
133  *
134  */
135 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
136 {
137         if (IS_PF(bp)) {
138                 uint8_t phy_fw_ver[PHY_FW_VER_LEN];
139
140                 phy_fw_ver[0] = '\0';
141                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
142                                              phy_fw_ver, PHY_FW_VER_LEN);
143                 strlcpy(buf, bp->fw_ver, buf_len);
144                 snprintf(buf + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
145                          "bc %d.%d.%d%s%s",
146                          (bp->common.bc_ver & 0xff0000) >> 16,
147                          (bp->common.bc_ver & 0xff00) >> 8,
148                          (bp->common.bc_ver & 0xff),
149                          ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
150         } else {
151                 bnx2x_vf_fill_fw_str(bp, buf, buf_len);
152         }
153 }
154
155 /**
156  * bnx2x_shrink_eth_fp - guarantees fastpath structures stay intact
157  *
158  * @bp: driver handle
159  * @delta:      number of eth queues which were not allocated
160  */
161 static void bnx2x_shrink_eth_fp(struct bnx2x *bp, int delta)
162 {
163         int i, cos, old_eth_num = BNX2X_NUM_ETH_QUEUES(bp);
164
165         /* Queue pointer cannot be re-set on an fp-basis, as moving pointer
166          * backward along the array could cause memory to be overridden
167          */
168         for (cos = 1; cos < bp->max_cos; cos++) {
169                 for (i = 0; i < old_eth_num - delta; i++) {
170                         struct bnx2x_fastpath *fp = &bp->fp[i];
171                         int new_idx = cos * (old_eth_num - delta) + i;
172
173                         memcpy(&bp->bnx2x_txq[new_idx], fp->txdata_ptr[cos],
174                                sizeof(struct bnx2x_fp_txdata));
175                         fp->txdata_ptr[cos] = &bp->bnx2x_txq[new_idx];
176                 }
177         }
178 }
179
180 int bnx2x_load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
181
182 /* free skb in the packet ring at pos idx
183  * return idx of last bd freed
184  */
185 static uint16_t bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
186                              uint16_t idx, unsigned int *pkts_compl,
187                              unsigned int *bytes_compl)
188 {
189         struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx];
190         struct eth_tx_start_bd *tx_start_bd;
191         struct eth_tx_bd *tx_data_bd;
192         struct sk_buff *skb = tx_buf->skb;
193         uint16_t bd_idx = TX_BD(tx_buf->first_bd), new_cons;
194         int nbd;
195         uint16_t split_bd_len = 0;
196
197         /* prefetch skb end pointer to speedup dev_kfree_skb() */
198         prefetch(&skb->end);
199
200         DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d  buff @(%p)->skb %p\n",
201            txdata->txq_index, idx, tx_buf, skb);
202
203         tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd;
204
205         nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
206 #ifdef BNX2X_STOP_ON_ERROR
207         if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
208                 BNX2X_ERR("BAD nbd!\n");
209                 bnx2x_panic();
210         }
211 #endif
212         new_cons = nbd + tx_buf->first_bd;
213
214         /* Get the next bd */
215         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
216
217         /* Skip a parse bd... */
218         --nbd;
219         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
220
221         if (tx_buf->flags & BNX2X_HAS_SECOND_PBD) {
222                 /* Skip second parse bd... */
223                 --nbd;
224                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
225         }
226
227         /* TSO headers+data bds share a common mapping. See bnx2x_tx_split() */
228         if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
229                 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
230                 split_bd_len = BD_UNMAP_LEN(tx_data_bd);
231                 --nbd;
232                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
233         }
234
235         /* unmap first bd */
236         dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
237                          BD_UNMAP_LEN(tx_start_bd) + split_bd_len,
238                          DMA_TO_DEVICE);
239
240         /* now free frags */
241         while (nbd > 0) {
242
243                 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
244                 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
245                                BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
246                 if (--nbd)
247                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
248         }
249
250         /* release skb */
251         WARN_ON(!skb);
252         if (likely(skb)) {
253                 (*pkts_compl)++;
254                 (*bytes_compl) += skb->len;
255         }
256
257         dev_kfree_skb_any(skb);
258         tx_buf->first_bd = 0;
259         tx_buf->skb = NULL;
260
261         return new_cons;
262 }
263
264 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
265 {
266         struct netdev_queue *txq;
267         uint16_t hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
268         unsigned int pkts_compl = 0, bytes_compl = 0;
269
270 #ifdef BNX2X_STOP_ON_ERROR
271         if (unlikely(bp->panic))
272                 return -1;
273 #endif
274
275         txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
276         hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
277         sw_cons = txdata->tx_pkt_cons;
278
279         while (sw_cons != hw_cons) {
280                 uint16_t pkt_cons;
281
282                 pkt_cons = TX_BD(sw_cons);
283
284                 DP(NETIF_MSG_TX_DONE,
285                    "queue[%d]: hw_cons %u  sw_cons %u  pkt_cons %u\n",
286                    txdata->txq_index, hw_cons, sw_cons, pkt_cons);
287
288                 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
289                                             &pkts_compl, &bytes_compl);
290
291                 sw_cons++;
292         }
293
294         netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
295
296         txdata->tx_pkt_cons = sw_cons;
297         txdata->tx_bd_cons = bd_cons;
298
299         /* Need to make the tx_bd_cons update visible to start_xmit()
300          * before checking for netif_tx_queue_stopped().  Without the
301          * memory barrier, there is a small possibility that
302          * start_xmit() will miss it and cause the queue to be stopped
303          * forever.
304          * On the other hand we need an rmb() here to ensure the proper
305          * ordering of bit testing in the following
306          * netif_tx_queue_stopped(txq) call.
307          */
308         mb();
309
310         if (unlikely(netif_tx_queue_stopped(txq))) {
311                 /* Taking tx_lock() is needed to prevent re-enabling the queue
312                  * while it's empty. This could have happen if rx_action() gets
313                  * suspended in bnx2x_tx_int() after the condition before
314                  * netif_tx_wake_queue(), while tx_action (bnx2x_start_xmit()):
315                  *
316                  * stops the queue->sees fresh tx_bd_cons->releases the queue->
317                  * sends some packets consuming the whole queue again->
318                  * stops the queue
319                  */
320
321                 __netif_tx_lock(txq, smp_processor_id());
322
323                 if ((netif_tx_queue_stopped(txq)) &&
324                     (bp->state == BNX2X_STATE_OPEN) &&
325                     (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT))
326                         netif_tx_wake_queue(txq);
327
328                 __netif_tx_unlock(txq);
329         }
330         return 0;
331 }
332
333 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
334                                              uint16_t idx)
335 {
336         uint16_t last_max = fp->last_max_sge;
337
338         if (SUB_S16(idx, last_max) > 0)
339                 fp->last_max_sge = idx;
340 }
341
342 static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
343                                          uint16_t sge_len,
344                                          struct eth_end_agg_rx_cqe *cqe)
345 {
346         struct bnx2x *bp = fp->bp;
347         uint16_t last_max, last_elem, first_elem;
348         uint16_t delta = 0;
349         uint16_t i;
350
351         if (!sge_len)
352                 return;
353
354         /* First mark all used pages */
355         for (i = 0; i < sge_len; i++)
356                 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
357                         RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[i])));
358
359         DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
360            sge_len - 1, le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
361
362         /* Here we assume that the last SGE index is the biggest */
363         prefetch((void *)(fp->sge_mask));
364         bnx2x_update_last_max_sge(fp,
365                 le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
366
367         last_max = RX_SGE(fp->last_max_sge);
368         last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
369         first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
370
371         /* If ring is not full */
372         if (last_elem + 1 != first_elem)
373                 last_elem++;
374
375         /* Now update the prod */
376         for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
377                 if (likely(fp->sge_mask[i]))
378                         break;
379
380                 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
381                 delta += BIT_VEC64_ELEM_SZ;
382         }
383
384         if (delta > 0) {
385                 fp->rx_sge_prod += delta;
386                 /* clear page-end entries */
387                 bnx2x_clear_sge_mask_next_elems(fp);
388         }
389
390         DP(NETIF_MSG_RX_STATUS,
391            "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
392            fp->last_max_sge, fp->rx_sge_prod);
393 }
394
395 /* Get Toeplitz hash value in the skb using the value from the
396  * CQE (calculated by HW).
397  */
398 static uint32_t bnx2x_get_rxhash(const struct bnx2x *bp,
399                             const struct eth_fast_path_rx_cqe *cqe,
400                             enum pkt_hash_types *rxhash_type)
401 {
402         /* Get Toeplitz hash from CQE */
403         if ((bp->dev->features & NETIF_F_RXHASH) &&
404             (cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) {
405                 enum eth_rss_hash_type htype;
406
407                 htype = cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE;
408                 *rxhash_type = ((htype == TCP_IPV4_HASH_TYPE) ||
409                                 (htype == TCP_IPV6_HASH_TYPE)) ?
410                                PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
411
412                 return le32_to_cpu(cqe->rss_hash_result);
413         }
414         *rxhash_type = PKT_HASH_TYPE_NONE;
415         return 0;
416 }
417
418 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, uint16_t queue,
419                             uint16_t cons, uint16_t prod,
420                             struct eth_fast_path_rx_cqe *cqe)
421 {
422         struct bnx2x *bp = fp->bp;
423         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
424         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
425         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
426         dma_addr_t mapping;
427         struct bnx2x_agg_info *tpa_info = &fp->tpa_info[queue];
428         struct sw_rx_bd *first_buf = &tpa_info->first_buf;
429
430         /* print error if current state != stop */
431         if (tpa_info->tpa_state != BNX2X_TPA_STOP)
432                 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
433
434         /* Try to map an empty data buffer from the aggregation info  */
435         mapping = dma_map_single(&bp->pdev->dev,
436                                  first_buf->data + NET_SKB_PAD,
437                                  fp->rx_buf_size, DMA_FROM_DEVICE);
438         /*
439          *  ...if it fails - move the skb from the consumer to the producer
440          *  and set the current aggregation state as ERROR to drop it
441          *  when TPA_STOP arrives.
442          */
443
444         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
445                 /* Move the BD from the consumer to the producer */
446                 bnx2x_reuse_rx_data(fp, cons, prod);
447                 tpa_info->tpa_state = BNX2X_TPA_ERROR;
448                 return;
449         }
450
451         /* move empty data from pool to prod */
452         prod_rx_buf->data = first_buf->data;
453         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
454         /* point prod_bd to new data */
455         prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
456         prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
457
458         /* move partial skb from cons to pool (don't unmap yet) */
459         *first_buf = *cons_rx_buf;
460
461         /* mark bin state as START */
462         tpa_info->parsing_flags =
463                 le16_to_cpu(cqe->pars_flags.flags);
464         tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
465         tpa_info->tpa_state = BNX2X_TPA_START;
466         tpa_info->len_on_bd = le16_to_cpu(cqe->len_on_bd);
467         tpa_info->placement_offset = cqe->placement_offset;
468         tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->rxhash_type);
469         if (fp->mode == TPA_MODE_GRO) {
470                 uint16_t gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
471                 tpa_info->full_page = SGE_PAGES / gro_size * gro_size;
472                 tpa_info->gro_size = gro_size;
473         }
474
475 #ifdef BNX2X_STOP_ON_ERROR
476         fp->tpa_queue_used |= (1 << queue);
477         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
478            fp->tpa_queue_used);
479 #endif
480 }
481
482 /* Timestamp option length allowed for TPA aggregation:
483  *
484  *              nop nop kind length echo val
485  */
486 #define TPA_TSTAMP_OPT_LEN      12
487 /**
488  * bnx2x_set_gro_params - compute GRO values
489  *
490  * @skb:                packet skb
491  * @parsing_flags:      parsing flags from the START CQE
492  * @len_on_bd:          total length of the first packet for the
493  *                      aggregation.
494  * @pkt_len:            length of all segments
495  *
496  * Approximate value of the MSS for this aggregation calculated using
497  * the first packet of it.
498  * Compute number of aggregated segments, and gso_type.
499  */
500 static void bnx2x_set_gro_params(struct sk_buff *skb, uint16_t parsing_flags,
501                                  uint16_t len_on_bd, unsigned int pkt_len,
502                                  uint16_t num_of_coalesced_segs)
503 {
504         /* TPA aggregation won't have either IP options or TCP options
505          * other than timestamp or IPv6 extension headers.
506          */
507         uint16_t hdrs_len = ETHERHDRSIZE + sizeof(struct tcphdr);
508
509         if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
510             PRS_FLAG_OVERETH_IPV6) {
511                 hdrs_len += sizeof(struct ipv6hdr);
512                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
513         } else {
514                 hdrs_len += sizeof(struct iphdr);
515                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
516         }
517
518         /* Check if there was a TCP timestamp, if there is it's will
519          * always be 12 bytes length: nop nop kind length echo val.
520          *
521          * Otherwise FW would close the aggregation.
522          */
523         if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG)
524                 hdrs_len += TPA_TSTAMP_OPT_LEN;
525
526         skb_shinfo(skb)->gso_size = len_on_bd - hdrs_len;
527
528         /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
529          * to skb_shinfo(skb)->gso_segs
530          */
531         NAPI_GRO_CB(skb)->count = num_of_coalesced_segs;
532 }
533
534 static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp,
535                               uint16_t index, gfp_t gfp_mask)
536 {
537         struct page *page = get_cont_pages(PAGES_PER_SGE_SHIFT, gfp_mask);
538         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
539         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
540         dma_addr_t mapping;
541
542         if (unlikely(page == NULL)) {
543                 BNX2X_ERR("Can't alloc sge\n");
544                 return -ENOMEM;
545         }
546
547         mapping = dma_map_page(&bp->pdev->dev, page, 0,
548                                SGE_PAGES, DMA_FROM_DEVICE);
549         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
550                 free_cont_pages(page, PAGES_PER_SGE_SHIFT);
551                 BNX2X_ERR("Can't map sge\n");
552                 return -ENOMEM;
553         }
554
555         sw_buf->page = page;
556         dma_unmap_addr_set(sw_buf, mapping, mapping);
557
558         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
559         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
560
561         return 0;
562 }
563
564 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
565                                struct bnx2x_agg_info *tpa_info,
566                                uint16_t pages,
567                                struct sk_buff *skb,
568                                struct eth_end_agg_rx_cqe *cqe,
569                                uint16_t cqe_idx)
570 {
571         struct sw_rx_page *rx_pg, old_rx_pg;
572         uint32_t i, frag_len, frag_size;
573         int err, j, frag_id = 0;
574         uint16_t len_on_bd = tpa_info->len_on_bd;
575         uint16_t full_page = 0, gro_size = 0;
576
577         frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd;
578
579         if (fp->mode == TPA_MODE_GRO) {
580                 gro_size = tpa_info->gro_size;
581                 full_page = tpa_info->full_page;
582         }
583
584         /* This is needed in order to enable forwarding support */
585         if (frag_size)
586                 bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd,
587                                      le16_to_cpu(cqe->pkt_len),
588                                      le16_to_cpu(cqe->num_of_coalesced_segs));
589
590 #ifdef BNX2X_STOP_ON_ERROR
591         if (pages > MIN_T(uint32_t, 8, MAX_SKB_FRAGS) * SGE_PAGES) {
592                 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
593                           pages, cqe_idx);
594                 BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len);
595                 bnx2x_panic();
596                 return -EINVAL;
597         }
598 #endif
599
600         /* Run through the SGL and compose the fragmented skb */
601         for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
602                 uint16_t sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
603
604                 /* FW gives the indices of the SGE as if the ring is an array
605                    (meaning that "next" element will consume 2 indices) */
606                 if (fp->mode == TPA_MODE_GRO)
607                         frag_len = MIN_T(uint32_t, frag_size,
608                                          (uint32_t)full_page);
609                 else /* LRO */
610                         frag_len = MIN_T(uint32_t, frag_size,
611                                          (uint32_t)SGE_PAGES);
612
613                 rx_pg = &fp->rx_page_ring[sge_idx];
614                 old_rx_pg = *rx_pg;
615
616                 /* If we fail to allocate a substitute page, we simply stop
617                    where we are and drop the whole packet */
618                 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx, 0);
619                 if (unlikely(err)) {
620                         bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
621                         return err;
622                 }
623
624                 /* Unmap the page as we're going to pass it to the stack */
625                 dma_unmap_page(&bp->pdev->dev,
626                                dma_unmap_addr(&old_rx_pg, mapping),
627                                SGE_PAGES, DMA_FROM_DEVICE);
628                 /* Add one frag and update the appropriate fields in the skb */
629                 if (fp->mode == TPA_MODE_LRO)
630                         skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
631                 else { /* GRO */
632                         int rem;
633                         int offset = 0;
634                         for (rem = frag_len; rem > 0; rem -= gro_size) {
635                                 int len = rem > gro_size ? gro_size : rem;
636                                 skb_fill_page_desc(skb, frag_id++,
637                                                    old_rx_pg.page, offset, len);
638                                 if (offset)
639                                         page_incref(old_rx_pg.page);
640                                 offset += len;
641                         }
642                 }
643
644                 skb->data_len += frag_len;
645                 skb->truesize += SGE_PAGES;
646                 skb->len += frag_len;
647
648                 frag_size -= frag_len;
649         }
650
651         return 0;
652 }
653
654 static void bnx2x_frag_free(const struct bnx2x_fastpath *fp, void *data)
655 {
656         if (fp->rx_frag_size)
657                 page_decref(kva2page(data));
658         else
659                 kfree(data);
660 }
661
662 static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp, gfp_t gfp_mask)
663 {
664         if (fp->rx_frag_size) {
665                 /* GFP_KERNEL allocations are used only during initialization */
666                 if (unlikely(gfp_mask & KMALLOC_WAIT))
667                         return (void *)kpage_alloc_addr();
668
669                 return netdev_alloc_frag(fp->rx_frag_size);
670         }
671
672         return kmalloc(fp->rx_buf_size + NET_SKB_PAD, gfp_mask);
673 }
674
675 #ifdef CONFIG_INET
676 static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb)
677 {
678         const struct iphdr *iph = ip_hdr(skb);
679         struct tcphdr *th;
680
681         skb_set_transport_header(skb, sizeof(struct iphdr));
682         th = tcp_hdr(skb);
683
684         th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
685                                   iph->saddr, iph->daddr, 0);
686 }
687
688 static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb)
689 {
690         struct ipv6hdr *iph = ipv6_hdr(skb);
691         struct tcphdr *th;
692
693         skb_set_transport_header(skb, sizeof(struct ipv6hdr));
694         th = tcp_hdr(skb);
695
696         th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
697                                   &iph->saddr, &iph->daddr, 0);
698 }
699
700 static void bnx2x_gro_csum(struct bnx2x *bp, struct sk_buff *skb,
701                             void (*gro_func)(struct bnx2x*, struct sk_buff*))
702 {
703         skb_set_network_header(skb, 0);
704         gro_func(bp, skb);
705         tcp_gro_complete(skb);
706 }
707 #endif
708
709 static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
710                                struct sk_buff *skb)
711 {
712 #ifdef CONFIG_INET
713         if (skb_shinfo(skb)->gso_size) {
714                 switch (be16_to_cpu(skb->protocol)) {
715                 case ETH_P_IP:
716                         bnx2x_gro_csum(bp, skb, bnx2x_gro_ip_csum);
717                         break;
718                 case ETH_P_IPV6:
719                         bnx2x_gro_csum(bp, skb, bnx2x_gro_ipv6_csum);
720                         break;
721                 default:
722                         BNX2X_ERR("Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
723                                   be16_to_cpu(skb->protocol));
724                 }
725         }
726 #endif
727         skb_record_rx_queue(skb, fp->rx_queue);
728         napi_gro_receive(&fp->napi, skb);
729 }
730
731 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
732                            struct bnx2x_agg_info *tpa_info,
733                            uint16_t pages,
734                            struct eth_end_agg_rx_cqe *cqe,
735                            uint16_t cqe_idx)
736 {
737         struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
738         uint8_t pad = tpa_info->placement_offset;
739         uint16_t len = tpa_info->len_on_bd;
740         struct sk_buff *skb = NULL;
741         uint8_t *new_data, *data = rx_buf->data;
742         uint8_t old_tpa_state = tpa_info->tpa_state;
743
744         tpa_info->tpa_state = BNX2X_TPA_STOP;
745
746         /* If we there was an error during the handling of the TPA_START -
747          * drop this aggregation.
748          */
749         if (old_tpa_state == BNX2X_TPA_ERROR)
750                 goto drop;
751
752         /* Try to allocate the new data */
753         new_data = bnx2x_frag_alloc(fp, 0);
754         /* Unmap skb in the pool anyway, as we are going to change
755            pool entry status to BNX2X_TPA_STOP even if new skb allocation
756            fails. */
757         dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
758                          fp->rx_buf_size, DMA_FROM_DEVICE);
759         if (likely(new_data))
760                 skb = build_skb(data, fp->rx_frag_size);
761
762         if (likely(skb)) {
763 #ifdef BNX2X_STOP_ON_ERROR
764                 if (pad + len > fp->rx_buf_size) {
765                         BNX2X_ERR("skb_put is about to fail...  pad %d  len %d  rx_buf_size %d\n",
766                                   pad, len, fp->rx_buf_size);
767                         bnx2x_panic();
768                         return;
769                 }
770 #endif
771
772                 skb_reserve(skb, pad + NET_SKB_PAD);
773                 skb_put(skb, len);
774                 skb_set_hash(skb, tpa_info->rxhash, tpa_info->rxhash_type);
775
776                 skb->protocol = eth_type_trans(skb, bp->dev);
777                 skb->ip_summed = CHECKSUM_UNNECESSARY;
778
779                 if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages,
780                                          skb, cqe, cqe_idx)) {
781                         if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN)
782                                 __vlan_hwaccel_put_tag(skb,
783                                                        cpu_to_be16(ETH_P_8021Q),
784                                                        tpa_info->vlan_tag);
785                         bnx2x_gro_receive(bp, fp, skb);
786                 } else {
787                         DP(NETIF_MSG_RX_STATUS,
788                            "Failed to allocate new pages - dropping packet!\n");
789                         dev_kfree_skb_any(skb);
790                 }
791
792                 /* put new data in bin */
793                 rx_buf->data = new_data;
794
795                 return;
796         }
797         if (new_data)
798                 bnx2x_frag_free(fp, new_data);
799 drop:
800         /* drop the packet and keep the buffer in the bin */
801         DP(NETIF_MSG_RX_STATUS,
802            "Failed to allocate or map a new skb - dropping packet!\n");
803         bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++;
804 }
805
806 static int bnx2x_alloc_rx_data(struct bnx2x *bp, struct bnx2x_fastpath *fp,
807                                uint16_t index, gfp_t gfp_mask)
808 {
809         uint8_t *data;
810         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
811         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
812         dma_addr_t mapping;
813
814         data = bnx2x_frag_alloc(fp, gfp_mask);
815         if (unlikely(data == NULL))
816                 return -ENOMEM;
817
818         mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
819                                  fp->rx_buf_size,
820                                  DMA_FROM_DEVICE);
821         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
822                 bnx2x_frag_free(fp, data);
823                 BNX2X_ERR("Can't map rx data\n");
824                 return -ENOMEM;
825         }
826
827         rx_buf->data = data;
828         dma_unmap_addr_set(rx_buf, mapping, mapping);
829
830         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
831         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
832
833         return 0;
834 }
835
836 static
837 void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe,
838                                  struct bnx2x_fastpath *fp,
839                                  struct bnx2x_eth_q_stats *qstats)
840 {
841         /* Do nothing if no L4 csum validation was done.
842          * We do not check whether IP csum was validated. For IPv4 we assume
843          * that if the card got as far as validating the L4 csum, it also
844          * validated the IP csum. IPv6 has no IP csum.
845          */
846         if (cqe->fast_path_cqe.status_flags &
847             ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)
848                 return;
849
850         /* If L4 validation was done, check if an error was found. */
851
852         if (cqe->fast_path_cqe.type_error_flags &
853             (ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG |
854              ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
855                 qstats->hw_csum_err++;
856         else
857                 skb->ip_summed = CHECKSUM_UNNECESSARY;
858 }
859
860 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
861 {
862         struct bnx2x *bp = fp->bp;
863         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
864         uint16_t sw_comp_cons, sw_comp_prod;
865         int rx_pkt = 0;
866         union eth_rx_cqe *cqe;
867         struct eth_fast_path_rx_cqe *cqe_fp;
868
869 #ifdef BNX2X_STOP_ON_ERROR
870         if (unlikely(bp->panic))
871                 return 0;
872 #endif
873         if (budget <= 0)
874                 return rx_pkt;
875
876         bd_cons = fp->rx_bd_cons;
877         bd_prod = fp->rx_bd_prod;
878         bd_prod_fw = bd_prod;
879         sw_comp_cons = fp->rx_comp_cons;
880         sw_comp_prod = fp->rx_comp_prod;
881
882         comp_ring_cons = RCQ_BD(sw_comp_cons);
883         cqe = &fp->rx_comp_ring[comp_ring_cons];
884         cqe_fp = &cqe->fast_path_cqe;
885
886         DP(NETIF_MSG_RX_STATUS,
887            "queue[%d]: sw_comp_cons %u\n", fp->index, sw_comp_cons);
888
889         while (BNX2X_IS_CQE_COMPLETED(cqe_fp)) {
890                 struct sw_rx_bd *rx_buf = NULL;
891                 struct sk_buff *skb;
892                 uint8_t cqe_fp_flags;
893                 enum eth_rx_cqe_type cqe_fp_type;
894                 uint16_t len, pad, queue;
895                 uint8_t *data;
896                 uint32_t rxhash;
897                 enum pkt_hash_types rxhash_type;
898
899 #ifdef BNX2X_STOP_ON_ERROR
900                 if (unlikely(bp->panic))
901                         return 0;
902 #endif
903
904                 bd_prod = RX_BD(bd_prod);
905                 bd_cons = RX_BD(bd_cons);
906
907                 /* A rmb() is required to ensure that the CQE is not read
908                  * before it is written by the adapter DMA.  PCI ordering
909                  * rules will make sure the other fields are written before
910                  * the marker at the end of struct eth_fast_path_rx_cqe
911                  * but without rmb() a weakly ordered processor can process
912                  * stale data.  Without the barrier TPA state-machine might
913                  * enter inconsistent state and kernel stack might be
914                  * provided with incorrect packet description - these lead
915                  * to various kernel crashed.
916                  */
917                 rmb();
918
919                 cqe_fp_flags = cqe_fp->type_error_flags;
920                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
921
922                 DP(NETIF_MSG_RX_STATUS,
923                    "CQE type %x  err %x  status %x  queue %x  vlan %x  len %u\n",
924                    CQE_TYPE(cqe_fp_flags),
925                    cqe_fp_flags, cqe_fp->status_flags,
926                    le32_to_cpu(cqe_fp->rss_hash_result),
927                    le16_to_cpu(cqe_fp->vlan_tag),
928                    le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len));
929
930                 /* is this a slowpath msg? */
931                 if (unlikely(CQE_TYPE_SLOW(cqe_fp_type))) {
932                         bnx2x_sp_event(fp, cqe);
933                         goto next_cqe;
934                 }
935
936                 rx_buf = &fp->rx_buf_ring[bd_cons];
937                 data = rx_buf->data;
938
939                 if (!CQE_TYPE_FAST(cqe_fp_type)) {
940                         struct bnx2x_agg_info *tpa_info;
941                         uint16_t frag_size, pages;
942 #ifdef BNX2X_STOP_ON_ERROR
943                         /* sanity check */
944                         if (fp->disable_tpa &&
945                             (CQE_TYPE_START(cqe_fp_type) ||
946                              CQE_TYPE_STOP(cqe_fp_type)))
947                                 BNX2X_ERR("START/STOP packet while disable_tpa type %x\n",
948                                           CQE_TYPE(cqe_fp_type));
949 #endif
950
951                         if (CQE_TYPE_START(cqe_fp_type)) {
952                                 uint16_t queue = cqe_fp->queue_index;
953                                 DP(NETIF_MSG_RX_STATUS,
954                                    "calling tpa_start on queue %d\n",
955                                    queue);
956
957                                 bnx2x_tpa_start(fp, queue,
958                                                 bd_cons, bd_prod,
959                                                 cqe_fp);
960
961                                 goto next_rx;
962                         }
963                         queue = cqe->end_agg_cqe.queue_index;
964                         tpa_info = &fp->tpa_info[queue];
965                         DP(NETIF_MSG_RX_STATUS,
966                            "calling tpa_stop on queue %d\n",
967                            queue);
968
969                         frag_size = le16_to_cpu(cqe->end_agg_cqe.pkt_len) -
970                                     tpa_info->len_on_bd;
971
972                         if (fp->mode == TPA_MODE_GRO)
973                                 pages = (frag_size + tpa_info->full_page - 1) /
974                                          tpa_info->full_page;
975                         else
976                                 pages = SGE_PAGE_ALIGN(frag_size) >>
977                                         SGE_PAGE_SHIFT;
978
979                         bnx2x_tpa_stop(bp, fp, tpa_info, pages,
980                                        &cqe->end_agg_cqe, comp_ring_cons);
981 #ifdef BNX2X_STOP_ON_ERROR
982                         if (bp->panic)
983                                 return 0;
984 #endif
985
986                         bnx2x_update_sge_prod(fp, pages, &cqe->end_agg_cqe);
987                         goto next_cqe;
988                 }
989                 /* non TPA */
990                 len = le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len);
991                 pad = cqe_fp->placement_offset;
992                 dma_sync_single_for_cpu(&bp->pdev->dev,
993                                         dma_unmap_addr(rx_buf, mapping),
994                                         pad + RX_COPY_THRESH,
995                                         DMA_FROM_DEVICE);
996                 pad += NET_SKB_PAD;
997                 prefetch(data + pad); /* speedup eth_type_trans() */
998                 /* is this an error packet? */
999                 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1000                         DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1001                            "ERROR  flags %x  rx packet %u\n",
1002                            cqe_fp_flags, sw_comp_cons);
1003                         bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++;
1004                         goto reuse_rx;
1005                 }
1006
1007                 /* Since we don't have a jumbo ring
1008                  * copy small packets if mtu > 1500
1009                  */
1010                 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1011                     (len <= RX_COPY_THRESH)) {
1012                         skb = napi_alloc_skb(&fp->napi, len);
1013                         if (skb == NULL) {
1014                                 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1015                                    "ERROR  packet dropped because of alloc failure\n");
1016                                 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1017                                 goto reuse_rx;
1018                         }
1019                         memcpy(skb->data, data + pad, len);
1020                         bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1021                 } else {
1022                         if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod,
1023                                                        0) == 0)) {
1024                                 dma_unmap_single(&bp->pdev->dev,
1025                                                  dma_unmap_addr(rx_buf, mapping),
1026                                                  fp->rx_buf_size,
1027                                                  DMA_FROM_DEVICE);
1028                                 skb = build_skb(data, fp->rx_frag_size);
1029                                 if (unlikely(!skb)) {
1030                                         bnx2x_frag_free(fp, data);
1031                                         bnx2x_fp_qstats(bp, fp)->
1032                                                         rx_skb_alloc_failed++;
1033                                         goto next_rx;
1034                                 }
1035                                 skb_reserve(skb, pad);
1036                         } else {
1037                                 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1038                                    "ERROR  packet dropped because of alloc failure\n");
1039                                 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1040 reuse_rx:
1041                                 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1042                                 goto next_rx;
1043                         }
1044                 }
1045
1046                 skb_put(skb, len);
1047                 skb->protocol = eth_type_trans(skb, bp->dev);
1048
1049                 /* Set Toeplitz hash for a none-LRO skb */
1050                 rxhash = bnx2x_get_rxhash(bp, cqe_fp, &rxhash_type);
1051                 skb_set_hash(skb, rxhash, rxhash_type);
1052
1053                 skb_checksum_none_assert(skb);
1054
1055                 if (bp->dev->features & NETIF_F_RXCSUM)
1056                         bnx2x_csum_validate(skb, cqe, fp,
1057                                             bnx2x_fp_qstats(bp, fp));
1058
1059                 skb_record_rx_queue(skb, fp->rx_queue);
1060
1061                 /* Check if this packet was timestamped */
1062                 if (unlikely(cqe->fast_path_cqe.type_error_flags &
1063                              (1 << ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT)))
1064                         bnx2x_set_rx_ts(bp, skb);
1065
1066                 if (le16_to_cpu(cqe_fp->pars_flags.flags) &
1067                     PARSING_FLAGS_VLAN)
1068                         __vlan_hwaccel_put_tag(skb, cpu_to_be16(ETH_P_8021Q),
1069                                                le16_to_cpu(cqe_fp->vlan_tag));
1070
1071                 skb_mark_napi_id(skb, &fp->napi);
1072
1073                 if (bnx2x_fp_ll_polling(fp))
1074                         netif_receive_skb(skb);
1075                 else
1076                         napi_gro_receive(&fp->napi, skb);
1077 next_rx:
1078                 rx_buf->data = NULL;
1079
1080                 bd_cons = NEXT_RX_IDX(bd_cons);
1081                 bd_prod = NEXT_RX_IDX(bd_prod);
1082                 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1083                 rx_pkt++;
1084 next_cqe:
1085                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1086                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1087
1088                 /* mark CQE as free */
1089                 BNX2X_SEED_CQE(cqe_fp);
1090
1091                 if (rx_pkt == budget)
1092                         break;
1093
1094                 comp_ring_cons = RCQ_BD(sw_comp_cons);
1095                 cqe = &fp->rx_comp_ring[comp_ring_cons];
1096                 cqe_fp = &cqe->fast_path_cqe;
1097         } /* while */
1098
1099         fp->rx_bd_cons = bd_cons;
1100         fp->rx_bd_prod = bd_prod_fw;
1101         fp->rx_comp_cons = sw_comp_cons;
1102         fp->rx_comp_prod = sw_comp_prod;
1103
1104         /* Update producers */
1105         bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1106                              fp->rx_sge_prod);
1107
1108         fp->rx_pkt += rx_pkt;
1109         fp->rx_calls++;
1110
1111         return rx_pkt;
1112 }
1113
1114 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1115 {
1116         struct bnx2x_fastpath *fp = fp_cookie;
1117         struct bnx2x *bp = fp->bp;
1118         uint8_t cos;
1119
1120         DP(NETIF_MSG_INTR,
1121            "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
1122            fp->index, fp->fw_sb_id, fp->igu_sb_id);
1123
1124         bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1125
1126 #ifdef BNX2X_STOP_ON_ERROR
1127         if (unlikely(bp->panic))
1128                 return IRQ_HANDLED;
1129 #endif
1130
1131         /* Handle Rx and Tx according to MSI-X vector */
1132         for_each_cos_in_tx_queue(fp, cos)
1133                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1134
1135         prefetch(&fp->sb_running_index[SM_RX_ID]);
1136         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1137
1138         return IRQ_HANDLED;
1139 }
1140
1141 /* HW Lock for shared dual port PHYs */
1142 void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1143 {
1144         qlock(&bp->port.phy_mutex);
1145
1146         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1147 }
1148
1149 void bnx2x_release_phy_lock(struct bnx2x *bp)
1150 {
1151         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1152
1153         qunlock(&bp->port.phy_mutex);
1154 }
1155
1156 /* calculates MF speed according to current linespeed and MF configuration */
1157 uint16_t bnx2x_get_mf_speed(struct bnx2x *bp)
1158 {
1159         uint16_t line_speed = bp->link_vars.line_speed;
1160         if (IS_MF(bp)) {
1161                 uint16_t maxCfg = bnx2x_extract_max_cfg(bp,
1162                                                    bp->mf_config[BP_VN(bp)]);
1163
1164                 /* Calculate the current MAX line speed limit for the MF
1165                  * devices
1166                  */
1167                 if (IS_MF_SI(bp))
1168                         line_speed = (line_speed * maxCfg) / 100;
1169                 else { /* SD mode */
1170                         uint16_t vn_max_rate = maxCfg * 100;
1171
1172                         if (vn_max_rate < line_speed)
1173                                 line_speed = vn_max_rate;
1174                 }
1175         }
1176
1177         return line_speed;
1178 }
1179
1180 /**
1181  * bnx2x_fill_report_data - fill link report data to report
1182  *
1183  * @bp:         driver handle
1184  * @data:       link state to update
1185  *
1186  * It uses a none-atomic bit operations because is called under the mutex.
1187  */
1188 static void bnx2x_fill_report_data(struct bnx2x *bp,
1189                                    struct bnx2x_link_report_data *data)
1190 {
1191         memset(data, 0, sizeof(*data));
1192
1193         if (IS_PF(bp)) {
1194                 /* Fill the report data: effective line speed */
1195                 data->line_speed = bnx2x_get_mf_speed(bp);
1196
1197                 /* Link is down */
1198                 if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS))
1199                         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1200                                   &data->link_report_flags);
1201
1202                 if (!BNX2X_NUM_ETH_QUEUES(bp))
1203                         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1204                                   &data->link_report_flags);
1205
1206                 /* Full DUPLEX */
1207                 if (bp->link_vars.duplex == DUPLEX_FULL)
1208                         __set_bit(BNX2X_LINK_REPORT_FD,
1209                                   &data->link_report_flags);
1210
1211                 /* Rx Flow Control is ON */
1212                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX)
1213                         __set_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1214                                   &data->link_report_flags);
1215
1216                 /* Tx Flow Control is ON */
1217                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1218                         __set_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1219                                   &data->link_report_flags);
1220         } else { /* VF */
1221                 *data = bp->vf_link_vars;
1222         }
1223 }
1224
1225 /**
1226  * bnx2x_link_report - report link status to OS.
1227  *
1228  * @bp:         driver handle
1229  *
1230  * Calls the __bnx2x_link_report() under the same locking scheme
1231  * as a link/PHY state managing code to ensure a consistent link
1232  * reporting.
1233  */
1234
1235 void bnx2x_link_report(struct bnx2x *bp)
1236 {
1237         bnx2x_acquire_phy_lock(bp);
1238         __bnx2x_link_report(bp);
1239         bnx2x_release_phy_lock(bp);
1240 }
1241
1242 /**
1243  * __bnx2x_link_report - report link status to OS.
1244  *
1245  * @bp:         driver handle
1246  *
1247  * None atomic implementation.
1248  * Should be called under the phy_lock.
1249  */
1250 void __bnx2x_link_report(struct bnx2x *bp)
1251 {
1252         struct bnx2x_link_report_data cur_data;
1253
1254         /* reread mf_cfg */
1255         if (IS_PF(bp) && !CHIP_IS_E1(bp))
1256                 bnx2x_read_mf_cfg(bp);
1257
1258         /* Read the current link report info */
1259         bnx2x_fill_report_data(bp, &cur_data);
1260
1261         /* Don't report link down or exactly the same link status twice */
1262         if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) ||
1263             (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1264                       &bp->last_reported_link.link_report_flags) &&
1265              test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1266                       &cur_data.link_report_flags)))
1267                 return;
1268
1269         bp->link_cnt++;
1270
1271         /* We are going to report a new link parameters now -
1272          * remember the current data for the next time.
1273          */
1274         memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data));
1275
1276         /* propagate status to VFs */
1277         if (IS_PF(bp))
1278                 bnx2x_iov_link_update(bp);
1279
1280         if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1281                      &cur_data.link_report_flags)) {
1282                 netif_carrier_off(bp->dev);
1283                 netdev_err(bp->dev, "NIC Link is Down\n");
1284                 return;
1285         } else {
1286                 const char *duplex;
1287                 const char *flow;
1288
1289                 netif_carrier_on(bp->dev);
1290
1291                 if (test_and_clear_bit(BNX2X_LINK_REPORT_FD,
1292                                        &cur_data.link_report_flags))
1293                         duplex = "full";
1294                 else
1295                         duplex = "half";
1296
1297                 /* Handle the FC at the end so that only these flags would be
1298                  * possibly set. This way we may easily check if there is no FC
1299                  * enabled.
1300                  */
1301                 if (cur_data.link_report_flags) {
1302                         if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1303                                      &cur_data.link_report_flags)) {
1304                                 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1305                                      &cur_data.link_report_flags))
1306                                         flow = "ON - receive & transmit";
1307                                 else
1308                                         flow = "ON - receive";
1309                         } else {
1310                                 flow = "ON - transmit";
1311                         }
1312                 } else {
1313                         flow = "none";
1314                 }
1315                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
1316                             cur_data.line_speed, duplex, flow);
1317         }
1318 }
1319
1320 static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
1321 {
1322         int i;
1323
1324         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1325                 struct eth_rx_sge *sge;
1326
1327                 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
1328                 sge->addr_hi =
1329                         cpu_to_le32(U64_HI(fp->rx_sge_mapping +
1330                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1331
1332                 sge->addr_lo =
1333                         cpu_to_le32(U64_LO(fp->rx_sge_mapping +
1334                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1335         }
1336 }
1337
1338 static void bnx2x_free_tpa_pool(struct bnx2x *bp,
1339                                 struct bnx2x_fastpath *fp, int last)
1340 {
1341         int i;
1342
1343         for (i = 0; i < last; i++) {
1344                 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
1345                 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
1346                 uint8_t *data = first_buf->data;
1347
1348                 if (data == NULL) {
1349                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
1350                         continue;
1351                 }
1352                 if (tpa_info->tpa_state == BNX2X_TPA_START)
1353                         dma_unmap_single(&bp->pdev->dev,
1354                                          dma_unmap_addr(first_buf, mapping),
1355                                          fp->rx_buf_size, DMA_FROM_DEVICE);
1356                 bnx2x_frag_free(fp, data);
1357                 first_buf->data = NULL;
1358         }
1359 }
1360
1361 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
1362 {
1363         int j;
1364
1365         for_each_rx_queue_cnic(bp, j) {
1366                 struct bnx2x_fastpath *fp = &bp->fp[j];
1367
1368                 fp->rx_bd_cons = 0;
1369
1370                 /* Activate BD ring */
1371                 /* Warning!
1372                  * this will generate an interrupt (to the TSTORM)
1373                  * must only be done after chip is initialized
1374                  */
1375                 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1376                                      fp->rx_sge_prod);
1377         }
1378 }
1379
1380 void bnx2x_init_rx_rings(struct bnx2x *bp)
1381 {
1382         int func = BP_FUNC(bp);
1383         uint16_t ring_prod;
1384         int i, j;
1385
1386         /* Allocate TPA resources */
1387         for_each_eth_queue(bp, j) {
1388                 struct bnx2x_fastpath *fp = &bp->fp[j];
1389
1390                 DP(NETIF_MSG_IFUP,
1391                    "mtu %d  rx_buf_size %d\n", bp->dev->mtu, fp->rx_buf_size);
1392
1393                 if (!fp->disable_tpa) {
1394                         /* Fill the per-aggregation pool */
1395                         for (i = 0; i < MAX_AGG_QS(bp); i++) {
1396                                 struct bnx2x_agg_info *tpa_info =
1397                                         &fp->tpa_info[i];
1398                                 struct sw_rx_bd *first_buf =
1399                                         &tpa_info->first_buf;
1400
1401                                 first_buf->data =
1402                                         bnx2x_frag_alloc(fp, KMALLOC_WAIT);
1403                                 if (!first_buf->data) {
1404                                         BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n",
1405                                                   j);
1406                                         bnx2x_free_tpa_pool(bp, fp, i);
1407                                         fp->disable_tpa = 1;
1408                                         break;
1409                                 }
1410                                 dma_unmap_addr_set(first_buf, mapping, 0);
1411                                 tpa_info->tpa_state = BNX2X_TPA_STOP;
1412                         }
1413
1414                         /* "next page" elements initialization */
1415                         bnx2x_set_next_page_sgl(fp);
1416
1417                         /* set SGEs bit mask */
1418                         bnx2x_init_sge_ring_bit_mask(fp);
1419
1420                         /* Allocate SGEs and initialize the ring elements */
1421                         for (i = 0, ring_prod = 0;
1422                              i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
1423
1424                                 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod,
1425                                                        KMALLOC_WAIT) < 0) {
1426                                         BNX2X_ERR("was only able to allocate %d rx sges\n",
1427                                                   i);
1428                                         BNX2X_ERR("disabling TPA for queue[%d]\n",
1429                                                   j);
1430                                         /* Cleanup already allocated elements */
1431                                         bnx2x_free_rx_sge_range(bp, fp,
1432                                                                 ring_prod);
1433                                         bnx2x_free_tpa_pool(bp, fp,
1434                                                             MAX_AGG_QS(bp));
1435                                         fp->disable_tpa = 1;
1436                                         ring_prod = 0;
1437                                         break;
1438                                 }
1439                                 ring_prod = NEXT_SGE_IDX(ring_prod);
1440                         }
1441
1442                         fp->rx_sge_prod = ring_prod;
1443                 }
1444         }
1445
1446         for_each_eth_queue(bp, j) {
1447                 struct bnx2x_fastpath *fp = &bp->fp[j];
1448
1449                 fp->rx_bd_cons = 0;
1450
1451                 /* Activate BD ring */
1452                 /* Warning!
1453                  * this will generate an interrupt (to the TSTORM)
1454                  * must only be done after chip is initialized
1455                  */
1456                 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1457                                      fp->rx_sge_prod);
1458
1459                 if (j != 0)
1460                         continue;
1461
1462                 if (CHIP_IS_E1(bp)) {
1463                         REG_WR(bp, BAR_USTRORM_INTMEM +
1464                                USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
1465                                U64_LO(fp->rx_comp_mapping));
1466                         REG_WR(bp, BAR_USTRORM_INTMEM +
1467                                USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
1468                                U64_HI(fp->rx_comp_mapping));
1469                 }
1470         }
1471 }
1472
1473 static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp)
1474 {
1475         uint8_t cos;
1476         struct bnx2x *bp = fp->bp;
1477
1478         for_each_cos_in_tx_queue(fp, cos) {
1479                 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1480                 unsigned pkts_compl = 0, bytes_compl = 0;
1481
1482                 uint16_t sw_prod = txdata->tx_pkt_prod;
1483                 uint16_t sw_cons = txdata->tx_pkt_cons;
1484
1485                 while (sw_cons != sw_prod) {
1486                         bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
1487                                           &pkts_compl, &bytes_compl);
1488                         sw_cons++;
1489                 }
1490
1491                 netdev_tx_reset_queue(
1492                         netdev_get_tx_queue(bp->dev,
1493                                             txdata->txq_index));
1494         }
1495 }
1496
1497 static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp)
1498 {
1499         int i;
1500
1501         for_each_tx_queue_cnic(bp, i) {
1502                 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1503         }
1504 }
1505
1506 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
1507 {
1508         int i;
1509
1510         for_each_eth_queue(bp, i) {
1511                 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1512         }
1513 }
1514
1515 static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp)
1516 {
1517         struct bnx2x *bp = fp->bp;
1518         int i;
1519
1520         /* ring wasn't allocated */
1521         if (fp->rx_buf_ring == NULL)
1522                 return;
1523
1524         for (i = 0; i < NUM_RX_BD; i++) {
1525                 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
1526                 uint8_t *data = rx_buf->data;
1527
1528                 if (data == NULL)
1529                         continue;
1530                 dma_unmap_single(&bp->pdev->dev,
1531                                  dma_unmap_addr(rx_buf, mapping),
1532                                  fp->rx_buf_size, DMA_FROM_DEVICE);
1533
1534                 rx_buf->data = NULL;
1535                 bnx2x_frag_free(fp, data);
1536         }
1537 }
1538
1539 static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp)
1540 {
1541         int j;
1542
1543         for_each_rx_queue_cnic(bp, j) {
1544                 bnx2x_free_rx_bds(&bp->fp[j]);
1545         }
1546 }
1547
1548 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
1549 {
1550         int j;
1551
1552         for_each_eth_queue(bp, j) {
1553                 struct bnx2x_fastpath *fp = &bp->fp[j];
1554
1555                 bnx2x_free_rx_bds(fp);
1556
1557                 if (!fp->disable_tpa)
1558                         bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
1559         }
1560 }
1561
1562 static void bnx2x_free_skbs_cnic(struct bnx2x *bp)
1563 {
1564         bnx2x_free_tx_skbs_cnic(bp);
1565         bnx2x_free_rx_skbs_cnic(bp);
1566 }
1567
1568 void bnx2x_free_skbs(struct bnx2x *bp)
1569 {
1570         bnx2x_free_tx_skbs(bp);
1571         bnx2x_free_rx_skbs(bp);
1572 }
1573
1574 void bnx2x_update_max_mf_config(struct bnx2x *bp, uint32_t value)
1575 {
1576         /* load old values */
1577         uint32_t mf_cfg = bp->mf_config[BP_VN(bp)];
1578
1579         if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
1580                 /* leave all but MAX value */
1581                 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
1582
1583                 /* set new MAX value */
1584                 mf_cfg |= (value << FUNC_MF_CFG_MAX_BW_SHIFT)
1585                                 & FUNC_MF_CFG_MAX_BW_MASK;
1586
1587                 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
1588         }
1589 }
1590
1591 /**
1592  * bnx2x_free_msix_irqs - free previously requested MSI-X IRQ vectors
1593  *
1594  * @bp:         driver handle
1595  * @nvecs:      number of vectors to be released
1596  */
1597 static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
1598 {
1599         int i, offset = 0;
1600
1601         if (nvecs == offset)
1602                 return;
1603
1604         /* VFs don't have a default SB */
1605         if (IS_PF(bp)) {
1606                 free_irq(bp->msix_table[offset].vector, bp->dev);
1607                 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
1608                    bp->msix_table[offset].vector);
1609                 offset++;
1610         }
1611
1612         if (CNIC_SUPPORT(bp)) {
1613                 if (nvecs == offset)
1614                         return;
1615                 offset++;
1616         }
1617
1618         for_each_eth_queue(bp, i) {
1619                 if (nvecs == offset)
1620                         return;
1621                 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n",
1622                    i, bp->msix_table[offset].vector);
1623
1624                 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
1625         }
1626 }
1627
1628 void bnx2x_free_irq(struct bnx2x *bp)
1629 {
1630         if (bp->flags & USING_MSIX_FLAG &&
1631             !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1632                 int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp);
1633
1634                 /* vfs don't have a default status block */
1635                 if (IS_PF(bp))
1636                         nvecs++;
1637
1638                 bnx2x_free_msix_irqs(bp, nvecs);
1639         } else {
1640                 free_irq(bp->dev->irq, bp->dev);
1641         }
1642 }
1643
1644 int bnx2x_enable_msix(struct bnx2x *bp)
1645 {
1646         int msix_vec = 0, i, rc;
1647
1648         /* VFs don't have a default status block */
1649         if (IS_PF(bp)) {
1650                 bp->msix_table[msix_vec].entry = msix_vec;
1651                 BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n",
1652                                bp->msix_table[0].entry);
1653                 msix_vec++;
1654         }
1655
1656         /* Cnic requires an msix vector for itself */
1657         if (CNIC_SUPPORT(bp)) {
1658                 bp->msix_table[msix_vec].entry = msix_vec;
1659                 BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n",
1660                                msix_vec, bp->msix_table[msix_vec].entry);
1661                 msix_vec++;
1662         }
1663
1664         /* We need separate vectors for ETH queues only (not FCoE) */
1665         for_each_eth_queue(bp, i) {
1666                 bp->msix_table[msix_vec].entry = msix_vec;
1667                 BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n",
1668                                msix_vec, msix_vec, i);
1669                 msix_vec++;
1670         }
1671
1672         DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n",
1673            msix_vec);
1674
1675         rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0],
1676                                    BNX2X_MIN_MSIX_VEC_CNT(bp), msix_vec);
1677         /*
1678          * reconfigure number of tx/rx queues according to available
1679          * MSI-X vectors
1680          */
1681         if (rc == -ENOSPC) {
1682                 /* Get by with single vector */
1683                 rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0], 1, 1);
1684                 if (rc < 0) {
1685                         BNX2X_DEV_INFO("Single MSI-X is not attainable rc %d\n",
1686                                        rc);
1687                         goto no_msix;
1688                 }
1689
1690                 BNX2X_DEV_INFO("Using single MSI-X vector\n");
1691                 bp->flags |= USING_SINGLE_MSIX_FLAG;
1692
1693                 BNX2X_DEV_INFO("set number of queues to 1\n");
1694                 bp->num_ethernet_queues = 1;
1695                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1696         } else if (rc < 0) {
1697                 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1698                 goto no_msix;
1699         } else if (rc < msix_vec) {
1700                 /* how less vectors we will have? */
1701                 int diff = msix_vec - rc;
1702
1703                 BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc);
1704
1705                 /*
1706                  * decrease number of queues by number of unallocated entries
1707                  */
1708                 bp->num_ethernet_queues -= diff;
1709                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1710
1711                 BNX2X_DEV_INFO("New queue configuration set: %d\n",
1712                                bp->num_queues);
1713         }
1714
1715         bp->flags |= USING_MSIX_FLAG;
1716
1717         return 0;
1718
1719 no_msix:
1720         /* fall to INTx if not enough memory */
1721         if (rc == -ENOMEM)
1722                 bp->flags |= DISABLE_MSI_FLAG;
1723
1724         return rc;
1725 }
1726
1727 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1728 {
1729         int i, rc, offset = 0;
1730
1731         /* no default status block for vf */
1732         if (IS_PF(bp)) {
1733                 rc = request_irq(bp->msix_table[offset++].vector,
1734                                  bnx2x_msix_sp_int, 0,
1735                                  bp->dev->name, bp->dev);
1736                 if (rc) {
1737                         BNX2X_ERR("request sp irq failed\n");
1738                         return -EBUSY;
1739                 }
1740         }
1741
1742         if (CNIC_SUPPORT(bp))
1743                 offset++;
1744
1745         for_each_eth_queue(bp, i) {
1746                 struct bnx2x_fastpath *fp = &bp->fp[i];
1747                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1748                          bp->dev->name, i);
1749
1750                 rc = request_irq(bp->msix_table[offset].vector,
1751                                  bnx2x_msix_fp_int, 0, fp->name, fp);
1752                 if (rc) {
1753                         BNX2X_ERR("request fp #%d irq (%d) failed  rc %d\n", i,
1754                               bp->msix_table[offset].vector, rc);
1755                         bnx2x_free_msix_irqs(bp, offset);
1756                         return -EBUSY;
1757                 }
1758
1759                 offset++;
1760         }
1761
1762         i = BNX2X_NUM_ETH_QUEUES(bp);
1763         if (IS_PF(bp)) {
1764                 offset = 1 + CNIC_SUPPORT(bp);
1765                 netdev_info(bp->dev,
1766                             "using MSI-X  IRQs: sp %d  fp[%d] %d ... fp[%d] %d\n",
1767                             bp->msix_table[0].vector,
1768                             0, bp->msix_table[offset].vector,
1769                             i - 1, bp->msix_table[offset + i - 1].vector);
1770         } else {
1771                 offset = CNIC_SUPPORT(bp);
1772                 netdev_info(bp->dev,
1773                             "using MSI-X  IRQs: fp[%d] %d ... fp[%d] %d\n",
1774                             0, bp->msix_table[offset].vector,
1775                             i - 1, bp->msix_table[offset + i - 1].vector);
1776         }
1777         return 0;
1778 }
1779
1780 int bnx2x_enable_msi(struct bnx2x *bp)
1781 {
1782         int rc;
1783
1784         rc = pci_enable_msi(bp->pdev);
1785         if (rc) {
1786                 BNX2X_DEV_INFO("MSI is not attainable\n");
1787                 return -1;
1788         }
1789         bp->flags |= USING_MSI_FLAG;
1790
1791         return 0;
1792 }
1793
1794 static int bnx2x_req_irq(struct bnx2x *bp)
1795 {
1796         unsigned long flags;
1797         unsigned int irq;
1798
1799         if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG))
1800                 flags = 0;
1801         else
1802                 flags = IRQF_SHARED;
1803
1804         if (bp->flags & USING_MSIX_FLAG)
1805                 irq = bp->msix_table[0].vector;
1806         else
1807                 irq = bp->pdev->irq;
1808
1809         return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev);
1810 }
1811
1812 static int bnx2x_setup_irqs(struct bnx2x *bp)
1813 {
1814         int rc = 0;
1815         if (bp->flags & USING_MSIX_FLAG &&
1816             !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1817                 rc = bnx2x_req_msix_irqs(bp);
1818                 if (rc)
1819                         return rc;
1820         } else {
1821                 rc = bnx2x_req_irq(bp);
1822                 if (rc) {
1823                         BNX2X_ERR("IRQ request failed  rc %d, aborting\n", rc);
1824                         return rc;
1825                 }
1826                 if (bp->flags & USING_MSI_FLAG) {
1827                         bp->dev->irq = bp->pdev->irq;
1828                         netdev_info(bp->dev, "using MSI IRQ %d\n",
1829                                     bp->dev->irq);
1830                 }
1831                 if (bp->flags & USING_MSIX_FLAG) {
1832                         bp->dev->irq = bp->msix_table[0].vector;
1833                         netdev_info(bp->dev, "using MSIX IRQ %d\n",
1834                                     bp->dev->irq);
1835                 }
1836         }
1837
1838         return 0;
1839 }
1840
1841 static void bnx2x_napi_enable_cnic(struct bnx2x *bp)
1842 {
1843         int i;
1844
1845         for_each_rx_queue_cnic(bp, i) {
1846                 bnx2x_fp_init_lock(&bp->fp[i]);
1847                 napi_enable(&bnx2x_fp(bp, i, napi));
1848         }
1849 }
1850
1851 static void bnx2x_napi_enable(struct bnx2x *bp)
1852 {
1853         int i;
1854
1855         for_each_eth_queue(bp, i) {
1856                 bnx2x_fp_init_lock(&bp->fp[i]);
1857                 napi_enable(&bnx2x_fp(bp, i, napi));
1858         }
1859 }
1860
1861 static void bnx2x_napi_disable_cnic(struct bnx2x *bp)
1862 {
1863         int i;
1864
1865         for_each_rx_queue_cnic(bp, i) {
1866                 napi_disable(&bnx2x_fp(bp, i, napi));
1867                 while (!bnx2x_fp_ll_disable(&bp->fp[i]))
1868                         kthread_usleep(1000);
1869         }
1870 }
1871
1872 static void bnx2x_napi_disable(struct bnx2x *bp)
1873 {
1874         int i;
1875
1876         for_each_eth_queue(bp, i) {
1877                 napi_disable(&bnx2x_fp(bp, i, napi));
1878                 while (!bnx2x_fp_ll_disable(&bp->fp[i]))
1879                         kthread_usleep(1000);
1880         }
1881 }
1882
1883 void bnx2x_netif_start(struct bnx2x *bp)
1884 {
1885         if (netif_running(bp->dev)) {
1886                 bnx2x_napi_enable(bp);
1887                 if (CNIC_LOADED(bp))
1888                         bnx2x_napi_enable_cnic(bp);
1889                 bnx2x_int_enable(bp);
1890                 if (bp->state == BNX2X_STATE_OPEN)
1891                         netif_tx_wake_all_queues(bp->dev);
1892         }
1893 }
1894
1895 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
1896 {
1897         bnx2x_int_disable_sync(bp, disable_hw);
1898         bnx2x_napi_disable(bp);
1899         if (CNIC_LOADED(bp))
1900                 bnx2x_napi_disable_cnic(bp);
1901 }
1902
1903 uint16_t bnx2x_select_queue(struct ether *dev, struct sk_buff *skb,
1904                        void *accel_priv, select_queue_fallback_t fallback)
1905 {
1906         struct bnx2x *bp = netdev_priv(dev);
1907
1908         if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
1909                 struct ethhdr *hdr = (struct ethhdr *)skb->data;
1910                 uint16_t ether_type = be16_to_cpu(hdr->h_proto);
1911
1912                 /* Skip VLAN tag if present */
1913                 if (ether_type == ETH_P_8021Q) {
1914                         struct vlan_ethhdr *vhdr =
1915                                 (struct vlan_ethhdr *)skb->data;
1916
1917                         ether_type = be16_to_cpu(vhdr->h_vlan_encapsulated_proto);
1918                 }
1919
1920                 /* If ethertype is FCoE or FIP - use FCoE ring */
1921                 if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP))
1922                         return bnx2x_fcoe_tx(bp, txq_index);
1923         }
1924
1925         /* select a non-FCoE queue */
1926         return fallback(dev, skb) % BNX2X_NUM_ETH_QUEUES(bp);
1927 }
1928
1929 void bnx2x_set_num_queues(struct bnx2x *bp)
1930 {
1931         /* RSS queues */
1932         bp->num_ethernet_queues = bnx2x_calc_num_queues(bp);
1933
1934         /* override in STORAGE SD modes */
1935         if (IS_MF_STORAGE_ONLY(bp))
1936                 bp->num_ethernet_queues = 1;
1937
1938         /* Add special queues */
1939         bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */
1940         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1941
1942         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
1943 }
1944
1945 /**
1946  * bnx2x_set_real_num_queues - configure netdev->real_num_[tx,rx]_queues
1947  *
1948  * @bp:         Driver handle
1949  *
1950  * We currently support for at most 16 Tx queues for each CoS thus we will
1951  * allocate a multiple of 16 for ETH L2 rings according to the value of the
1952  * bp->max_cos.
1953  *
1954  * If there is an FCoE L2 queue the appropriate Tx queue will have the next
1955  * index after all ETH L2 indices.
1956  *
1957  * If the actual number of Tx queues (for each CoS) is less than 16 then there
1958  * will be the holes at the end of each group of 16 ETh L2 indices (0..15,
1959  * 16..31,...) with indices that are not coupled with any real Tx queue.
1960  *
1961  * The proper configuration of skb->queue_mapping is handled by
1962  * bnx2x_select_queue() and __skb_tx_hash().
1963  *
1964  * bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash()
1965  * will return a proper Tx index if TC is enabled (netdev->num_tc > 0).
1966  */
1967 static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic)
1968 {
1969         int rc, tx, rx;
1970
1971         tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos;
1972         rx = BNX2X_NUM_ETH_QUEUES(bp);
1973
1974 /* account for fcoe queue */
1975         if (include_cnic && !NO_FCOE(bp)) {
1976                 rx++;
1977                 tx++;
1978         }
1979
1980         rc = netif_set_real_num_tx_queues(bp->dev, tx);
1981         if (rc) {
1982                 BNX2X_ERR("Failed to set real number of Tx queues: %d\n", rc);
1983                 return rc;
1984         }
1985         rc = netif_set_real_num_rx_queues(bp->dev, rx);
1986         if (rc) {
1987                 BNX2X_ERR("Failed to set real number of Rx queues: %d\n", rc);
1988                 return rc;
1989         }
1990
1991         DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n",
1992                           tx, rx);
1993
1994         return rc;
1995 }
1996
1997 static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
1998 {
1999         int i;
2000
2001         for_each_queue(bp, i) {
2002                 struct bnx2x_fastpath *fp = &bp->fp[i];
2003                 uint32_t mtu;
2004
2005                 /* Always use a mini-jumbo MTU for the FCoE L2 ring */
2006                 if (IS_FCOE_IDX(i))
2007                         /*
2008                          * Although there are no IP frames expected to arrive to
2009                          * this ring we still want to add an
2010                          * IP_HEADER_ALIGNMENT_PADDING to prevent a buffer
2011                          * overrun attack.
2012                          */
2013                         mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2014                 else
2015                         mtu = bp->dev->mtu;
2016                 fp->rx_buf_size = BNX2X_FW_RX_ALIGN_START +
2017                                   IP_HEADER_ALIGNMENT_PADDING +
2018                                   ETH_OVREHEAD +
2019                                   mtu +
2020                                   BNX2X_FW_RX_ALIGN_END;
2021                 /* Note : rx_buf_size doesn't take into account NET_SKB_PAD */
2022                 if (fp->rx_buf_size + NET_SKB_PAD <= PAGE_SIZE)
2023                         fp->rx_frag_size = fp->rx_buf_size + NET_SKB_PAD;
2024                 else
2025                         fp->rx_frag_size = 0;
2026         }
2027 }
2028
2029 static int bnx2x_init_rss(struct bnx2x *bp)
2030 {
2031         int i;
2032         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2033
2034         /* Prepare the initial contents for the indirection table if RSS is
2035          * enabled
2036          */
2037         for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++)
2038                 bp->rss_conf_obj.ind_table[i] =
2039                         bp->fp->cl_id +
2040                         ethtool_rxfh_indir_default(i, num_eth_queues);
2041
2042         /*
2043          * For 57710 and 57711 SEARCHER configuration (rss_keys) is
2044          * per-port, so if explicit configuration is needed , do it only
2045          * for a PMF.
2046          *
2047          * For 57712 and newer on the other hand it's a per-function
2048          * configuration.
2049          */
2050         return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp));
2051 }
2052
2053 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
2054               bool config_hash, bool enable)
2055 {
2056         struct bnx2x_config_rss_params params = {NULL};
2057
2058         /* Although RSS is meaningless when there is a single HW queue we
2059          * still need it enabled in order to have HW Rx hash generated.
2060          *
2061          * if (!is_eth_multi(bp))
2062          *      bp->multi_mode = ETH_RSS_MODE_DISABLED;
2063          */
2064
2065         params.rss_obj = rss_obj;
2066
2067         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2068
2069         if (enable) {
2070                 __set_bit(BNX2X_RSS_MODE_REGULAR, &params.rss_flags);
2071
2072                 /* RSS configuration */
2073                 __set_bit(BNX2X_RSS_IPV4, &params.rss_flags);
2074                 __set_bit(BNX2X_RSS_IPV4_TCP, &params.rss_flags);
2075                 __set_bit(BNX2X_RSS_IPV6, &params.rss_flags);
2076                 __set_bit(BNX2X_RSS_IPV6_TCP, &params.rss_flags);
2077                 if (rss_obj->udp_rss_v4)
2078                         __set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags);
2079                 if (rss_obj->udp_rss_v6)
2080                         __set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);
2081
2082                 if (!CHIP_IS_E1x(bp))
2083                         /* valid only for TUNN_MODE_GRE tunnel mode */
2084                         __set_bit(BNX2X_RSS_GRE_INNER_HDRS, &params.rss_flags);
2085         } else {
2086                 __set_bit(BNX2X_RSS_MODE_DISABLED, &params.rss_flags);
2087         }
2088
2089         /* Hash bits */
2090         params.rss_result_mask = MULTI_MASK;
2091
2092         memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
2093
2094         if (config_hash) {
2095                 /* RSS keys */
2096                 netdev_rss_key_fill(params.rss_key, T_ETH_RSS_KEY * 4);
2097                 __set_bit(BNX2X_RSS_SET_SRCH, &params.rss_flags);
2098         }
2099
2100         if (IS_PF(bp))
2101                 return bnx2x_config_rss(bp, &params);
2102         else
2103                 return bnx2x_vfpf_config_rss(bp, &params);
2104 }
2105
2106 static int bnx2x_init_hw(struct bnx2x *bp, uint32_t load_code)
2107 {
2108         struct bnx2x_func_state_params func_params = {NULL};
2109
2110         /* Prepare parameters for function state transitions */
2111         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
2112
2113         func_params.f_obj = &bp->func_obj;
2114         func_params.cmd = BNX2X_F_CMD_HW_INIT;
2115
2116         func_params.params.hw_init.load_phase = load_code;
2117
2118         return bnx2x_func_state_change(bp, &func_params);
2119 }
2120
2121 /*
2122  * Cleans the object that have internal lists without sending
2123  * ramrods. Should be run when interrupts are disabled.
2124  */
2125 void bnx2x_squeeze_objects(struct bnx2x *bp)
2126 {
2127         int rc;
2128         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
2129         struct bnx2x_mcast_ramrod_params rparam = {NULL};
2130         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
2131
2132         /***************** Cleanup MACs' object first *************************/
2133
2134         /* Wait for completion of requested */
2135         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2136         /* Perform a dry cleanup */
2137         __set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
2138
2139         /* Clean ETH primary MAC */
2140         __set_bit(BNX2X_ETH_MAC, &vlan_mac_flags);
2141         rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags,
2142                                  &ramrod_flags);
2143         if (rc != 0)
2144                 BNX2X_ERR("Failed to clean ETH MACs: %d\n", rc);
2145
2146         /* Cleanup UC list */
2147         vlan_mac_flags = 0;
2148         __set_bit(BNX2X_UC_LIST_MAC, &vlan_mac_flags);
2149         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags,
2150                                  &ramrod_flags);
2151         if (rc != 0)
2152                 BNX2X_ERR("Failed to clean UC list MACs: %d\n", rc);
2153
2154         /***************** Now clean mcast object *****************************/
2155         rparam.mcast_obj = &bp->mcast_obj;
2156         __set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
2157
2158         /* Add a DEL command... - Since we're doing a driver cleanup only,
2159          * we take a lock surrounding both the initial send and the CONTs,
2160          * as we don't want a true completion to disrupt us in the middle.
2161          */
2162         netif_addr_lock_bh(bp->dev);
2163         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
2164         if (rc < 0)
2165                 BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n",
2166                           rc);
2167
2168         /* ...and wait until all pending commands are cleared */
2169         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2170         while (rc != 0) {
2171                 if (rc < 0) {
2172                         BNX2X_ERR("Failed to clean multi-cast object: %d\n",
2173                                   rc);
2174                         netif_addr_unlock_bh(bp->dev);
2175                         return;
2176                 }
2177
2178                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2179         }
2180         netif_addr_unlock_bh(bp->dev);
2181 }
2182
2183 #ifndef BNX2X_STOP_ON_ERROR
2184 #define LOAD_ERROR_EXIT(bp, label) \
2185         do { \
2186                 (bp)->state = BNX2X_STATE_ERROR; \
2187                 goto label; \
2188         } while (0)
2189
2190 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2191         do { \
2192                 bp->cnic_loaded = false; \
2193                 goto label; \
2194         } while (0)
2195 #else /*BNX2X_STOP_ON_ERROR*/
2196 #define LOAD_ERROR_EXIT(bp, label) \
2197         do { \
2198                 (bp)->state = BNX2X_STATE_ERROR; \
2199                 (bp)->panic = 1; \
2200                 return -EBUSY; \
2201         } while (0)
2202 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2203         do { \
2204                 bp->cnic_loaded = false; \
2205                 (bp)->panic = 1; \
2206                 return -EBUSY; \
2207         } while (0)
2208 #endif /*BNX2X_STOP_ON_ERROR*/
2209
2210 static void bnx2x_free_fw_stats_mem(struct bnx2x *bp)
2211 {
2212         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
2213                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2214         return;
2215 }
2216
2217 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
2218 {
2219         int num_groups, vf_headroom = 0;
2220         int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
2221
2222         /* number of queues for statistics is number of eth queues + FCoE */
2223         uint8_t num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
2224
2225         /* Total number of FW statistics requests =
2226          * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper
2227          * and fcoe l2 queue) stats + num of queues (which includes another 1
2228          * for fcoe l2 queue if applicable)
2229          */
2230         bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
2231
2232         /* vf stats appear in the request list, but their data is allocated by
2233          * the VFs themselves. We don't include them in the bp->fw_stats_num as
2234          * it is used to determine where to place the vf stats queries in the
2235          * request struct
2236          */
2237         if (IS_SRIOV(bp))
2238                 vf_headroom = bnx2x_vf_headroom(bp);
2239
2240         /* Request is built from stats_query_header and an array of
2241          * stats_query_cmd_group each of which contains
2242          * STATS_QUERY_CMD_COUNT rules. The real number or requests is
2243          * configured in the stats_query_header.
2244          */
2245         num_groups =
2246                 (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +
2247                  (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?
2248                  1 : 0));
2249
2250         DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n",
2251            bp->fw_stats_num, vf_headroom, num_groups);
2252         bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
2253                 num_groups * sizeof(struct stats_query_cmd_group);
2254
2255         /* Data for statistics requests + stats_counter
2256          * stats_counter holds per-STORM counters that are incremented
2257          * when STORM has finished with the current request.
2258          * memory for FCoE offloaded statistics are counted anyway,
2259          * even if they will not be sent.
2260          * VF stats are not accounted for here as the data of VF stats is stored
2261          * in memory allocated by the VF, not here.
2262          */
2263         bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
2264                 sizeof(struct per_pf_stats) +
2265                 sizeof(struct fcoe_statistics_params) +
2266                 sizeof(struct per_queue_stats) * num_queue_stats +
2267                 sizeof(struct stats_counter);
2268
2269         bp->fw_stats = BNX2X_PCI_ALLOC(&bp->fw_stats_mapping,
2270                                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2271         if (!bp->fw_stats)
2272                 goto alloc_mem_err;
2273
2274         /* Set shortcuts */
2275         bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
2276         bp->fw_stats_req_mapping = bp->fw_stats_mapping;
2277         bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
2278                 ((uint8_t *)bp->fw_stats + bp->fw_stats_req_sz);
2279         bp->fw_stats_data_mapping = bp->fw_stats_mapping +
2280                 bp->fw_stats_req_sz;
2281
2282         DP(BNX2X_MSG_SP, "statistics request base address set to %x %x\n",
2283            U64_HI(bp->fw_stats_req_mapping),
2284            U64_LO(bp->fw_stats_req_mapping));
2285         DP(BNX2X_MSG_SP, "statistics data base address set to %x %x\n",
2286            U64_HI(bp->fw_stats_data_mapping),
2287            U64_LO(bp->fw_stats_data_mapping));
2288         return 0;
2289
2290 alloc_mem_err:
2291         bnx2x_free_fw_stats_mem(bp);
2292         BNX2X_ERR("Can't allocate FW stats memory\n");
2293         return -ENOMEM;
2294 }
2295
2296 /* send load request to mcp and analyze response */
2297 static int bnx2x_nic_load_request(struct bnx2x *bp, uint32_t *load_code)
2298 {
2299         uint32_t param;
2300
2301         /* init fw_seq */
2302         bp->fw_seq =
2303                 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
2304                  DRV_MSG_SEQ_NUMBER_MASK);
2305         BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
2306
2307         /* Get current FW pulse sequence */
2308         bp->fw_drv_pulse_wr_seq =
2309                 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) &
2310                  DRV_PULSE_SEQ_MASK);
2311         BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
2312
2313         param = DRV_MSG_CODE_LOAD_REQ_WITH_LFA;
2314
2315         if (IS_MF_SD(bp) && bnx2x_port_after_undi(bp))
2316                 param |= DRV_MSG_CODE_LOAD_REQ_FORCE_LFA;
2317
2318         /* load request */
2319         (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, param);
2320
2321         /* if mcp fails to respond we must abort */
2322         if (!(*load_code)) {
2323                 BNX2X_ERR("MCP response failure, aborting\n");
2324                 return -EBUSY;
2325         }
2326
2327         /* If mcp refused (e.g. other port is in diagnostic mode) we
2328          * must abort
2329          */
2330         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2331                 BNX2X_ERR("MCP refused load request, aborting\n");
2332                 return -EBUSY;
2333         }
2334         return 0;
2335 }
2336
2337 /* check whether another PF has already loaded FW to chip. In
2338  * virtualized environments a pf from another VM may have already
2339  * initialized the device including loading FW
2340  */
2341 int bnx2x_compare_fw_ver(struct bnx2x *bp, uint32_t load_code,
2342                          bool print_err)
2343 {
2344         /* is another pf loaded on this engine? */
2345         if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
2346             load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
2347                 /* build my FW version dword */
2348                 uint32_t my_fw = (BCM_5710_FW_MAJOR_VERSION) +
2349                         (BCM_5710_FW_MINOR_VERSION << 8) +
2350                         (BCM_5710_FW_REVISION_VERSION << 16) +
2351                         (BCM_5710_FW_ENGINEERING_VERSION << 24);
2352
2353                 /* read loaded FW from chip */
2354                 uint32_t loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
2355
2356                 DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n",
2357                    loaded_fw, my_fw);
2358
2359                 /* abort nic load if version mismatch */
2360                 if (my_fw != loaded_fw) {
2361                         if (print_err)
2362                                 BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. Aborting\n",
2363                                           loaded_fw, my_fw);
2364                         else
2365                                 BNX2X_DEV_INFO("bnx2x with FW %x was already loaded which mismatches my %x FW, possibly due to MF UNDI\n",
2366                                                loaded_fw, my_fw);
2367                         return -EBUSY;
2368                 }
2369         }
2370         return 0;
2371 }
2372
2373 /* returns the "mcp load_code" according to global load_count array */
2374 static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
2375 {
2376         int path = BP_PATH(bp);
2377
2378         DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d]      %d, %d, %d\n",
2379            path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2380            bnx2x_load_count[path][2]);
2381         bnx2x_load_count[path][0]++;
2382         bnx2x_load_count[path][1 + port]++;
2383         DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d]  %d, %d, %d\n",
2384            path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2385            bnx2x_load_count[path][2]);
2386         if (bnx2x_load_count[path][0] == 1)
2387                 return FW_MSG_CODE_DRV_LOAD_COMMON;
2388         else if (bnx2x_load_count[path][1 + port] == 1)
2389                 return FW_MSG_CODE_DRV_LOAD_PORT;
2390         else
2391                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
2392 }
2393
2394 /* mark PMF if applicable */
2395 static void bnx2x_nic_load_pmf(struct bnx2x *bp, uint32_t load_code)
2396 {
2397         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2398             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2399             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2400                 bp->port.pmf = 1;
2401                 /* We need the barrier to ensure the ordering between the
2402                  * writing to bp->port.pmf here and reading it from the
2403                  * bnx2x_periodic_task().
2404                  */
2405                 mb();
2406         } else {
2407                 bp->port.pmf = 0;
2408         }
2409
2410         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2411 }
2412
2413 static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code)
2414 {
2415         if (((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2416              (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP)) &&
2417             (bp->common.shmem2_base)) {
2418                 if (SHMEM2_HAS(bp, dcc_support))
2419                         SHMEM2_WR(bp, dcc_support,
2420                                   (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
2421                                    SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
2422                 if (SHMEM2_HAS(bp, afex_driver_support))
2423                         SHMEM2_WR(bp, afex_driver_support,
2424                                   SHMEM_AFEX_SUPPORTED_VERSION_ONE);
2425         }
2426
2427         /* Set AFEX default VLAN tag to an invalid value */
2428         bp->afex_def_vlan_tag = -1;
2429 }
2430
2431 /**
2432  * bnx2x_bz_fp - zero content of the fastpath structure.
2433  *
2434  * @bp:         driver handle
2435  * @index:      fastpath index to be zeroed
2436  *
2437  * Makes sure the contents of the bp->fp[index].napi is kept
2438  * intact.
2439  */
2440 static void bnx2x_bz_fp(struct bnx2x *bp, int index)
2441 {
2442         struct bnx2x_fastpath *fp = &bp->fp[index];
2443         int cos;
2444         struct napi_struct orig_napi = fp->napi;
2445         struct bnx2x_agg_info *orig_tpa_info = fp->tpa_info;
2446
2447         /* bzero bnx2x_fastpath contents */
2448         if (fp->tpa_info)
2449                 memset(fp->tpa_info, 0, ETH_MAX_AGGREGATION_QUEUES_E1H_E2 *
2450                        sizeof(struct bnx2x_agg_info));
2451         memset(fp, 0, sizeof(*fp));
2452
2453         /* Restore the NAPI object as it has been already initialized */
2454         fp->napi = orig_napi;
2455         fp->tpa_info = orig_tpa_info;
2456         fp->bp = bp;
2457         fp->index = index;
2458         if (IS_ETH_FP(fp))
2459                 fp->max_cos = bp->max_cos;
2460         else
2461                 /* Special queues support only one CoS */
2462                 fp->max_cos = 1;
2463
2464         /* Init txdata pointers */
2465         if (IS_FCOE_FP(fp))
2466                 fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)];
2467         if (IS_ETH_FP(fp))
2468                 for_each_cos_in_tx_queue(fp, cos)
2469                         fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos *
2470                                 BNX2X_NUM_ETH_QUEUES(bp) + index];
2471
2472         /* set the tpa flag for each queue. The tpa flag determines the queue
2473          * minimal size so it must be set prior to queue memory allocation
2474          */
2475         fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG ||
2476                                   (bp->flags & GRO_ENABLE_FLAG &&
2477                                    bnx2x_mtu_allows_gro(bp->dev->mtu)));
2478         if (bp->flags & TPA_ENABLE_FLAG)
2479                 fp->mode = TPA_MODE_LRO;
2480         else if (bp->flags & GRO_ENABLE_FLAG)
2481                 fp->mode = TPA_MODE_GRO;
2482
2483         /* We don't want TPA on an FCoE L2 ring */
2484         if (IS_FCOE_FP(fp))
2485                 fp->disable_tpa = 1;
2486 }
2487
2488 int bnx2x_load_cnic(struct bnx2x *bp)
2489 {
2490         int i, rc, port = BP_PORT(bp);
2491
2492         DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n");
2493
2494         mutex_init(&bp->cnic_mutex);
2495
2496         if (IS_PF(bp)) {
2497                 rc = bnx2x_alloc_mem_cnic(bp);
2498                 if (rc) {
2499                         BNX2X_ERR("Unable to allocate bp memory for cnic\n");
2500                         LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2501                 }
2502         }
2503
2504         rc = bnx2x_alloc_fp_mem_cnic(bp);
2505         if (rc) {
2506                 BNX2X_ERR("Unable to allocate memory for cnic fps\n");
2507                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2508         }
2509
2510         /* Update the number of queues with the cnic queues */
2511         rc = bnx2x_set_real_num_queues(bp, 1);
2512         if (rc) {
2513                 BNX2X_ERR("Unable to set real_num_queues including cnic\n");
2514                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2515         }
2516
2517         /* Add all CNIC NAPI objects */
2518         bnx2x_add_all_napi_cnic(bp);
2519         DP(NETIF_MSG_IFUP, "cnic napi added\n");
2520         bnx2x_napi_enable_cnic(bp);
2521
2522         rc = bnx2x_init_hw_func_cnic(bp);
2523         if (rc)
2524                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1);
2525
2526         bnx2x_nic_init_cnic(bp);
2527
2528         if (IS_PF(bp)) {
2529                 /* Enable Timer scan */
2530                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1);
2531
2532                 /* setup cnic queues */
2533                 for_each_cnic_queue(bp, i) {
2534                         rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2535                         if (rc) {
2536                                 BNX2X_ERR("Queue setup failed\n");
2537                                 LOAD_ERROR_EXIT(bp, load_error_cnic2);
2538                         }
2539                 }
2540         }
2541
2542         /* Initialize Rx filter. */
2543         bnx2x_set_rx_mode_inner(bp);
2544
2545         /* re-read iscsi info */
2546         bnx2x_get_iscsi_info(bp);
2547         bnx2x_setup_cnic_irq_info(bp);
2548         bnx2x_setup_cnic_info(bp);
2549         bp->cnic_loaded = true;
2550         if (bp->state == BNX2X_STATE_OPEN)
2551                 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
2552
2553         DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n");
2554
2555         return 0;
2556
2557 #ifndef BNX2X_STOP_ON_ERROR
2558 load_error_cnic2:
2559         /* Disable Timer scan */
2560         REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
2561
2562 load_error_cnic1:
2563         bnx2x_napi_disable_cnic(bp);
2564         /* Update the number of queues without the cnic queues */
2565         if (bnx2x_set_real_num_queues(bp, 0))
2566                 BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
2567 load_error_cnic0:
2568         BNX2X_ERR("CNIC-related load failed\n");
2569         bnx2x_free_fp_mem_cnic(bp);
2570         bnx2x_free_mem_cnic(bp);
2571         return rc;
2572 #endif /* ! BNX2X_STOP_ON_ERROR */
2573 }
2574
2575 /* must be called with rtnl_lock */
2576 int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
2577 {
2578         int port = BP_PORT(bp);
2579         int i, rc = 0, load_code = 0;
2580
2581         DP(NETIF_MSG_IFUP, "Starting NIC load\n");
2582         DP(NETIF_MSG_IFUP,
2583            "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled");
2584
2585 #ifdef BNX2X_STOP_ON_ERROR
2586         if (unlikely(bp->panic)) {
2587                 BNX2X_ERR("Can't load NIC when there is panic\n");
2588                 return -EPERM;
2589         }
2590 #endif
2591
2592         bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
2593
2594         /* zero the structure w/o any lock, before SP handler is initialized */
2595         memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link));
2596         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
2597                 &bp->last_reported_link.link_report_flags);
2598
2599         if (IS_PF(bp))
2600                 /* must be called before memory allocation and HW init */
2601                 bnx2x_ilt_set_info(bp);
2602
2603         /*
2604          * Zero fastpath structures preserving invariants like napi, which are
2605          * allocated only once, fp index, max_cos, bp pointer.
2606          * Also set fp->disable_tpa and txdata_ptr.
2607          */
2608         DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
2609         for_each_queue(bp, i)
2610                 bnx2x_bz_fp(bp, i);
2611         memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS +
2612                                   bp->num_cnic_queues) *
2613                                   sizeof(struct bnx2x_fp_txdata));
2614
2615         bp->fcoe_init = false;
2616
2617         /* Set the receive queues buffer size */
2618         bnx2x_set_rx_buf_size(bp);
2619
2620         if (IS_PF(bp)) {
2621                 rc = bnx2x_alloc_mem(bp);
2622                 if (rc) {
2623                         BNX2X_ERR("Unable to allocate bp memory\n");
2624                         return rc;
2625                 }
2626         }
2627
2628         /* need to be done after alloc mem, since it's self adjusting to amount
2629          * of memory available for RSS queues
2630          */
2631         rc = bnx2x_alloc_fp_mem(bp);
2632         if (rc) {
2633                 BNX2X_ERR("Unable to allocate memory for fps\n");
2634                 LOAD_ERROR_EXIT(bp, load_error0);
2635         }
2636
2637         /* Allocated memory for FW statistics  */
2638         if (bnx2x_alloc_fw_stats_mem(bp))
2639                 LOAD_ERROR_EXIT(bp, load_error0);
2640
2641         /* request pf to initialize status blocks */
2642         if (IS_VF(bp)) {
2643                 rc = bnx2x_vfpf_init(bp);
2644                 if (rc)
2645                         LOAD_ERROR_EXIT(bp, load_error0);
2646         }
2647
2648         /* As long as bnx2x_alloc_mem() may possibly update
2649          * bp->num_queues, bnx2x_set_real_num_queues() should always
2650          * come after it. At this stage cnic queues are not counted.
2651          */
2652         rc = bnx2x_set_real_num_queues(bp, 0);
2653         if (rc) {
2654                 BNX2X_ERR("Unable to set real_num_queues\n");
2655                 LOAD_ERROR_EXIT(bp, load_error0);
2656         }
2657
2658         /* configure multi cos mappings in kernel.
2659          * this configuration may be overridden by a multi class queue
2660          * discipline or by a dcbx negotiation result.
2661          */
2662         bnx2x_setup_tc(bp->dev, bp->max_cos);
2663
2664         /* Add all NAPI objects */
2665         bnx2x_add_all_napi(bp);
2666         DP(NETIF_MSG_IFUP, "napi added\n");
2667         bnx2x_napi_enable(bp);
2668
2669         if (IS_PF(bp)) {
2670                 /* set pf load just before approaching the MCP */
2671                 bnx2x_set_pf_load(bp);
2672
2673                 /* if mcp exists send load request and analyze response */
2674                 if (!BP_NOMCP(bp)) {
2675                         /* attempt to load pf */
2676                         rc = bnx2x_nic_load_request(bp, &load_code);
2677                         if (rc)
2678                                 LOAD_ERROR_EXIT(bp, load_error1);
2679
2680                         /* what did mcp say? */
2681                         rc = bnx2x_compare_fw_ver(bp, load_code, true);
2682                         if (rc) {
2683                                 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2684                                 LOAD_ERROR_EXIT(bp, load_error2);
2685                         }
2686                 } else {
2687                         load_code = bnx2x_nic_load_no_mcp(bp, port);
2688                 }
2689
2690                 /* mark pmf if applicable */
2691                 bnx2x_nic_load_pmf(bp, load_code);
2692
2693                 /* Init Function state controlling object */
2694                 bnx2x__init_func_obj(bp);
2695
2696                 /* Initialize HW */
2697                 rc = bnx2x_init_hw(bp, load_code);
2698                 if (rc) {
2699                         BNX2X_ERR("HW init failed, aborting\n");
2700                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2701                         LOAD_ERROR_EXIT(bp, load_error2);
2702                 }
2703         }
2704
2705         bnx2x_pre_irq_nic_init(bp);
2706
2707         /* Connect to IRQs */
2708         rc = bnx2x_setup_irqs(bp);
2709         if (rc) {
2710                 BNX2X_ERR("setup irqs failed\n");
2711                 if (IS_PF(bp))
2712                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2713                 LOAD_ERROR_EXIT(bp, load_error2);
2714         }
2715
2716         /* Init per-function objects */
2717         if (IS_PF(bp)) {
2718                 /* Setup NIC internals and enable interrupts */
2719                 bnx2x_post_irq_nic_init(bp, load_code);
2720
2721                 bnx2x_init_bp_objs(bp);
2722                 bnx2x_iov_nic_init(bp);
2723
2724                 /* Set AFEX default VLAN tag to an invalid value */
2725                 bp->afex_def_vlan_tag = -1;
2726                 bnx2x_nic_load_afex_dcc(bp, load_code);
2727                 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
2728                 rc = bnx2x_func_start(bp);
2729                 if (rc) {
2730                         BNX2X_ERR("Function start failed!\n");
2731                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2732
2733                         LOAD_ERROR_EXIT(bp, load_error3);
2734                 }
2735
2736                 /* Send LOAD_DONE command to MCP */
2737                 if (!BP_NOMCP(bp)) {
2738                         load_code = bnx2x_fw_command(bp,
2739                                                      DRV_MSG_CODE_LOAD_DONE, 0);
2740                         if (!load_code) {
2741                                 BNX2X_ERR("MCP response failure, aborting\n");
2742                                 rc = -EBUSY;
2743                                 LOAD_ERROR_EXIT(bp, load_error3);
2744                         }
2745                 }
2746
2747                 /* initialize FW coalescing state machines in RAM */
2748                 bnx2x_update_coalesce(bp);
2749         }
2750
2751         /* setup the leading queue */
2752         rc = bnx2x_setup_leading(bp);
2753         if (rc) {
2754                 BNX2X_ERR("Setup leading failed!\n");
2755                 LOAD_ERROR_EXIT(bp, load_error3);
2756         }
2757
2758         /* set up the rest of the queues */
2759         for_each_nondefault_eth_queue(bp, i) {
2760                 if (IS_PF(bp))
2761                         rc = bnx2x_setup_queue(bp, &bp->fp[i], false);
2762                 else /* VF */
2763                         rc = bnx2x_vfpf_setup_q(bp, &bp->fp[i], false);
2764                 if (rc) {
2765                         BNX2X_ERR("Queue %d setup failed\n", i);
2766                         LOAD_ERROR_EXIT(bp, load_error3);
2767                 }
2768         }
2769
2770         /* setup rss */
2771         rc = bnx2x_init_rss(bp);
2772         if (rc) {
2773                 BNX2X_ERR("PF RSS init failed\n");
2774                 LOAD_ERROR_EXIT(bp, load_error3);
2775         }
2776
2777         /* Now when Clients are configured we are ready to work */
2778         bp->state = BNX2X_STATE_OPEN;
2779
2780         /* Configure a ucast MAC */
2781         if (IS_PF(bp))
2782                 rc = bnx2x_set_eth_mac(bp, true);
2783         else /* vf */
2784                 rc = bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, bp->fp->index,
2785                                            true);
2786         if (rc) {
2787                 BNX2X_ERR("Setting Ethernet MAC failed\n");
2788                 LOAD_ERROR_EXIT(bp, load_error3);
2789         }
2790
2791         if (IS_PF(bp) && bp->pending_max) {
2792                 bnx2x_update_max_mf_config(bp, bp->pending_max);
2793                 bp->pending_max = 0;
2794         }
2795
2796         if (bp->port.pmf) {
2797                 rc = bnx2x_initial_phy_init(bp, load_mode);
2798                 if (rc)
2799                         LOAD_ERROR_EXIT(bp, load_error3);
2800         }
2801         bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN;
2802
2803         /* Start fast path */
2804
2805         /* Initialize Rx filter. */
2806         bnx2x_set_rx_mode_inner(bp);
2807
2808         if (bp->flags & PTP_SUPPORTED) {
2809                 bnx2x_init_ptp(bp);
2810                 bnx2x_configure_ptp_filters(bp);
2811         }
2812         /* Start Tx */
2813         switch (load_mode) {
2814         case LOAD_NORMAL:
2815                 /* Tx queue should be only re-enabled */
2816                 netif_tx_wake_all_queues(bp->dev);
2817                 break;
2818
2819         case LOAD_OPEN:
2820                 netif_tx_start_all_queues(bp->dev);
2821                 cmb();
2822                 break;
2823
2824         case LOAD_DIAG:
2825         case LOAD_LOOPBACK_EXT:
2826                 bp->state = BNX2X_STATE_DIAG;
2827                 break;
2828
2829         default:
2830                 break;
2831         }
2832
2833         if (bp->port.pmf)
2834                 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0);
2835         else
2836                 bnx2x__link_status_update(bp);
2837
2838         /* start the timer */
2839         mod_timer(&bp->timer, jiffies + bp->current_interval);
2840
2841         if (CNIC_ENABLED(bp))
2842                 bnx2x_load_cnic(bp);
2843
2844         if (IS_PF(bp))
2845                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
2846
2847         if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2848                 /* mark driver is loaded in shmem2 */
2849                 uint32_t val;
2850                 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2851                 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2852                           val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
2853                           DRV_FLAGS_CAPABILITIES_LOADED_L2);
2854         }
2855
2856         /* Wait for all pending SP commands to complete */
2857         if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) {
2858                 BNX2X_ERR("Timeout waiting for SP elements to complete\n");
2859                 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
2860                 return -EBUSY;
2861         }
2862
2863         /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
2864         if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
2865                 bnx2x_dcbx_init(bp, false);
2866
2867         DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
2868
2869         return 0;
2870
2871 #ifndef BNX2X_STOP_ON_ERROR
2872 load_error3:
2873         if (IS_PF(bp)) {
2874                 bnx2x_int_disable_sync(bp, 1);
2875
2876                 /* Clean queueable objects */
2877                 bnx2x_squeeze_objects(bp);
2878         }
2879
2880         /* Free SKBs, SGEs, TPA pool and driver internals */
2881         bnx2x_free_skbs(bp);
2882         for_each_rx_queue(bp, i)
2883                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2884
2885         /* Release IRQs */
2886         bnx2x_free_irq(bp);
2887 load_error2:
2888         if (IS_PF(bp) && !BP_NOMCP(bp)) {
2889                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
2890                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
2891         }
2892
2893         bp->port.pmf = 0;
2894 load_error1:
2895         bnx2x_napi_disable(bp);
2896         bnx2x_del_all_napi(bp);
2897
2898         /* clear pf_load status, as it was already set */
2899         if (IS_PF(bp))
2900                 bnx2x_clear_pf_load(bp);
2901 load_error0:
2902         bnx2x_free_fw_stats_mem(bp);
2903         bnx2x_free_fp_mem(bp);
2904         bnx2x_free_mem(bp);
2905
2906         return rc;
2907 #endif /* ! BNX2X_STOP_ON_ERROR */
2908 }
2909
2910 int bnx2x_drain_tx_queues(struct bnx2x *bp)
2911 {
2912         uint8_t rc = 0, cos, i;
2913
2914         /* Wait until tx fastpath tasks complete */
2915         for_each_tx_queue(bp, i) {
2916                 struct bnx2x_fastpath *fp = &bp->fp[i];
2917
2918                 for_each_cos_in_tx_queue(fp, cos)
2919                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
2920                 if (rc)
2921                         return rc;
2922         }
2923         return 0;
2924 }
2925
2926 /* must be called with rtnl_lock */
2927 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
2928 {
2929         int i;
2930         bool global = false;
2931
2932         DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
2933
2934         /* mark driver is unloaded in shmem2 */
2935         if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2936                 uint32_t val;
2937                 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2938                 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2939                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2940         }
2941
2942         if (IS_PF(bp) && bp->recovery_state != BNX2X_RECOVERY_DONE &&
2943             (bp->state == BNX2X_STATE_CLOSED ||
2944              bp->state == BNX2X_STATE_ERROR)) {
2945                 /* We can get here if the driver has been unloaded
2946                  * during parity error recovery and is either waiting for a
2947                  * leader to complete or for other functions to unload and
2948                  * then ifdown has been issued. In this case we want to
2949                  * unload and let other functions to complete a recovery
2950                  * process.
2951                  */
2952                 bp->recovery_state = BNX2X_RECOVERY_DONE;
2953                 bp->is_leader = 0;
2954                 bnx2x_release_leader_lock(bp);
2955                 mb();
2956
2957                 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n");
2958                 BNX2X_ERR("Can't unload in closed or error state\n");
2959                 return -EINVAL;
2960         }
2961
2962         /* Nothing to do during unload if previous bnx2x_nic_load()
2963          * have not completed successfully - all resources are released.
2964          *
2965          * we can get here only after unsuccessful ndo_* callback, during which
2966          * dev->IFF_UP flag is still on.
2967          */
2968         if (bp->state == BNX2X_STATE_CLOSED || bp->state == BNX2X_STATE_ERROR)
2969                 return 0;
2970
2971         /* It's important to set the bp->state to the value different from
2972          * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int()
2973          * may restart the Tx from the NAPI context (see bnx2x_tx_int()).
2974          */
2975         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
2976         mb();
2977
2978         /* indicate to VFs that the PF is going down */
2979         bnx2x_iov_channel_down(bp);
2980
2981         if (CNIC_LOADED(bp))
2982                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
2983
2984         /* Stop Tx */
2985         bnx2x_tx_disable(bp);
2986         netdev_reset_tc(bp->dev);
2987
2988         bp->rx_mode = BNX2X_RX_MODE_NONE;
2989
2990         del_timer_sync(&bp->timer);
2991
2992         if (IS_PF(bp)) {
2993                 /* Set ALWAYS_ALIVE bit in shmem */
2994                 bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2995                 bnx2x_drv_pulse(bp);
2996                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2997                 bnx2x_save_statistics(bp);
2998         }
2999
3000         /* wait till consumers catch up with producers in all queues */
3001         bnx2x_drain_tx_queues(bp);
3002
3003         /* if VF indicate to PF this function is going down (PF will delete sp
3004          * elements and clear initializations
3005          */
3006         if (IS_VF(bp))
3007                 bnx2x_vfpf_close_vf(bp);
3008         else if (unload_mode != UNLOAD_RECOVERY)
3009                 /* if this is a normal/close unload need to clean up chip*/
3010                 bnx2x_chip_cleanup(bp, unload_mode, keep_link);
3011         else {
3012                 /* Send the UNLOAD_REQUEST to the MCP */
3013                 bnx2x_send_unload_req(bp, unload_mode);
3014
3015                 /* Prevent transactions to host from the functions on the
3016                  * engine that doesn't reset global blocks in case of global
3017                  * attention once global blocks are reset and gates are opened
3018                  * (the engine which leader will perform the recovery
3019                  * last).
3020                  */
3021                 if (!CHIP_IS_E1x(bp))
3022                         bnx2x_pf_disable(bp);
3023
3024                 /* Disable HW interrupts, NAPI */
3025                 bnx2x_netif_stop(bp, 1);
3026                 /* Delete all NAPI objects */
3027                 bnx2x_del_all_napi(bp);
3028                 if (CNIC_LOADED(bp))
3029                         bnx2x_del_all_napi_cnic(bp);
3030                 /* Release IRQs */
3031                 bnx2x_free_irq(bp);
3032
3033                 /* Report UNLOAD_DONE to MCP */
3034                 bnx2x_send_unload_done(bp, false);
3035         }
3036
3037         /*
3038          * At this stage no more interrupts will arrive so we may safely clean
3039          * the queueable objects here in case they failed to get cleaned so far.
3040          */
3041         if (IS_PF(bp))
3042                 bnx2x_squeeze_objects(bp);
3043
3044         /* There should be no more pending SP commands at this stage */
3045         bp->sp_state = 0;
3046
3047         bp->port.pmf = 0;
3048
3049         /* clear pending work in rtnl task */
3050         bp->sp_rtnl_state = 0;
3051         mb();
3052
3053         /* Free SKBs, SGEs, TPA pool and driver internals */
3054         bnx2x_free_skbs(bp);
3055         if (CNIC_LOADED(bp))
3056                 bnx2x_free_skbs_cnic(bp);
3057         for_each_rx_queue(bp, i)
3058                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
3059
3060         bnx2x_free_fp_mem(bp);
3061         if (CNIC_LOADED(bp))
3062                 bnx2x_free_fp_mem_cnic(bp);
3063
3064         if (IS_PF(bp)) {
3065                 if (CNIC_LOADED(bp))
3066                         bnx2x_free_mem_cnic(bp);
3067         }
3068         bnx2x_free_mem(bp);
3069
3070         bp->state = BNX2X_STATE_CLOSED;
3071         bp->cnic_loaded = false;
3072
3073         /* Clear driver version indication in shmem */
3074         if (IS_PF(bp))
3075                 bnx2x_update_mng_version(bp);
3076
3077         /* Check if there are pending parity attentions. If there are - set
3078          * RECOVERY_IN_PROGRESS.
3079          */
3080         if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) {
3081                 bnx2x_set_reset_in_progress(bp);
3082
3083                 /* Set RESET_IS_GLOBAL if needed */
3084                 if (global)
3085                         bnx2x_set_reset_global(bp);
3086         }
3087
3088         /* The last driver must disable a "close the gate" if there is no
3089          * parity attention or "process kill" pending.
3090          */
3091         if (IS_PF(bp) &&
3092             !bnx2x_clear_pf_load(bp) &&
3093             bnx2x_reset_is_done(bp, BP_PATH(bp)))
3094                 bnx2x_disable_close_the_gate(bp);
3095
3096         DP(NETIF_MSG_IFUP, "Ending NIC unload\n");
3097
3098         return 0;
3099 }
3100
3101 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
3102 {
3103         uint16_t pmcsr;
3104
3105         /* If there is no power capability, silently succeed */
3106         if (!bp->pdev->pm_cap) {
3107                 BNX2X_DEV_INFO("No power capability. Breaking.\n");
3108                 return 0;
3109         }
3110
3111         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL, &pmcsr);
3112
3113         switch (state) {
3114         case PCI_D0:
3115                 pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
3116                                       ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3117                                        PCI_PM_CTRL_PME_STATUS));
3118
3119                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3120                         /* delay required during transition out of D3hot */
3121                         kthread_usleep(1000 * 20);
3122                 break;
3123
3124         case PCI_D3hot:
3125                 /* If there are other clients above don't
3126                    shut down the power */
3127                 if (atomic_read(&bp->pdev->enable_cnt) != 1)
3128                         return 0;
3129                 /* Don't shut down the power for emulation and FPGA */
3130                 if (CHIP_REV_IS_SLOW(bp))
3131                         return 0;
3132
3133                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3134                 pmcsr |= 3;
3135
3136                 if (bp->wol)
3137                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3138
3139                 pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
3140                                       pmcsr);
3141
3142                 /* No more memory access after this point until
3143                 * device is brought back to D0.
3144                 */
3145                 break;
3146
3147         default:
3148                 dev_err(&bp->pdev->dev, "Can't support state = %d\n", state);
3149                 return -EINVAL;
3150         }
3151         return 0;
3152 }
3153
3154 /*
3155  * net_device service functions
3156  */
3157 static int bnx2x_poll(struct napi_struct *napi, int budget)
3158 {
3159         int work_done = 0;
3160         uint8_t cos;
3161         struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
3162                                                  napi);
3163         struct bnx2x *bp = fp->bp;
3164
3165         while (1) {
3166 #ifdef BNX2X_STOP_ON_ERROR
3167                 if (unlikely(bp->panic)) {
3168                         napi_complete(napi);
3169                         return 0;
3170                 }
3171 #endif
3172                 if (!bnx2x_fp_lock_napi(fp))
3173                         return budget;
3174
3175                 for_each_cos_in_tx_queue(fp, cos)
3176                         if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
3177                                 bnx2x_tx_int(bp,