BNX2X: 9ns device infrastructure
[akaros.git] / kern / drivers / net / bnx2x / bnx2x_cmn.c
1 /* bnx2x_cmn.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath and fastpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include "akaros_compat.h"
19
20 #include "bnx2x_cmn.h"
21 #include "bnx2x_init.h"
22 #include "bnx2x_sp.h"
23
24 static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp);
25 static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp);
26 static int bnx2x_alloc_fp_mem(struct bnx2x *bp);
27 static int bnx2x_poll(struct napi_struct *napi, int budget);
28
29 static void bnx2x_add_all_napi_cnic(struct bnx2x *bp)
30 {
31 panic("Not implemented");
32 #if 0 // AKAROS_PORT
33         int i;
34
35         /* Add NAPI objects */
36         for_each_rx_queue_cnic(bp, i) {
37                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
38                                bnx2x_poll, NAPI_POLL_WEIGHT);
39                 napi_hash_add(&bnx2x_fp(bp, i, napi));
40         }
41 #endif
42 }
43
44 static void bnx2x_add_all_napi(struct bnx2x *bp)
45 {
46 panic("Not implemented");
47 #if 0 // AKAROS_PORT
48         int i;
49
50         /* Add NAPI objects */
51         for_each_eth_queue(bp, i) {
52                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
53                                bnx2x_poll, NAPI_POLL_WEIGHT);
54                 napi_hash_add(&bnx2x_fp(bp, i, napi));
55         }
56 #endif
57 }
58
59 static int bnx2x_calc_num_queues(struct bnx2x *bp)
60 {
61 panic("Not implemented");
62 #if 0 // AKAROS_PORT
63         int nq = bnx2x_num_queues ? : netif_get_num_default_rss_queues();
64
65         /* Reduce memory usage in kdump environment by using only one queue */
66         if (is_kdump_kernel())
67                 nq = 1;
68
69         nq = CLAMP(nq, 1, BNX2X_MAX_QUEUES(bp));
70         return nq;
71 #endif
72 }
73
74 /**
75  * bnx2x_move_fp - move content of the fastpath structure.
76  *
77  * @bp:         driver handle
78  * @from:       source FP index
79  * @to:         destination FP index
80  *
81  * Makes sure the contents of the bp->fp[to].napi is kept
82  * intact. This is done by first copying the napi struct from
83  * the target to the source, and then mem copying the entire
84  * source onto the target. Update txdata pointers and related
85  * content.
86  */
87 static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
88 {
89         struct bnx2x_fastpath *from_fp = &bp->fp[from];
90         struct bnx2x_fastpath *to_fp = &bp->fp[to];
91         struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from];
92         struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to];
93         struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from];
94         struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to];
95         int old_max_eth_txqs, new_max_eth_txqs;
96         int old_txdata_index = 0, new_txdata_index = 0;
97         struct bnx2x_agg_info *old_tpa_info = to_fp->tpa_info;
98
99         /* Copy the NAPI object as it has been already initialized */
100         from_fp->napi = to_fp->napi;
101
102         /* Move bnx2x_fastpath contents */
103         memcpy(to_fp, from_fp, sizeof(*to_fp));
104         to_fp->index = to;
105
106         /* Retain the tpa_info of the original `to' version as we don't want
107          * 2 FPs to contain the same tpa_info pointer.
108          */
109         to_fp->tpa_info = old_tpa_info;
110
111         /* move sp_objs contents as well, as their indices match fp ones */
112         memcpy(to_sp_objs, from_sp_objs, sizeof(*to_sp_objs));
113
114         /* move fp_stats contents as well, as their indices match fp ones */
115         memcpy(to_fp_stats, from_fp_stats, sizeof(*to_fp_stats));
116
117         /* Update txdata pointers in fp and move txdata content accordingly:
118          * Each fp consumes 'max_cos' txdata structures, so the index should be
119          * decremented by max_cos x delta.
120          */
121
122         old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos;
123         new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) *
124                                 (bp)->max_cos;
125         if (from == FCOE_IDX(bp)) {
126                 old_txdata_index = old_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
127                 new_txdata_index = new_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
128         }
129
130         memcpy(&bp->bnx2x_txq[new_txdata_index],
131                &bp->bnx2x_txq[old_txdata_index],
132                sizeof(struct bnx2x_fp_txdata));
133         to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index];
134 }
135
136 /**
137  * bnx2x_fill_fw_str - Fill buffer with FW version string.
138  *
139  * @bp:        driver handle
140  * @buf:       character buffer to fill with the fw name
141  * @buf_len:   length of the above buffer
142  *
143  */
144 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
145 {
146         if (IS_PF(bp)) {
147                 uint8_t phy_fw_ver[PHY_FW_VER_LEN];
148
149                 phy_fw_ver[0] = '\0';
150                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
151                                              phy_fw_ver, PHY_FW_VER_LEN);
152                 strlcpy(buf, bp->fw_ver, buf_len);
153                 snprintf(buf + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
154                          "bc %d.%d.%d%s%s",
155                          (bp->common.bc_ver & 0xff0000) >> 16,
156                          (bp->common.bc_ver & 0xff00) >> 8,
157                          (bp->common.bc_ver & 0xff),
158                          ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
159         } else {
160                 bnx2x_vf_fill_fw_str(bp, buf, buf_len);
161         }
162 }
163
164 /**
165  * bnx2x_shrink_eth_fp - guarantees fastpath structures stay intact
166  *
167  * @bp: driver handle
168  * @delta:      number of eth queues which were not allocated
169  */
170 static void bnx2x_shrink_eth_fp(struct bnx2x *bp, int delta)
171 {
172         int i, cos, old_eth_num = BNX2X_NUM_ETH_QUEUES(bp);
173
174         /* Queue pointer cannot be re-set on an fp-basis, as moving pointer
175          * backward along the array could cause memory to be overridden
176          */
177         for (cos = 1; cos < bp->max_cos; cos++) {
178                 for (i = 0; i < old_eth_num - delta; i++) {
179                         struct bnx2x_fastpath *fp = &bp->fp[i];
180                         int new_idx = cos * (old_eth_num - delta) + i;
181
182                         memcpy(&bp->bnx2x_txq[new_idx], fp->txdata_ptr[cos],
183                                sizeof(struct bnx2x_fp_txdata));
184                         fp->txdata_ptr[cos] = &bp->bnx2x_txq[new_idx];
185                 }
186         }
187 }
188
189 int bnx2x_load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
190
191 /* free skb in the packet ring at pos idx
192  * return idx of last bd freed
193  */
194 static uint16_t bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
195                              uint16_t idx, unsigned int *pkts_compl,
196                              unsigned int *bytes_compl)
197 {
198 panic("Not implemented");
199 #if 0 // AKAROS_PORT
200         struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx];
201         struct eth_tx_start_bd *tx_start_bd;
202         struct eth_tx_bd *tx_data_bd;
203         struct sk_buff *skb = tx_buf->skb;
204         uint16_t bd_idx = TX_BD(tx_buf->first_bd), new_cons;
205         int nbd;
206         uint16_t split_bd_len = 0;
207
208         /* prefetch skb end pointer to speedup dev_kfree_skb() */
209         prefetch(&skb->end);
210
211         DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d  buff @(%p)->skb %p\n",
212            txdata->txq_index, idx, tx_buf, skb);
213
214         tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd;
215
216         nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
217 #ifdef BNX2X_STOP_ON_ERROR
218         if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
219                 BNX2X_ERR("BAD nbd!\n");
220                 bnx2x_panic();
221         }
222 #endif
223         new_cons = nbd + tx_buf->first_bd;
224
225         /* Get the next bd */
226         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
227
228         /* Skip a parse bd... */
229         --nbd;
230         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
231
232         if (tx_buf->flags & BNX2X_HAS_SECOND_PBD) {
233                 /* Skip second parse bd... */
234                 --nbd;
235                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
236         }
237
238         /* TSO headers+data bds share a common mapping. See bnx2x_tx_split() */
239         if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
240                 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
241                 split_bd_len = BD_UNMAP_LEN(tx_data_bd);
242                 --nbd;
243                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
244         }
245
246         /* unmap first bd */
247         dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
248                          BD_UNMAP_LEN(tx_start_bd) + split_bd_len,
249                          DMA_TO_DEVICE);
250
251         /* now free frags */
252         while (nbd > 0) {
253
254                 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
255                 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
256                                BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
257                 if (--nbd)
258                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
259         }
260
261         /* release skb */
262         WARN_ON(!skb);
263         if (likely(skb)) {
264                 (*pkts_compl)++;
265                 (*bytes_compl) += skb->len;
266         }
267
268         dev_kfree_skb_any(skb);
269         tx_buf->first_bd = 0;
270         tx_buf->skb = NULL;
271
272         return new_cons;
273 #endif
274 }
275
276 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
277 {
278 panic("Not implemented");
279 #if 0 // AKAROS_PORT
280         struct netdev_queue *txq;
281         uint16_t hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
282         unsigned int pkts_compl = 0, bytes_compl = 0;
283
284 #ifdef BNX2X_STOP_ON_ERROR
285         if (unlikely(bp->panic))
286                 return -1;
287 #endif
288
289         txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
290         hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
291         sw_cons = txdata->tx_pkt_cons;
292
293         while (sw_cons != hw_cons) {
294                 uint16_t pkt_cons;
295
296                 pkt_cons = TX_BD(sw_cons);
297
298                 DP(NETIF_MSG_TX_DONE,
299                    "queue[%d]: hw_cons %u  sw_cons %u  pkt_cons %u\n",
300                    txdata->txq_index, hw_cons, sw_cons, pkt_cons);
301
302                 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
303                                             &pkts_compl, &bytes_compl);
304
305                 sw_cons++;
306         }
307
308         netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
309
310         txdata->tx_pkt_cons = sw_cons;
311         txdata->tx_bd_cons = bd_cons;
312
313         /* Need to make the tx_bd_cons update visible to start_xmit()
314          * before checking for netif_tx_queue_stopped().  Without the
315          * memory barrier, there is a small possibility that
316          * start_xmit() will miss it and cause the queue to be stopped
317          * forever.
318          * On the other hand we need an rmb() here to ensure the proper
319          * ordering of bit testing in the following
320          * netif_tx_queue_stopped(txq) call.
321          */
322         mb();
323
324         if (unlikely(netif_tx_queue_stopped(txq))) {
325                 /* Taking tx_lock() is needed to prevent re-enabling the queue
326                  * while it's empty. This could have happen if rx_action() gets
327                  * suspended in bnx2x_tx_int() after the condition before
328                  * netif_tx_wake_queue(), while tx_action (bnx2x_start_xmit()):
329                  *
330                  * stops the queue->sees fresh tx_bd_cons->releases the queue->
331                  * sends some packets consuming the whole queue again->
332                  * stops the queue
333                  */
334
335                 __netif_tx_lock(txq, core_id());
336
337                 if ((netif_tx_queue_stopped(txq)) &&
338                     (bp->state == BNX2X_STATE_OPEN) &&
339                     (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT))
340                         netif_tx_wake_queue(txq);
341
342                 __netif_tx_unlock(txq);
343         }
344         return 0;
345 #endif
346 }
347
348 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
349                                              uint16_t idx)
350 {
351         uint16_t last_max = fp->last_max_sge;
352
353         if (SUB_S16(idx, last_max) > 0)
354                 fp->last_max_sge = idx;
355 }
356
357 static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
358                                          uint16_t sge_len,
359                                          struct eth_end_agg_rx_cqe *cqe)
360 {
361         struct bnx2x *bp = fp->bp;
362         uint16_t last_max, last_elem, first_elem;
363         uint16_t delta = 0;
364         uint16_t i;
365
366         if (!sge_len)
367                 return;
368
369         /* First mark all used pages */
370         for (i = 0; i < sge_len; i++)
371                 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
372                         RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[i])));
373
374         DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
375            sge_len - 1, le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
376
377         /* Here we assume that the last SGE index is the biggest */
378         prefetch((void *)(fp->sge_mask));
379         bnx2x_update_last_max_sge(fp,
380                 le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
381
382         last_max = RX_SGE(fp->last_max_sge);
383         last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
384         first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
385
386         /* If ring is not full */
387         if (last_elem + 1 != first_elem)
388                 last_elem++;
389
390         /* Now update the prod */
391         for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
392                 if (likely(fp->sge_mask[i]))
393                         break;
394
395                 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
396                 delta += BIT_VEC64_ELEM_SZ;
397         }
398
399         if (delta > 0) {
400                 fp->rx_sge_prod += delta;
401                 /* clear page-end entries */
402                 bnx2x_clear_sge_mask_next_elems(fp);
403         }
404
405         DP(NETIF_MSG_RX_STATUS,
406            "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
407            fp->last_max_sge, fp->rx_sge_prod);
408 }
409
410 /* Get Toeplitz hash value in the skb using the value from the
411  * CQE (calculated by HW).
412  */
413 static uint32_t bnx2x_get_rxhash(const struct bnx2x *bp,
414                             const struct eth_fast_path_rx_cqe *cqe,
415                             enum pkt_hash_types *rxhash_type)
416 {
417 panic("Not implemented");
418 #if 0 // AKAROS_PORT
419         /* Get Toeplitz hash from CQE */
420         if ((bp->dev->feat & NETIF_F_RXHASH) &&
421             (cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) {
422                 enum eth_rss_hash_type htype;
423
424                 htype = cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE;
425                 *rxhash_type = ((htype == TCP_IPV4_HASH_TYPE) ||
426                                 (htype == TCP_IPV6_HASH_TYPE)) ?
427                                PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
428
429                 return le32_to_cpu(cqe->rss_hash_result);
430         }
431         *rxhash_type = PKT_HASH_TYPE_NONE;
432         return 0;
433 #endif
434 }
435
436 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, uint16_t queue,
437                             uint16_t cons, uint16_t prod,
438                             struct eth_fast_path_rx_cqe *cqe)
439 {
440 panic("Not implemented");
441 #if 0 // AKAROS_PORT
442         struct bnx2x *bp = fp->bp;
443         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
444         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
445         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
446         dma_addr_t mapping;
447         struct bnx2x_agg_info *tpa_info = &fp->tpa_info[queue];
448         struct sw_rx_bd *first_buf = &tpa_info->first_buf;
449
450         /* print error if current state != stop */
451         if (tpa_info->tpa_state != BNX2X_TPA_STOP)
452                 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
453
454         /* Try to map an empty data buffer from the aggregation info  */
455         mapping = dma_map_single(&bp->pdev->dev,
456                                  first_buf->data + NET_SKB_PAD,
457                                  fp->rx_buf_size, DMA_FROM_DEVICE);
458         /*
459          *  ...if it fails - move the skb from the consumer to the producer
460          *  and set the current aggregation state as ERROR to drop it
461          *  when TPA_STOP arrives.
462          */
463
464         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
465                 /* Move the BD from the consumer to the producer */
466                 bnx2x_reuse_rx_data(fp, cons, prod);
467                 tpa_info->tpa_state = BNX2X_TPA_ERROR;
468                 return;
469         }
470
471         /* move empty data from pool to prod */
472         prod_rx_buf->data = first_buf->data;
473         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
474         /* point prod_bd to new data */
475         prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
476         prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
477
478         /* move partial skb from cons to pool (don't unmap yet) */
479         *first_buf = *cons_rx_buf;
480
481         /* mark bin state as START */
482         tpa_info->parsing_flags =
483                 le16_to_cpu(cqe->pars_flags.flags);
484         tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
485         tpa_info->tpa_state = BNX2X_TPA_START;
486         tpa_info->len_on_bd = le16_to_cpu(cqe->len_on_bd);
487         tpa_info->placement_offset = cqe->placement_offset;
488         tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->rxhash_type);
489         if (fp->mode == TPA_MODE_GRO) {
490                 uint16_t gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
491                 tpa_info->full_page = SGE_PAGES / gro_size * gro_size;
492                 tpa_info->gro_size = gro_size;
493         }
494
495 #ifdef BNX2X_STOP_ON_ERROR
496         fp->tpa_queue_used |= (1 << queue);
497         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
498            fp->tpa_queue_used);
499 #endif
500 #endif
501 }
502
503 /* Timestamp option length allowed for TPA aggregation:
504  *
505  *              nop nop kind length echo val
506  */
507 #define TPA_TSTAMP_OPT_LEN      12
508 /**
509  * bnx2x_set_gro_params - compute GRO values
510  *
511  * @skb:                packet skb
512  * @parsing_flags:      parsing flags from the START CQE
513  * @len_on_bd:          total length of the first packet for the
514  *                      aggregation.
515  * @pkt_len:            length of all segments
516  *
517  * Approximate value of the MSS for this aggregation calculated using
518  * the first packet of it.
519  * Compute number of aggregated segments, and gso_type.
520  */
521 static void bnx2x_set_gro_params(struct sk_buff *skb, uint16_t parsing_flags,
522                                  uint16_t len_on_bd, unsigned int pkt_len,
523                                  uint16_t num_of_coalesced_segs)
524 {
525 panic("Not implemented");
526 #if 0 // AKAROS_PORT
527         /* TPA aggregation won't have either IP options or TCP options
528          * other than timestamp or IPv6 extension headers.
529          */
530         uint16_t hdrs_len = ETHERHDRSIZE + sizeof(struct tcphdr);
531
532         if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
533             PRS_FLAG_OVERETH_IPV6) {
534                 hdrs_len += sizeof(struct ipv6hdr);
535                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
536         } else {
537                 hdrs_len += sizeof(struct iphdr);
538                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
539         }
540
541         /* Check if there was a TCP timestamp, if there is it's will
542          * always be 12 bytes length: nop nop kind length echo val.
543          *
544          * Otherwise FW would close the aggregation.
545          */
546         if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG)
547                 hdrs_len += TPA_TSTAMP_OPT_LEN;
548
549         skb_shinfo(skb)->gso_size = len_on_bd - hdrs_len;
550
551         /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
552          * to skb_shinfo(skb)->gso_segs
553          */
554         NAPI_GRO_CB(skb)->count = num_of_coalesced_segs;
555 #endif
556 }
557
558 static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp,
559                               uint16_t index, gfp_t gfp_mask)
560 {
561         struct page *page = get_cont_pages(PAGES_PER_SGE_SHIFT, gfp_mask);
562         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
563         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
564         dma_addr_t mapping;
565
566         if (unlikely(page == NULL)) {
567                 BNX2X_ERR("Can't alloc sge\n");
568                 return -ENOMEM;
569         }
570
571         mapping = dma_map_page(&bp->pdev->dev, page, 0,
572                                SGE_PAGES, DMA_FROM_DEVICE);
573         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
574                 free_cont_pages(page, PAGES_PER_SGE_SHIFT);
575                 BNX2X_ERR("Can't map sge\n");
576                 return -ENOMEM;
577         }
578
579         sw_buf->page = page;
580         dma_unmap_addr_set(sw_buf, mapping, mapping);
581
582         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
583         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
584
585         return 0;
586 }
587
588 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
589                                struct bnx2x_agg_info *tpa_info,
590                                uint16_t pages,
591                                struct sk_buff *skb,
592                                struct eth_end_agg_rx_cqe *cqe,
593                                uint16_t cqe_idx)
594 {
595 panic("Not implemented");
596 #if 0 // AKAROS_PORT
597         struct sw_rx_page *rx_pg, old_rx_pg;
598         uint32_t i, frag_len, frag_size;
599         int err, j, frag_id = 0;
600         uint16_t len_on_bd = tpa_info->len_on_bd;
601         uint16_t full_page = 0, gro_size = 0;
602
603         frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd;
604
605         if (fp->mode == TPA_MODE_GRO) {
606                 gro_size = tpa_info->gro_size;
607                 full_page = tpa_info->full_page;
608         }
609
610         /* This is needed in order to enable forwarding support */
611         if (frag_size)
612                 bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd,
613                                      le16_to_cpu(cqe->pkt_len),
614                                      le16_to_cpu(cqe->num_of_coalesced_segs));
615
616 #ifdef BNX2X_STOP_ON_ERROR
617         if (pages > MIN_T(uint32_t, 8, MAX_SKB_FRAGS) * SGE_PAGES) {
618                 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
619                           pages, cqe_idx);
620                 BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len);
621                 bnx2x_panic();
622                 return -EINVAL;
623         }
624 #endif
625
626         /* Run through the SGL and compose the fragmented skb */
627         for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
628                 uint16_t sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
629
630                 /* FW gives the indices of the SGE as if the ring is an array
631                    (meaning that "next" element will consume 2 indices) */
632                 if (fp->mode == TPA_MODE_GRO)
633                         frag_len = MIN_T(uint32_t, frag_size,
634                                          (uint32_t)full_page);
635                 else /* LRO */
636                         frag_len = MIN_T(uint32_t, frag_size,
637                                          (uint32_t)SGE_PAGES);
638
639                 rx_pg = &fp->rx_page_ring[sge_idx];
640                 old_rx_pg = *rx_pg;
641
642                 /* If we fail to allocate a substitute page, we simply stop
643                    where we are and drop the whole packet */
644                 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx, 0);
645                 if (unlikely(err)) {
646                         bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
647                         return err;
648                 }
649
650                 /* Unmap the page as we're going to pass it to the stack */
651                 dma_unmap_page(&bp->pdev->dev,
652                                dma_unmap_addr(&old_rx_pg, mapping),
653                                SGE_PAGES, DMA_FROM_DEVICE);
654                 /* Add one frag and update the appropriate fields in the skb */
655                 if (fp->mode == TPA_MODE_LRO)
656                         skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
657                 else { /* GRO */
658                         int rem;
659                         int offset = 0;
660                         for (rem = frag_len; rem > 0; rem -= gro_size) {
661                                 int len = rem > gro_size ? gro_size : rem;
662                                 skb_fill_page_desc(skb, frag_id++,
663                                                    old_rx_pg.page, offset, len);
664                                 if (offset)
665                                         page_incref(old_rx_pg.page);
666                                 offset += len;
667                         }
668                 }
669
670                 skb->data_len += frag_len;
671                 skb->truesize += SGE_PAGES;
672                 skb->len += frag_len;
673
674                 frag_size -= frag_len;
675         }
676
677         return 0;
678 #endif
679 }
680
681 static void bnx2x_frag_free(const struct bnx2x_fastpath *fp, void *data)
682 {
683         if (fp->rx_frag_size)
684                 page_decref(kva2page(data));
685         else
686                 kfree(data);
687 }
688
689 static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp, gfp_t gfp_mask)
690 {
691 panic("Not implemented");
692 #if 0 // AKAROS_PORT
693         if (fp->rx_frag_size) {
694                 /* GFP_KERNEL allocations are used only during initialization */
695                 if (unlikely(gfp_mask & KMALLOC_WAIT))
696                         return (void *)kpage_alloc_addr();
697
698                 return netdev_alloc_frag(fp->rx_frag_size);
699         }
700
701         return kmalloc(fp->rx_buf_size + NET_SKB_PAD, gfp_mask);
702 #endif
703 }
704
705 #ifdef CONFIG_INET
706 static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb)
707 {
708         const struct iphdr *iph = ip_hdr(skb);
709         struct tcphdr *th;
710
711         skb_set_transport_header(skb, sizeof(struct iphdr));
712         th = tcp_hdr(skb);
713
714         th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
715                                   iph->saddr, iph->daddr, 0);
716 }
717
718 static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb)
719 {
720         struct ipv6hdr *iph = ipv6_hdr(skb);
721         struct tcphdr *th;
722
723         skb_set_transport_header(skb, sizeof(struct ipv6hdr));
724         th = tcp_hdr(skb);
725
726         th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
727                                   &iph->saddr, &iph->daddr, 0);
728 }
729
730 static void bnx2x_gro_csum(struct bnx2x *bp, struct sk_buff *skb,
731                             void (*gro_func)(struct bnx2x*, struct sk_buff*))
732 {
733         skb_set_network_header(skb, 0);
734         gro_func(bp, skb);
735         tcp_gro_complete(skb);
736 }
737 #endif
738
739 static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
740                                struct sk_buff *skb)
741 {
742 panic("Not implemented");
743 #if 0 // AKAROS_PORT
744 #ifdef CONFIG_INET
745         if (skb_shinfo(skb)->gso_size) {
746                 switch (be16_to_cpu(skb->protocol)) {
747                 case ETH_P_IP:
748                         bnx2x_gro_csum(bp, skb, bnx2x_gro_ip_csum);
749                         break;
750                 case ETH_P_IPV6:
751                         bnx2x_gro_csum(bp, skb, bnx2x_gro_ipv6_csum);
752                         break;
753                 default:
754                         BNX2X_ERR("Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
755                                   be16_to_cpu(skb->protocol));
756                 }
757         }
758 #endif
759         skb_record_rx_queue(skb, fp->rx_queue);
760         napi_gro_receive(&fp->napi, skb);
761 #endif
762 }
763
764 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
765                            struct bnx2x_agg_info *tpa_info,
766                            uint16_t pages,
767                            struct eth_end_agg_rx_cqe *cqe,
768                            uint16_t cqe_idx)
769 {
770 panic("Not implemented");
771 #if 0 // AKAROS_PORT
772         struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
773         uint8_t pad = tpa_info->placement_offset;
774         uint16_t len = tpa_info->len_on_bd;
775         struct sk_buff *skb = NULL;
776         uint8_t *new_data, *data = rx_buf->data;
777         uint8_t old_tpa_state = tpa_info->tpa_state;
778
779         tpa_info->tpa_state = BNX2X_TPA_STOP;
780
781         /* If we there was an error during the handling of the TPA_START -
782          * drop this aggregation.
783          */
784         if (old_tpa_state == BNX2X_TPA_ERROR)
785                 goto drop;
786
787         /* Try to allocate the new data */
788         new_data = bnx2x_frag_alloc(fp, 0);
789         /* Unmap skb in the pool anyway, as we are going to change
790            pool entry status to BNX2X_TPA_STOP even if new skb allocation
791            fails. */
792         dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
793                          fp->rx_buf_size, DMA_FROM_DEVICE);
794         if (likely(new_data))
795                 skb = build_skb(data, fp->rx_frag_size);
796
797         if (likely(skb)) {
798 #ifdef BNX2X_STOP_ON_ERROR
799                 if (pad + len > fp->rx_buf_size) {
800                         BNX2X_ERR("skb_put is about to fail...  pad %d  len %d  rx_buf_size %d\n",
801                                   pad, len, fp->rx_buf_size);
802                         bnx2x_panic();
803                         return;
804                 }
805 #endif
806
807                 skb_reserve(skb, pad + NET_SKB_PAD);
808                 skb_put(skb, len);
809                 skb_set_hash(skb, tpa_info->rxhash, tpa_info->rxhash_type);
810
811                 skb->protocol = eth_type_trans(skb, bp->dev);
812                 skb->ip_summed = CHECKSUM_UNNECESSARY;
813
814                 if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages,
815                                          skb, cqe, cqe_idx)) {
816                         if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN)
817                                 __vlan_hwaccel_put_tag(skb,
818                                                        cpu_to_be16(ETH_P_8021Q),
819                                                        tpa_info->vlan_tag);
820                         bnx2x_gro_receive(bp, fp, skb);
821                 } else {
822                         DP(NETIF_MSG_RX_STATUS,
823                            "Failed to allocate new pages - dropping packet!\n");
824                         dev_kfree_skb_any(skb);
825                 }
826
827                 /* put new data in bin */
828                 rx_buf->data = new_data;
829
830                 return;
831         }
832         if (new_data)
833                 bnx2x_frag_free(fp, new_data);
834 drop:
835         /* drop the packet and keep the buffer in the bin */
836         DP(NETIF_MSG_RX_STATUS,
837            "Failed to allocate or map a new skb - dropping packet!\n");
838         bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++;
839 #endif
840 }
841
842 static int bnx2x_alloc_rx_data(struct bnx2x *bp, struct bnx2x_fastpath *fp,
843                                uint16_t index, gfp_t gfp_mask)
844 {
845 panic("Not implemented");
846 #if 0 // AKAROS_PORT
847         uint8_t *data;
848         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
849         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
850         dma_addr_t mapping;
851
852         data = bnx2x_frag_alloc(fp, gfp_mask);
853         if (unlikely(data == NULL))
854                 return -ENOMEM;
855
856         mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
857                                  fp->rx_buf_size,
858                                  DMA_FROM_DEVICE);
859         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
860                 bnx2x_frag_free(fp, data);
861                 BNX2X_ERR("Can't map rx data\n");
862                 return -ENOMEM;
863         }
864
865         rx_buf->data = data;
866         dma_unmap_addr_set(rx_buf, mapping, mapping);
867
868         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
869         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
870
871         return 0;
872 #endif
873 }
874
875 static
876 void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe,
877                                  struct bnx2x_fastpath *fp,
878                                  struct bnx2x_eth_q_stats *qstats)
879 {
880 panic("Not implemented");
881 #if 0 // AKAROS_PORT
882         /* Do nothing if no L4 csum validation was done.
883          * We do not check whether IP csum was validated. For IPv4 we assume
884          * that if the card got as far as validating the L4 csum, it also
885          * validated the IP csum. IPv6 has no IP csum.
886          */
887         if (cqe->fast_path_cqe.status_flags &
888             ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)
889                 return;
890
891         /* If L4 validation was done, check if an error was found. */
892
893         if (cqe->fast_path_cqe.type_error_flags &
894             (ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG |
895              ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
896                 qstats->hw_csum_err++;
897         else
898                 skb->ip_summed = CHECKSUM_UNNECESSARY;
899 #endif
900 }
901
902 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
903 {
904 panic("Not implemented");
905 #if 0 // AKAROS_PORT
906         struct bnx2x *bp = fp->bp;
907         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
908         uint16_t sw_comp_cons, sw_comp_prod;
909         int rx_pkt = 0;
910         union eth_rx_cqe *cqe;
911         struct eth_fast_path_rx_cqe *cqe_fp;
912
913 #ifdef BNX2X_STOP_ON_ERROR
914         if (unlikely(bp->panic))
915                 return 0;
916 #endif
917         if (budget <= 0)
918                 return rx_pkt;
919
920         bd_cons = fp->rx_bd_cons;
921         bd_prod = fp->rx_bd_prod;
922         bd_prod_fw = bd_prod;
923         sw_comp_cons = fp->rx_comp_cons;
924         sw_comp_prod = fp->rx_comp_prod;
925
926         comp_ring_cons = RCQ_BD(sw_comp_cons);
927         cqe = &fp->rx_comp_ring[comp_ring_cons];
928         cqe_fp = &cqe->fast_path_cqe;
929
930         DP(NETIF_MSG_RX_STATUS,
931            "queue[%d]: sw_comp_cons %u\n", fp->index, sw_comp_cons);
932
933         while (BNX2X_IS_CQE_COMPLETED(cqe_fp)) {
934                 struct sw_rx_bd *rx_buf = NULL;
935                 struct sk_buff *skb;
936                 uint8_t cqe_fp_flags;
937                 enum eth_rx_cqe_type cqe_fp_type;
938                 uint16_t len, pad, queue;
939                 uint8_t *data;
940                 uint32_t rxhash;
941                 enum pkt_hash_types rxhash_type;
942
943 #ifdef BNX2X_STOP_ON_ERROR
944                 if (unlikely(bp->panic))
945                         return 0;
946 #endif
947
948                 bd_prod = RX_BD(bd_prod);
949                 bd_cons = RX_BD(bd_cons);
950
951                 /* A rmb() is required to ensure that the CQE is not read
952                  * before it is written by the adapter DMA.  PCI ordering
953                  * rules will make sure the other fields are written before
954                  * the marker at the end of struct eth_fast_path_rx_cqe
955                  * but without rmb() a weakly ordered processor can process
956                  * stale data.  Without the barrier TPA state-machine might
957                  * enter inconsistent state and kernel stack might be
958                  * provided with incorrect packet description - these lead
959                  * to various kernel crashed.
960                  */
961                 rmb();
962
963                 cqe_fp_flags = cqe_fp->type_error_flags;
964                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
965
966                 DP(NETIF_MSG_RX_STATUS,
967                    "CQE type %x  err %x  status %x  queue %x  vlan %x  len %u\n",
968                    CQE_TYPE(cqe_fp_flags),
969                    cqe_fp_flags, cqe_fp->status_flags,
970                    le32_to_cpu(cqe_fp->rss_hash_result),
971                    le16_to_cpu(cqe_fp->vlan_tag),
972                    le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len));
973
974                 /* is this a slowpath msg? */
975                 if (unlikely(CQE_TYPE_SLOW(cqe_fp_type))) {
976                         bnx2x_sp_event(fp, cqe);
977                         goto next_cqe;
978                 }
979
980                 rx_buf = &fp->rx_buf_ring[bd_cons];
981                 data = rx_buf->data;
982
983                 if (!CQE_TYPE_FAST(cqe_fp_type)) {
984                         struct bnx2x_agg_info *tpa_info;
985                         uint16_t frag_size, pages;
986 #ifdef BNX2X_STOP_ON_ERROR
987                         /* sanity check */
988                         if (fp->disable_tpa &&
989                             (CQE_TYPE_START(cqe_fp_type) ||
990                              CQE_TYPE_STOP(cqe_fp_type)))
991                                 BNX2X_ERR("START/STOP packet while disable_tpa type %x\n",
992                                           CQE_TYPE(cqe_fp_type));
993 #endif
994
995                         if (CQE_TYPE_START(cqe_fp_type)) {
996                                 uint16_t queue = cqe_fp->queue_index;
997                                 DP(NETIF_MSG_RX_STATUS,
998                                    "calling tpa_start on queue %d\n",
999                                    queue);
1000
1001                                 bnx2x_tpa_start(fp, queue,
1002                                                 bd_cons, bd_prod,
1003                                                 cqe_fp);
1004
1005                                 goto next_rx;
1006                         }
1007                         queue = cqe->end_agg_cqe.queue_index;
1008                         tpa_info = &fp->tpa_info[queue];
1009                         DP(NETIF_MSG_RX_STATUS,
1010                            "calling tpa_stop on queue %d\n",
1011                            queue);
1012
1013                         frag_size = le16_to_cpu(cqe->end_agg_cqe.pkt_len) -
1014                                     tpa_info->len_on_bd;
1015
1016                         if (fp->mode == TPA_MODE_GRO)
1017                                 pages = (frag_size + tpa_info->full_page - 1) /
1018                                          tpa_info->full_page;
1019                         else
1020                                 pages = SGE_PAGE_ALIGN(frag_size) >>
1021                                         SGE_PAGE_SHIFT;
1022
1023                         bnx2x_tpa_stop(bp, fp, tpa_info, pages,
1024                                        &cqe->end_agg_cqe, comp_ring_cons);
1025 #ifdef BNX2X_STOP_ON_ERROR
1026                         if (bp->panic)
1027                                 return 0;
1028 #endif
1029
1030                         bnx2x_update_sge_prod(fp, pages, &cqe->end_agg_cqe);
1031                         goto next_cqe;
1032                 }
1033                 /* non TPA */
1034                 len = le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len);
1035                 pad = cqe_fp->placement_offset;
1036                 dma_sync_single_for_cpu(&bp->pdev->dev,
1037                                         dma_unmap_addr(rx_buf, mapping),
1038                                         pad + RX_COPY_THRESH,
1039                                         DMA_FROM_DEVICE);
1040                 pad += NET_SKB_PAD;
1041                 prefetch(data + pad); /* speedup eth_type_trans() */
1042                 /* is this an error packet? */
1043                 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1044                         DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1045                            "ERROR  flags %x  rx packet %u\n",
1046                            cqe_fp_flags, sw_comp_cons);
1047                         bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++;
1048                         goto reuse_rx;
1049                 }
1050
1051                 /* Since we don't have a jumbo ring
1052                  * copy small packets if mtu > 1500
1053                  */
1054                 if ((bp->dev->maxmtu > ETH_MAX_PACKET_SIZE) &&
1055                     (len <= RX_COPY_THRESH)) {
1056                         skb = napi_alloc_skb(&fp->napi, len);
1057                         if (skb == NULL) {
1058                                 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1059                                    "ERROR  packet dropped because of alloc failure\n");
1060                                 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1061                                 goto reuse_rx;
1062                         }
1063                         memcpy(skb->data, data + pad, len);
1064                         bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1065                 } else {
1066                         if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod,
1067                                                        0) == 0)) {
1068                                 dma_unmap_single(&bp->pdev->dev,
1069                                                  dma_unmap_addr(rx_buf, mapping),
1070                                                  fp->rx_buf_size,
1071                                                  DMA_FROM_DEVICE);
1072                                 skb = build_skb(data, fp->rx_frag_size);
1073                                 if (unlikely(!skb)) {
1074                                         bnx2x_frag_free(fp, data);
1075                                         bnx2x_fp_qstats(bp, fp)->
1076                                                         rx_skb_alloc_failed++;
1077                                         goto next_rx;
1078                                 }
1079                                 skb_reserve(skb, pad);
1080                         } else {
1081                                 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1082                                    "ERROR  packet dropped because of alloc failure\n");
1083                                 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1084 reuse_rx:
1085                                 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1086                                 goto next_rx;
1087                         }
1088                 }
1089
1090                 skb_put(skb, len);
1091                 skb->protocol = eth_type_trans(skb, bp->dev);
1092
1093                 /* Set Toeplitz hash for a none-LRO skb */
1094                 rxhash = bnx2x_get_rxhash(bp, cqe_fp, &rxhash_type);
1095                 skb_set_hash(skb, rxhash, rxhash_type);
1096
1097                 skb_checksum_none_assert(skb);
1098
1099                 if (bp->dev->feat & NETIF_F_RXCSUM)
1100                         bnx2x_csum_validate(skb, cqe, fp,
1101                                             bnx2x_fp_qstats(bp, fp));
1102
1103                 skb_record_rx_queue(skb, fp->rx_queue);
1104
1105                 if (le16_to_cpu(cqe_fp->pars_flags.flags) &
1106                     PARSING_FLAGS_VLAN)
1107                         __vlan_hwaccel_put_tag(skb, cpu_to_be16(ETH_P_8021Q),
1108                                                le16_to_cpu(cqe_fp->vlan_tag));
1109
1110                 skb_mark_napi_id(skb, &fp->napi);
1111
1112                 if (bnx2x_fp_ll_polling(fp))
1113                         netif_receive_skb(skb);
1114                 else
1115                         napi_gro_receive(&fp->napi, skb);
1116 next_rx:
1117                 rx_buf->data = NULL;
1118
1119                 bd_cons = NEXT_RX_IDX(bd_cons);
1120                 bd_prod = NEXT_RX_IDX(bd_prod);
1121                 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1122                 rx_pkt++;
1123 next_cqe:
1124                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1125                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1126
1127                 /* mark CQE as free */
1128                 BNX2X_SEED_CQE(cqe_fp);
1129
1130                 if (rx_pkt == budget)
1131                         break;
1132
1133                 comp_ring_cons = RCQ_BD(sw_comp_cons);
1134                 cqe = &fp->rx_comp_ring[comp_ring_cons];
1135                 cqe_fp = &cqe->fast_path_cqe;
1136         } /* while */
1137
1138         fp->rx_bd_cons = bd_cons;
1139         fp->rx_bd_prod = bd_prod_fw;
1140         fp->rx_comp_cons = sw_comp_cons;
1141         fp->rx_comp_prod = sw_comp_prod;
1142
1143         /* Update producers */
1144         bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1145                              fp->rx_sge_prod);
1146
1147         fp->rx_pkt += rx_pkt;
1148         fp->rx_calls++;
1149
1150         return rx_pkt;
1151 #endif
1152 }
1153
1154 static void bnx2x_msix_fp_int(struct hw_trapframe *hw_tf, void *fp_cookie)
1155 {
1156 panic("Not implemented");
1157 #if 0 // AKAROS_PORT
1158         struct bnx2x_fastpath *fp = fp_cookie;
1159         struct bnx2x *bp = fp->bp;
1160         uint8_t cos;
1161
1162         DP(NETIF_MSG_INTR,
1163            "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
1164            fp->index, fp->fw_sb_id, fp->igu_sb_id);
1165
1166         bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1167
1168 #ifdef BNX2X_STOP_ON_ERROR
1169         if (unlikely(bp->panic))
1170                 return;
1171 #endif
1172
1173         /* Handle Rx and Tx according to MSI-X vector */
1174         for_each_cos_in_tx_queue(fp, cos)
1175                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1176
1177         prefetch(&fp->sb_running_index[SM_RX_ID]);
1178         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1179
1180         return;
1181 #endif
1182 }
1183
1184 /* HW Lock for shared dual port PHYs */
1185 void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1186 {
1187         qlock(&bp->port.phy_mutex);
1188
1189         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1190 }
1191
1192 void bnx2x_release_phy_lock(struct bnx2x *bp)
1193 {
1194         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1195
1196         qunlock(&bp->port.phy_mutex);
1197 }
1198
1199 /* calculates MF speed according to current linespeed and MF configuration */
1200 uint16_t bnx2x_get_mf_speed(struct bnx2x *bp)
1201 {
1202         uint16_t line_speed = bp->link_vars.line_speed;
1203         if (IS_MF(bp)) {
1204                 uint16_t maxCfg = bnx2x_extract_max_cfg(bp,
1205                                                    bp->mf_config[BP_VN(bp)]);
1206
1207                 /* Calculate the current MAX line speed limit for the MF
1208                  * devices
1209                  */
1210                 if (IS_MF_SI(bp))
1211                         line_speed = (line_speed * maxCfg) / 100;
1212                 else { /* SD mode */
1213                         uint16_t vn_max_rate = maxCfg * 100;
1214
1215                         if (vn_max_rate < line_speed)
1216                                 line_speed = vn_max_rate;
1217                 }
1218         }
1219
1220         return line_speed;
1221 }
1222
1223 /**
1224  * bnx2x_fill_report_data - fill link report data to report
1225  *
1226  * @bp:         driver handle
1227  * @data:       link state to update
1228  *
1229  * It uses a none-atomic bit operations because is called under the mutex.
1230  */
1231 static void bnx2x_fill_report_data(struct bnx2x *bp,
1232                                    struct bnx2x_link_report_data *data)
1233 {
1234 panic("Not implemented");
1235 #if 0 // AKAROS_PORT
1236         memset(data, 0, sizeof(*data));
1237
1238         if (IS_PF(bp)) {
1239                 /* Fill the report data: effective line speed */
1240                 data->line_speed = bnx2x_get_mf_speed(bp);
1241
1242                 /* Link is down */
1243                 if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS))
1244                         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1245                                   &data->link_report_flags);
1246
1247                 if (!BNX2X_NUM_ETH_QUEUES(bp))
1248                         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1249                                   &data->link_report_flags);
1250
1251                 /* Full DUPLEX */
1252                 if (bp->link_vars.duplex == DUPLEX_FULL)
1253                         __set_bit(BNX2X_LINK_REPORT_FD,
1254                                   &data->link_report_flags);
1255
1256                 /* Rx Flow Control is ON */
1257                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX)
1258                         __set_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1259                                   &data->link_report_flags);
1260
1261                 /* Tx Flow Control is ON */
1262                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1263                         __set_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1264                                   &data->link_report_flags);
1265         } else { /* VF */
1266                 *data = bp->vf_link_vars;
1267         }
1268 #endif
1269 }
1270
1271 /**
1272  * bnx2x_link_report - report link status to OS.
1273  *
1274  * @bp:         driver handle
1275  *
1276  * Calls the __bnx2x_link_report() under the same locking scheme
1277  * as a link/PHY state managing code to ensure a consistent link
1278  * reporting.
1279  */
1280
1281 void bnx2x_link_report(struct bnx2x *bp)
1282 {
1283         bnx2x_acquire_phy_lock(bp);
1284         __bnx2x_link_report(bp);
1285         bnx2x_release_phy_lock(bp);
1286 }
1287
1288 /**
1289  * __bnx2x_link_report - report link status to OS.
1290  *
1291  * @bp:         driver handle
1292  *
1293  * None atomic implementation.
1294  * Should be called under the phy_lock.
1295  */
1296 void __bnx2x_link_report(struct bnx2x *bp)
1297 {
1298 panic("Not implemented");
1299 #if 0 // AKAROS_PORT
1300         struct bnx2x_link_report_data cur_data;
1301
1302         /* reread mf_cfg */
1303         if (IS_PF(bp) && !CHIP_IS_E1(bp))
1304                 bnx2x_read_mf_cfg(bp);
1305
1306         /* Read the current link report info */
1307         bnx2x_fill_report_data(bp, &cur_data);
1308
1309         /* Don't report link down or exactly the same link status twice */
1310         if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) ||
1311             (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1312                       &bp->last_reported_link.link_report_flags) &&
1313              test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1314                       &cur_data.link_report_flags)))
1315                 return;
1316
1317         bp->link_cnt++;
1318
1319         /* We are going to report a new link parameters now -
1320          * remember the current data for the next time.
1321          */
1322         memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data));
1323
1324         /* propagate status to VFs */
1325         if (IS_PF(bp))
1326                 bnx2x_iov_link_update(bp);
1327
1328         if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1329                      &cur_data.link_report_flags)) {
1330                 netif_carrier_off(bp->dev);
1331                 netdev_err(bp->dev, "NIC Link is Down\n");
1332                 return;
1333         } else {
1334                 const char *duplex;
1335                 const char *flow;
1336
1337                 netif_carrier_on(bp->dev);
1338
1339                 if (test_and_clear_bit(BNX2X_LINK_REPORT_FD,
1340                                        &cur_data.link_report_flags))
1341                         duplex = "full";
1342                 else
1343                         duplex = "half";
1344
1345                 /* Handle the FC at the end so that only these flags would be
1346                  * possibly set. This way we may easily check if there is no FC
1347                  * enabled.
1348                  */
1349                 if (cur_data.link_report_flags) {
1350                         if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1351                                      &cur_data.link_report_flags)) {
1352                                 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1353                                      &cur_data.link_report_flags))
1354                                         flow = "ON - receive & transmit";
1355                                 else
1356                                         flow = "ON - receive";
1357                         } else {
1358                                 flow = "ON - transmit";
1359                         }
1360                 } else {
1361                         flow = "none";
1362                 }
1363                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
1364                             cur_data.line_speed, duplex, flow);
1365         }
1366 #endif
1367 }
1368
1369 static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
1370 {
1371         int i;
1372
1373         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1374                 struct eth_rx_sge *sge;
1375
1376                 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
1377                 sge->addr_hi =
1378                         cpu_to_le32(U64_HI(fp->rx_sge_mapping +
1379                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1380
1381                 sge->addr_lo =
1382                         cpu_to_le32(U64_LO(fp->rx_sge_mapping +
1383                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1384         }
1385 }
1386
1387 static void bnx2x_free_tpa_pool(struct bnx2x *bp,
1388                                 struct bnx2x_fastpath *fp, int last)
1389 {
1390         int i;
1391
1392         for (i = 0; i < last; i++) {
1393                 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
1394                 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
1395                 uint8_t *data = first_buf->data;
1396
1397                 if (data == NULL) {
1398                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
1399                         continue;
1400                 }
1401                 if (tpa_info->tpa_state == BNX2X_TPA_START)
1402                         dma_unmap_single(&bp->pdev->dev,
1403                                          dma_unmap_addr(first_buf, mapping),
1404                                          fp->rx_buf_size, DMA_FROM_DEVICE);
1405                 bnx2x_frag_free(fp, data);
1406                 first_buf->data = NULL;
1407         }
1408 }
1409
1410 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
1411 {
1412         int j;
1413
1414         for_each_rx_queue_cnic(bp, j) {
1415                 struct bnx2x_fastpath *fp = &bp->fp[j];
1416
1417                 fp->rx_bd_cons = 0;
1418
1419                 /* Activate BD ring */
1420                 /* Warning!
1421                  * this will generate an interrupt (to the TSTORM)
1422                  * must only be done after chip is initialized
1423                  */
1424                 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1425                                      fp->rx_sge_prod);
1426         }
1427 }
1428
1429 void bnx2x_init_rx_rings(struct bnx2x *bp)
1430 {
1431         int func = BP_FUNC(bp);
1432         uint16_t ring_prod;
1433         int i, j;
1434
1435         /* Allocate TPA resources */
1436         for_each_eth_queue(bp, j) {
1437                 struct bnx2x_fastpath *fp = &bp->fp[j];
1438
1439                 DP(NETIF_MSG_IFUP,
1440                    "mtu %d  rx_buf_size %d\n", bp->dev->maxmtu, fp->rx_buf_size);
1441
1442                 if (!fp->disable_tpa) {
1443                         /* Fill the per-aggregation pool */
1444                         for (i = 0; i < MAX_AGG_QS(bp); i++) {
1445                                 struct bnx2x_agg_info *tpa_info =
1446                                         &fp->tpa_info[i];
1447                                 struct sw_rx_bd *first_buf =
1448                                         &tpa_info->first_buf;
1449
1450                                 first_buf->data =
1451                                         bnx2x_frag_alloc(fp, KMALLOC_WAIT);
1452                                 if (!first_buf->data) {
1453                                         BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n",
1454                                                   j);
1455                                         bnx2x_free_tpa_pool(bp, fp, i);
1456                                         fp->disable_tpa = 1;
1457                                         break;
1458                                 }
1459                                 dma_unmap_addr_set(first_buf, mapping, 0);
1460                                 tpa_info->tpa_state = BNX2X_TPA_STOP;
1461                         }
1462
1463                         /* "next page" elements initialization */
1464                         bnx2x_set_next_page_sgl(fp);
1465
1466                         /* set SGEs bit mask */
1467                         bnx2x_init_sge_ring_bit_mask(fp);
1468
1469                         /* Allocate SGEs and initialize the ring elements */
1470                         for (i = 0, ring_prod = 0;
1471                              i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
1472
1473                                 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod,
1474                                                        KMALLOC_WAIT) < 0) {
1475                                         BNX2X_ERR("was only able to allocate %d rx sges\n",
1476                                                   i);
1477                                         BNX2X_ERR("disabling TPA for queue[%d]\n",
1478                                                   j);
1479                                         /* Cleanup already allocated elements */
1480                                         bnx2x_free_rx_sge_range(bp, fp,
1481                                                                 ring_prod);
1482                                         bnx2x_free_tpa_pool(bp, fp,
1483                                                             MAX_AGG_QS(bp));
1484                                         fp->disable_tpa = 1;
1485                                         ring_prod = 0;
1486                                         break;
1487                                 }
1488                                 ring_prod = NEXT_SGE_IDX(ring_prod);
1489                         }
1490
1491                         fp->rx_sge_prod = ring_prod;
1492                 }
1493         }
1494
1495         for_each_eth_queue(bp, j) {
1496                 struct bnx2x_fastpath *fp = &bp->fp[j];
1497
1498                 fp->rx_bd_cons = 0;
1499
1500                 /* Activate BD ring */
1501                 /* Warning!
1502                  * this will generate an interrupt (to the TSTORM)
1503                  * must only be done after chip is initialized
1504                  */
1505                 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1506                                      fp->rx_sge_prod);
1507
1508                 if (j != 0)
1509                         continue;
1510
1511                 if (CHIP_IS_E1(bp)) {
1512                         REG_WR(bp, BAR_USTRORM_INTMEM +
1513                                USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
1514                                U64_LO(fp->rx_comp_mapping));
1515                         REG_WR(bp, BAR_USTRORM_INTMEM +
1516                                USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
1517                                U64_HI(fp->rx_comp_mapping));
1518                 }
1519         }
1520 }
1521
1522 static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp)
1523 {
1524 panic("Not implemented");
1525 #if 0 // AKAROS_PORT
1526         uint8_t cos;
1527         struct bnx2x *bp = fp->bp;
1528
1529         for_each_cos_in_tx_queue(fp, cos) {
1530                 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1531                 unsigned pkts_compl = 0, bytes_compl = 0;
1532
1533                 uint16_t sw_prod = txdata->tx_pkt_prod;
1534                 uint16_t sw_cons = txdata->tx_pkt_cons;
1535
1536                 while (sw_cons != sw_prod) {
1537                         bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
1538                                           &pkts_compl, &bytes_compl);
1539                         sw_cons++;
1540                 }
1541
1542                 netdev_tx_reset_queue(
1543                         netdev_get_tx_queue(bp->dev,
1544                                             txdata->txq_index));
1545         }
1546 #endif
1547 }
1548
1549 static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp)
1550 {
1551         int i;
1552
1553         for_each_tx_queue_cnic(bp, i) {
1554                 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1555         }
1556 }
1557
1558 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
1559 {
1560         int i;
1561
1562         for_each_eth_queue(bp, i) {
1563                 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1564         }
1565 }
1566
1567 static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp)
1568 {
1569         struct bnx2x *bp = fp->bp;
1570         int i;
1571
1572         /* ring wasn't allocated */
1573         if (fp->rx_buf_ring == NULL)
1574                 return;
1575
1576         for (i = 0; i < NUM_RX_BD; i++) {
1577                 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
1578                 uint8_t *data = rx_buf->data;
1579
1580                 if (data == NULL)
1581                         continue;
1582                 dma_unmap_single(&bp->pdev->dev,
1583                                  dma_unmap_addr(rx_buf, mapping),
1584                                  fp->rx_buf_size, DMA_FROM_DEVICE);
1585
1586                 rx_buf->data = NULL;
1587                 bnx2x_frag_free(fp, data);
1588         }
1589 }
1590
1591 static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp)
1592 {
1593         int j;
1594
1595         for_each_rx_queue_cnic(bp, j) {
1596                 bnx2x_free_rx_bds(&bp->fp[j]);
1597         }
1598 }
1599
1600 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
1601 {
1602         int j;
1603
1604         for_each_eth_queue(bp, j) {
1605                 struct bnx2x_fastpath *fp = &bp->fp[j];
1606
1607                 bnx2x_free_rx_bds(fp);
1608
1609                 if (!fp->disable_tpa)
1610                         bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
1611         }
1612 }
1613
1614 static void bnx2x_free_skbs_cnic(struct bnx2x *bp)
1615 {
1616         bnx2x_free_tx_skbs_cnic(bp);
1617         bnx2x_free_rx_skbs_cnic(bp);
1618 }
1619
1620 void bnx2x_free_skbs(struct bnx2x *bp)
1621 {
1622         bnx2x_free_tx_skbs(bp);
1623         bnx2x_free_rx_skbs(bp);
1624 }
1625
1626 void bnx2x_update_max_mf_config(struct bnx2x *bp, uint32_t value)
1627 {
1628         /* load old values */
1629         uint32_t mf_cfg = bp->mf_config[BP_VN(bp)];
1630
1631         if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
1632                 /* leave all but MAX value */
1633                 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
1634
1635                 /* set new MAX value */
1636                 mf_cfg |= (value << FUNC_MF_CFG_MAX_BW_SHIFT)
1637                                 & FUNC_MF_CFG_MAX_BW_MASK;
1638
1639                 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
1640         }
1641 }
1642
1643 /**
1644  * bnx2x_free_msix_irqs - free previously requested MSI-X IRQ vectors
1645  *
1646  * @bp:         driver handle
1647  * @nvecs:      number of vectors to be released
1648  */
1649 static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
1650 {
1651 panic("Not implemented");
1652 #if 0 // AKAROS_PORT
1653         int i, offset = 0;
1654
1655         if (nvecs == offset)
1656                 return;
1657
1658         /* VFs don't have a default SB */
1659         if (IS_PF(bp)) {
1660                 free_irq(bp->msix_table[offset].vector, bp->dev);
1661                 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
1662                    bp->msix_table[offset].vector);
1663                 offset++;
1664         }
1665
1666         if (CNIC_SUPPORT(bp)) {
1667                 if (nvecs == offset)
1668                         return;
1669                 offset++;
1670         }
1671
1672         for_each_eth_queue(bp, i) {
1673                 if (nvecs == offset)
1674                         return;
1675                 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n",
1676                    i, bp->msix_table[offset].vector);
1677
1678                 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
1679         }
1680 #endif
1681 }
1682
1683 void bnx2x_free_irq(struct bnx2x *bp)
1684 {
1685 panic("Not implemented");
1686 #if 0 // AKAROS_PORT
1687         if (bp->flags & USING_MSIX_FLAG &&
1688             !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1689                 int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp);
1690
1691                 /* vfs don't have a default status block */
1692                 if (IS_PF(bp))
1693                         nvecs++;
1694
1695                 bnx2x_free_msix_irqs(bp, nvecs);
1696         } else {
1697                 free_irq(bp->dev->irq, bp->dev);
1698         }
1699 #endif
1700 }
1701
1702 int bnx2x_enable_msix(struct bnx2x *bp)
1703 {
1704         int msix_vec = 0, i, rc;
1705 panic("Not implemented");
1706 #if 0 // AKAROS_PORT
1707         /* VFs don't have a default status block */
1708         if (IS_PF(bp)) {
1709                 bp->msix_table[msix_vec].entry = msix_vec;
1710                 BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n",
1711                                bp->msix_table[0].entry);
1712                 msix_vec++;
1713         }
1714
1715         /* Cnic requires an msix vector for itself */
1716         if (CNIC_SUPPORT(bp)) {
1717                 bp->msix_table[msix_vec].entry = msix_vec;
1718                 BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n",
1719                                msix_vec, bp->msix_table[msix_vec].entry);
1720                 msix_vec++;
1721         }
1722
1723         /* We need separate vectors for ETH queues only (not FCoE) */
1724         for_each_eth_queue(bp, i) {
1725                 bp->msix_table[msix_vec].entry = msix_vec;
1726                 BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n",
1727                                msix_vec, msix_vec, i);
1728                 msix_vec++;
1729         }
1730
1731         DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n",
1732            msix_vec);
1733
1734         rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0],
1735                                    BNX2X_MIN_MSIX_VEC_CNT(bp), msix_vec);
1736         /*
1737          * reconfigure number of tx/rx queues according to available
1738          * MSI-X vectors
1739          */
1740         if (rc == -ENOSPC) {
1741                 /* Get by with single vector */
1742                 rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0], 1, 1);
1743                 if (rc < 0) {
1744                         BNX2X_DEV_INFO("Single MSI-X is not attainable rc %d\n",
1745                                        rc);
1746                         goto no_msix;
1747                 }
1748
1749                 BNX2X_DEV_INFO("Using single MSI-X vector\n");
1750                 bp->flags |= USING_SINGLE_MSIX_FLAG;
1751
1752                 BNX2X_DEV_INFO("set number of queues to 1\n");
1753                 bp->num_ethernet_queues = 1;
1754                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1755         } else if (rc < 0) {
1756                 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1757                 goto no_msix;
1758         } else if (rc < msix_vec) {
1759                 /* how less vectors we will have? */
1760                 int diff = msix_vec - rc;
1761
1762                 BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc);
1763
1764                 /*
1765                  * decrease number of queues by number of unallocated entries
1766                  */
1767                 bp->num_ethernet_queues -= diff;
1768                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1769
1770                 BNX2X_DEV_INFO("New queue configuration set: %d\n",
1771                                bp->num_queues);
1772         }
1773
1774         bp->flags |= USING_MSIX_FLAG;
1775
1776         return 0;
1777
1778 no_msix:
1779         /* fall to INTx if not enough memory */
1780         if (rc == -ENOMEM)
1781                 bp->flags |= DISABLE_MSI_FLAG;
1782
1783         return rc;
1784 #endif
1785 }
1786
1787 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1788 {
1789 panic("Not implemented");
1790 #if 0 // AKAROS_PORT
1791         int i, rc, offset = 0;
1792
1793         /* no default status block for vf */
1794         if (IS_PF(bp)) {
1795                 rc = register_irq(bp->msix_table[offset++].vector,
1796                                   bnx2x_msix_sp_int, bp->dev,
1797                                   pci_to_tbdf(bp->pdev));
1798                 if (rc) {
1799                         BNX2X_ERR("request sp irq failed\n");
1800                         return -EBUSY;
1801                 }
1802         }
1803
1804         if (CNIC_SUPPORT(bp))
1805                 offset++;
1806
1807         for_each_eth_queue(bp, i) {
1808                 struct bnx2x_fastpath *fp = &bp->fp[i];
1809                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1810                          bp->dev->name, i);
1811
1812                 rc = register_irq(bp->msix_table[offset].vector,
1813                                   bnx2x_msix_fp_int, fp, pci_to_tbdf(bp->pdev));
1814                 if (rc) {
1815                         BNX2X_ERR("request fp #%d irq (%d) failed  rc %d\n", i,
1816                               bp->msix_table[offset].vector, rc);
1817                         bnx2x_free_msix_irqs(bp, offset);
1818                         return -EBUSY;
1819                 }
1820
1821                 offset++;
1822         }
1823
1824         i = BNX2X_NUM_ETH_QUEUES(bp);
1825         if (IS_PF(bp)) {
1826                 offset = 1 + CNIC_SUPPORT(bp);
1827                 netdev_info(bp->dev,
1828                             "using MSI-X  IRQs: sp %d  fp[%d] %d ... fp[%d] %d\n",
1829                             bp->msix_table[0].vector,
1830                             0, bp->msix_table[offset].vector,
1831                             i - 1, bp->msix_table[offset + i - 1].vector);
1832         } else {
1833                 offset = CNIC_SUPPORT(bp);
1834                 netdev_info(bp->dev,
1835                             "using MSI-X  IRQs: fp[%d] %d ... fp[%d] %d\n",
1836                             0, bp->msix_table[offset].vector,
1837                             i - 1, bp->msix_table[offset + i - 1].vector);
1838         }
1839         return 0;
1840 #endif
1841 }
1842
1843 int bnx2x_enable_msi(struct bnx2x *bp)
1844 {
1845 panic("Not implemented");
1846 #if 0 // AKAROS_PORT
1847         int rc;
1848
1849         rc = pci_enable_msi(bp->pdev);
1850         if (rc) {
1851                 BNX2X_DEV_INFO("MSI is not attainable\n");
1852                 return -1;
1853         }
1854         bp->flags |= USING_MSI_FLAG;
1855
1856         return 0;
1857 #endif
1858 }
1859
1860 static int bnx2x_req_irq(struct bnx2x *bp)
1861 {
1862         unsigned long flags;
1863 panic("Not implemented");
1864 #if 0 // AKAROS_PORT
1865         unsigned int irq;
1866
1867         if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG))
1868                 flags = 0;
1869         else
1870                 flags = IRQF_SHARED;
1871
1872         if (bp->flags & USING_MSIX_FLAG)
1873                 irq = bp->msix_table[0].vector;
1874         else
1875                 irq = bp->pdev->irq;
1876
1877         return register_irq(irq, bnx2x_interrupt, bp->dev,
1878                             pci_to_tbdf(bp->pdev));
1879 #endif
1880 }
1881
1882 static int bnx2x_setup_irqs(struct bnx2x *bp)
1883 {
1884         int rc = 0;
1885 panic("Not implemented");
1886 #if 0 // AKAROS_PORT
1887         if (bp->flags & USING_MSIX_FLAG &&
1888             !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1889                 rc = bnx2x_req_msix_irqs(bp);
1890                 if (rc)
1891                         return rc;
1892         } else {
1893                 rc = bnx2x_req_irq(bp);
1894                 if (rc) {
1895                         BNX2X_ERR("IRQ request failed  rc %d, aborting\n", rc);
1896                         return rc;
1897                 }
1898                 if (bp->flags & USING_MSI_FLAG) {
1899                         bp->dev->irq = bp->pdev->irq;
1900                         netdev_info(bp->dev, "using MSI IRQ %d\n",
1901                                     bp->dev->irq);
1902                 }
1903                 if (bp->flags & USING_MSIX_FLAG) {
1904                         bp->dev->irq = bp->msix_table[0].vector;
1905                         netdev_info(bp->dev, "using MSIX IRQ %d\n",
1906                                     bp->dev->irq);
1907                 }
1908         }
1909
1910         return 0;
1911 #endif
1912 }
1913
1914 static void bnx2x_napi_enable_cnic(struct bnx2x *bp)
1915 {
1916 panic("Not implemented");
1917 #if 0 // AKAROS_PORT
1918         int i;
1919
1920         for_each_rx_queue_cnic(bp, i) {
1921                 bnx2x_fp_init_lock(&bp->fp[i]);
1922                 napi_enable(&bnx2x_fp(bp, i, napi));
1923         }
1924 #endif
1925 }
1926
1927 static void bnx2x_napi_enable(struct bnx2x *bp)
1928 {
1929 panic("Not implemented");
1930 #if 0 // AKAROS_PORT
1931         int i;
1932
1933         for_each_eth_queue(bp, i) {
1934                 bnx2x_fp_init_lock(&bp->fp[i]);
1935                 napi_enable(&bnx2x_fp(bp, i, napi));
1936         }
1937 #endif
1938 }
1939
1940 static void bnx2x_napi_disable_cnic(struct bnx2x *bp)
1941 {
1942 panic("Not implemented");
1943 #if 0 // AKAROS_PORT
1944         int i;
1945
1946         for_each_rx_queue_cnic(bp, i) {
1947                 napi_disable(&bnx2x_fp(bp, i, napi));
1948                 while (!bnx2x_fp_ll_disable(&bp->fp[i]))
1949                         kthread_usleep(1000);
1950         }
1951 #endif
1952 }
1953
1954 static void bnx2x_napi_disable(struct bnx2x *bp)
1955 {
1956 panic("Not implemented");
1957 #if 0 // AKAROS_PORT
1958         int i;
1959
1960         for_each_eth_queue(bp, i) {
1961                 napi_disable(&bnx2x_fp(bp, i, napi));
1962                 while (!bnx2x_fp_ll_disable(&bp->fp[i]))
1963                         kthread_usleep(1000);
1964         }
1965 #endif
1966 }
1967
1968 void bnx2x_netif_start(struct bnx2x *bp)
1969 {
1970 panic("Not implemented");
1971 #if 0 // AKAROS_PORT
1972         if (netif_running(bp->dev)) {
1973                 bnx2x_napi_enable(bp);
1974                 if (CNIC_LOADED(bp))
1975                         bnx2x_napi_enable_cnic(bp);
1976                 bnx2x_int_enable(bp);
1977                 if (bp->state == BNX2X_STATE_OPEN)
1978                         netif_tx_wake_all_queues(bp->dev);
1979         }
1980 #endif
1981 }
1982
1983 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
1984 {
1985         bnx2x_int_disable_sync(bp, disable_hw);
1986         bnx2x_napi_disable(bp);
1987         if (CNIC_LOADED(bp))
1988                 bnx2x_napi_disable_cnic(bp);
1989 }
1990
1991 uint16_t bnx2x_select_queue(struct ether *dev, struct sk_buff *skb,
1992                        void *accel_priv, select_queue_fallback_t fallback)
1993 {
1994 panic("Not implemented");
1995 #if 0 // AKAROS_PORT
1996         struct bnx2x *bp = netdev_priv(dev);
1997
1998         if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
1999                 struct ethhdr *hdr = (struct ethhdr *)skb->data;
2000                 uint16_t ether_type = be16_to_cpu(hdr->h_proto);
2001
2002                 /* Skip VLAN tag if present */
2003                 if (ether_type == ETH_P_8021Q) {
2004                         struct vlan_ethhdr *vhdr =
2005                                 (struct vlan_ethhdr *)skb->data;
2006
2007                         ether_type = be16_to_cpu(vhdr->h_vlan_encapsulated_proto);
2008                 }
2009
2010                 /* If ethertype is FCoE or FIP - use FCoE ring */
2011                 if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP))
2012                         return bnx2x_fcoe_tx(bp, txq_index);
2013         }
2014
2015         /* select a non-FCoE queue */
2016         return fallback(dev, skb) % BNX2X_NUM_ETH_QUEUES(bp);
2017 #endif
2018 }
2019
2020 void bnx2x_set_num_queues(struct bnx2x *bp)
2021 {
2022 panic("Not implemented");
2023 #if 0 // AKAROS_PORT
2024         /* RSS queues */
2025         bp->num_ethernet_queues = bnx2x_calc_num_queues(bp);
2026
2027         /* override in STORAGE SD modes */
2028         if (IS_MF_STORAGE_ONLY(bp))
2029                 bp->num_ethernet_queues = 1;
2030
2031         /* Add special queues */
2032         bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */
2033         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
2034
2035         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
2036 #endif
2037 }
2038
2039 /**
2040  * bnx2x_set_real_num_queues - configure netdev->real_num_[tx,rx]_queues
2041  *
2042  * @bp:         Driver handle
2043  *
2044  * We currently support for at most 16 Tx queues for each CoS thus we will
2045  * allocate a multiple of 16 for ETH L2 rings according to the value of the
2046  * bp->max_cos.
2047  *
2048  * If there is an FCoE L2 queue the appropriate Tx queue will have the next
2049  * index after all ETH L2 indices.
2050  *
2051  * If the actual number of Tx queues (for each CoS) is less than 16 then there
2052  * will be the holes at the end of each group of 16 ETh L2 indices (0..15,
2053  * 16..31,...) with indices that are not coupled with any real Tx queue.
2054  *
2055  * The proper configuration of skb->queue_mapping is handled by
2056  * bnx2x_select_queue() and __skb_tx_hash().
2057  *
2058  * bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash()
2059  * will return a proper Tx index if TC is enabled (netdev->num_tc > 0).
2060  */
2061 static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic)
2062 {
2063 panic("Not implemented");
2064 #if 0 // AKAROS_PORT
2065         int rc, tx, rx;
2066
2067         tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos;
2068         rx = BNX2X_NUM_ETH_QUEUES(bp);
2069
2070 /* account for fcoe queue */
2071         if (include_cnic && !NO_FCOE(bp)) {
2072                 rx++;
2073                 tx++;
2074         }
2075
2076         rc = netif_set_real_num_tx_queues(bp->dev, tx);
2077         if (rc) {
2078                 BNX2X_ERR("Failed to set real number of Tx queues: %d\n", rc);
2079                 return rc;
2080         }
2081         rc = netif_set_real_num_rx_queues(bp->dev, rx);
2082         if (rc) {
2083                 BNX2X_ERR("Failed to set real number of Rx queues: %d\n", rc);
2084                 return rc;
2085         }
2086
2087         DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n",
2088                           tx, rx);
2089
2090         return rc;
2091 #endif
2092 }
2093
2094 static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
2095 {
2096 panic("Not implemented");
2097 #if 0 // AKAROS_PORT
2098         int i;
2099
2100         for_each_queue(bp, i) {
2101                 struct bnx2x_fastpath *fp = &bp->fp[i];
2102                 uint32_t mtu;
2103
2104                 /* Always use a mini-jumbo MTU for the FCoE L2 ring */
2105                 if (IS_FCOE_IDX(i))
2106                         /*
2107                          * Although there are no IP frames expected to arrive to
2108                          * this ring we still want to add an
2109                          * IP_HEADER_ALIGNMENT_PADDING to prevent a buffer
2110                          * overrun attack.
2111                          */
2112                         mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2113                 else
2114                         mtu = bp->dev->maxmtu;
2115                 fp->rx_buf_size = BNX2X_FW_RX_ALIGN_START +
2116                                   IP_HEADER_ALIGNMENT_PADDING +
2117                                   ETH_OVREHEAD +
2118                                   mtu +
2119                                   BNX2X_FW_RX_ALIGN_END;
2120                 /* Note : rx_buf_size doesn't take into account NET_SKB_PAD */
2121                 if (fp->rx_buf_size + NET_SKB_PAD <= PAGE_SIZE)
2122                         fp->rx_frag_size = fp->rx_buf_size + NET_SKB_PAD;
2123                 else
2124                         fp->rx_frag_size = 0;
2125         }
2126 #endif
2127 }
2128
2129 static int bnx2x_init_rss(struct bnx2x *bp)
2130 {
2131 panic("Not implemented");
2132 #if 0 // AKAROS_PORT
2133         int i;
2134         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2135
2136         /* Prepare the initial contents for the indirection table if RSS is
2137          * enabled
2138          */
2139         for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++)
2140                 bp->rss_conf_obj.ind_table[i] =
2141                         bp->fp->cl_id +
2142                         ethtool_rxfh_indir_default(i, num_eth_queues);
2143
2144         /*
2145          * For 57710 and 57711 SEARCHER configuration (rss_keys) is
2146          * per-port, so if explicit configuration is needed , do it only
2147          * for a PMF.
2148          *
2149          * For 57712 and newer on the other hand it's a per-function
2150          * configuration.
2151          */
2152         return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp));
2153 #endif
2154 }
2155
2156 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
2157               bool config_hash, bool enable)
2158 {
2159 panic("Not implemented");
2160 #if 0 // AKAROS_PORT
2161         struct bnx2x_config_rss_params params = {NULL};
2162
2163         /* Although RSS is meaningless when there is a single HW queue we
2164          * still need it enabled in order to have HW Rx hash generated.
2165          *
2166          * if (!is_eth_multi(bp))
2167          *      bp->multi_mode = ETH_RSS_MODE_DISABLED;
2168          */
2169
2170         params.rss_obj = rss_obj;
2171
2172         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2173
2174         if (enable) {
2175                 __set_bit(BNX2X_RSS_MODE_REGULAR, &params.rss_flags);
2176
2177                 /* RSS configuration */
2178                 __set_bit(BNX2X_RSS_IPV4, &params.rss_flags);
2179                 __set_bit(BNX2X_RSS_IPV4_TCP, &params.rss_flags);
2180                 __set_bit(BNX2X_RSS_IPV6, &params.rss_flags);
2181                 __set_bit(BNX2X_RSS_IPV6_TCP, &params.rss_flags);
2182                 if (rss_obj->udp_rss_v4)
2183                         __set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags);
2184                 if (rss_obj->udp_rss_v6)
2185                         __set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);
2186
2187                 if (!CHIP_IS_E1x(bp))
2188                         /* valid only for TUNN_MODE_GRE tunnel mode */
2189                         __set_bit(BNX2X_RSS_GRE_INNER_HDRS, &params.rss_flags);
2190         } else {
2191                 __set_bit(BNX2X_RSS_MODE_DISABLED, &params.rss_flags);
2192         }
2193
2194         /* Hash bits */
2195         params.rss_result_mask = MULTI_MASK;
2196
2197         memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
2198
2199         if (config_hash) {
2200                 /* RSS keys */
2201                 netdev_rss_key_fill(params.rss_key, T_ETH_RSS_KEY * 4);
2202                 __set_bit(BNX2X_RSS_SET_SRCH, &params.rss_flags);
2203         }
2204
2205         if (IS_PF(bp))
2206                 return bnx2x_config_rss(bp, &params);
2207         else
2208                 return bnx2x_vfpf_config_rss(bp, &params);
2209 #endif
2210 }
2211
2212 static int bnx2x_init_hw(struct bnx2x *bp, uint32_t load_code)
2213 {
2214         struct bnx2x_func_state_params func_params = {NULL};
2215
2216         /* Prepare parameters for function state transitions */
2217         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
2218
2219         func_params.f_obj = &bp->func_obj;
2220         func_params.cmd = BNX2X_F_CMD_HW_INIT;
2221
2222         func_params.params.hw_init.load_phase = load_code;
2223
2224         return bnx2x_func_state_change(bp, &func_params);
2225 }
2226
2227 /*
2228  * Cleans the object that have internal lists without sending
2229  * ramrods. Should be run when interrupts are disabled.
2230  */
2231 void bnx2x_squeeze_objects(struct bnx2x *bp)
2232 {
2233         int rc;
2234         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
2235         struct bnx2x_mcast_ramrod_params rparam = {NULL};
2236         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
2237
2238         /***************** Cleanup MACs' object first *************************/
2239
2240         /* Wait for completion of requested */
2241         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2242         /* Perform a dry cleanup */
2243         __set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
2244
2245         /* Clean ETH primary MAC */
2246         __set_bit(BNX2X_ETH_MAC, &vlan_mac_flags);
2247         rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags,
2248                                  &ramrod_flags);
2249         if (rc != 0)
2250                 BNX2X_ERR("Failed to clean ETH MACs: %d\n", rc);
2251
2252         /* Cleanup UC list */
2253         vlan_mac_flags = 0;
2254         __set_bit(BNX2X_UC_LIST_MAC, &vlan_mac_flags);
2255         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags,
2256                                  &ramrod_flags);
2257         if (rc != 0)
2258                 BNX2X_ERR("Failed to clean UC list MACs: %d\n", rc);
2259
2260         /***************** Now clean mcast object *****************************/
2261         rparam.mcast_obj = &bp->mcast_obj;
2262         __set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
2263
2264         /* Add a DEL command... - Since we're doing a driver cleanup only,
2265          * we take a lock surrounding both the initial send and the CONTs,
2266          * as we don't want a true completion to disrupt us in the middle.
2267          */
2268         qlock(&bp->dev->qlock);
2269         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
2270         if (rc < 0)
2271                 BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n",
2272                           rc);
2273
2274         /* ...and wait until all pending commands are cleared */
2275         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2276         while (rc != 0) {
2277                 if (rc < 0) {
2278                         BNX2X_ERR("Failed to clean multi-cast object: %d\n",
2279                                   rc);
2280                         qunlock(&bp->dev->qlock);
2281                         return;
2282                 }
2283
2284                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2285         }
2286         qunlock(&bp->dev->qlock);
2287 }
2288
2289 #ifndef BNX2X_STOP_ON_ERROR
2290 #define LOAD_ERROR_EXIT(bp, label) \
2291         do { \
2292                 (bp)->state = BNX2X_STATE_ERROR; \
2293                 goto label; \
2294         } while (0)
2295
2296 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2297         do { \
2298                 bp->cnic_loaded = false; \
2299                 goto label; \
2300         } while (0)
2301 #else /*BNX2X_STOP_ON_ERROR*/
2302 #define LOAD_ERROR_EXIT(bp, label) \
2303         do { \
2304                 (bp)->state = BNX2X_STATE_ERROR; \
2305                 (bp)->panic = 1; \
2306                 return -EBUSY; \
2307         } while (0)
2308 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2309         do { \
2310                 bp->cnic_loaded = false; \
2311                 (bp)->panic = 1; \
2312                 return -EBUSY; \
2313         } while (0)
2314 #endif /*BNX2X_STOP_ON_ERROR*/
2315
2316 static void bnx2x_free_fw_stats_mem(struct bnx2x *bp)
2317 {
2318         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
2319                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2320         return;
2321 }
2322
2323 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
2324 {
2325         int num_groups, vf_headroom = 0;
2326         int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
2327
2328         /* number of queues for statistics is number of eth queues + FCoE */
2329         uint8_t num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
2330
2331         /* Total number of FW statistics requests =
2332          * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper
2333          * and fcoe l2 queue) stats + num of queues (which includes another 1
2334          * for fcoe l2 queue if applicable)
2335          */
2336         bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
2337
2338         /* vf stats appear in the request list, but their data is allocated by
2339          * the VFs themselves. We don't include them in the bp->fw_stats_num as
2340          * it is used to determine where to place the vf stats queries in the
2341          * request struct
2342          */
2343         if (IS_SRIOV(bp))
2344                 vf_headroom = bnx2x_vf_headroom(bp);
2345
2346         /* Request is built from stats_query_header and an array of
2347          * stats_query_cmd_group each of which contains
2348          * STATS_QUERY_CMD_COUNT rules. The real number or requests is
2349          * configured in the stats_query_header.
2350          */
2351         num_groups =
2352                 (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +
2353                  (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?
2354                  1 : 0));
2355
2356         DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n",
2357            bp->fw_stats_num, vf_headroom, num_groups);
2358         bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
2359                 num_groups * sizeof(struct stats_query_cmd_group);
2360
2361         /* Data for statistics requests + stats_counter
2362          * stats_counter holds per-STORM counters that are incremented
2363          * when STORM has finished with the current request.
2364          * memory for FCoE offloaded statistics are counted anyway,
2365          * even if they will not be sent.
2366          * VF stats are not accounted for here as the data of VF stats is stored
2367          * in memory allocated by the VF, not here.
2368          */
2369         bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
2370                 sizeof(struct per_pf_stats) +
2371                 sizeof(struct fcoe_statistics_params) +
2372                 sizeof(struct per_queue_stats) * num_queue_stats +
2373                 sizeof(struct stats_counter);
2374
2375         bp->fw_stats = BNX2X_PCI_ALLOC(&bp->fw_stats_mapping,
2376                                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2377         if (!bp->fw_stats)
2378                 goto alloc_mem_err;
2379
2380         /* Set shortcuts */
2381         bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
2382         bp->fw_stats_req_mapping = bp->fw_stats_mapping;
2383         bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
2384                 ((uint8_t *)bp->fw_stats + bp->fw_stats_req_sz);
2385         bp->fw_stats_data_mapping = bp->fw_stats_mapping +
2386                 bp->fw_stats_req_sz;
2387
2388         DP(BNX2X_MSG_SP, "statistics request base address set to %x %x\n",
2389            U64_HI(bp->fw_stats_req_mapping),
2390            U64_LO(bp->fw_stats_req_mapping));
2391         DP(BNX2X_MSG_SP, "statistics data base address set to %x %x\n",
2392            U64_HI(bp->fw_stats_data_mapping),
2393            U64_LO(bp->fw_stats_data_mapping));
2394         return 0;
2395
2396 alloc_mem_err:
2397         bnx2x_free_fw_stats_mem(bp);
2398         BNX2X_ERR("Can't allocate FW stats memory\n");
2399         return -ENOMEM;
2400 }
2401
2402 /* send load request to mcp and analyze response */
2403 static int bnx2x_nic_load_request(struct bnx2x *bp, uint32_t *load_code)
2404 {
2405 panic("Not implemented");
2406 #if 0 // AKAROS_PORT
2407         uint32_t param;
2408
2409         /* init fw_seq */
2410         bp->fw_seq =
2411                 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
2412                  DRV_MSG_SEQ_NUMBER_MASK);
2413         BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
2414
2415         /* Get current FW pulse sequence */
2416         bp->fw_drv_pulse_wr_seq =
2417                 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) &
2418                  DRV_PULSE_SEQ_MASK);
2419         BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
2420
2421         param = DRV_MSG_CODE_LOAD_REQ_WITH_LFA;
2422
2423         if (IS_MF_SD(bp) && bnx2x_port_after_undi(bp))
2424                 param |= DRV_MSG_CODE_LOAD_REQ_FORCE_LFA;
2425
2426         /* load request */
2427         (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, param);
2428
2429         /* if mcp fails to respond we must abort */
2430         if (!(*load_code)) {
2431                 BNX2X_ERR("MCP response failure, aborting\n");
2432                 return -EBUSY;
2433         }
2434
2435         /* If mcp refused (e.g. other port is in diagnostic mode) we
2436          * must abort
2437          */
2438         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2439                 BNX2X_ERR("MCP refused load request, aborting\n");
2440                 return -EBUSY;
2441         }
2442         return 0;
2443 #endif
2444 }
2445
2446 /* check whether another PF has already loaded FW to chip. In
2447  * virtualized environments a pf from another VM may have already
2448  * initialized the device including loading FW
2449  */
2450 int bnx2x_compare_fw_ver(struct bnx2x *bp, uint32_t load_code,
2451                          bool print_err)
2452 {
2453 panic("Not implemented");
2454 #if 0 // AKAROS_PORT
2455         /* is another pf loaded on this engine? */
2456         if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
2457             load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
2458                 /* build my FW version dword */
2459                 uint32_t my_fw = (BCM_5710_FW_MAJOR_VERSION) +
2460                         (BCM_5710_FW_MINOR_VERSION << 8) +
2461                         (BCM_5710_FW_REVISION_VERSION << 16) +
2462                         (BCM_5710_FW_ENGINEERING_VERSION << 24);
2463
2464                 /* read loaded FW from chip */
2465                 uint32_t loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
2466
2467                 DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n",
2468                    loaded_fw, my_fw);
2469
2470                 /* abort nic load if version mismatch */
2471                 if (my_fw != loaded_fw) {
2472                         if (print_err)
2473                                 BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. Aborting\n",
2474                                           loaded_fw, my_fw);
2475                         else
2476                                 BNX2X_DEV_INFO("bnx2x with FW %x was already loaded which mismatches my %x FW, possibly due to MF UNDI\n",
2477                                                loaded_fw, my_fw);
2478                         return -EBUSY;
2479                 }
2480         }
2481         return 0;
2482 #endif
2483 }
2484
2485 /* returns the "mcp load_code" according to global load_count array */
2486 static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
2487 {
2488         int path = BP_PATH(bp);
2489
2490         DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d]      %d, %d, %d\n",
2491            path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2492            bnx2x_load_count[path][2]);
2493         bnx2x_load_count[path][0]++;
2494         bnx2x_load_count[path][1 + port]++;
2495         DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d]  %d, %d, %d\n",
2496            path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2497            bnx2x_load_count[path][2]);
2498         if (bnx2x_load_count[path][0] == 1)
2499                 return FW_MSG_CODE_DRV_LOAD_COMMON;
2500         else if (bnx2x_load_count[path][1 + port] == 1)
2501                 return FW_MSG_CODE_DRV_LOAD_PORT;
2502         else
2503                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
2504 }
2505
2506 /* mark PMF if applicable */
2507 static void bnx2x_nic_load_pmf(struct bnx2x *bp, uint32_t load_code)
2508 {
2509         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2510             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2511             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2512                 bp->port.pmf = 1;
2513                 /* We need the barrier to ensure the ordering between the
2514                  * writing to bp->port.pmf here and reading it from the
2515                  * bnx2x_periodic_task().
2516                  */
2517                 mb();
2518         } else {
2519                 bp->port.pmf = 0;
2520         }
2521
2522         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2523 }
2524
2525 static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code)
2526 {
2527         if (((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2528              (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP)) &&
2529             (bp->common.shmem2_base)) {
2530                 if (SHMEM2_HAS(bp, dcc_support))
2531                         SHMEM2_WR(bp, dcc_support,
2532                                   (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
2533                                    SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
2534                 if (SHMEM2_HAS(bp, afex_driver_support))
2535                         SHMEM2_WR(bp, afex_driver_support,
2536                                   SHMEM_AFEX_SUPPORTED_VERSION_ONE);
2537         }
2538
2539         /* Set AFEX default VLAN tag to an invalid value */
2540         bp->afex_def_vlan_tag = -1;
2541 }
2542
2543 /**
2544  * bnx2x_bz_fp - zero content of the fastpath structure.
2545  *
2546  * @bp:         driver handle
2547  * @index:      fastpath index to be zeroed
2548  *
2549  * Makes sure the contents of the bp->fp[index].napi is kept
2550  * intact.
2551  */
2552 static void bnx2x_bz_fp(struct bnx2x *bp, int index)
2553 {
2554         struct bnx2x_fastpath *fp = &bp->fp[index];
2555         int cos;
2556         struct napi_struct orig_napi = fp->napi;
2557         struct bnx2x_agg_info *orig_tpa_info = fp->tpa_info;
2558
2559         /* bzero bnx2x_fastpath contents */
2560         if (fp->tpa_info)
2561                 memset(fp->tpa_info, 0, ETH_MAX_AGGREGATION_QUEUES_E1H_E2 *
2562                        sizeof(struct bnx2x_agg_info));
2563         memset(fp, 0, sizeof(*fp));
2564
2565         /* Restore the NAPI object as it has been already initialized */
2566         fp->napi = orig_napi;
2567         fp->tpa_info = orig_tpa_info;
2568         fp->bp = bp;
2569         fp->index = index;
2570         if (IS_ETH_FP(fp))
2571                 fp->max_cos = bp->max_cos;
2572         else
2573                 /* Special queues support only one CoS */
2574                 fp->max_cos = 1;
2575
2576         /* Init txdata pointers */
2577         if (IS_FCOE_FP(fp))
2578                 fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)];
2579         if (IS_ETH_FP(fp))
2580                 for_each_cos_in_tx_queue(fp, cos)
2581                         fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos *
2582                                 BNX2X_NUM_ETH_QUEUES(bp) + index];
2583
2584         /* set the tpa flag for each queue. The tpa flag determines the queue
2585          * minimal size so it must be set prior to queue memory allocation
2586          */
2587         fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG ||
2588                                   (bp->flags & GRO_ENABLE_FLAG &&
2589                                    bnx2x_mtu_allows_gro(bp->dev->maxmtu)));
2590         if (bp->flags & TPA_ENABLE_FLAG)
2591                 fp->mode = TPA_MODE_LRO;
2592         else if (bp->flags & GRO_ENABLE_FLAG)
2593                 fp->mode = TPA_MODE_GRO;
2594
2595         /* We don't want TPA on an FCoE L2 ring */
2596         if (IS_FCOE_FP(fp))
2597                 fp->disable_tpa = 1;
2598 }
2599
2600 int bnx2x_load_cnic(struct bnx2x *bp)
2601 {
2602         int i, rc, port = BP_PORT(bp);
2603
2604         DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n");
2605
2606         qlock_init(&bp->cnic_mutex);
2607
2608         if (IS_PF(bp)) {
2609                 rc = bnx2x_alloc_mem_cnic(bp);
2610                 if (rc) {
2611                         BNX2X_ERR("Unable to allocate bp memory for cnic\n");
2612                         LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2613                 }
2614         }
2615
2616         rc = bnx2x_alloc_fp_mem_cnic(bp);
2617         if (rc) {
2618                 BNX2X_ERR("Unable to allocate memory for cnic fps\n");
2619                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2620         }
2621
2622         /* Update the number of queues with the cnic queues */
2623         rc = bnx2x_set_real_num_queues(bp, 1);
2624         if (rc) {
2625                 BNX2X_ERR("Unable to set real_num_queues including cnic\n");
2626                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2627         }
2628
2629         /* Add all CNIC NAPI objects */
2630         bnx2x_add_all_napi_cnic(bp);
2631         DP(NETIF_MSG_IFUP, "cnic napi added\n");
2632         bnx2x_napi_enable_cnic(bp);
2633
2634         rc = bnx2x_init_hw_func_cnic(bp);
2635         if (rc)
2636                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1);
2637
2638         bnx2x_nic_init_cnic(bp);
2639
2640         if (IS_PF(bp)) {
2641                 /* Enable Timer scan */
2642                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1);
2643
2644                 /* setup cnic queues */
2645                 for_each_cnic_queue(bp, i) {
2646                         rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2647                         if (rc) {
2648                                 BNX2X_ERR("Queue setup failed\n");
2649                                 LOAD_ERROR_EXIT(bp, load_error_cnic2);
2650                         }
2651                 }
2652         }
2653
2654         /* Initialize Rx filter. */
2655         bnx2x_set_rx_mode_inner(bp);
2656
2657         /* re-read iscsi info */
2658         bnx2x_get_iscsi_info(bp);
2659         bnx2x_setup_cnic_irq_info(bp);
2660         bnx2x_setup_cnic_info(bp);
2661         bp->cnic_loaded = true;
2662         if (bp->state == BNX2X_STATE_OPEN)
2663                 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
2664
2665         DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n");
2666
2667         return 0;
2668
2669 #ifndef BNX2X_STOP_ON_ERROR
2670 load_error_cnic2:
2671         /* Disable Timer scan */
2672         REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
2673
2674 load_error_cnic1:
2675         bnx2x_napi_disable_cnic(bp);
2676         /* Update the number of queues without the cnic queues */
2677         if (bnx2x_set_real_num_queues(bp, 0))
2678                 BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
2679 load_error_cnic0:
2680         BNX2X_ERR("CNIC-related load failed\n");
2681         bnx2x_free_fp_mem_cnic(bp);
2682         bnx2x_free_mem_cnic(bp);
2683         return rc;
2684 #endif /* ! BNX2X_STOP_ON_ERROR */
2685 }
2686
2687 /* must be called with rtnl_lock */
2688 int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
2689 {
2690 panic("Not implemented");
2691 #if 0 // AKAROS_PORT
2692         int port = BP_PORT(bp);
2693         int i, rc = 0;
2694         uint32_t load_code = 0;
2695
2696         DP(NETIF_MSG_IFUP, "Starting NIC load\n");
2697         DP(NETIF_MSG_IFUP,
2698            "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled");
2699
2700 #ifdef BNX2X_STOP_ON_ERROR
2701         if (unlikely(bp->panic)) {
2702                 BNX2X_ERR("Can't load NIC when there is panic\n");
2703                 return -EPERM;
2704         }
2705 #endif
2706
2707         bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
2708
2709         /* zero the structure w/o any lock, before SP handler is initialized */
2710         memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link));
2711         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
2712                 &bp->last_reported_link.link_report_flags);
2713
2714         if (IS_PF(bp))
2715                 /* must be called before memory allocation and HW init */
2716                 bnx2x_ilt_set_info(bp);
2717
2718         /*
2719          * Zero fastpath structures preserving invariants like napi, which are
2720          * allocated only once, fp index, max_cos, bp pointer.
2721          * Also set fp->disable_tpa and txdata_ptr.
2722          */
2723         DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
2724         for_each_queue(bp, i)
2725                 bnx2x_bz_fp(bp, i);
2726         memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS +
2727                                   bp->num_cnic_queues) *
2728                                   sizeof(struct bnx2x_fp_txdata));
2729
2730         bp->fcoe_init = false;
2731
2732         /* Set the receive queues buffer size */
2733         bnx2x_set_rx_buf_size(bp);
2734
2735         if (IS_PF(bp)) {
2736                 rc = bnx2x_alloc_mem(bp);
2737                 if (rc) {
2738                         BNX2X_ERR("Unable to allocate bp memory\n");
2739                         return rc;
2740                 }
2741         }
2742
2743         /* need to be done after alloc mem, since it's self adjusting to amount
2744          * of memory available for RSS queues
2745          */
2746         rc = bnx2x_alloc_fp_mem(bp);
2747         if (rc) {
2748                 BNX2X_ERR("Unable to allocate memory for fps\n");
2749                 LOAD_ERROR_EXIT(bp, load_error0);
2750         }
2751
2752         /* Allocated memory for FW statistics  */
2753         if (bnx2x_alloc_fw_stats_mem(bp))
2754                 LOAD_ERROR_EXIT(bp, load_error0);
2755
2756         /* request pf to initialize status blocks */
2757         if (IS_VF(bp)) {
2758                 rc = bnx2x_vfpf_init(bp);
2759                 if (rc)
2760                         LOAD_ERROR_EXIT(bp, load_error0);
2761         }
2762
2763         /* As long as bnx2x_alloc_mem() may possibly update
2764          * bp->num_queues, bnx2x_set_real_num_queues() should always
2765          * come after it. At this stage cnic queues are not counted.
2766          */
2767         rc = bnx2x_set_real_num_queues(bp, 0);
2768         if (rc) {
2769                 BNX2X_ERR("Unable to set real_num_queues\n");
2770                 LOAD_ERROR_EXIT(bp, load_error0);
2771         }
2772
2773         /* configure multi cos mappings in kernel.
2774          * this configuration may be overridden by a multi class queue
2775          * discipline or by a dcbx negotiation result.
2776          */
2777         bnx2x_setup_tc(bp->dev, bp->max_cos);
2778
2779         /* Add all NAPI objects */
2780         bnx2x_add_all_napi(bp);
2781         DP(NETIF_MSG_IFUP, "napi added\n");
2782         bnx2x_napi_enable(bp);
2783
2784         if (IS_PF(bp)) {
2785                 /* set pf load just before approaching the MCP */
2786                 bnx2x_set_pf_load(bp);
2787
2788                 /* if mcp exists send load request and analyze response */
2789                 if (!BP_NOMCP(bp)) {
2790                         /* attempt to load pf */
2791                         rc = bnx2x_nic_load_request(bp, &load_code);
2792                         if (rc)
2793                                 LOAD_ERROR_EXIT(bp, load_error1);
2794
2795                         /* what did mcp say? */
2796                         rc = bnx2x_compare_fw_ver(bp, load_code, true);
2797                         if (rc) {
2798                                 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2799                                 LOAD_ERROR_EXIT(bp, load_error2);
2800                         }
2801                 } else {
2802                         load_code = bnx2x_nic_load_no_mcp(bp, port);
2803                 }
2804
2805                 /* mark pmf if applicable */
2806                 bnx2x_nic_load_pmf(bp, load_code);
2807
2808                 /* Init Function state controlling object */
2809                 bnx2x__init_func_obj(bp);
2810
2811                 /* Initialize HW */
2812                 rc = bnx2x_init_hw(bp, load_code);
2813                 if (rc) {
2814                         BNX2X_ERR("HW init failed, aborting\n");
2815                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2816                         LOAD_ERROR_EXIT(bp, load_error2);
2817                 }
2818         }
2819
2820         bnx2x_pre_irq_nic_init(bp);
2821
2822         /* Connect to IRQs */
2823         rc = bnx2x_setup_irqs(bp);
2824         if (rc) {
2825                 BNX2X_ERR("setup irqs failed\n");
2826                 if (IS_PF(bp))
2827                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2828                 LOAD_ERROR_EXIT(bp, load_error2);
2829         }
2830
2831         /* Init per-function objects */
2832         if (IS_PF(bp)) {
2833                 /* Setup NIC internals and enable interrupts */
2834                 bnx2x_post_irq_nic_init(bp, load_code);
2835
2836                 bnx2x_init_bp_objs(bp);
2837                 bnx2x_iov_nic_init(bp);
2838
2839                 /* Set AFEX default VLAN tag to an invalid value */
2840                 bp->afex_def_vlan_tag = -1;
2841                 bnx2x_nic_load_afex_dcc(bp, load_code);
2842                 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
2843                 rc = bnx2x_func_start(bp);
2844                 if (rc) {
2845                         BNX2X_ERR("Function start failed!\n");
2846                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2847
2848                         LOAD_ERROR_EXIT(bp, load_error3);
2849                 }
2850
2851                 /* Send LOAD_DONE command to MCP */
2852                 if (!BP_NOMCP(bp)) {
2853                         load_code = bnx2x_fw_command(bp,
2854                                                      DRV_MSG_CODE_LOAD_DONE, 0);
2855                         if (!load_code) {
2856                                 BNX2X_ERR("MCP response failure, aborting\n");
2857                                 rc = -EBUSY;
2858                                 LOAD_ERROR_EXIT(bp, load_error3);
2859                         }
2860                 }
2861
2862                 /* initialize FW coalescing state machines in RAM */
2863                 bnx2x_update_coalesce(bp);
2864         }
2865
2866         /* setup the leading queue */
2867         rc = bnx2x_setup_leading(bp);
2868         if (rc) {
2869                 BNX2X_ERR("Setup leading failed!\n");
2870                 LOAD_ERROR_EXIT(bp, load_error3);
2871         }
2872
2873         /* set up the rest of the queues */
2874         for_each_nondefault_eth_queue(bp, i) {
2875                 if (IS_PF(bp))
2876                         rc = bnx2x_setup_queue(bp, &bp->fp[i], false);
2877                 else /* VF */
2878                         rc = bnx2x_vfpf_setup_q(bp, &bp->fp[i], false);
2879                 if (rc) {
2880                         BNX2X_ERR("Queue %d setup failed\n", i);
2881                         LOAD_ERROR_EXIT(bp, load_error3);
2882                 }
2883         }
2884
2885         /* setup rss */
2886         rc = bnx2x_init_rss(bp);
2887         if (rc) {
2888                 BNX2X_ERR("PF RSS init failed\n");
2889                 LOAD_ERROR_EXIT(bp, load_error3);
2890         }
2891
2892         /* Now when Clients are configured we are ready to work */
2893         bp->state = BNX2X_STATE_OPEN;
2894
2895         /* Configure a ucast MAC */
2896 panic("Not implemented");
2897 #if 0 // AKAROS_PORT
2898         if (IS_PF(bp))
2899                 rc = bnx2x_set_eth_mac(bp, true);
2900         else /* vf */
2901                 rc = bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, bp->fp->index,
2902                                            true);
2903 #endif
2904         if (rc) {
2905                 BNX2X_ERR("Setting Ethernet MAC failed\n");
2906                 LOAD_ERROR_EXIT(bp, load_error3);
2907         }
2908
2909         if (IS_PF(bp) && bp->pending_max) {
2910                 bnx2x_update_max_mf_config(bp, bp->pending_max);
2911                 bp->pending_max = 0;
2912         }
2913
2914         if (bp->port.pmf) {
2915                 rc = bnx2x_initial_phy_init(bp, load_mode);
2916                 if (rc)
2917                         LOAD_ERROR_EXIT(bp, load_error3);
2918         }
2919         bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN;
2920
2921         /* Start fast path */
2922
2923         /* Initialize Rx filter. */
2924         bnx2x_set_rx_mode_inner(bp);
2925
2926         /* Start Tx */
2927         switch (load_mode) {
2928         case LOAD_NORMAL:
2929                 /* Tx queue should be only re-enabled */
2930                 netif_tx_wake_all_queues(bp->dev);
2931                 break;
2932
2933         case LOAD_OPEN:
2934                 netif_tx_start_all_queues(bp->dev);
2935                 cmb();
2936                 break;
2937
2938         case LOAD_DIAG:
2939         case LOAD_LOOPBACK_EXT:
2940                 bp->state = BNX2X_STATE_DIAG;
2941                 break;
2942
2943         default:
2944                 break;
2945         }
2946
2947         if (bp->port.pmf)
2948                 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0);
2949         else
2950                 bnx2x__link_status_update(bp);
2951
2952         /* start the timer */
2953         mod_timer(&bp->timer, jiffies + bp->current_interval);
2954
2955         if (CNIC_ENABLED(bp))
2956                 bnx2x_load_cnic(bp);
2957
2958         if (IS_PF(bp))
2959                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
2960
2961         if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2962                 /* mark driver is loaded in shmem2 */
2963                 uint32_t val;
2964                 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2965                 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2966                           val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
2967                           DRV_FLAGS_CAPABILITIES_LOADED_L2);
2968         }
2969
2970         /* Wait for all pending SP commands to complete */
2971         if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) {
2972                 BNX2X_ERR("Timeout waiting for SP elements to complete\n");
2973                 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
2974                 return -EBUSY;
2975         }
2976
2977         /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
2978         if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
2979                 bnx2x_dcbx_init(bp, false);
2980
2981         DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
2982
2983         return 0;
2984
2985 #ifndef BNX2X_STOP_ON_ERROR
2986 load_error3:
2987         if (IS_PF(bp)) {
2988                 bnx2x_int_disable_sync(bp, 1);
2989
2990                 /* Clean queueable objects */
2991                 bnx2x_squeeze_objects(bp);
2992         }
2993
2994         /* Free SKBs, SGEs, TPA pool and driver internals */
2995         bnx2x_free_skbs(bp);
2996         for_each_rx_queue(bp, i)
2997                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2998
2999         /* Release IRQs */
3000         bnx2x_free_irq(bp);
3001 load_error2:
3002         if (IS_PF(bp) && !BP_NOMCP(bp)) {
3003                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
3004                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
3005         }
3006
3007         bp->port.pmf = 0;
3008 load_error1:
3009         bnx2x_napi_disable(bp);
3010         bnx2x_del_all_napi(bp);
3011
3012         /* clear pf_load status, as it was already set */
3013         if (IS_PF(bp))
3014                 bnx2x_clear_pf_load(bp);
3015 load_error0:
3016         bnx2x_free_fw_stats_mem(bp);
3017         bnx2x_free_fp_mem(bp);
3018         bnx2x_free_mem(bp);
3019
3020         return rc;
3021 #endif /* ! BNX2X_STOP_ON_ERROR */
3022 #endif
3023 }
3024
3025 int bnx2x_drain_tx_queues(struct bnx2x *bp)
3026 {
3027         uint8_t rc = 0, cos, i;
3028
3029         /* Wait until tx fastpath tasks complete */
3030         for_each_tx_queue(bp, i) {
3031                 struct bnx2x_fastpath *fp = &bp->fp[i];
3032
3033                 for_each_cos_in_tx_queue(fp, cos)
3034                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
3035                 if (rc)
3036                         return rc;
3037         }
3038         return 0;
3039 }
3040
3041 /* must be called with rtnl_lock */
3042 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
3043 {
3044 panic("Not implemented");
3045 #if 0 // AKAROS_PORT
3046         int i;
3047         bool global = false;
3048
3049         DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
3050
3051         /* mark driver is unloaded in shmem2 */
3052         if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
3053                 uint32_t val;
3054                 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
3055                 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
3056                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
3057         }
3058
3059         if (IS_PF(bp) && bp->recovery_state != BNX2X_RECOVERY_DONE &&
3060             (bp->state == BNX2X_STATE_CLOSED ||
3061              bp->state == BNX2X_STATE_ERROR)) {
3062                 /* We can get here if the driver has been unloaded
3063                  * during parity error recovery and is either waiting for a
3064                  * leader to complete or for other functions to unload and
3065                  * then ifdown has been issued. In this case we want to
3066                  * unload and let other functions to complete a recovery
3067                  * process.
3068                  */
3069                 bp->recovery_state = BNX2X_RECOVERY_DONE;
3070                 bp->is_leader = 0;
3071                 bnx2x_release_leader_lock(bp);
3072                 mb();
3073
3074                 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n");
3075                 BNX2X_ERR("Can't unload in closed or error state\n");
3076                 return -EINVAL;
3077         }
3078
3079         /* Nothing to do during unload if previous bnx2x_nic_load()
3080          * have not completed successfully - all resources are released.
3081          *
3082          * we can get here only after unsuccessful ndo_* callback, during which
3083          * dev->IFF_UP flag is still on.
3084          */
3085         if (bp->state == BNX2X_STATE_CLOSED || bp->state == BNX2X_STATE_ERROR)
3086                 return 0;
3087
3088         /* It's important to set the bp->state to the value different from
3089          * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int()
3090          * may restart the Tx from the NAPI context (see bnx2x_tx_int()).
3091          */
3092         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
3093         mb();
3094
3095         /* indicate to VFs that the PF is going down */
3096         bnx2x_iov_channel_down(bp);
3097
3098         if (CNIC_LOADED(bp))
3099                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
3100
3101         /* Stop Tx */
3102         bnx2x_tx_disable(bp);
3103         netdev_reset_tc(bp->dev);
3104
3105         bp->rx_mode = BNX2X_RX_MODE_NONE;
3106
3107         del_timer_sync(&bp->timer);
3108
3109         if (IS_PF(bp)) {
3110                 /* Set ALWAYS_ALIVE bit in shmem */
3111                 bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
3112                 bnx2x_drv_pulse(bp);
3113                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
3114                 bnx2x_save_statistics(bp);
3115         }
3116
3117         /* wait till consumers catch up with producers in all queues */
3118         bnx2x_drain_tx_queues(bp);
3119
3120         /* if VF indicate to PF this function is going down (PF will delete sp
3121          * elements and clear initializations
3122          */
3123         if (IS_VF(bp))
3124                 bnx2x_vfpf_close_vf(bp);
3125         else if (unload_mode != UNLOAD_RECOVERY)
3126                 /* if this is a normal/close unload need to clean up chip*/
3127                 bnx2x_chip_cleanup(bp, unload_mode, keep_link);
3128         else {
3129                 /* Send the UNLOAD_REQUEST to the MCP */
3130                 bnx2x_send_unload_req(bp, unload_mode);
3131
3132                 /* Prevent transactions to host from the functions on the
3133                  * engine that doesn't reset global blocks in case of global
3134                  * attention once global blocks are reset and gates are opened
3135                  * (the engine which leader will perform the recovery
3136                  * last).
3137                  */
3138                 if (!CHIP_IS_E1x(bp))
3139                         bnx2x_pf_disable(bp);
3140
3141                 /* Disable HW interrupts, NAPI */
3142                 bnx2x_netif_stop(bp, 1);
3143                 /* Delete all NAPI objects */
3144                 bnx2x_del_all_napi(bp);
3145                 if (CNIC_LOADED(bp))
3146                         bnx2x_del_all_napi_cnic(bp);
3147                 /* Release IRQs */
3148                 bnx2x_free_irq(bp);
3149
3150                 /* Report UNLOAD_DONE to MCP */
3151                 bnx2x_send_unload_done(bp, false);
3152         }
3153
3154         /*
3155          * At this stage no more interrupts will arrive so we may safely clean
3156          * the queueable objects here in case they failed to get cleaned so far.
3157          */
3158         if (IS_PF(bp))
3159                 bnx2x_squeeze_objects(bp);
3160
3161         /* There should be no more pending SP commands at this stage */
3162         bp->sp_state = 0;
3163
3164         bp->port.pmf = 0;
3165
3166         /* clear pending work in rtnl task */
3167         bp->sp_rtnl_state = 0;
3168         mb();
3169
3170         /* Free SKBs, SGEs, TPA pool and driver internals */
3171         bnx2x_free_skbs(bp);
3172         if (CNIC_LOADED(bp))
3173                 bnx2x_free_skbs_cnic(bp);
3174         for_each_rx_queue(bp, i)
3175                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
3176
3177         bnx2x_free_fp_mem(bp);
3178         if (CNIC_LOADED(bp))
3179                 bnx2x_free_fp_mem_cnic(bp);
3180
3181         if (IS_PF(bp)) {
3182                 if (CNIC_LOADED(bp))
3183                         bnx2x_free_mem_cnic(bp);
3184         }
3185         bnx2x_free_mem(bp);
3186
3187         bp->state = BNX2X_STATE_CLOSED;
3188         bp->cnic_loaded = false;
3189
3190         /* Clear driver version indication in shmem */
3191         if (IS_PF(bp))
3192                 bnx2x_update_mng_version(bp);
3193
3194         /* Check if there are pending parity attentions. If there are - set
3195          * RECOVERY_IN_PROGRESS.
3196          */
3197         if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) {
3198                 bnx2x_set_reset_in_progress(bp);
3199
3200                 /* Set RESET_IS_GLOBAL if needed */
3201                 if (global)
3202                         bnx2x_set_reset_global(bp);
3203         }
3204
3205         /* The last driver must disable a&nb