net: Use NULL to signal lack of promisc/multicast
[akaros.git] / kern / drivers / net / bnx2x / bnx2x_cmn.c
1 /* bnx2x_cmn.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath and fastpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include <linux_compat.h>
19
20 #include "bnx2x_cmn.h"
21 #include "bnx2x_init.h"
22 #include "bnx2x_sp.h"
23
24 static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp);
25 static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp);
26 static int bnx2x_alloc_fp_mem(struct bnx2x *bp);
27 static void bnx2x_poll(uint32_t srcid, long a0, long a1, long a2);
28
29 static void bnx2x_add_all_napi_cnic(struct bnx2x *bp)
30 {
31         int i;
32
33         /* Add NAPI objects */
34         for_each_rx_queue_cnic(bp, i) {
35                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
36                                bnx2x_poll, NAPI_POLL_WEIGHT);
37                 napi_hash_add(&bnx2x_fp(bp, i, napi));
38         }
39 }
40
41 static void bnx2x_add_all_napi(struct bnx2x *bp)
42 {
43         int i;
44
45         /* Add NAPI objects */
46         for_each_eth_queue(bp, i) {
47                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
48                                bnx2x_poll, NAPI_POLL_WEIGHT);
49                 napi_hash_add(&bnx2x_fp(bp, i, napi));
50         }
51 }
52
53 static int bnx2x_calc_num_queues(struct bnx2x *bp)
54 {
55         /* default is min(8, num_cores) in Linux.  we'll set it elsewhere */
56         int nq = bnx2x_num_queues ? : 8;
57
58         /* Reduce memory usage in kdump environment by using only one queue */
59         if (is_kdump_kernel())
60                 nq = 1;
61
62         nq = CLAMP(nq, 1, BNX2X_MAX_QUEUES(bp));
63         return nq;
64 }
65
66 /**
67  * bnx2x_move_fp - move content of the fastpath structure.
68  *
69  * @bp:         driver handle
70  * @from:       source FP index
71  * @to:         destination FP index
72  *
73  * Makes sure the contents of the bp->fp[to].napi is kept
74  * intact. This is done by first copying the napi struct from
75  * the target to the source, and then mem copying the entire
76  * source onto the target. Update txdata pointers and related
77  * content.
78  */
79 static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
80 {
81         struct bnx2x_fastpath *from_fp = &bp->fp[from];
82         struct bnx2x_fastpath *to_fp = &bp->fp[to];
83         struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from];
84         struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to];
85         struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from];
86         struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to];
87         int old_max_eth_txqs, new_max_eth_txqs;
88         int old_txdata_index = 0, new_txdata_index = 0;
89         struct bnx2x_agg_info *old_tpa_info = to_fp->tpa_info;
90
91         /* Copy the NAPI object as it has been already initialized */
92         from_fp->napi = to_fp->napi;
93
94         /* Move bnx2x_fastpath contents */
95         memcpy(to_fp, from_fp, sizeof(*to_fp));
96         to_fp->index = to;
97
98         /* Retain the tpa_info of the original `to' version as we don't want
99          * 2 FPs to contain the same tpa_info pointer.
100          */
101         to_fp->tpa_info = old_tpa_info;
102
103         /* move sp_objs contents as well, as their indices match fp ones */
104         memcpy(to_sp_objs, from_sp_objs, sizeof(*to_sp_objs));
105
106         /* move fp_stats contents as well, as their indices match fp ones */
107         memcpy(to_fp_stats, from_fp_stats, sizeof(*to_fp_stats));
108
109         /* Update txdata pointers in fp and move txdata content accordingly:
110          * Each fp consumes 'max_cos' txdata structures, so the index should be
111          * decremented by max_cos x delta.
112          */
113
114         old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos;
115         new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) *
116                                 (bp)->max_cos;
117         if (from == FCOE_IDX(bp)) {
118                 old_txdata_index = old_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
119                 new_txdata_index = new_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
120         }
121
122         memcpy(&bp->bnx2x_txq[new_txdata_index],
123                &bp->bnx2x_txq[old_txdata_index],
124                sizeof(struct bnx2x_fp_txdata));
125         to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index];
126 }
127
128 /**
129  * bnx2x_fill_fw_str - Fill buffer with FW version string.
130  *
131  * @bp:        driver handle
132  * @buf:       character buffer to fill with the fw name
133  * @buf_len:   length of the above buffer
134  *
135  */
136 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
137 {
138         if (IS_PF(bp)) {
139                 uint8_t phy_fw_ver[PHY_FW_VER_LEN];
140
141                 phy_fw_ver[0] = '\0';
142                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
143                                              phy_fw_ver, PHY_FW_VER_LEN);
144                 strlcpy(buf, bp->fw_ver, buf_len);
145                 snprintf(buf + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
146                          "bc %d.%d.%d%s%s",
147                          (bp->common.bc_ver & 0xff0000) >> 16,
148                          (bp->common.bc_ver & 0xff00) >> 8,
149                          (bp->common.bc_ver & 0xff),
150                          ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
151         } else {
152                 bnx2x_vf_fill_fw_str(bp, buf, buf_len);
153         }
154 }
155
156 /**
157  * bnx2x_shrink_eth_fp - guarantees fastpath structures stay intact
158  *
159  * @bp: driver handle
160  * @delta:      number of eth queues which were not allocated
161  */
162 static void bnx2x_shrink_eth_fp(struct bnx2x *bp, int delta)
163 {
164         int i, cos, old_eth_num = BNX2X_NUM_ETH_QUEUES(bp);
165
166         /* Queue pointer cannot be re-set on an fp-basis, as moving pointer
167          * backward along the array could cause memory to be overridden
168          */
169         for (cos = 1; cos < bp->max_cos; cos++) {
170                 for (i = 0; i < old_eth_num - delta; i++) {
171                         struct bnx2x_fastpath *fp = &bp->fp[i];
172                         int new_idx = cos * (old_eth_num - delta) + i;
173
174                         memcpy(&bp->bnx2x_txq[new_idx], fp->txdata_ptr[cos],
175                                sizeof(struct bnx2x_fp_txdata));
176                         fp->txdata_ptr[cos] = &bp->bnx2x_txq[new_idx];
177                 }
178         }
179 }
180
181 int bnx2x_load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
182
183 /* free skb in the packet ring at pos idx
184  * return idx of last bd freed
185  */
186 static uint16_t bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
187                              uint16_t idx, unsigned int *pkts_compl,
188                              unsigned int *bytes_compl)
189 {
190         struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx];
191         struct eth_tx_start_bd *tx_start_bd;
192         struct eth_tx_bd *tx_data_bd;
193         struct block *block = tx_buf->block;
194         uint16_t bd_idx = TX_BD(tx_buf->first_bd), new_cons;
195         int nbd;
196         uint16_t split_bd_len = 0;
197
198         /* prefetch skb end pointer to speedup dev_kfree_skb() */
199         //prefetch(&skb->end); // AKAROS_PORT
200
201         DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d  buff @(%p)->block %p\n",
202            txdata->txq_index, idx, tx_buf, block);
203
204         tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd;
205
206         nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
207 #ifdef BNX2X_STOP_ON_ERROR
208         if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
209                 BNX2X_ERR("BAD nbd!\n");
210                 bnx2x_panic();
211         }
212 #endif
213         new_cons = nbd + tx_buf->first_bd;
214
215         /* Get the next bd */
216         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
217
218         /* Skip a parse bd... */
219         --nbd;
220         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
221
222         if (tx_buf->flags & BNX2X_HAS_SECOND_PBD) {
223                 /* Skip second parse bd... */
224                 --nbd;
225                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
226         }
227
228         /* TSO headers+data bds share a common mapping. See bnx2x_tx_split() */
229         if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
230                 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
231                 split_bd_len = BD_UNMAP_LEN(tx_data_bd);
232                 --nbd;
233                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
234         }
235
236         /* unmap first bd */
237         dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
238                          BD_UNMAP_LEN(tx_start_bd) + split_bd_len,
239                          DMA_TO_DEVICE);
240
241         /* now free frags */
242         while (nbd > 0) {
243
244                 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
245                 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
246                                BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
247                 if (--nbd)
248                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
249         }
250
251         /* release block */
252         warn_on(!block);
253         if (likely(block)) {
254                 (*pkts_compl)++;
255                 (*bytes_compl) += BLEN(block);
256         }
257
258         freeb(block);
259         tx_buf->first_bd = 0;
260         tx_buf->block = NULL;
261
262         return new_cons;
263 }
264
265 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
266 {
267         uint16_t hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
268         unsigned int pkts_compl = 0, bytes_compl = 0;
269
270 #ifdef BNX2X_STOP_ON_ERROR
271         if (unlikely(bp->panic))
272                 return -1;
273 #endif
274
275         hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
276         sw_cons = txdata->tx_pkt_cons;
277
278         while (sw_cons != hw_cons) {
279                 uint16_t pkt_cons;
280
281                 pkt_cons = TX_BD(sw_cons);
282
283                 DP(NETIF_MSG_TX_DONE,
284                    "queue[%d]: hw_cons %u  sw_cons %u  pkt_cons %u\n",
285                    txdata->txq_index, hw_cons, sw_cons, pkt_cons);
286
287                 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
288                                             &pkts_compl, &bytes_compl);
289
290                 sw_cons++;
291         }
292
293         txdata->tx_pkt_cons = sw_cons;
294         txdata->tx_bd_cons = bd_cons;
295
296         poke(&txdata->poker, txdata);
297         return 0;
298 }
299
300 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
301                                              uint16_t idx)
302 {
303         uint16_t last_max = fp->last_max_sge;
304
305         if (SUB_S16(idx, last_max) > 0)
306                 fp->last_max_sge = idx;
307 }
308
309 static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
310                                          uint16_t sge_len,
311                                          struct eth_end_agg_rx_cqe *cqe)
312 {
313         struct bnx2x *bp = fp->bp;
314         uint16_t last_max, last_elem, first_elem;
315         uint16_t delta = 0;
316         uint16_t i;
317
318         if (!sge_len)
319                 return;
320
321         /* First mark all used pages */
322         for (i = 0; i < sge_len; i++)
323                 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
324                         RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[i])));
325
326         DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
327            sge_len - 1, le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
328
329         /* Here we assume that the last SGE index is the biggest */
330         prefetch((void *)(fp->sge_mask));
331         bnx2x_update_last_max_sge(fp,
332                 le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
333
334         last_max = RX_SGE(fp->last_max_sge);
335         last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
336         first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
337
338         /* If ring is not full */
339         if (last_elem + 1 != first_elem)
340                 last_elem++;
341
342         /* Now update the prod */
343         for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
344                 if (likely(fp->sge_mask[i]))
345                         break;
346
347                 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
348                 delta += BIT_VEC64_ELEM_SZ;
349         }
350
351         if (delta > 0) {
352                 fp->rx_sge_prod += delta;
353                 /* clear page-end entries */
354                 bnx2x_clear_sge_mask_next_elems(fp);
355         }
356
357         DP(NETIF_MSG_RX_STATUS,
358            "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
359            fp->last_max_sge, fp->rx_sge_prod);
360 }
361
362 /* Get Toeplitz hash value in the skb using the value from the
363  * CQE (calculated by HW).
364  */
365 static uint32_t bnx2x_get_rxhash(const struct bnx2x *bp,
366                             const struct eth_fast_path_rx_cqe *cqe,
367                             enum pkt_hash_types *rxhash_type)
368 {
369 panic("Not implemented");
370 #if 0 // AKAROS_PORT
371         /* Get Toeplitz hash from CQE */
372         if ((bp->dev->feat & NETIF_F_RXHASH) &&
373             (cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) {
374                 enum eth_rss_hash_type htype;
375
376                 htype = cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE;
377                 *rxhash_type = ((htype == TCP_IPV4_HASH_TYPE) ||
378                                 (htype == TCP_IPV6_HASH_TYPE)) ?
379                                PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
380
381                 return le32_to_cpu(cqe->rss_hash_result);
382         }
383         *rxhash_type = PKT_HASH_TYPE_NONE;
384         return 0;
385 #endif
386 }
387
388 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, uint16_t queue,
389                             uint16_t cons, uint16_t prod,
390                             struct eth_fast_path_rx_cqe *cqe)
391 {
392 panic("Not implemented");
393 #if 0 // AKAROS_PORT
394         struct bnx2x *bp = fp->bp;
395         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
396         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
397         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
398         dma_addr_t mapping;
399         struct bnx2x_agg_info *tpa_info = &fp->tpa_info[queue];
400         struct sw_rx_bd *first_buf = &tpa_info->first_buf;
401
402         /* print error if current state != stop */
403         if (tpa_info->tpa_state != BNX2X_TPA_STOP)
404                 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
405
406         /* Try to map an empty data buffer from the aggregation info  */
407         mapping = dma_map_single(&bp->pdev->dev,
408                                  first_buf->data + NET_SKB_PAD,
409                                  fp->rx_buf_size, DMA_FROM_DEVICE);
410         /*
411          *  ...if it fails - move the skb from the consumer to the producer
412          *  and set the current aggregation state as ERROR to drop it
413          *  when TPA_STOP arrives.
414          */
415
416         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
417                 /* Move the BD from the consumer to the producer */
418                 bnx2x_reuse_rx_data(fp, cons, prod);
419                 tpa_info->tpa_state = BNX2X_TPA_ERROR;
420                 return;
421         }
422
423         /* move empty data from pool to prod */
424         prod_rx_buf->data = first_buf->data;
425         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
426         /* point prod_bd to new data */
427         prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
428         prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
429
430         /* move partial skb from cons to pool (don't unmap yet) */
431         *first_buf = *cons_rx_buf;
432
433         /* mark bin state as START */
434         tpa_info->parsing_flags =
435                 le16_to_cpu(cqe->pars_flags.flags);
436         tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
437         tpa_info->tpa_state = BNX2X_TPA_START;
438         tpa_info->len_on_bd = le16_to_cpu(cqe->len_on_bd);
439         tpa_info->placement_offset = cqe->placement_offset;
440         tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->rxhash_type);
441         if (fp->mode == TPA_MODE_GRO) {
442                 uint16_t gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
443                 tpa_info->full_page = SGE_PAGES / gro_size * gro_size;
444                 tpa_info->gro_size = gro_size;
445         }
446
447 #ifdef BNX2X_STOP_ON_ERROR
448         fp->tpa_queue_used |= (1 << queue);
449         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
450            fp->tpa_queue_used);
451 #endif
452 #endif
453 }
454
455 /* Timestamp option length allowed for TPA aggregation:
456  *
457  *              nop nop kind length echo val
458  */
459 #define TPA_TSTAMP_OPT_LEN      12
460 /**
461  * bnx2x_set_gro_params - compute GRO values
462  *
463  * @skb:                packet skb
464  * @parsing_flags:      parsing flags from the START CQE
465  * @len_on_bd:          total length of the first packet for the
466  *                      aggregation.
467  * @pkt_len:            length of all segments
468  *
469  * Approximate value of the MSS for this aggregation calculated using
470  * the first packet of it.
471  * Compute number of aggregated segments, and gso_type.
472  */
473 static void bnx2x_set_gro_params(struct sk_buff *skb, uint16_t parsing_flags,
474                                  uint16_t len_on_bd, unsigned int pkt_len,
475                                  uint16_t num_of_coalesced_segs)
476 {
477 panic("Not implemented");
478 #if 0 // AKAROS_PORT
479         /* TPA aggregation won't have either IP options or TCP options
480          * other than timestamp or IPv6 extension headers.
481          */
482         uint16_t hdrs_len = ETHERHDRSIZE + sizeof(struct tcphdr);
483
484         if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
485             PRS_FLAG_OVERETH_IPV6) {
486                 hdrs_len += sizeof(struct ipv6hdr);
487                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
488         } else {
489                 hdrs_len += sizeof(struct iphdr);
490                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
491         }
492
493         /* Check if there was a TCP timestamp, if there is it's will
494          * always be 12 bytes length: nop nop kind length echo val.
495          *
496          * Otherwise FW would close the aggregation.
497          */
498         if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG)
499                 hdrs_len += TPA_TSTAMP_OPT_LEN;
500
501         skb_shinfo(skb)->gso_size = len_on_bd - hdrs_len;
502
503         /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
504          * to skb_shinfo(skb)->gso_segs
505          */
506         NAPI_GRO_CB(skb)->count = num_of_coalesced_segs;
507 #endif
508 }
509
510 static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp,
511                               uint16_t index, gfp_t gfp_mask)
512 {
513         /* AKAROS_PORT: our get_cont_pages returns KVAs, not struct page * */
514         struct page *page = kva2page(get_cont_pages(PAGES_PER_SGE_SHIFT, gfp_mask));
515         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
516         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
517         dma_addr_t mapping;
518
519         if (unlikely(page == NULL)) {
520                 BNX2X_ERR("Can't alloc sge\n");
521                 return -ENOMEM;
522         }
523
524         mapping = dma_map_page(&bp->pdev->dev, page, 0,
525                                SGE_PAGES, DMA_FROM_DEVICE);
526         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
527                 free_cont_pages(page2kva(page), PAGES_PER_SGE_SHIFT);
528                 BNX2X_ERR("Can't map sge\n");
529                 return -ENOMEM;
530         }
531
532         sw_buf->page = page;
533         dma_unmap_addr_set(sw_buf, mapping, mapping);
534
535         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
536         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
537
538         return 0;
539 }
540
541 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
542                                struct bnx2x_agg_info *tpa_info,
543                                uint16_t pages,
544                                struct sk_buff *skb,
545                                struct eth_end_agg_rx_cqe *cqe,
546                                uint16_t cqe_idx)
547 {
548 panic("Not implemented");
549 #if 0 // AKAROS_PORT
550         struct sw_rx_page *rx_pg, old_rx_pg;
551         uint32_t i, frag_len, frag_size;
552         int err, j, frag_id = 0;
553         uint16_t len_on_bd = tpa_info->len_on_bd;
554         uint16_t full_page = 0, gro_size = 0;
555
556         frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd;
557
558         if (fp->mode == TPA_MODE_GRO) {
559                 gro_size = tpa_info->gro_size;
560                 full_page = tpa_info->full_page;
561         }
562
563         /* This is needed in order to enable forwarding support */
564         if (frag_size)
565                 bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd,
566                                      le16_to_cpu(cqe->pkt_len),
567                                      le16_to_cpu(cqe->num_of_coalesced_segs));
568
569 #ifdef BNX2X_STOP_ON_ERROR
570         if (pages > MIN_T(uint32_t, 8, MAX_SKB_FRAGS) * SGE_PAGES) {
571                 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
572                           pages, cqe_idx);
573                 BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len);
574                 bnx2x_panic();
575                 return -EINVAL;
576         }
577 #endif
578
579         /* Run through the SGL and compose the fragmented skb */
580         for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
581                 uint16_t sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
582
583                 /* FW gives the indices of the SGE as if the ring is an array
584                    (meaning that "next" element will consume 2 indices) */
585                 if (fp->mode == TPA_MODE_GRO)
586                         frag_len = MIN_T(uint32_t, frag_size,
587                                          (uint32_t)full_page);
588                 else /* LRO */
589                         frag_len = MIN_T(uint32_t, frag_size,
590                                          (uint32_t)SGE_PAGES);
591
592                 rx_pg = &fp->rx_page_ring[sge_idx];
593                 old_rx_pg = *rx_pg;
594
595                 /* If we fail to allocate a substitute page, we simply stop
596                    where we are and drop the whole packet */
597                 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx, 0);
598                 if (unlikely(err)) {
599                         bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
600                         return err;
601                 }
602
603                 /* Unmap the page as we're going to pass it to the stack */
604                 dma_unmap_page(&bp->pdev->dev,
605                                dma_unmap_addr(&old_rx_pg, mapping),
606                                SGE_PAGES, DMA_FROM_DEVICE);
607                 /* Add one frag and update the appropriate fields in the skb */
608                 if (fp->mode == TPA_MODE_LRO)
609                         skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
610                 else { /* GRO */
611                         int rem;
612                         int offset = 0;
613                         for (rem = frag_len; rem > 0; rem -= gro_size) {
614                                 int len = rem > gro_size ? gro_size : rem;
615                                 skb_fill_page_desc(skb, frag_id++,
616                                                    old_rx_pg.page, offset, len);
617                                 /* TODO: if this is pinning for I/O, we need to change to a
618                                  * device-ownership / mmap model. */
619                                 if (offset)
620                                         page_incref(old_rx_pg.page);
621                                 offset += len;
622                         }
623                 }
624
625                 skb->data_len += frag_len;
626                 skb->truesize += SGE_PAGES;
627                 skb->len += frag_len;
628
629                 frag_size -= frag_len;
630         }
631
632         return 0;
633 #endif
634 }
635
636 static void bnx2x_frag_free(const struct bnx2x_fastpath *fp, void *data)
637 {
638         if (fp->rx_frag_size)
639                 page_decref(kva2page(data));
640         else
641                 kfree(data);
642 }
643
644 static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp, gfp_t gfp_mask)
645 {
646         if (fp->rx_frag_size) {
647                 /* GFP_KERNEL allocations are used only during initialization */
648                 if (unlikely(gfp_mask & MEM_WAIT))
649                         return (void *)kpage_alloc_addr();
650
651 #if 0 // AKAROS_PORT
652                 return netdev_alloc_frag(fp->rx_frag_size);
653 #else
654                 return (void *)kpage_alloc_addr();
655 #endif
656         }
657
658         return kmalloc(fp->rx_buf_size + NET_SKB_PAD, gfp_mask);
659 }
660
661 #ifdef CONFIG_INET
662 static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb)
663 {
664         const struct iphdr *iph = ip_hdr(skb);
665         struct tcphdr *th;
666
667         skb_set_transport_header(skb, sizeof(struct iphdr));
668         th = tcp_hdr(skb);
669
670         th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
671                                   iph->saddr, iph->daddr, 0);
672 }
673
674 static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb)
675 {
676         struct ipv6hdr *iph = ipv6_hdr(skb);
677         struct tcphdr *th;
678
679         skb_set_transport_header(skb, sizeof(struct ipv6hdr));
680         th = tcp_hdr(skb);
681
682         th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
683                                   &iph->saddr, &iph->daddr, 0);
684 }
685
686 static void bnx2x_gro_csum(struct bnx2x *bp, struct sk_buff *skb,
687                             void (*gro_func)(struct bnx2x*, struct sk_buff*))
688 {
689         skb_set_network_header(skb, 0);
690         gro_func(bp, skb);
691         tcp_gro_complete(skb);
692 }
693 #endif
694
695 static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
696                                struct sk_buff *skb)
697 {
698 panic("Not implemented");
699 #if 0 // AKAROS_PORT
700 #ifdef CONFIG_INET
701         if (skb_shinfo(skb)->gso_size) {
702                 switch (be16_to_cpu(skb->protocol)) {
703                 case ETH_P_IP:
704                         bnx2x_gro_csum(bp, skb, bnx2x_gro_ip_csum);
705                         break;
706                 case ETH_P_IPV6:
707                         bnx2x_gro_csum(bp, skb, bnx2x_gro_ipv6_csum);
708                         break;
709                 default:
710                         BNX2X_ERR("Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
711                                   be16_to_cpu(skb->protocol));
712                 }
713         }
714 #endif
715         skb_record_rx_queue(skb, fp->rx_queue);
716         napi_gro_receive(&fp->napi, skb);
717 #endif
718 }
719
720 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
721                            struct bnx2x_agg_info *tpa_info,
722                            uint16_t pages,
723                            struct eth_end_agg_rx_cqe *cqe,
724                            uint16_t cqe_idx)
725 {
726 panic("Not implemented");
727 #if 0 // AKAROS_PORT
728         struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
729         uint8_t pad = tpa_info->placement_offset;
730         uint16_t len = tpa_info->len_on_bd;
731         struct sk_buff *skb = NULL;
732         uint8_t *new_data, *data = rx_buf->data;
733         uint8_t old_tpa_state = tpa_info->tpa_state;
734
735         tpa_info->tpa_state = BNX2X_TPA_STOP;
736
737         /* If we there was an error during the handling of the TPA_START -
738          * drop this aggregation.
739          */
740         if (old_tpa_state == BNX2X_TPA_ERROR)
741                 goto drop;
742
743         /* Try to allocate the new data */
744         new_data = bnx2x_frag_alloc(fp, 0);
745         /* Unmap skb in the pool anyway, as we are going to change
746            pool entry status to BNX2X_TPA_STOP even if new skb allocation
747            fails. */
748         dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
749                          fp->rx_buf_size, DMA_FROM_DEVICE);
750         if (likely(new_data))
751                 skb = build_skb(data, fp->rx_frag_size);
752
753         if (likely(skb)) {
754 #ifdef BNX2X_STOP_ON_ERROR
755                 if (pad + len > fp->rx_buf_size) {
756                         BNX2X_ERR("skb_put is about to fail...  pad %d  len %d  rx_buf_size %d\n",
757                                   pad, len, fp->rx_buf_size);
758                         bnx2x_panic();
759                         return;
760                 }
761 #endif
762
763                 skb_reserve(skb, pad + NET_SKB_PAD);
764                 skb_put(skb, len);
765                 skb_set_hash(skb, tpa_info->rxhash, tpa_info->rxhash_type);
766
767                 skb->protocol = eth_type_trans(skb, bp->dev);
768                 skb->ip_summed = CHECKSUM_UNNECESSARY;
769
770                 if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages,
771                                          skb, cqe, cqe_idx)) {
772                         if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN)
773                                 __vlan_hwaccel_put_tag(skb,
774                                                        cpu_to_be16(ETH_P_8021Q),
775                                                        tpa_info->vlan_tag);
776                         bnx2x_gro_receive(bp, fp, skb);
777                 } else {
778                         DP(NETIF_MSG_RX_STATUS,
779                            "Failed to allocate new pages - dropping packet!\n");
780                         dev_kfree_skb_any(skb);
781                 }
782
783                 /* put new data in bin */
784                 rx_buf->data = new_data;
785
786                 return;
787         }
788         if (new_data)
789                 bnx2x_frag_free(fp, new_data);
790 drop:
791         /* drop the packet and keep the buffer in the bin */
792         DP(NETIF_MSG_RX_STATUS,
793            "Failed to allocate or map a new skb - dropping packet!\n");
794         bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++;
795 #endif
796 }
797
798 static int bnx2x_alloc_rx_data(struct bnx2x *bp, struct bnx2x_fastpath *fp,
799                                uint16_t index, gfp_t gfp_mask)
800 {
801         uint8_t *data;
802         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
803         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
804         dma_addr_t mapping;
805
806         data = bnx2x_frag_alloc(fp, gfp_mask);
807         if (unlikely(data == NULL))
808                 return -ENOMEM;
809
810         mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
811                                  fp->rx_buf_size,
812                                  DMA_FROM_DEVICE);
813         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
814                 bnx2x_frag_free(fp, data);
815                 BNX2X_ERR("Can't map rx data\n");
816                 return -ENOMEM;
817         }
818
819         rx_buf->data = data;
820         dma_unmap_addr_set(rx_buf, mapping, mapping);
821
822         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
823         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
824
825         return 0;
826 }
827
828 static
829 void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe,
830                                  struct bnx2x_fastpath *fp,
831                                  struct bnx2x_eth_q_stats *qstats)
832 {
833 panic("Not implemented");
834 #if 0 // AKAROS_PORT
835         /* Do nothing if no L4 csum validation was done.
836          * We do not check whether IP csum was validated. For IPv4 we assume
837          * that if the card got as far as validating the L4 csum, it also
838          * validated the IP csum. IPv6 has no IP csum.
839          */
840         if (cqe->fast_path_cqe.status_flags &
841             ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)
842                 return;
843
844         /* If L4 validation was done, check if an error was found. */
845
846         if (cqe->fast_path_cqe.type_error_flags &
847             (ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG |
848              ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
849                 qstats->hw_csum_err++;
850         else
851                 skb->ip_summed = CHECKSUM_UNNECESSARY;
852 #endif
853 }
854
855 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
856 {
857         struct bnx2x *bp = fp->bp;
858         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
859         uint16_t sw_comp_cons, sw_comp_prod;
860         int rx_pkt = 0;
861         union eth_rx_cqe *cqe;
862         struct eth_fast_path_rx_cqe *cqe_fp;
863
864         struct block *block;
865
866 #ifdef BNX2X_STOP_ON_ERROR
867         if (unlikely(bp->panic))
868                 return 0;
869 #endif
870         if (budget <= 0)
871                 return rx_pkt;
872
873         bd_cons = fp->rx_bd_cons;
874         bd_prod = fp->rx_bd_prod;
875         bd_prod_fw = bd_prod;
876         sw_comp_cons = fp->rx_comp_cons;
877         sw_comp_prod = fp->rx_comp_prod;
878
879         comp_ring_cons = RCQ_BD(sw_comp_cons);
880         cqe = &fp->rx_comp_ring[comp_ring_cons];
881         cqe_fp = &cqe->fast_path_cqe;
882
883         DP(NETIF_MSG_RX_STATUS,
884            "queue[%d]: sw_comp_cons %u\n", fp->index, sw_comp_cons);
885
886         while (BNX2X_IS_CQE_COMPLETED(cqe_fp)) {
887                 struct sw_rx_bd *rx_buf = NULL;
888                 uint8_t cqe_fp_flags;
889                 enum eth_rx_cqe_type cqe_fp_type;
890                 uint16_t len, pad, queue;
891                 uint8_t *data;
892                 uint32_t rxhash;
893
894 #ifdef BNX2X_STOP_ON_ERROR
895                 if (unlikely(bp->panic))
896                         return 0;
897 #endif
898
899                 bd_prod = RX_BD(bd_prod);
900                 bd_cons = RX_BD(bd_cons);
901
902                 /* A rmb() is required to ensure that the CQE is not read
903                  * before it is written by the adapter DMA.  PCI ordering
904                  * rules will make sure the other fields are written before
905                  * the marker at the end of struct eth_fast_path_rx_cqe
906                  * but without rmb() a weakly ordered processor can process
907                  * stale data.  Without the barrier TPA state-machine might
908                  * enter inconsistent state and kernel stack might be
909                  * provided with incorrect packet description - these lead
910                  * to various kernel crashed.
911                  */
912                 rmb();
913
914                 cqe_fp_flags = cqe_fp->type_error_flags;
915                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
916
917                 DP(NETIF_MSG_RX_STATUS,
918                    "CQE type %x  err %x  status %x  queue %x  vlan %x  len %u\n",
919                    CQE_TYPE(cqe_fp_flags),
920                    cqe_fp_flags, cqe_fp->status_flags,
921                    le32_to_cpu(cqe_fp->rss_hash_result),
922                    le16_to_cpu(cqe_fp->vlan_tag),
923                    le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len));
924
925                 /* is this a slowpath msg? */
926                 if (unlikely(CQE_TYPE_SLOW(cqe_fp_type))) {
927                         bnx2x_sp_event(fp, cqe);
928                         goto next_cqe;
929                 }
930
931                 rx_buf = &fp->rx_buf_ring[bd_cons];
932                 data = rx_buf->data;
933
934                 if (!CQE_TYPE_FAST(cqe_fp_type)) {
935                         struct bnx2x_agg_info *tpa_info;
936                         uint16_t frag_size, pages;
937 #ifdef BNX2X_STOP_ON_ERROR
938                         /* sanity check */
939                         if (fp->disable_tpa &&
940                             (CQE_TYPE_START(cqe_fp_type) ||
941                              CQE_TYPE_STOP(cqe_fp_type)))
942                                 BNX2X_ERR("START/STOP packet while disable_tpa type %x\n",
943                                           CQE_TYPE(cqe_fp_type));
944 #endif
945
946                         if (CQE_TYPE_START(cqe_fp_type)) {
947                                 uint16_t queue = cqe_fp->queue_index;
948                                 DP(NETIF_MSG_RX_STATUS,
949                                    "calling tpa_start on queue %d\n",
950                                    queue);
951
952                                 bnx2x_tpa_start(fp, queue,
953                                                 bd_cons, bd_prod,
954                                                 cqe_fp);
955
956                                 goto next_rx;
957                         }
958                         queue = cqe->end_agg_cqe.queue_index;
959                         tpa_info = &fp->tpa_info[queue];
960                         DP(NETIF_MSG_RX_STATUS,
961                            "calling tpa_stop on queue %d\n",
962                            queue);
963
964                         frag_size = le16_to_cpu(cqe->end_agg_cqe.pkt_len) -
965                                     tpa_info->len_on_bd;
966
967                         if (fp->mode == TPA_MODE_GRO)
968                                 pages = (frag_size + tpa_info->full_page - 1) /
969                                          tpa_info->full_page;
970                         else
971                                 pages = SGE_PAGE_ALIGN(frag_size) >>
972                                         SGE_PAGE_SHIFT;
973
974                         bnx2x_tpa_stop(bp, fp, tpa_info, pages,
975                                        &cqe->end_agg_cqe, comp_ring_cons);
976 #ifdef BNX2X_STOP_ON_ERROR
977                         if (bp->panic)
978                                 return 0;
979 #endif
980
981                         bnx2x_update_sge_prod(fp, pages, &cqe->end_agg_cqe);
982                         goto next_cqe;
983                 }
984                 /* non TPA */
985                 len = le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len);
986                 pad = cqe_fp->placement_offset;
987                 dma_sync_single_for_cpu(&bp->pdev->dev,
988                                         dma_unmap_addr(rx_buf, mapping),
989                                         pad + RX_COPY_THRESH,
990                                         DMA_FROM_DEVICE);
991                 pad += NET_SKB_PAD;
992                 prefetch(data + pad); /* speedup eth_type_trans() */
993                 /* is this an error packet? */
994                 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
995                         DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
996                            "ERROR  flags %x  rx packet %u\n",
997                            cqe_fp_flags, sw_comp_cons);
998                         bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++;
999                         goto reuse_rx;
1000                 }
1001
1002                 /* Since we don't have a jumbo ring
1003                  * copy small packets if mtu > 1500
1004                  */
1005                 /* TODO: AKAROS_PORT always copy out the packet for now. */
1006                 if (1) {
1007 //              if ((bp->dev->maxmtu > ETH_MAX_PACKET_SIZE) &&
1008 //                  (len <= RX_COPY_THRESH)) {
1009                         block = block_alloc(len, MEM_ATOMIC);
1010                         if (block == NULL) {
1011                                 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1012                                    "ERROR  packet dropped because of alloc failure\n");
1013                                 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1014                                 goto reuse_rx;
1015                         }
1016                         memcpy(block->wp, data + pad, len);
1017                         block->wp += len;
1018                         bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1019                 } else {
1020                         if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod,
1021                                                        0) == 0)) {
1022                                 dma_unmap_single(&bp->pdev->dev,
1023                                                  dma_unmap_addr(rx_buf, mapping),
1024                                                  fp->rx_buf_size,
1025                                                  DMA_FROM_DEVICE);
1026                                 /* TODO: block extra data here */
1027                                 panic("Extra-data not implemented");
1028                                 #if 0 // AKAROS_PORT
1029                                 skb = build_skb(data, fp->rx_frag_size);
1030                                 if (unlikely(!skb)) {
1031                                         bnx2x_frag_free(fp, data);
1032                                         bnx2x_fp_qstats(bp, fp)->
1033                                                         rx_skb_alloc_failed++;
1034                                         goto next_rx;
1035                                 }
1036                                 skb_reserve(skb, pad);
1037                                 #endif
1038                         } else {
1039                                 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1040                                    "ERROR  packet dropped because of alloc failure\n");
1041                                 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1042 reuse_rx:
1043                                 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1044                                 goto next_rx;
1045                         }
1046                 }
1047
1048                 // AKAROS_PORT TODO: set hash and checksum stuff
1049 #if 0
1050                 skb_put(skb, len);
1051                 skb->protocol = eth_type_trans(skb, bp->dev);
1052
1053                 /* Set Toeplitz hash for a none-LRO skb */
1054                 rxhash = bnx2x_get_rxhash(bp, cqe_fp, &rxhash_type);
1055                 skb_set_hash(skb, rxhash, rxhash_type);
1056
1057                 skb_checksum_none_assert(skb);
1058
1059                 if (bp->dev->feat & NETIF_F_RXCSUM)
1060                         bnx2x_csum_validate(skb, cqe, fp,
1061                                             bnx2x_fp_qstats(bp, fp));
1062
1063                 skb_record_rx_queue(skb, fp->rx_queue);
1064
1065                 if (le16_to_cpu(cqe_fp->pars_flags.flags) &
1066                     PARSING_FLAGS_VLAN)
1067                         __vlan_hwaccel_put_tag(skb, cpu_to_be16(ETH_P_8021Q),
1068                                                le16_to_cpu(cqe_fp->vlan_tag));
1069
1070                 skb_mark_napi_id(skb, &fp->napi);
1071
1072                 if (bnx2x_fp_ll_polling(fp))
1073                         netif_receive_skb(skb);
1074                 else
1075                         napi_gro_receive(&fp->napi, skb);
1076 #endif
1077                 etheriq(bp->edev, block, TRUE);
1078 next_rx:
1079                 rx_buf->data = NULL;
1080
1081                 bd_cons = NEXT_RX_IDX(bd_cons);
1082                 bd_prod = NEXT_RX_IDX(bd_prod);
1083                 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1084                 rx_pkt++;
1085 next_cqe:
1086                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1087                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1088
1089                 /* mark CQE as free */
1090                 BNX2X_SEED_CQE(cqe_fp);
1091
1092                 if (rx_pkt == budget)
1093                         break;
1094
1095                 comp_ring_cons = RCQ_BD(sw_comp_cons);
1096                 cqe = &fp->rx_comp_ring[comp_ring_cons];
1097                 cqe_fp = &cqe->fast_path_cqe;
1098         } /* while */
1099
1100         fp->rx_bd_cons = bd_cons;
1101         fp->rx_bd_prod = bd_prod_fw;
1102         fp->rx_comp_cons = sw_comp_cons;
1103         fp->rx_comp_prod = sw_comp_prod;
1104
1105         /* Update producers */
1106         bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1107                              fp->rx_sge_prod);
1108
1109         fp->rx_pkt += rx_pkt;
1110         fp->rx_calls++;
1111
1112         return rx_pkt;
1113 }
1114
1115 static void bnx2x_msix_fp_int(struct hw_trapframe *hw_tf, void *fp_cookie)
1116 {
1117         struct bnx2x_fastpath *fp = fp_cookie;
1118         struct bnx2x *bp = fp->bp;
1119         uint8_t cos;
1120
1121         DP(NETIF_MSG_INTR,
1122            "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
1123            fp->index, fp->fw_sb_id, fp->igu_sb_id);
1124
1125         bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1126
1127 #ifdef BNX2X_STOP_ON_ERROR
1128         if (unlikely(bp->panic))
1129                 return;
1130 #endif
1131
1132         /* Handle Rx and Tx according to MSI-X vector */
1133         for_each_cos_in_tx_queue(fp, cos)
1134                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1135
1136         prefetch(&fp->sb_running_index[SM_RX_ID]);
1137         // AKAROS_PORT
1138         send_kernel_message(core_id(), bnx2x_poll, (long)fp, 0, 0, KMSG_ROUTINE);
1139         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1140
1141         return;
1142 }
1143
1144 /* HW Lock for shared dual port PHYs */
1145 void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1146 {
1147         qlock(&bp->port.phy_mutex);
1148
1149         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1150 }
1151
1152 void bnx2x_release_phy_lock(struct bnx2x *bp)
1153 {
1154         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1155
1156         qunlock(&bp->port.phy_mutex);
1157 }
1158
1159 /* calculates MF speed according to current linespeed and MF configuration */
1160 uint16_t bnx2x_get_mf_speed(struct bnx2x *bp)
1161 {
1162         uint16_t line_speed = bp->link_vars.line_speed;
1163         if (IS_MF(bp)) {
1164                 uint16_t maxCfg = bnx2x_extract_max_cfg(bp,
1165                                                    bp->mf_config[BP_VN(bp)]);
1166
1167                 /* Calculate the current MAX line speed limit for the MF
1168                  * devices
1169                  */
1170                 if (IS_MF_SI(bp))
1171                         line_speed = (line_speed * maxCfg) / 100;
1172                 else { /* SD mode */
1173                         uint16_t vn_max_rate = maxCfg * 100;
1174
1175                         if (vn_max_rate < line_speed)
1176                                 line_speed = vn_max_rate;
1177                 }
1178         }
1179
1180         return line_speed;
1181 }
1182
1183 /**
1184  * bnx2x_fill_report_data - fill link report data to report
1185  *
1186  * @bp:         driver handle
1187  * @data:       link state to update
1188  *
1189  * It uses a none-atomic bit operations because is called under the mutex.
1190  */
1191 static void bnx2x_fill_report_data(struct bnx2x *bp,
1192                                    struct bnx2x_link_report_data *data)
1193 {
1194         memset(data, 0, sizeof(*data));
1195
1196         if (IS_PF(bp)) {
1197                 /* Fill the report data: effective line speed */
1198                 data->line_speed = bnx2x_get_mf_speed(bp);
1199
1200                 /* Link is down */
1201                 if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS))
1202                         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1203                                   &data->link_report_flags);
1204
1205                 if (!BNX2X_NUM_ETH_QUEUES(bp))
1206                         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1207                                   &data->link_report_flags);
1208
1209                 /* Full DUPLEX */
1210                 if (bp->link_vars.duplex == DUPLEX_FULL)
1211                         __set_bit(BNX2X_LINK_REPORT_FD,
1212                                   &data->link_report_flags);
1213
1214                 /* Rx Flow Control is ON */
1215                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX)
1216                         __set_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1217                                   &data->link_report_flags);
1218
1219                 /* Tx Flow Control is ON */
1220                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1221                         __set_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1222                                   &data->link_report_flags);
1223         } else { /* VF */
1224                 *data = bp->vf_link_vars;
1225         }
1226 }
1227
1228 /**
1229  * bnx2x_link_report - report link status to OS.
1230  *
1231  * @bp:         driver handle
1232  *
1233  * Calls the __bnx2x_link_report() under the same locking scheme
1234  * as a link/PHY state managing code to ensure a consistent link
1235  * reporting.
1236  */
1237
1238 void bnx2x_link_report(struct bnx2x *bp)
1239 {
1240         bnx2x_acquire_phy_lock(bp);
1241         __bnx2x_link_report(bp);
1242         bnx2x_release_phy_lock(bp);
1243 }
1244
1245 /**
1246  * __bnx2x_link_report - report link status to OS.
1247  *
1248  * @bp:         driver handle
1249  *
1250  * None atomic implementation.
1251  * Should be called under the phy_lock.
1252  */
1253 void __bnx2x_link_report(struct bnx2x *bp)
1254 {
1255         struct bnx2x_link_report_data cur_data;
1256
1257         /* reread mf_cfg */
1258         if (IS_PF(bp) && !CHIP_IS_E1(bp))
1259                 bnx2x_read_mf_cfg(bp);
1260
1261         /* Read the current link report info */
1262         bnx2x_fill_report_data(bp, &cur_data);
1263
1264         /* Don't report link down or exactly the same link status twice */
1265         if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) ||
1266             (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1267                       &bp->last_reported_link.link_report_flags) &&
1268              test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1269                       &cur_data.link_report_flags)))
1270                 return;
1271
1272         bp->link_cnt++;
1273
1274         /* We are going to report a new link parameters now -
1275          * remember the current data for the next time.
1276          */
1277         memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data));
1278
1279         /* propagate status to VFs */
1280         if (IS_PF(bp))
1281                 bnx2x_iov_link_update(bp);
1282
1283         if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1284                      &cur_data.link_report_flags)) {
1285                 netif_carrier_off(bp->dev);
1286                 netdev_err(bp->dev, "NIC Link is Down\n");
1287                 return;
1288         } else {
1289                 const char *duplex;
1290                 const char *flow;
1291
1292                 netif_carrier_on(bp->dev);
1293
1294                 if (test_and_clear_bit(BNX2X_LINK_REPORT_FD,
1295                                        &cur_data.link_report_flags))
1296                         duplex = "full";
1297                 else
1298                         duplex = "half";
1299
1300                 /* Handle the FC at the end so that only these flags would be
1301                  * possibly set. This way we may easily check if there is no FC
1302                  * enabled.
1303                  */
1304                 if (cur_data.link_report_flags) {
1305                         if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1306                                      &cur_data.link_report_flags)) {
1307                                 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1308                                      &cur_data.link_report_flags))
1309                                         flow = "ON - receive & transmit";
1310                                 else
1311                                         flow = "ON - receive";
1312                         } else {
1313                                 flow = "ON - transmit";
1314                         }
1315                 } else {
1316                         flow = "none";
1317                 }
1318                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
1319                             cur_data.line_speed, duplex, flow);
1320         }
1321 }
1322
1323 static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
1324 {
1325         int i;
1326
1327         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1328                 struct eth_rx_sge *sge;
1329
1330                 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
1331                 sge->addr_hi =
1332                         cpu_to_le32(U64_HI(fp->rx_sge_mapping +
1333                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1334
1335                 sge->addr_lo =
1336                         cpu_to_le32(U64_LO(fp->rx_sge_mapping +
1337                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1338         }
1339 }
1340
1341 static void bnx2x_free_tpa_pool(struct bnx2x *bp,
1342                                 struct bnx2x_fastpath *fp, int last)
1343 {
1344         int i;
1345
1346         for (i = 0; i < last; i++) {
1347                 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
1348                 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
1349                 uint8_t *data = first_buf->data;
1350
1351                 if (data == NULL) {
1352                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
1353                         continue;
1354                 }
1355                 if (tpa_info->tpa_state == BNX2X_TPA_START)
1356                         dma_unmap_single(&bp->pdev->dev,
1357                                          dma_unmap_addr(first_buf, mapping),
1358                                          fp->rx_buf_size, DMA_FROM_DEVICE);
1359                 bnx2x_frag_free(fp, data);
1360                 first_buf->data = NULL;
1361         }
1362 }
1363
1364 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
1365 {
1366         int j;
1367
1368         for_each_rx_queue_cnic(bp, j) {
1369                 struct bnx2x_fastpath *fp = &bp->fp[j];
1370
1371                 fp->rx_bd_cons = 0;
1372
1373                 /* Activate BD ring */
1374                 /* Warning!
1375                  * this will generate an interrupt (to the TSTORM)
1376                  * must only be done after chip is initialized
1377                  */
1378                 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1379                                      fp->rx_sge_prod);
1380         }
1381 }
1382
1383 void bnx2x_init_rx_rings(struct bnx2x *bp)
1384 {
1385         int func = BP_FUNC(bp);
1386         uint16_t ring_prod;
1387         int i, j;
1388
1389         /* Allocate TPA resources */
1390         for_each_eth_queue(bp, j) {
1391                 struct bnx2x_fastpath *fp = &bp->fp[j];
1392
1393                 DP(NETIF_MSG_IFUP,
1394                    "mtu %d  rx_buf_size %d\n", bp->dev->maxmtu, fp->rx_buf_size);
1395
1396                 if (!fp->disable_tpa) {
1397                         /* Fill the per-aggregation pool */
1398                         for (i = 0; i < MAX_AGG_QS(bp); i++) {
1399                                 struct bnx2x_agg_info *tpa_info =
1400                                         &fp->tpa_info[i];
1401                                 struct sw_rx_bd *first_buf =
1402                                         &tpa_info->first_buf;
1403
1404                                 first_buf->data =
1405                                         bnx2x_frag_alloc(fp, MEM_WAIT);
1406                                 if (!first_buf->data) {
1407                                         BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n",
1408                                                   j);
1409                                         bnx2x_free_tpa_pool(bp, fp, i);
1410                                         fp->disable_tpa = 1;
1411                                         break;
1412                                 }
1413                                 dma_unmap_addr_set(first_buf, mapping, 0);
1414                                 tpa_info->tpa_state = BNX2X_TPA_STOP;
1415                         }
1416
1417                         /* "next page" elements initialization */
1418                         bnx2x_set_next_page_sgl(fp);
1419
1420                         /* set SGEs bit mask */
1421                         bnx2x_init_sge_ring_bit_mask(fp);
1422
1423                         /* Allocate SGEs and initialize the ring elements */
1424                         for (i = 0, ring_prod = 0;
1425                              i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
1426
1427                                 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod,
1428                                                        MEM_WAIT) < 0) {
1429                                         BNX2X_ERR("was only able to allocate %d rx sges\n",
1430                                                   i);
1431                                         BNX2X_ERR("disabling TPA for queue[%d]\n",
1432                                                   j);
1433                                         /* Cleanup already allocated elements */
1434                                         bnx2x_free_rx_sge_range(bp, fp,
1435                                                                 ring_prod);
1436                                         bnx2x_free_tpa_pool(bp, fp,
1437                                                             MAX_AGG_QS(bp));
1438                                         fp->disable_tpa = 1;
1439                                         ring_prod = 0;
1440                                         break;
1441                                 }
1442                                 ring_prod = NEXT_SGE_IDX(ring_prod);
1443                         }
1444
1445                         fp->rx_sge_prod = ring_prod;
1446                 }
1447         }
1448
1449         for_each_eth_queue(bp, j) {
1450                 struct bnx2x_fastpath *fp = &bp->fp[j];
1451
1452                 fp->rx_bd_cons = 0;
1453
1454                 /* Activate BD ring */
1455                 /* Warning!
1456                  * this will generate an interrupt (to the TSTORM)
1457                  * must only be done after chip is initialized
1458                  */
1459                 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1460                                      fp->rx_sge_prod);
1461
1462                 if (j != 0)
1463                         continue;
1464
1465                 if (CHIP_IS_E1(bp)) {
1466                         REG_WR(bp, BAR_USTRORM_INTMEM +
1467                                USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
1468                                U64_LO(fp->rx_comp_mapping));
1469                         REG_WR(bp, BAR_USTRORM_INTMEM +
1470                                USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
1471                                U64_HI(fp->rx_comp_mapping));
1472                 }
1473         }
1474 }
1475
1476 static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp)
1477 {
1478 panic("Not implemented");
1479 #if 0 // AKAROS_PORT
1480         uint8_t cos;
1481         struct bnx2x *bp = fp->bp;
1482
1483         for_each_cos_in_tx_queue(fp, cos) {
1484                 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1485                 unsigned pkts_compl = 0, bytes_compl = 0;
1486
1487                 uint16_t sw_prod = txdata->tx_pkt_prod;
1488                 uint16_t sw_cons = txdata->tx_pkt_cons;
1489
1490                 while (sw_cons != sw_prod) {
1491                         bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
1492                                           &pkts_compl, &bytes_compl);
1493                         sw_cons++;
1494                 }
1495
1496                 netdev_tx_reset_queue(
1497                         netdev_get_tx_queue(bp->dev,
1498                                             txdata->txq_index));
1499         }
1500 #endif
1501 }
1502
1503 static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp)
1504 {
1505         int i;
1506
1507         for_each_tx_queue_cnic(bp, i) {
1508                 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1509         }
1510 }
1511
1512 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
1513 {
1514         int i;
1515
1516         for_each_eth_queue(bp, i) {
1517                 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1518         }
1519 }
1520
1521 static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp)
1522 {
1523         struct bnx2x *bp = fp->bp;
1524         int i;
1525
1526         /* ring wasn't allocated */
1527         if (fp->rx_buf_ring == NULL)
1528                 return;
1529
1530         for (i = 0; i < NUM_RX_BD; i++) {
1531                 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
1532                 uint8_t *data = rx_buf->data;
1533
1534                 if (data == NULL)
1535                         continue;
1536                 dma_unmap_single(&bp->pdev->dev,
1537                                  dma_unmap_addr(rx_buf, mapping),
1538                                  fp->rx_buf_size, DMA_FROM_DEVICE);
1539
1540                 rx_buf->data = NULL;
1541                 bnx2x_frag_free(fp, data);
1542         }
1543 }
1544
1545 static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp)
1546 {
1547         int j;
1548
1549         for_each_rx_queue_cnic(bp, j) {
1550                 bnx2x_free_rx_bds(&bp->fp[j]);
1551         }
1552 }
1553
1554 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
1555 {
1556         int j;
1557
1558         for_each_eth_queue(bp, j) {
1559                 struct bnx2x_fastpath *fp = &bp->fp[j];
1560
1561                 bnx2x_free_rx_bds(fp);
1562
1563                 if (!fp->disable_tpa)
1564                         bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
1565         }
1566 }
1567
1568 static void bnx2x_free_skbs_cnic(struct bnx2x *bp)
1569 {
1570         bnx2x_free_tx_skbs_cnic(bp);
1571         bnx2x_free_rx_skbs_cnic(bp);
1572 }
1573
1574 void bnx2x_free_skbs(struct bnx2x *bp)
1575 {
1576         bnx2x_free_tx_skbs(bp);
1577         bnx2x_free_rx_skbs(bp);
1578 }
1579
1580 void bnx2x_update_max_mf_config(struct bnx2x *bp, uint32_t value)
1581 {
1582         /* load old values */
1583         uint32_t mf_cfg = bp->mf_config[BP_VN(bp)];
1584
1585         if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
1586                 /* leave all but MAX value */
1587                 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
1588
1589                 /* set new MAX value */
1590                 mf_cfg |= (value << FUNC_MF_CFG_MAX_BW_SHIFT)
1591                                 & FUNC_MF_CFG_MAX_BW_MASK;
1592
1593                 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
1594         }
1595 }
1596
1597 /**
1598  * bnx2x_free_msix_irqs - free previously requested MSI-X IRQ vectors
1599  *
1600  * @bp:         driver handle
1601  * @nvecs:      number of vectors to be released
1602  */
1603 static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
1604 {
1605 panic("Not implemented");
1606 #if 0 // AKAROS_PORT
1607         int i, offset = 0;
1608
1609         if (nvecs == offset)
1610                 return;
1611
1612         /* VFs don't have a default SB */
1613         if (IS_PF(bp)) {
1614                 free_irq(bp->msix_table[offset].vector, bp->dev);
1615                 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
1616                    bp->msix_table[offset].vector);
1617                 offset++;
1618         }
1619
1620         if (CNIC_SUPPORT(bp)) {
1621                 if (nvecs == offset)
1622                         return;
1623                 offset++;
1624         }
1625
1626         for_each_eth_queue(bp, i) {
1627                 if (nvecs == offset)
1628                         return;
1629                 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n",
1630                    i, bp->msix_table[offset].vector);
1631
1632                 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
1633         }
1634 #endif
1635 }
1636
1637 void bnx2x_free_irq(struct bnx2x *bp)
1638 {
1639 panic("Not implemented");
1640 #if 0 // AKAROS_PORT
1641         if (bp->flags & USING_MSIX_FLAG &&
1642             !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1643                 int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp);
1644
1645                 /* vfs don't have a default status block */
1646                 if (IS_PF(bp))
1647                         nvecs++;
1648
1649                 bnx2x_free_msix_irqs(bp, nvecs);
1650         } else {
1651                 free_irq(bp->dev->irq, bp->dev);
1652         }
1653 #endif
1654 }
1655
1656 int bnx2x_enable_msix(struct bnx2x *bp)
1657 {
1658         int msix_vec = 0, i, rc;
1659 panic("Not implemented");
1660 #if 0 // AKAROS_PORT
1661         /* VFs don't have a default status block */
1662         if (IS_PF(bp)) {
1663                 bp->msix_table[msix_vec].entry = msix_vec;
1664                 BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n",
1665                                bp->msix_table[0].entry);
1666                 msix_vec++;
1667         }
1668
1669         /* Cnic requires an msix vector for itself */
1670         if (CNIC_SUPPORT(bp)) {
1671                 bp->msix_table[msix_vec].entry = msix_vec;
1672                 BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n",
1673                                msix_vec, bp->msix_table[msix_vec].entry);
1674                 msix_vec++;
1675         }
1676
1677         /* We need separate vectors for ETH queues only (not FCoE) */
1678         for_each_eth_queue(bp, i) {
1679                 bp->msix_table[msix_vec].entry = msix_vec;
1680                 BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n",
1681                                msix_vec, msix_vec, i);
1682                 msix_vec++;
1683         }
1684
1685         DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n",
1686            msix_vec);
1687
1688         rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0],
1689                                    BNX2X_MIN_MSIX_VEC_CNT(bp), msix_vec);
1690         /*
1691          * reconfigure number of tx/rx queues according to available
1692          * MSI-X vectors
1693          */
1694         if (rc == -ENOSPC) {
1695                 /* Get by with single vector */
1696                 rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0], 1, 1);
1697                 if (rc < 0) {
1698                         BNX2X_DEV_INFO("Single MSI-X is not attainable rc %d\n",
1699                                        rc);
1700                         goto no_msix;
1701                 }
1702
1703                 BNX2X_DEV_INFO("Using single MSI-X vector\n");
1704                 bp->flags |= USING_SINGLE_MSIX_FLAG;
1705
1706                 BNX2X_DEV_INFO("set number of queues to 1\n");
1707                 bp->num_ethernet_queues = 1;
1708                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1709         } else if (rc < 0) {
1710                 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1711                 goto no_msix;
1712         } else if (rc < msix_vec) {
1713                 /* how less vectors we will have? */
1714                 int diff = msix_vec - rc;
1715
1716                 BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc);
1717
1718                 /*
1719                  * decrease number of queues by number of unallocated entries
1720                  */
1721                 bp->num_ethernet_queues -= diff;
1722                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1723
1724                 BNX2X_DEV_INFO("New queue configuration set: %d\n",
1725                                bp->num_queues);
1726         }
1727
1728         bp->flags |= USING_MSIX_FLAG;
1729
1730         return 0;
1731
1732 no_msix:
1733         /* fall to INTx if not enough memory */
1734         if (rc == -ENOMEM)
1735                 bp->flags |= DISABLE_MSI_FLAG;
1736
1737         return rc;
1738 #endif
1739 }
1740
1741 static void bullshit_handler(struct hw_trapframe *hw_tf, void *cnic_turd)
1742 {
1743         printk("bnx2x CNIC IRQ fired.  Probably a bug!\n");
1744 }
1745
1746 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1747 {
1748         int i, rc, offset = 0;
1749
1750         /* no default status block for vf */
1751         if (IS_PF(bp)) {
1752                 rc = register_irq(bp->msix_table[offset++].vector,
1753                                   bnx2x_msix_sp_int, bp->dev,
1754                                   pci_to_tbdf(bp->pdev));
1755                 if (rc) {
1756                         BNX2X_ERR("request sp irq failed\n");
1757                         return -EBUSY;
1758                 }
1759         }
1760
1761         if (CNIC_SUPPORT(bp)) {
1762                 offset++;
1763                 // AKAROS_PORT
1764                 rc = register_irq(0, bullshit_handler, 0, pci_to_tbdf(bp->pdev));
1765                 if (rc) {
1766                         BNX2X_ERR("Fucked up getting a CNIC MSIX vector!");
1767                         return -EBUSY;
1768                 }
1769         }
1770
1771         for_each_eth_queue(bp, i) {
1772                 struct bnx2x_fastpath *fp = &bp->fp[i];
1773                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1774                          bp->dev->name, i);
1775
1776                 rc = register_irq(bp->msix_table[offset].vector,
1777                                   bnx2x_msix_fp_int, fp, pci_to_tbdf(bp->pdev));
1778                 if (rc) {
1779                         BNX2X_ERR("request fp #%d irq (%d) failed  rc %d\n", i,
1780                               bp->msix_table[offset].vector, rc);
1781                         bnx2x_free_msix_irqs(bp, offset);
1782                         return -EBUSY;
1783                 }
1784
1785                 offset++;
1786         }
1787
1788         i = BNX2X_NUM_ETH_QUEUES(bp);
1789         if (IS_PF(bp)) {
1790                 offset = 1 + CNIC_SUPPORT(bp);
1791                 netdev_info(bp->dev,
1792                             "using MSI-X  IRQs: sp %d  fp[%d] %d ... fp[%d] %d\n",
1793                             bp->msix_table[0].vector,
1794                             0, bp->msix_table[offset].vector,
1795                             i - 1, bp->msix_table[offset + i - 1].vector);
1796         } else {
1797                 offset = CNIC_SUPPORT(bp);
1798                 netdev_info(bp->dev,
1799                             "using MSI-X  IRQs: fp[%d] %d ... fp[%d] %d\n",
1800                             0, bp->msix_table[offset].vector,
1801                             i - 1, bp->msix_table[offset + i - 1].vector);
1802         }
1803         return 0;
1804 }
1805
1806 int bnx2x_enable_msi(struct bnx2x *bp)
1807 {
1808 panic("Not implemented");
1809 #if 0 // AKAROS_PORT
1810         int rc;
1811
1812         rc = pci_enable_msi(bp->pdev);
1813         if (rc) {
1814                 BNX2X_DEV_INFO("MSI is not attainable\n");
1815                 return -1;
1816         }
1817         bp->flags |= USING_MSI_FLAG;
1818
1819         return 0;
1820 #endif
1821 }
1822
1823 static int bnx2x_req_irq(struct bnx2x *bp)
1824 {
1825         unsigned long flags;
1826 panic("Not implemented");
1827 #if 0 // AKAROS_PORT
1828         unsigned int irq;
1829
1830         if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG))
1831                 flags = 0;
1832         else
1833                 flags = IRQF_SHARED;
1834
1835         if (bp->flags & USING_MSIX_FLAG)
1836                 irq = bp->msix_table[0].vector;
1837         else
1838                 irq = bp->pdev->irq;
1839
1840         return register_irq(irq, bnx2x_interrupt, bp->dev,
1841                             pci_to_tbdf(bp->pdev));
1842 #endif
1843 }
1844
1845 static int bnx2x_setup_irqs(struct bnx2x *bp)
1846 {
1847         return bnx2x_req_msix_irqs(bp);
1848 #if 0 // AKAROS_PORT we just register_irq
1849         if (bp->flags & USING_MSIX_FLAG &&
1850             !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1851                 rc = bnx2x_req_msix_irqs(bp);
1852                 if (rc)
1853                         return rc;
1854         } else {
1855                 rc = bnx2x_req_irq(bp);
1856                 if (rc) {
1857                         BNX2X_ERR("IRQ request failed  rc %d, aborting\n", rc);
1858                         return rc;
1859                 }
1860                 if (bp->flags & USING_MSI_FLAG) {
1861                         bp->dev->irq = bp->pdev->irq;
1862                         netdev_info(bp->dev, "using MSI IRQ %d\n",
1863                                     bp->dev->irq);
1864                 }
1865                 if (bp->flags & USING_MSIX_FLAG) {
1866                         bp->dev->irq = bp->msix_table[0].vector;
1867                         netdev_info(bp->dev, "using MSIX IRQ %d\n",
1868                                     bp->dev->irq);
1869                 }
1870         }
1871
1872         return 0;
1873 #endif
1874 }
1875
1876 static void bnx2x_napi_enable_cnic(struct bnx2x *bp)
1877 {
1878         int i;
1879
1880         for_each_rx_queue_cnic(bp, i) {
1881                 bnx2x_fp_init_lock(&bp->fp[i]);
1882                 napi_enable(&bnx2x_fp(bp, i, napi));
1883         }
1884 }
1885
1886 static void bnx2x_napi_enable(struct bnx2x *bp)
1887 {
1888         int i;
1889
1890         for_each_eth_queue(bp, i) {
1891                 bnx2x_fp_init_lock(&bp->fp[i]);
1892                 napi_enable(&bnx2x_fp(bp, i, napi));
1893         }
1894 }
1895
1896 static void bnx2x_napi_disable_cnic(struct bnx2x *bp)
1897 {
1898         int i;
1899
1900         for_each_rx_queue_cnic(bp, i) {
1901                 napi_disable(&bnx2x_fp(bp, i, napi));
1902                 while (!bnx2x_fp_ll_disable(&bp->fp[i]))
1903                         kthread_usleep(1000);
1904         }
1905 }
1906
1907 static void bnx2x_napi_disable(struct bnx2x *bp)
1908 {
1909         int i;
1910
1911         for_each_eth_queue(bp, i) {
1912                 napi_disable(&bnx2x_fp(bp, i, napi));
1913                 while (!bnx2x_fp_ll_disable(&bp->fp[i]))
1914                         kthread_usleep(1000);
1915         }
1916 }
1917
1918 void bnx2x_netif_start(struct bnx2x *bp)
1919 {
1920 panic("Not implemented");
1921 #if 0 // AKAROS_PORT
1922         if (netif_running(bp->dev)) {
1923                 bnx2x_napi_enable(bp);
1924                 if (CNIC_LOADED(bp))
1925                         bnx2x_napi_enable_cnic(bp);
1926                 bnx2x_int_enable(bp);
1927                 if (bp->state == BNX2X_STATE_OPEN)
1928                         netif_tx_wake_all_queues(bp->dev);
1929         }
1930 #endif
1931 }
1932
1933 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
1934 {
1935         bnx2x_int_disable_sync(bp, disable_hw);
1936         bnx2x_napi_disable(bp);
1937         if (CNIC_LOADED(bp))
1938                 bnx2x_napi_disable_cnic(bp);
1939 }
1940
1941 uint16_t bnx2x_select_queue(struct ether *dev, struct sk_buff *skb,
1942                        void *accel_priv, select_queue_fallback_t fallback)
1943 {
1944 panic("Not implemented");
1945 #if 0 // AKAROS_PORT
1946         struct bnx2x *bp = netdev_priv(dev);
1947
1948         if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
1949                 struct ethhdr *hdr = (struct ethhdr *)skb->data;
1950                 uint16_t ether_type = be16_to_cpu(hdr->h_proto);
1951
1952                 /* Skip VLAN tag if present */
1953                 if (ether_type == ETH_P_8021Q) {
1954                         struct vlan_ethhdr *vhdr =
1955                                 (struct vlan_ethhdr *)skb->data;
1956
1957                         ether_type = be16_to_cpu(vhdr->h_vlan_encapsulated_proto);
1958                 }
1959
1960                 /* If ethertype is FCoE or FIP - use FCoE ring */
1961                 if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP))
1962                         return bnx2x_fcoe_tx(bp, txq_index);
1963         }
1964
1965         /* select a non-FCoE queue */
1966         return fallback(dev, skb) % BNX2X_NUM_ETH_QUEUES(bp);
1967 #endif
1968 }
1969
1970 void bnx2x_set_num_queues(struct bnx2x *bp)
1971 {
1972         /* RSS queues */
1973         bp->num_ethernet_queues = bnx2x_calc_num_queues(bp);
1974
1975         /* override in STORAGE SD modes */
1976         if (IS_MF_STORAGE_ONLY(bp))
1977                 bp->num_ethernet_queues = 1;
1978
1979         /* Add special queues */
1980         bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */
1981         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1982
1983         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
1984 }
1985
1986 /**
1987  * bnx2x_set_real_num_queues - configure netdev->real_num_[tx,rx]_queues
1988  *
1989  * @bp:         Driver handle
1990  *
1991  * We currently support for at most 16 Tx queues for each CoS thus we will
1992  * allocate a multiple of 16 for ETH L2 rings according to the value of the
1993  * bp->max_cos.
1994  *
1995  * If there is an FCoE L2 queue the appropriate Tx queue will have the next
1996  * index after all ETH L2 indices.
1997  *
1998  * If the actual number of Tx queues (for each CoS) is less than 16 then there
1999  * will be the holes at the end of each group of 16 ETh L2 indices (0..15,
2000  * 16..31,...) with indices that are not coupled with any real Tx queue.
2001  *
2002  * The proper configuration of skb->queue_mapping is handled by
2003  * bnx2x_select_queue() and __skb_tx_hash().
2004  *
2005  * bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash()
2006  * will return a proper Tx index if TC is enabled (netdev->num_tc > 0).
2007  */
2008 static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic)
2009 {
2010         int rc, tx, rx;
2011
2012         tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos;
2013         rx = BNX2X_NUM_ETH_QUEUES(bp);
2014
2015 /* account for fcoe queue */
2016         if (include_cnic && !NO_FCOE(bp)) {
2017                 rx++;
2018                 tx++;
2019         }
2020
2021 #if 0 // AKAROS_PORT XME: set queues in ether
2022         rc = netif_set_real_num_tx_queues(bp->dev, tx);
2023         if (rc) {
2024                 BNX2X_ERR("Failed to set real number of Tx queues: %d\n", rc);
2025                 return rc;
2026         }
2027         rc = netif_set_real_num_rx_queues(bp->dev, rx);
2028         if (rc) {
2029                 BNX2X_ERR("Failed to set real number of Rx queues: %d\n", rc);
2030                 return rc;
2031         }
2032 #else
2033         rc = 0;
2034 #endif
2035
2036         DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n",
2037                           tx, rx);
2038
2039         return rc;
2040 }
2041
2042 static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
2043 {
2044         int i;
2045
2046         for_each_queue(bp, i) {
2047                 struct bnx2x_fastpath *fp = &bp->fp[i];
2048                 uint32_t mtu;
2049
2050                 /* Always use a mini-jumbo MTU for the FCoE L2 ring */
2051                 if (IS_FCOE_IDX(i))
2052                         /*
2053                          * Although there are no IP frames expected to arrive to
2054                          * this ring we still want to add an
2055                          * IP_HEADER_ALIGNMENT_PADDING to prevent a buffer
2056                          * overrun attack.
2057                          */
2058                         mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2059                 else
2060                         mtu = bp->dev->maxmtu;
2061                 /* AKAROS_PORT XME struct block alignment and size issues? */
2062                 fp->rx_buf_size = BNX2X_FW_RX_ALIGN_START +
2063                                   IP_HEADER_ALIGNMENT_PADDING +
2064                                   ETH_OVREHEAD +
2065                                   mtu +
2066                                   BNX2X_FW_RX_ALIGN_END;
2067                 /* Note : rx_buf_size doesn't take into account NET_SKB_PAD */
2068                 if (fp->rx_buf_size + NET_SKB_PAD <= PAGE_SIZE)
2069                         fp->rx_frag_size = fp->rx_buf_size + NET_SKB_PAD;
2070                 else
2071                         fp->rx_frag_size = 0;
2072         }
2073 }
2074
2075 static int bnx2x_init_rss(struct bnx2x *bp)
2076 {
2077         int i;
2078         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2079
2080         /* Prepare the initial contents for the indirection table if RSS is
2081          * enabled
2082          */
2083         for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++)
2084                 bp->rss_conf_obj.ind_table[i] =
2085                         bp->fp->cl_id +
2086                         ethtool_rxfh_indir_default(i, num_eth_queues);
2087
2088         /*
2089          * For 57710 and 57711 SEARCHER configuration (rss_keys) is
2090          * per-port, so if explicit configuration is needed , do it only
2091          * for a PMF.
2092          *
2093          * For 57712 and newer on the other hand it's a per-function
2094          * configuration.
2095          */
2096         return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp));
2097 }
2098
2099 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
2100               bool config_hash, bool enable)
2101 {
2102         struct bnx2x_config_rss_params params = {NULL};
2103
2104         /* Although RSS is meaningless when there is a single HW queue we
2105          * still need it enabled in order to have HW Rx hash generated.
2106          *
2107          * if (!is_eth_multi(bp))
2108          *      bp->multi_mode = ETH_RSS_MODE_DISABLED;
2109          */
2110
2111         params.rss_obj = rss_obj;
2112
2113         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2114
2115         if (enable) {
2116                 __set_bit(BNX2X_RSS_MODE_REGULAR, &params.rss_flags);
2117
2118                 /* RSS configuration */
2119                 __set_bit(BNX2X_RSS_IPV4, &params.rss_flags);
2120                 __set_bit(BNX2X_RSS_IPV4_TCP, &params.rss_flags);
2121                 __set_bit(BNX2X_RSS_IPV6, &params.rss_flags);
2122                 __set_bit(BNX2X_RSS_IPV6_TCP, &params.rss_flags);
2123                 if (rss_obj->udp_rss_v4)
2124                         __set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags);
2125                 if (rss_obj->udp_rss_v6)
2126                         __set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);
2127
2128                 if (!CHIP_IS_E1x(bp))
2129                         /* valid only for TUNN_MODE_GRE tunnel mode */
2130                         __set_bit(BNX2X_RSS_GRE_INNER_HDRS, &params.rss_flags);
2131         } else {
2132                 __set_bit(BNX2X_RSS_MODE_DISABLED, &params.rss_flags);
2133         }
2134
2135         /* Hash bits */
2136         params.rss_result_mask = MULTI_MASK;
2137
2138         memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
2139
2140         if (config_hash) {
2141                 /* RSS keys */
2142                 #if 0 // AKAROS_PORT
2143                 netdev_rss_key_fill(params.rss_key, T_ETH_RSS_KEY * 4);
2144                 #else
2145                 /* linux picks a random, once, then uses it here.  it could be 5a! */
2146                 memset(params.rss_key, 0x5a, T_ETH_RSS_KEY * 4);
2147                 #endif
2148                 __set_bit(BNX2X_RSS_SET_SRCH, &params.rss_flags);
2149         }
2150
2151         if (IS_PF(bp))
2152                 return bnx2x_config_rss(bp, &params);
2153         else
2154                 return bnx2x_vfpf_config_rss(bp, &params);
2155 }
2156
2157 static int bnx2x_init_hw(struct bnx2x *bp, uint32_t load_code)
2158 {
2159         struct bnx2x_func_state_params func_params = {NULL};
2160
2161         /* Prepare parameters for function state transitions */
2162         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
2163
2164         func_params.f_obj = &bp->func_obj;
2165         func_params.cmd = BNX2X_F_CMD_HW_INIT;
2166
2167         func_params.params.hw_init.load_phase = load_code;
2168
2169         return bnx2x_func_state_change(bp, &func_params);
2170 }
2171
2172 /*
2173  * Cleans the object that have internal lists without sending
2174  * ramrods. Should be run when interrupts are disabled.
2175  */
2176 void bnx2x_squeeze_objects(struct bnx2x *bp)
2177 {
2178         int rc;
2179         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
2180         struct bnx2x_mcast_ramrod_params rparam = {NULL};
2181         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
2182
2183         /***************** Cleanup MACs' object first *************************/
2184
2185         /* Wait for completion of requested */
2186         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2187         /* Perform a dry cleanup */
2188         __set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
2189
2190         /* Clean ETH primary MAC */
2191         __set_bit(BNX2X_ETH_MAC, &vlan_mac_flags);
2192         rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags,
2193                                  &ramrod_flags);
2194         if (rc != 0)
2195                 BNX2X_ERR("Failed to clean ETH MACs: %d\n", rc);
2196
2197         /* Cleanup UC list */
2198         vlan_mac_flags = 0;
2199         __set_bit(BNX2X_UC_LIST_MAC, &vlan_mac_flags);
2200         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags,
2201                                  &ramrod_flags);
2202         if (rc != 0)
2203                 BNX2X_ERR("Failed to clean UC list MACs: %d\n", rc);
2204
2205         /***************** Now clean mcast object *****************************/
2206         rparam.mcast_obj = &bp->mcast_obj;
2207         __set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
2208
2209         /* Add a DEL command... - Since we're doing a driver cleanup only,
2210          * we take a lock surrounding both the initial send and the CONTs,
2211          * as we don't want a true completion to disrupt us in the middle.
2212          */
2213         qlock(&bp->dev->qlock);
2214         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
2215         if (rc < 0)
2216                 BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n",
2217                           rc);
2218
2219         /* ...and wait until all pending commands are cleared */
2220         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2221         while (rc != 0) {
2222                 if (rc < 0) {
2223                         BNX2X_ERR("Failed to clean multi-cast object: %d\n",
2224                                   rc);
2225                         qunlock(&bp->dev->qlock);
2226                         return;
2227                 }
2228
2229                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2230         }
2231         qunlock(&bp->dev->qlock);
2232 }
2233
2234 #ifndef BNX2X_STOP_ON_ERROR
2235 #define LOAD_ERROR_EXIT(bp, label) \
2236         do { \
2237                 (bp)->state = BNX2X_STATE_ERROR; \
2238                 goto label; \
2239         } while (0)
2240
2241 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2242         do { \
2243                 bp->cnic_loaded = false; \
2244                 goto label; \
2245         } while (0)
2246 #else /*BNX2X_STOP_ON_ERROR*/
2247 #define LOAD_ERROR_EXIT(bp, label) \
2248         do { \
2249                 (bp)->state = BNX2X_STATE_ERROR; \
2250                 (bp)->panic = 1; \
2251                 return -EBUSY; \
2252         } while (0)
2253 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2254         do { \
2255                 bp->cnic_loaded = false; \
2256                 (bp)->panic = 1; \
2257                 return -EBUSY; \
2258         } while (0)
2259 #endif /*BNX2X_STOP_ON_ERROR*/
2260
2261 static void bnx2x_free_fw_stats_mem(struct bnx2x *bp)
2262 {
2263         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
2264                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2265         return;
2266 }
2267
2268 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
2269 {
2270         int num_groups, vf_headroom = 0;
2271         int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
2272
2273         /* number of queues for statistics is number of eth queues + FCoE */
2274         uint8_t num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
2275
2276         /* Total number of FW statistics requests =
2277          * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper
2278          * and fcoe l2 queue) stats + num of queues (which includes another 1
2279          * for fcoe l2 queue if applicable)
2280          */
2281         bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
2282
2283         /* vf stats appear in the request list, but their data is allocated by
2284          * the VFs themselves. We don't include them in the bp->fw_stats_num as
2285          * it is used to determine where to place the vf stats queries in the
2286          * request struct
2287          */
2288         if (IS_SRIOV(bp))
2289                 vf_headroom = bnx2x_vf_headroom(bp);
2290
2291         /* Request is built from stats_query_header and an array of
2292          * stats_query_cmd_group each of which contains
2293          * STATS_QUERY_CMD_COUNT rules. The real number or requests is
2294          * configured in the stats_query_header.
2295          */
2296         num_groups =
2297                 (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +
2298                  (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?
2299                  1 : 0));
2300
2301         DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n",
2302            bp->fw_stats_num, vf_headroom, num_groups);
2303         bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
2304                 num_groups * sizeof(struct stats_query_cmd_group);
2305
2306         /* Data for statistics requests + stats_counter
2307          * stats_counter holds per-STORM counters that are incremented
2308          * when STORM has finished with the current request.
2309          * memory for FCoE offloaded statistics are counted anyway,
2310          * even if they will not be sent.
2311          * VF stats are not accounted for here as the data of VF stats is stored
2312          * in memory allocated by the VF, not here.
2313          */
2314         bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
2315                 sizeof(struct per_pf_stats) +
2316                 sizeof(struct fcoe_statistics_params) +
2317                 sizeof(struct per_queue_stats) * num_queue_stats +
2318                 sizeof(struct stats_counter);
2319
2320         bp->fw_stats = BNX2X_PCI_ALLOC(&bp->fw_stats_mapping,
2321                                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2322         if (!bp->fw_stats)
2323                 goto alloc_mem_err;
2324
2325         /* Set shortcuts */
2326         bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
2327         bp->fw_stats_req_mapping = bp->fw_stats_mapping;
2328         bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
2329                 ((uint8_t *)bp->fw_stats + bp->fw_stats_req_sz);
2330         bp->fw_stats_data_mapping = bp->fw_stats_mapping +
2331                 bp->fw_stats_req_sz;
2332
2333         DP(BNX2X_MSG_SP, "statistics request base address set to %x %x\n",
2334            U64_HI(bp->fw_stats_req_mapping),
2335            U64_LO(bp->fw_stats_req_mapping));
2336         DP(BNX2X_MSG_SP, "statistics data base address set to %x %x\n",
2337            U64_HI(bp->fw_stats_data_mapping),
2338            U64_LO(bp->fw_stats_data_mapping));
2339         return 0;
2340
2341 alloc_mem_err:
2342         bnx2x_free_fw_stats_mem(bp);
2343         BNX2X_ERR("Can't allocate FW stats memory\n");
2344         return -ENOMEM;
2345 }
2346
2347 /* send load request to mcp and analyze response */
2348 static int bnx2x_nic_load_request(struct bnx2x *bp, uint32_t *load_code)
2349 {
2350         uint32_t param;
2351
2352         /* init fw_seq */
2353         bp->fw_seq =
2354                 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
2355                  DRV_MSG_SEQ_NUMBER_MASK);
2356         BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
2357
2358         /* Get current FW pulse sequence */
2359         bp->fw_drv_pulse_wr_seq =
2360                 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) &
2361                  DRV_PULSE_SEQ_MASK);
2362         BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
2363
2364         param = DRV_MSG_CODE_LOAD_REQ_WITH_LFA;
2365
2366         if (IS_MF_SD(bp) && bnx2x_port_after_undi(bp))
2367                 param |= DRV_MSG_CODE_LOAD_REQ_FORCE_LFA;
2368
2369         /* load request */
2370         (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, param);
2371
2372         /* if mcp fails to respond we must abort */
2373         if (!(*load_code)) {
2374                 BNX2X_ERR("MCP response failure, aborting\n");
2375                 return -EBUSY;
2376         }
2377
2378         /* If mcp refused (e.g. other port is in diagnostic mode) we
2379          * must abort
2380          */
2381         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2382                 BNX2X_ERR("MCP refused load request, aborting\n");
2383                 return -EBUSY;
2384         }
2385         return 0;
2386 }
2387
2388 /* check whether another PF has already loaded FW to chip. In
2389  * virtualized environments a pf from another VM may have already
2390  * initialized the device including loading FW
2391  */
2392 int bnx2x_compare_fw_ver(struct bnx2x *bp, uint32_t load_code,
2393                          bool print_err)
2394 {
2395         /* is another pf loaded on this engine? */
2396         if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
2397             load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
2398                 /* build my FW version dword */
2399                 uint32_t my_fw = (BCM_5710_FW_MAJOR_VERSION) +
2400                         (BCM_5710_FW_MINOR_VERSION << 8) +
2401                         (BCM_5710_FW_REVISION_VERSION << 16) +
2402                         (BCM_5710_FW_ENGINEERING_VERSION << 24);
2403
2404                 /* read loaded FW from chip */
2405                 uint32_t loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
2406
2407                 DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n",
2408                    loaded_fw, my_fw);
2409
2410                 /* abort nic load if version mismatch */
2411                 if (my_fw != loaded_fw) {
2412                         if (print_err)
2413                                 BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. Aborting\n",
2414                                           loaded_fw, my_fw);
2415                         else
2416                                 BNX2X_DEV_INFO("bnx2x with FW %x was already loaded which mismatches my %x FW, possibly due to MF UNDI\n",
2417                                                loaded_fw, my_fw);
2418                         return -EBUSY;
2419                 }
2420         }
2421         return 0;
2422 }
2423
2424 /* returns the "mcp load_code" according to global load_count array */
2425 static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
2426 {
2427         int path = BP_PATH(bp);
2428
2429         DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d]      %d, %d, %d\n",
2430            path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2431            bnx2x_load_count[path][2]);
2432         bnx2x_load_count[path][0]++;
2433         bnx2x_load_count[path][1 + port]++;
2434         DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d]  %d, %d, %d\n",
2435            path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2436            bnx2x_load_count[path][2]);
2437         if (bnx2x_load_count[path][0] == 1)
2438                 return FW_MSG_CODE_DRV_LOAD_COMMON;
2439         else if (bnx2x_load_count[path][1 + port] == 1)
2440                 return FW_MSG_CODE_DRV_LOAD_PORT;
2441         else
2442                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
2443 }
2444
2445 /* mark PMF if applicable */
2446 static void bnx2x_nic_load_pmf(struct bnx2x *bp, uint32_t load_code)
2447 {
2448         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2449             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2450             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2451                 bp->port.pmf = 1;
2452                 /* We need the barrier to ensure the ordering between the
2453                  * writing to bp->port.pmf here and reading it from the
2454                  * bnx2x_periodic_task().
2455                  */
2456                 mb();
2457         } else {
2458                 bp->port.pmf = 0;
2459         }
2460
2461         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2462 }
2463
2464 static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code)
2465 {
2466         if (((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2467              (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP)) &&
2468             (bp->common.shmem2_base)) {
2469                 if (SHMEM2_HAS(bp, dcc_support))
2470                         SHMEM2_WR(bp, dcc_support,
2471                                   (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
2472                                    SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
2473                 if (SHMEM2_HAS(bp, afex_driver_support))
2474                         SHMEM2_WR(bp, afex_driver_support,
2475                                   SHMEM_AFEX_SUPPORTED_VERSION_ONE);
2476         }
2477
2478         /* Set AFEX default VLAN tag to an invalid value */
2479         bp->afex_def_vlan_tag = -1;
2480 }
2481
2482 /**
2483  * bnx2x_bz_fp - zero content of the fastpath structure.
2484  *
2485  * @bp:         driver handle
2486  * @index:      fastpath index to be zeroed
2487  *
2488  * Makes sure the contents of the bp->fp[index].napi is kept
2489  * intact.
2490  */
2491 static void bnx2x_bz_fp(struct bnx2x *bp, int index)
2492 {
2493         struct bnx2x_fastpath *fp = &bp->fp[index];
2494         int cos;
2495         struct napi_struct orig_napi = fp->napi;
2496         struct bnx2x_agg_info *orig_tpa_info = fp->tpa_info;
2497
2498         /* bzero bnx2x_fastpath contents */
2499         if (fp->tpa_info)
2500                 memset(fp->tpa_info, 0, ETH_MAX_AGGREGATION_QUEUES_E1H_E2 *
2501                        sizeof(struct bnx2x_agg_info));
2502         memset(fp, 0, sizeof(*fp));
2503
2504         /* AKAROS_PORT: let the code set up whatever fake napi stuff it needs */
2505         /* Restore the NAPI object as it has been already initialized */
2506         fp->napi = orig_napi;
2507         fp->tpa_info = orig_tpa_info;
2508         fp->bp = bp;
2509         fp->index = index;
2510         if (IS_ETH_FP(fp))
2511                 fp->max_cos = bp->max_cos;
2512         else
2513                 /* Special queues support only one CoS */
2514                 fp->max_cos = 1;
2515
2516         /* Init txdata pointers */
2517         if (IS_FCOE_FP(fp))
2518                 fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)];
2519         if (IS_ETH_FP(fp))
2520                 for_each_cos_in_tx_queue(fp, cos)
2521                         fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos *
2522                                 BNX2X_NUM_ETH_QUEUES(bp) + index];
2523
2524         /* set the tpa flag for each queue. The tpa flag determines the queue
2525          * minimal size so it must be set prior to queue memory allocation
2526          */
2527         fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG ||
2528                                   (bp->flags & GRO_ENABLE_FLAG &&
2529                                    bnx2x_mtu_allows_gro(bp->dev->maxmtu)));
2530         if (bp->flags & TPA_ENABLE_FLAG)
2531                 fp->mode = TPA_MODE_LRO;
2532         else if (bp->flags & GRO_ENABLE_FLAG)
2533                 fp->mode = TPA_MODE_GRO;
2534
2535         /* We don't want TPA on an FCoE L2 ring */
2536         if (IS_FCOE_FP(fp))
2537                 fp->disable_tpa = 1;
2538 }
2539
2540 int bnx2x_load_cnic(struct bnx2x *bp)
2541 {
2542         int i, rc, port = BP_PORT(bp);
2543
2544         DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n");
2545
2546         qlock_init(&bp->cnic_mutex);
2547
2548         if (IS_PF(bp)) {
2549                 rc = bnx2x_alloc_mem_cnic(bp);
2550                 if (rc) {
2551                         BNX2X_ERR("Unable to allocate bp memory for cnic\n");
2552                         LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2553                 }
2554         }
2555
2556         rc = bnx2x_alloc_fp_mem_cnic(bp);
2557         if (rc) {
2558                 BNX2X_ERR("Unable to allocate memory for cnic fps\n");
2559                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2560         }
2561
2562         /* Update the number of queues with the cnic queues */
2563         rc = bnx2x_set_real_num_queues(bp, 1);
2564         if (rc) {
2565                 BNX2X_ERR("Unable to set real_num_queues including cnic\n");
2566                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2567         }
2568
2569         /* Add all CNIC NAPI objects */
2570         bnx2x_add_all_napi_cnic(bp);
2571         DP(NETIF_MSG_IFUP, "cnic napi added\n");
2572         bnx2x_napi_enable_cnic(bp);
2573
2574         rc = bnx2x_init_hw_func_cnic(bp);
2575         if (rc)
2576                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1);
2577
2578         bnx2x_nic_init_cnic(bp);
2579
2580         if (IS_PF(bp)) {
2581                 /* Enable Timer scan */
2582                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1);
2583
2584                 /* setup cnic queues */
2585                 for_each_cnic_queue(bp, i) {
2586                         rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2587                         if (rc) {
2588                                 BNX2X_ERR("Queue setup failed\n");
2589                                 LOAD_ERROR_EXIT(bp, load_error_cnic2);
2590                         }
2591                 }
2592         }
2593
2594         /* Initialize Rx filter. */
2595         bnx2x_set_rx_mode_inner(bp);
2596
2597         /* re-read iscsi info */
2598         bnx2x_get_iscsi_info(bp);
2599         bnx2x_setup_cnic_irq_info(bp);
2600         bnx2x_setup_cnic_info(bp);
2601         bp->cnic_loaded = true;
2602         if (bp->state == BNX2X_STATE_OPEN)
2603                 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
2604
2605         DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n");
2606
2607         return 0;
2608
2609 #ifndef BNX2X_STOP_ON_ERROR
2610 load_error_cnic2:
2611         /* Disable Timer scan */
2612         REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
2613
2614 load_error_cnic1:
2615         bnx2x_napi_disable_cnic(bp);
2616         /* Update the number of queues without the cnic queues */
2617         if (bnx2x_set_real_num_queues(bp, 0))
2618                 BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
2619 load_error_cnic0:
2620         BNX2X_ERR("CNIC-related load failed\n");
2621         bnx2x_free_fp_mem_cnic(bp);
2622         bnx2x_free_mem_cnic(bp);
2623         return rc;
2624 #endif /* ! BNX2X_STOP_ON_ERROR */
2625 }
2626
2627 /* must be called with rtnl_lock */
2628 int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
2629 {
2630         int port = BP_PORT(bp);
2631         int i, rc = 0;
2632         uint32_t load_code = 0;
2633
2634         DP(NETIF_MSG_IFUP, "Starting NIC load\n");
2635         DP(NETIF_MSG_IFUP,
2636            "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled");
2637
2638 #ifdef BNX2X_STOP_ON_ERROR
2639         if (unlikely(bp->panic)) {
2640                 BNX2X_ERR("Can't load NIC when there is panic\n");
2641                 return -EPERM;
2642         }
2643 #endif
2644
2645         bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
2646
2647         /* zero the structure w/o any lock, before SP handler is initialized */
2648         memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link));
2649         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
2650                 &bp->last_reported_link.link_report_flags);
2651
2652         if (IS_PF(bp))
2653                 /* must be called before memory allocation and HW init */
2654                 bnx2x_ilt_set_info(bp);
2655
2656         /*
2657          * Zero fastpath structures preserving invariants like napi, which are
2658          * allocated only once, fp index, max_cos, bp pointer.
2659          * Also set fp->disable_tpa and txdata_ptr.
2660          */
2661         DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
2662         for_each_queue(bp, i)
2663                 bnx2x_bz_fp(bp, i);
2664         memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS +
2665                                   bp->num_cnic_queues) *
2666                                   sizeof(struct bnx2x_fp_txdata));
2667
2668         bp->fcoe_init = false;
2669
2670         /* Set the receive queues buffer size */
2671         bnx2x_set_rx_buf_size(bp);
2672
2673         if (IS_PF(bp)) {
2674                 rc = bnx2x_alloc_mem(bp);
2675                 if (rc) {
2676                         BNX2X_ERR("Unable to allocate bp memory\n");
2677                         return rc;
2678                 }
2679         }
2680
2681         /* need to be done after alloc mem, since it's self adjusting to amount
2682          * of memory available for RSS queues
2683          */
2684         rc = bnx2x_alloc_fp_mem(bp);
2685         if (rc) {
2686                 BNX2X_ERR("Unable to allocate memory for fps\n");
2687                 LOAD_ERROR_EXIT(bp, load_error0);
2688         }
2689
2690         /* Allocated memory for FW statistics  */
2691         if (bnx2x_alloc_fw_stats_mem(bp))
2692                 LOAD_ERROR_EXIT(bp, load_error0);
2693
2694         /* request pf to initialize status blocks */
2695         if (IS_VF(bp)) {
2696                 rc = bnx2x_vfpf_init(bp);
2697                 if (rc)
2698                         LOAD_ERROR_EXIT(bp, load_error0);
2699         }
2700
2701         /* As long as bnx2x_alloc_mem() may possibly update
2702          * bp->num_queues, bnx2x_set_real_num_queues() should always
2703          * come after it. At this stage cnic queues are not counted.
2704          */
2705         rc = bnx2x_set_real_num_queues(bp, 0);
2706         if (rc) {
2707                 BNX2X_ERR("Unable to set real_num_queues\n");
2708                 LOAD_ERROR_EXIT(bp, load_error0);
2709         }
2710
2711         /* configure multi cos mappings in kernel.
2712          * this configuration may be overridden by a multi class queue
2713          * discipline or by a dcbx negotiation result.
2714          */
2715         bnx2x_setup_tc(bp->dev, bp->max_cos);
2716
2717         /* Add all NAPI objects */
2718         bnx2x_add_all_napi(bp);
2719         DP(NETIF_MSG_IFUP, "napi added\n");
2720         bnx2x_napi_enable(bp);
2721
2722         if (IS_PF(bp)) {
2723                 /* set pf load just before approaching the MCP */
2724                 bnx2x_set_pf_load(bp);
2725
2726                 /* if mcp exists send load request and analyze response */
2727                 if (!BP_NOMCP(bp)) {
2728                         /* attempt to load pf */
2729                         rc = bnx2x_nic_load_request(bp, &load_code);
2730                         if (rc)
2731                                 LOAD_ERROR_EXIT(bp, load_error1);
2732
2733                         /* what did mcp say? */
2734                         rc = bnx2x_compare_fw_ver(bp, load_code, true);
2735                         if (rc) {
2736                                 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2737                                 LOAD_ERROR_EXIT(bp, load_error2);
2738                         }
2739                 } else {
2740                         load_code = bnx2x_nic_load_no_mcp(bp, port);
2741                 }
2742
2743                 /* mark pmf if applicable */
2744                 bnx2x_nic_load_pmf(bp, load_code);
2745
2746                 /* Init Function state controlling object */
2747                 bnx2x__init_func_obj(bp);
2748
2749                 /* Initialize HW */
2750                 rc = bnx2x_init_hw(bp, load_code);
2751                 if (rc) {
2752                         BNX2X_ERR("HW init failed, aborting\n");
2753                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2754                         LOAD_ERROR_EXIT(bp, load_error2);
2755                 }
2756         }
2757
2758         bnx2x_pre_irq_nic_init(bp);
2759
2760         /* Connect to IRQs */
2761         rc = bnx2x_setup_irqs(bp);
2762         if (rc) {
2763                 BNX2X_ERR("setup irqs failed\n");
2764                 if (IS_PF(bp))
2765                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2766                 LOAD_ERROR_EXIT(bp, load_error2);
2767         }
2768
2769         /* Init per-function objects */
2770         if (IS_PF(bp)) {
2771                 /* Setup NIC internals and enable interrupts */
2772                 bnx2x_post_irq_nic_init(bp, load_code);
2773
2774                 bnx2x_init_bp_objs(bp);
2775                 bnx2x_iov_nic_init(bp);
2776
2777                 /* Set AFEX default VLAN tag to an invalid value */
2778                 bp->afex_def_vlan_tag = -1;
2779                 bnx2x_nic_load_afex_dcc(bp, load_code);
2780                 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
2781                 rc = bnx2x_func_start(bp);
2782                 if (rc) {
2783                         BNX2X_ERR("Function start failed!\n");
2784                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2785
2786                         LOAD_ERROR_EXIT(bp, load_error3);
2787                 }
2788
2789                 /* Send LOAD_DONE command to MCP */
2790                 if (!BP_NOMCP(bp)) {
2791                         load_code = bnx2x_fw_command(bp,
2792                                                      DRV_MSG_CODE_LOAD_DONE, 0);
2793                         if (!load_code) {
2794                                 BNX2X_ERR("MCP response failure, aborting\n");
2795                                 rc = -EBUSY;
2796                                 LOAD_ERROR_EXIT(bp, load_error3);
2797                         }
2798                 }
2799
2800                 /* initialize FW coalescing state machines in RAM */
2801                 bnx2x_update_coalesce(bp);
2802         }
2803
2804         /* setup the leading queue */
2805         rc = bnx2x_setup_leading(bp);
2806         if (rc) {
2807                 BNX2X_ERR("Setup leading failed!\n");
2808                 LOAD_ERROR_EXIT(bp, load_error3);
2809         }
2810
2811         /* set up the rest of the queues */
2812         for_each_nondefault_eth_queue(bp, i) {
2813                 if (IS_PF(bp))
2814                         rc = bnx2x_setup_queue(bp, &bp->fp[i], false);
2815                 else /* VF */
2816                         rc = bnx2x_vfpf_setup_q(bp, &bp->fp[i], false);
2817                 if (rc) {
2818                         BNX2X_ERR("Queue %d setup failed\n", i);
2819                         LOAD_ERROR_EXIT(bp, load_error3);
2820                 }
2821         }
2822
2823         /* setup rss */
2824         rc = bnx2x_init_rss(bp);
2825         if (rc) {
2826                 BNX2X_ERR("PF RSS init failed\n");
2827                 LOAD_ERROR_EXIT(bp, load_error3);
2828         }
2829
2830         /* Now when Clients are configured we are ready to work */
2831         bp->state = BNX2X_STATE_OPEN;
2832
2833         /* Configure a ucast MAC */
2834         if (IS_PF(bp))
2835                 rc = bnx2x_set_eth_mac(bp, true);
2836         else /* vf */
2837                 rc = bnx2x_vfpf_config_mac(bp, bp->dev->ea, bp->fp->index,
2838                                            true);
2839         if (rc) {
2840                 BNX2X_ERR("Setting Ethernet MAC failed\n");
2841                 LOAD_ERROR_EXIT(bp, load_error3);
2842         }
2843
2844         if (IS_PF(bp) && bp->pending_max) {
2845                 bnx2x_update_max_mf_config(bp, bp->pending_max);
2846                 bp->pending_max = 0;
2847         }
2848
2849         if (bp->port.pmf) {
2850                 rc = bnx2x_initial_phy_init(bp, load_mode);
2851                 if (rc)
2852                         LOAD_ERROR_EXIT(bp, load_error3);
2853         }
2854         bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN;
2855
2856         /* Start fast path */
2857
2858         /* Initialize Rx filter. */
2859         bnx2x_set_rx_mode_inner(bp);
2860
2861         /* Start Tx */
2862         switch (load_mode) {
2863         case LOAD_NORMAL:
2864                 /* Tx queue should be only re-enabled */
2865                 netif_tx_wake_all_queues(bp->dev);
2866                 break;
2867
2868         case LOAD_OPEN:
2869                 netif_tx_start_all_queues(bp->dev);
2870                 cmb();
2871                 break;
2872
2873         case LOAD_DIAG:
2874         case LOAD_LOOPBACK_EXT:
2875                 bp->state = BNX2X_STATE_DIAG;
2876                 break;
2877
2878         default:
2879                 break;
2880         }
2881
2882         if (bp->port.pmf)
2883                 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0);
2884         else
2885                 bnx2x__link_status_update(bp);
2886
2887         /* start the timer */
2888         set_awaiter_rel(&bp->timer, bp->current_interval * 1000); // fudge
2889         set_alarm(&per_cpu_info[0].tchain, &bp->timer);
2890
2891         if (CNIC_ENABLED(bp))
2892                 bnx2x_load_cnic(bp);
2893
2894         if (IS_PF(bp))
2895                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
2896
2897         if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2898                 /* mark driver is loaded in shmem2 */
2899                 uint32_t val;
2900                 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2901                 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2902                           val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
2903                           DRV_FLAGS_CAPABILITIES_LOADED_L2);
2904         }
2905
2906         /* Wait for all pending SP commands to complete */
2907         if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) {
2908                 BNX2X_ERR("Timeout waiting for SP elements to complete\n");
2909                 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
2910                 return -EBUSY;
2911         }
2912
2913         /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
2914         if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
2915                 bnx2x_dcbx_init(bp, false);
2916
2917         DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
2918
2919         return 0;
2920
2921 #ifndef BNX2X_STOP_ON_ERROR
2922 load_error3:
2923         if (IS_PF(bp)) {
2924                 bnx2x_int_disable_sync(bp, 1);
2925
2926                 /* Clean queueable objects */
2927                 bnx2x_squeeze_objects(bp);
2928         }
2929
2930         /* Free SKBs, SGEs, TPA pool and driver internals */
2931         bnx2x_free_skbs(bp);
2932         for_each_rx_queue(bp, i)
2933                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2934
2935         /* Release IRQs */
2936         bnx2x_free_irq(bp);
2937 load_error2:
2938         if (IS_PF(bp) && !BP_NOMCP(bp)) {
2939                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
2940                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
2941         }
2942
2943         bp->port.pmf = 0;
2944 load_error1:
2945         bnx2x_napi_disable(bp);
2946         bnx2x_del_all_napi(bp);
2947
2948         /* clear pf_load status, as it was already set */
2949         if (IS_PF(bp))
2950                 bnx2x_clear_pf_load(bp);
2951 load_error0:
2952         bnx2x_free_fw_stats_mem(bp);
2953         bnx2x_free_fp_mem(bp);
2954         bnx2x_free_mem(bp);
2955
2956         return rc;
2957 #endif /* ! BNX2X_STOP_ON_ERROR */
2958 }
2959
2960 int bnx2x_drain_tx_queues(struct bnx2x *bp)
2961 {
2962         uint8_t rc = 0, cos, i;
2963
2964         /* Wait until tx fastpath tasks complete */
2965         for_each_tx_queue(bp, i) {
2966                 struct bnx2x_fastpath *fp = &bp->fp[i];
2967
2968                 for_each_cos_in_tx_queue(fp, cos)
2969                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
2970                 if (rc)
2971                         return rc;
2972         }
2973         return 0;
2974 }
2975
2976 /* must be called with rtnl_lock */
2977 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
2978 {
2979 panic("Not implemented");
2980 #if 0 // AKAROS_PORT
2981         int i;
2982         bool global = false;
2983
2984         DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
2985
2986         /* mark driver is unloaded in shmem2 */
2987         if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2988                 uint32_t val;
2989                 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2990                 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2991                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2992         }
2993
2994         if (IS_PF(bp) && bp->recovery_state != BNX2X_RECOVERY_DONE &&
2995             (bp->state == BNX2X_STATE_CLOSED ||
2996              bp->state == BNX2X_STATE_ERROR)) {
2997                 /* We can get here if the driver has been unloaded
2998                  * during parity error recovery and is either waiting for a
2999                  * leader to complete or for other functions to unload and
3000                  * then ifdown has been issued. In this case we want to
3001                  * unload and let other functions to complete a recovery
3002                  * process.
3003                  */
3004                 bp->recovery_state = BNX2X_RECOVERY_DONE;
3005                 bp->is_leader = 0;
3006                 bnx2x_release_leader_lock(bp);
3007                 mb();
3008
3009                 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n");
3010                 BNX2X_ERR("Can't unload in closed or error state\n");
3011                 return -EINVAL;
3012         }
3013
3014         /* Nothing to do during unload if previous bnx2x_nic_load()
3015          * have not completed successfully - all resources are released.
3016          *
3017          * we can get here only after unsuccessful ndo_* callback, during which
3018          * dev->IFF_UP flag is still on.
3019          */
3020         if (bp->state == BNX2X_STATE_CLOSED || bp->state == BNX2X_STATE_ERROR)
3021                 return 0;
3022
3023         /* It's important to set the bp->state to the value different from
3024          * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int()
3025          * may restart the Tx from the NAPI context (see bnx2x_tx_int()).
3026          */
3027         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
3028         mb();
3029
3030         /* indicate to VFs that the PF is going down */
3031         bnx2x_iov_channel_down(bp);
3032
3033         if (CNIC_LOADED(bp))
3034                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
3035
3036         /* Stop Tx */
3037         bnx2x_tx_disable(bp);
3038         netdev_reset_tc(bp->dev);
3039
3040         bp->rx_mode = BNX2X_RX_MODE_NONE;
3041
3042         del_timer_sync(&bp->timer);
3043
3044         if (IS_PF(bp)) {
3045                 /* Set ALWAYS_ALIVE bit in shmem */
3046                 bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
3047                 bnx2x_drv_pulse(bp);
3048                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
3049                 bnx2x_save_statistics(bp);
3050         }
3051
3052         /* wait till consumers catch up with producers in all queues */
3053         bnx2x_drain_tx_queues(bp);
3054
3055         /* if VF indicate to PF this function is going down (PF will delete sp
3056          * elements and clear initializations
3057          */
3058         if (IS_VF(bp))
3059                 bnx2x_vfpf_close_vf(bp);
3060         else if (unload_mode != UNLOAD_RECOVERY)
3061                 /* if this is a normal/close unload need to clean up chip*/
3062                 bnx2x_chip_cleanup(bp, unload_mode, keep_link);
3063         else {
3064                 /* Send the UNLOAD_REQUEST to the MCP */
3065                 bnx2x_send_unload_req(bp, unload_mode);
3066
3067                 /* Prevent transactions to host from the functions on the
3068                  * engine that doesn't reset global blocks in case of global
3069                  * attention once global blocks are reset and gates are opened
3070                  * (the engine which leader will perform the recovery
3071                  * last).
3072                  */
3073                 if (!CHIP_IS_E1x(bp))
3074                         bnx2x_pf_disable(bp);
3075
3076                 /* Disable HW interrupts, NAPI */
3077                 bnx2x_netif_stop(bp, 1);
3078                 /* Delete all NAPI objects */
3079                 bnx2x_del_all_napi(bp);
3080                 if (CNIC_LOADED(bp))
3081                         bnx2x_del_all_napi_cnic(bp);
3082                 /* Release IRQs */
3083                 bnx2x_free_irq(bp);
3084
3085                 /* Report UNLOAD_DONE to MCP */
3086                 bnx2x_send_unload_done(bp, false);
3087         }
3088
3089         /*
3090          * At this stage no more interrupts will arrive so we may safely clean
3091          * the queueable objects here in case they failed to get cleaned so far.
3092          */
3093         if (IS_PF(bp))
3094                 bnx2x_squeeze_objects(bp);
3095
3096         /* There should be no more pending SP commands at this stage */
3097         bp->sp_state = 0;
3098
3099         bp->port.pmf = 0;
3100
3101         /* clear pending work in rtnl task */
3102         bp->sp_rtnl_state = 0;
3103         mb();
3104
3105         /* Free SKBs, SGEs, TPA pool and driver internals */
3106         bnx2x_free_skbs(bp);
3107         if (CNIC_LOADED(bp))
3108                 bnx2x_free_skbs_cnic(bp);
3109         for_each_rx_queue(bp, i)
3110                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
3111
3112         bnx2x_free_fp_mem(bp);
3113         if (CNIC_LOADED(bp))
3114                 bnx2x_free_fp_mem_cnic(bp);
3115
3116         if (IS_PF(bp)) {
3117                 if (CNIC_LOADED(bp))
3118                         bnx2x_free_mem_cnic(bp);
3119         }
3120         bnx2x_free_mem(bp);
3121
3122         bp->state = BNX2X_STATE_CLOSED;
3123         bp->cnic_loaded = false;
3124
3125         /* Clear driver version indication in shmem */
3126         if (IS_PF(bp))
3127                 bnx2x_update_mng_version(bp);
3128
3129         /* Check if there are pending parity attentions. If there are - set
3130          * RECOVERY_IN_PROGRESS.
3131          */
3132         if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) {
3133                 bnx2x_set_reset_in_progress(bp);
3134
3135                 /* Set RESET_IS_GLOBAL if needed */
3136                 if (global)
3137                         bnx2x_set_reset_global(bp);
3138         }
3139
3140         /* The last driver must disable a "close the gate" if there is no
3141          * parity attention or "process kill" pending.
3142          */
3143         if (IS_PF(bp) &&
3144             !bnx2x_clear_pf_load(bp) &&
3145             bnx2x_reset_is_done(bp, BP_PATH(bp)))
3146                 bnx2x_disable_close_the_gate(bp);
3147
3148         DP(NETIF_MSG_IFUP, "Ending NIC unload\n");
3149
3150         return 0;
3151 #endif
3152 }
3153
3154 #if 0 // AKAROS_PORT
3155 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
3156 {
3157         uint16_t pmcsr;
3158
3159         /* If there is no power capability, silently succeed */
3160         if (!bp->pdev->pm_cap) {
3161                 BNX2X_DEV_INFO("No power capability. Breaking.\n");
3162                 return 0;
3163         }
3164
3165         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL, &pmcsr);
3166
3167         switch (state) {
3168         case PCI_D0:
3169                 pci_write_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_CTRL,
3170                                       ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3171                                        PCI_PM_CTRL_PME_STATUS));
3172
3173                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3174                         /* delay required during transition out of D3hot */
3175                         kthread_usleep(1000 * 20);
3176                 break;
3177
3178         case PCI_D3hot:
3179                 /* If there are other clients above don't
3180                    shut down the power */
3181                 if (atomic_read(&bp->pdev->enable_cnt) != 1)
3182                         return 0;
3183                 /* Don't shut down the power for emulation and FPGA */
3184                 if (CHIP_REV_IS_SLOW(bp))
3185                         return 0;
3186
3187                 pmcsr &= ~P