BNX2X: spatch changes for BUG and WARN
[akaros.git] / kern / drivers / net / bnx2x / bnx2x_cmn.c
1 /* bnx2x_cmn.c: Broadcom Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10  * Written by: Eliezer Tamir
11  * Based on code from Michael Chan's bnx2 driver
12  * UDP CSUM errata workaround by Arik Gendelman
13  * Slowpath and fastpath rework by Vladislav Zolotarov
14  * Statistics and Link management by Yitchak Gertner
15  *
16  */
17
18 #include "akaros_compat.h"
19
20 #include "bnx2x_cmn.h"
21 #include "bnx2x_init.h"
22 #include "bnx2x_sp.h"
23
24 static void bnx2x_free_fp_mem_cnic(struct bnx2x *bp);
25 static int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp);
26 static int bnx2x_alloc_fp_mem(struct bnx2x *bp);
27 static int bnx2x_poll(struct napi_struct *napi, int budget);
28
29 static void bnx2x_add_all_napi_cnic(struct bnx2x *bp)
30 {
31 panic("Not implemented");
32 #if 0 // AKAROS_PORT
33         int i;
34
35         /* Add NAPI objects */
36         for_each_rx_queue_cnic(bp, i) {
37                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
38                                bnx2x_poll, NAPI_POLL_WEIGHT);
39                 napi_hash_add(&bnx2x_fp(bp, i, napi));
40         }
41 #endif
42 }
43
44 static void bnx2x_add_all_napi(struct bnx2x *bp)
45 {
46 panic("Not implemented");
47 #if 0 // AKAROS_PORT
48         int i;
49
50         /* Add NAPI objects */
51         for_each_eth_queue(bp, i) {
52                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
53                                bnx2x_poll, NAPI_POLL_WEIGHT);
54                 napi_hash_add(&bnx2x_fp(bp, i, napi));
55         }
56 #endif
57 }
58
59 static int bnx2x_calc_num_queues(struct bnx2x *bp)
60 {
61         /* default is min(8, num_cpus) in Linux.  we'll set it elsewhere */
62         int nq = bnx2x_num_queues ? : 8;
63
64         /* Reduce memory usage in kdump environment by using only one queue */
65         if (is_kdump_kernel())
66                 nq = 1;
67
68         nq = CLAMP(nq, 1, BNX2X_MAX_QUEUES(bp));
69         return nq;
70 }
71
72 /**
73  * bnx2x_move_fp - move content of the fastpath structure.
74  *
75  * @bp:         driver handle
76  * @from:       source FP index
77  * @to:         destination FP index
78  *
79  * Makes sure the contents of the bp->fp[to].napi is kept
80  * intact. This is done by first copying the napi struct from
81  * the target to the source, and then mem copying the entire
82  * source onto the target. Update txdata pointers and related
83  * content.
84  */
85 static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
86 {
87         struct bnx2x_fastpath *from_fp = &bp->fp[from];
88         struct bnx2x_fastpath *to_fp = &bp->fp[to];
89         struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from];
90         struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to];
91         struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from];
92         struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to];
93         int old_max_eth_txqs, new_max_eth_txqs;
94         int old_txdata_index = 0, new_txdata_index = 0;
95         struct bnx2x_agg_info *old_tpa_info = to_fp->tpa_info;
96
97         /* Copy the NAPI object as it has been already initialized */
98         from_fp->napi = to_fp->napi;
99
100         /* Move bnx2x_fastpath contents */
101         memcpy(to_fp, from_fp, sizeof(*to_fp));
102         to_fp->index = to;
103
104         /* Retain the tpa_info of the original `to' version as we don't want
105          * 2 FPs to contain the same tpa_info pointer.
106          */
107         to_fp->tpa_info = old_tpa_info;
108
109         /* move sp_objs contents as well, as their indices match fp ones */
110         memcpy(to_sp_objs, from_sp_objs, sizeof(*to_sp_objs));
111
112         /* move fp_stats contents as well, as their indices match fp ones */
113         memcpy(to_fp_stats, from_fp_stats, sizeof(*to_fp_stats));
114
115         /* Update txdata pointers in fp and move txdata content accordingly:
116          * Each fp consumes 'max_cos' txdata structures, so the index should be
117          * decremented by max_cos x delta.
118          */
119
120         old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos;
121         new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) *
122                                 (bp)->max_cos;
123         if (from == FCOE_IDX(bp)) {
124                 old_txdata_index = old_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
125                 new_txdata_index = new_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
126         }
127
128         memcpy(&bp->bnx2x_txq[new_txdata_index],
129                &bp->bnx2x_txq[old_txdata_index],
130                sizeof(struct bnx2x_fp_txdata));
131         to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index];
132 }
133
134 /**
135  * bnx2x_fill_fw_str - Fill buffer with FW version string.
136  *
137  * @bp:        driver handle
138  * @buf:       character buffer to fill with the fw name
139  * @buf_len:   length of the above buffer
140  *
141  */
142 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
143 {
144         if (IS_PF(bp)) {
145                 uint8_t phy_fw_ver[PHY_FW_VER_LEN];
146
147                 phy_fw_ver[0] = '\0';
148                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
149                                              phy_fw_ver, PHY_FW_VER_LEN);
150                 strlcpy(buf, bp->fw_ver, buf_len);
151                 snprintf(buf + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
152                          "bc %d.%d.%d%s%s",
153                          (bp->common.bc_ver & 0xff0000) >> 16,
154                          (bp->common.bc_ver & 0xff00) >> 8,
155                          (bp->common.bc_ver & 0xff),
156                          ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
157         } else {
158                 bnx2x_vf_fill_fw_str(bp, buf, buf_len);
159         }
160 }
161
162 /**
163  * bnx2x_shrink_eth_fp - guarantees fastpath structures stay intact
164  *
165  * @bp: driver handle
166  * @delta:      number of eth queues which were not allocated
167  */
168 static void bnx2x_shrink_eth_fp(struct bnx2x *bp, int delta)
169 {
170         int i, cos, old_eth_num = BNX2X_NUM_ETH_QUEUES(bp);
171
172         /* Queue pointer cannot be re-set on an fp-basis, as moving pointer
173          * backward along the array could cause memory to be overridden
174          */
175         for (cos = 1; cos < bp->max_cos; cos++) {
176                 for (i = 0; i < old_eth_num - delta; i++) {
177                         struct bnx2x_fastpath *fp = &bp->fp[i];
178                         int new_idx = cos * (old_eth_num - delta) + i;
179
180                         memcpy(&bp->bnx2x_txq[new_idx], fp->txdata_ptr[cos],
181                                sizeof(struct bnx2x_fp_txdata));
182                         fp->txdata_ptr[cos] = &bp->bnx2x_txq[new_idx];
183                 }
184         }
185 }
186
187 int bnx2x_load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
188
189 /* free skb in the packet ring at pos idx
190  * return idx of last bd freed
191  */
192 static uint16_t bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
193                              uint16_t idx, unsigned int *pkts_compl,
194                              unsigned int *bytes_compl)
195 {
196 panic("Not implemented");
197 #if 0 // AKAROS_PORT
198         struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx];
199         struct eth_tx_start_bd *tx_start_bd;
200         struct eth_tx_bd *tx_data_bd;
201         struct sk_buff *skb = tx_buf->skb;
202         uint16_t bd_idx = TX_BD(tx_buf->first_bd), new_cons;
203         int nbd;
204         uint16_t split_bd_len = 0;
205
206         /* prefetch skb end pointer to speedup dev_kfree_skb() */
207         prefetch(&skb->end);
208
209         DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d  buff @(%p)->skb %p\n",
210            txdata->txq_index, idx, tx_buf, skb);
211
212         tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd;
213
214         nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
215 #ifdef BNX2X_STOP_ON_ERROR
216         if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
217                 BNX2X_ERR("BAD nbd!\n");
218                 bnx2x_panic();
219         }
220 #endif
221         new_cons = nbd + tx_buf->first_bd;
222
223         /* Get the next bd */
224         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
225
226         /* Skip a parse bd... */
227         --nbd;
228         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
229
230         if (tx_buf->flags & BNX2X_HAS_SECOND_PBD) {
231                 /* Skip second parse bd... */
232                 --nbd;
233                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
234         }
235
236         /* TSO headers+data bds share a common mapping. See bnx2x_tx_split() */
237         if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
238                 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
239                 split_bd_len = BD_UNMAP_LEN(tx_data_bd);
240                 --nbd;
241                 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
242         }
243
244         /* unmap first bd */
245         dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
246                          BD_UNMAP_LEN(tx_start_bd) + split_bd_len,
247                          DMA_TO_DEVICE);
248
249         /* now free frags */
250         while (nbd > 0) {
251
252                 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
253                 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
254                                BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
255                 if (--nbd)
256                         bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
257         }
258
259         /* release skb */
260         warn_on(!skb);
261         if (likely(skb)) {
262                 (*pkts_compl)++;
263                 (*bytes_compl) += skb->len;
264         }
265
266         dev_kfree_skb_any(skb);
267         tx_buf->first_bd = 0;
268         tx_buf->skb = NULL;
269
270         return new_cons;
271 #endif
272 }
273
274 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
275 {
276 panic("Not implemented");
277 #if 0 // AKAROS_PORT
278         struct netdev_queue *txq;
279         uint16_t hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
280         unsigned int pkts_compl = 0, bytes_compl = 0;
281
282 #ifdef BNX2X_STOP_ON_ERROR
283         if (unlikely(bp->panic))
284                 return -1;
285 #endif
286
287         txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
288         hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
289         sw_cons = txdata->tx_pkt_cons;
290
291         while (sw_cons != hw_cons) {
292                 uint16_t pkt_cons;
293
294                 pkt_cons = TX_BD(sw_cons);
295
296                 DP(NETIF_MSG_TX_DONE,
297                    "queue[%d]: hw_cons %u  sw_cons %u  pkt_cons %u\n",
298                    txdata->txq_index, hw_cons, sw_cons, pkt_cons);
299
300                 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
301                                             &pkts_compl, &bytes_compl);
302
303                 sw_cons++;
304         }
305
306         netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
307
308         txdata->tx_pkt_cons = sw_cons;
309         txdata->tx_bd_cons = bd_cons;
310
311         /* Need to make the tx_bd_cons update visible to start_xmit()
312          * before checking for netif_tx_queue_stopped().  Without the
313          * memory barrier, there is a small possibility that
314          * start_xmit() will miss it and cause the queue to be stopped
315          * forever.
316          * On the other hand we need an rmb() here to ensure the proper
317          * ordering of bit testing in the following
318          * netif_tx_queue_stopped(txq) call.
319          */
320         mb();
321
322         if (unlikely(netif_tx_queue_stopped(txq))) {
323                 /* Taking tx_lock() is needed to prevent re-enabling the queue
324                  * while it's empty. This could have happen if rx_action() gets
325                  * suspended in bnx2x_tx_int() after the condition before
326                  * netif_tx_wake_queue(), while tx_action (bnx2x_start_xmit()):
327                  *
328                  * stops the queue->sees fresh tx_bd_cons->releases the queue->
329                  * sends some packets consuming the whole queue again->
330                  * stops the queue
331                  */
332
333                 __netif_tx_lock(txq, core_id());
334
335                 if ((netif_tx_queue_stopped(txq)) &&
336                     (bp->state == BNX2X_STATE_OPEN) &&
337                     (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT))
338                         netif_tx_wake_queue(txq);
339
340                 __netif_tx_unlock(txq);
341         }
342         return 0;
343 #endif
344 }
345
346 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
347                                              uint16_t idx)
348 {
349         uint16_t last_max = fp->last_max_sge;
350
351         if (SUB_S16(idx, last_max) > 0)
352                 fp->last_max_sge = idx;
353 }
354
355 static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
356                                          uint16_t sge_len,
357                                          struct eth_end_agg_rx_cqe *cqe)
358 {
359         struct bnx2x *bp = fp->bp;
360         uint16_t last_max, last_elem, first_elem;
361         uint16_t delta = 0;
362         uint16_t i;
363
364         if (!sge_len)
365                 return;
366
367         /* First mark all used pages */
368         for (i = 0; i < sge_len; i++)
369                 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
370                         RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[i])));
371
372         DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
373            sge_len - 1, le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
374
375         /* Here we assume that the last SGE index is the biggest */
376         prefetch((void *)(fp->sge_mask));
377         bnx2x_update_last_max_sge(fp,
378                 le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
379
380         last_max = RX_SGE(fp->last_max_sge);
381         last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
382         first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
383
384         /* If ring is not full */
385         if (last_elem + 1 != first_elem)
386                 last_elem++;
387
388         /* Now update the prod */
389         for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
390                 if (likely(fp->sge_mask[i]))
391                         break;
392
393                 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
394                 delta += BIT_VEC64_ELEM_SZ;
395         }
396
397         if (delta > 0) {
398                 fp->rx_sge_prod += delta;
399                 /* clear page-end entries */
400                 bnx2x_clear_sge_mask_next_elems(fp);
401         }
402
403         DP(NETIF_MSG_RX_STATUS,
404            "fp->last_max_sge = %d  fp->rx_sge_prod = %d\n",
405            fp->last_max_sge, fp->rx_sge_prod);
406 }
407
408 /* Get Toeplitz hash value in the skb using the value from the
409  * CQE (calculated by HW).
410  */
411 static uint32_t bnx2x_get_rxhash(const struct bnx2x *bp,
412                             const struct eth_fast_path_rx_cqe *cqe,
413                             enum pkt_hash_types *rxhash_type)
414 {
415 panic("Not implemented");
416 #if 0 // AKAROS_PORT
417         /* Get Toeplitz hash from CQE */
418         if ((bp->dev->feat & NETIF_F_RXHASH) &&
419             (cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) {
420                 enum eth_rss_hash_type htype;
421
422                 htype = cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE;
423                 *rxhash_type = ((htype == TCP_IPV4_HASH_TYPE) ||
424                                 (htype == TCP_IPV6_HASH_TYPE)) ?
425                                PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
426
427                 return le32_to_cpu(cqe->rss_hash_result);
428         }
429         *rxhash_type = PKT_HASH_TYPE_NONE;
430         return 0;
431 #endif
432 }
433
434 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, uint16_t queue,
435                             uint16_t cons, uint16_t prod,
436                             struct eth_fast_path_rx_cqe *cqe)
437 {
438 panic("Not implemented");
439 #if 0 // AKAROS_PORT
440         struct bnx2x *bp = fp->bp;
441         struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
442         struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
443         struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
444         dma_addr_t mapping;
445         struct bnx2x_agg_info *tpa_info = &fp->tpa_info[queue];
446         struct sw_rx_bd *first_buf = &tpa_info->first_buf;
447
448         /* print error if current state != stop */
449         if (tpa_info->tpa_state != BNX2X_TPA_STOP)
450                 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
451
452         /* Try to map an empty data buffer from the aggregation info  */
453         mapping = dma_map_single(&bp->pdev->dev,
454                                  first_buf->data + NET_SKB_PAD,
455                                  fp->rx_buf_size, DMA_FROM_DEVICE);
456         /*
457          *  ...if it fails - move the skb from the consumer to the producer
458          *  and set the current aggregation state as ERROR to drop it
459          *  when TPA_STOP arrives.
460          */
461
462         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
463                 /* Move the BD from the consumer to the producer */
464                 bnx2x_reuse_rx_data(fp, cons, prod);
465                 tpa_info->tpa_state = BNX2X_TPA_ERROR;
466                 return;
467         }
468
469         /* move empty data from pool to prod */
470         prod_rx_buf->data = first_buf->data;
471         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
472         /* point prod_bd to new data */
473         prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
474         prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
475
476         /* move partial skb from cons to pool (don't unmap yet) */
477         *first_buf = *cons_rx_buf;
478
479         /* mark bin state as START */
480         tpa_info->parsing_flags =
481                 le16_to_cpu(cqe->pars_flags.flags);
482         tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
483         tpa_info->tpa_state = BNX2X_TPA_START;
484         tpa_info->len_on_bd = le16_to_cpu(cqe->len_on_bd);
485         tpa_info->placement_offset = cqe->placement_offset;
486         tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->rxhash_type);
487         if (fp->mode == TPA_MODE_GRO) {
488                 uint16_t gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
489                 tpa_info->full_page = SGE_PAGES / gro_size * gro_size;
490                 tpa_info->gro_size = gro_size;
491         }
492
493 #ifdef BNX2X_STOP_ON_ERROR
494         fp->tpa_queue_used |= (1 << queue);
495         DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
496            fp->tpa_queue_used);
497 #endif
498 #endif
499 }
500
501 /* Timestamp option length allowed for TPA aggregation:
502  *
503  *              nop nop kind length echo val
504  */
505 #define TPA_TSTAMP_OPT_LEN      12
506 /**
507  * bnx2x_set_gro_params - compute GRO values
508  *
509  * @skb:                packet skb
510  * @parsing_flags:      parsing flags from the START CQE
511  * @len_on_bd:          total length of the first packet for the
512  *                      aggregation.
513  * @pkt_len:            length of all segments
514  *
515  * Approximate value of the MSS for this aggregation calculated using
516  * the first packet of it.
517  * Compute number of aggregated segments, and gso_type.
518  */
519 static void bnx2x_set_gro_params(struct sk_buff *skb, uint16_t parsing_flags,
520                                  uint16_t len_on_bd, unsigned int pkt_len,
521                                  uint16_t num_of_coalesced_segs)
522 {
523 panic("Not implemented");
524 #if 0 // AKAROS_PORT
525         /* TPA aggregation won't have either IP options or TCP options
526          * other than timestamp or IPv6 extension headers.
527          */
528         uint16_t hdrs_len = ETHERHDRSIZE + sizeof(struct tcphdr);
529
530         if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
531             PRS_FLAG_OVERETH_IPV6) {
532                 hdrs_len += sizeof(struct ipv6hdr);
533                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
534         } else {
535                 hdrs_len += sizeof(struct iphdr);
536                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
537         }
538
539         /* Check if there was a TCP timestamp, if there is it's will
540          * always be 12 bytes length: nop nop kind length echo val.
541          *
542          * Otherwise FW would close the aggregation.
543          */
544         if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG)
545                 hdrs_len += TPA_TSTAMP_OPT_LEN;
546
547         skb_shinfo(skb)->gso_size = len_on_bd - hdrs_len;
548
549         /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
550          * to skb_shinfo(skb)->gso_segs
551          */
552         NAPI_GRO_CB(skb)->count = num_of_coalesced_segs;
553 #endif
554 }
555
556 static int bnx2x_alloc_rx_sge(struct bnx2x *bp, struct bnx2x_fastpath *fp,
557                               uint16_t index, gfp_t gfp_mask)
558 {
559         struct page *page = get_cont_pages(PAGES_PER_SGE_SHIFT, gfp_mask);
560         struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
561         struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
562         dma_addr_t mapping;
563
564         if (unlikely(page == NULL)) {
565                 BNX2X_ERR("Can't alloc sge\n");
566                 return -ENOMEM;
567         }
568
569         mapping = dma_map_page(&bp->pdev->dev, page, 0,
570                                SGE_PAGES, DMA_FROM_DEVICE);
571         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
572                 free_cont_pages(page, PAGES_PER_SGE_SHIFT);
573                 BNX2X_ERR("Can't map sge\n");
574                 return -ENOMEM;
575         }
576
577         sw_buf->page = page;
578         dma_unmap_addr_set(sw_buf, mapping, mapping);
579
580         sge->addr_hi = cpu_to_le32(U64_HI(mapping));
581         sge->addr_lo = cpu_to_le32(U64_LO(mapping));
582
583         return 0;
584 }
585
586 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
587                                struct bnx2x_agg_info *tpa_info,
588                                uint16_t pages,
589                                struct sk_buff *skb,
590                                struct eth_end_agg_rx_cqe *cqe,
591                                uint16_t cqe_idx)
592 {
593 panic("Not implemented");
594 #if 0 // AKAROS_PORT
595         struct sw_rx_page *rx_pg, old_rx_pg;
596         uint32_t i, frag_len, frag_size;
597         int err, j, frag_id = 0;
598         uint16_t len_on_bd = tpa_info->len_on_bd;
599         uint16_t full_page = 0, gro_size = 0;
600
601         frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd;
602
603         if (fp->mode == TPA_MODE_GRO) {
604                 gro_size = tpa_info->gro_size;
605                 full_page = tpa_info->full_page;
606         }
607
608         /* This is needed in order to enable forwarding support */
609         if (frag_size)
610                 bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd,
611                                      le16_to_cpu(cqe->pkt_len),
612                                      le16_to_cpu(cqe->num_of_coalesced_segs));
613
614 #ifdef BNX2X_STOP_ON_ERROR
615         if (pages > MIN_T(uint32_t, 8, MAX_SKB_FRAGS) * SGE_PAGES) {
616                 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
617                           pages, cqe_idx);
618                 BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len);
619                 bnx2x_panic();
620                 return -EINVAL;
621         }
622 #endif
623
624         /* Run through the SGL and compose the fragmented skb */
625         for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
626                 uint16_t sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
627
628                 /* FW gives the indices of the SGE as if the ring is an array
629                    (meaning that "next" element will consume 2 indices) */
630                 if (fp->mode == TPA_MODE_GRO)
631                         frag_len = MIN_T(uint32_t, frag_size,
632                                          (uint32_t)full_page);
633                 else /* LRO */
634                         frag_len = MIN_T(uint32_t, frag_size,
635                                          (uint32_t)SGE_PAGES);
636
637                 rx_pg = &fp->rx_page_ring[sge_idx];
638                 old_rx_pg = *rx_pg;
639
640                 /* If we fail to allocate a substitute page, we simply stop
641                    where we are and drop the whole packet */
642                 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx, 0);
643                 if (unlikely(err)) {
644                         bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
645                         return err;
646                 }
647
648                 /* Unmap the page as we're going to pass it to the stack */
649                 dma_unmap_page(&bp->pdev->dev,
650                                dma_unmap_addr(&old_rx_pg, mapping),
651                                SGE_PAGES, DMA_FROM_DEVICE);
652                 /* Add one frag and update the appropriate fields in the skb */
653                 if (fp->mode == TPA_MODE_LRO)
654                         skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
655                 else { /* GRO */
656                         int rem;
657                         int offset = 0;
658                         for (rem = frag_len; rem > 0; rem -= gro_size) {
659                                 int len = rem > gro_size ? gro_size : rem;
660                                 skb_fill_page_desc(skb, frag_id++,
661                                                    old_rx_pg.page, offset, len);
662                                 if (offset)
663                                         page_incref(old_rx_pg.page);
664                                 offset += len;
665                         }
666                 }
667
668                 skb->data_len += frag_len;
669                 skb->truesize += SGE_PAGES;
670                 skb->len += frag_len;
671
672                 frag_size -= frag_len;
673         }
674
675         return 0;
676 #endif
677 }
678
679 static void bnx2x_frag_free(const struct bnx2x_fastpath *fp, void *data)
680 {
681         if (fp->rx_frag_size)
682                 page_decref(kva2page(data));
683         else
684                 kfree(data);
685 }
686
687 static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp, gfp_t gfp_mask)
688 {
689 panic("Not implemented");
690 #if 0 // AKAROS_PORT
691         if (fp->rx_frag_size) {
692                 /* GFP_KERNEL allocations are used only during initialization */
693                 if (unlikely(gfp_mask & KMALLOC_WAIT))
694                         return (void *)kpage_alloc_addr();
695
696                 return netdev_alloc_frag(fp->rx_frag_size);
697         }
698
699         return kmalloc(fp->rx_buf_size + NET_SKB_PAD, gfp_mask);
700 #endif
701 }
702
703 #ifdef CONFIG_INET
704 static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb)
705 {
706         const struct iphdr *iph = ip_hdr(skb);
707         struct tcphdr *th;
708
709         skb_set_transport_header(skb, sizeof(struct iphdr));
710         th = tcp_hdr(skb);
711
712         th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
713                                   iph->saddr, iph->daddr, 0);
714 }
715
716 static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb)
717 {
718         struct ipv6hdr *iph = ipv6_hdr(skb);
719         struct tcphdr *th;
720
721         skb_set_transport_header(skb, sizeof(struct ipv6hdr));
722         th = tcp_hdr(skb);
723
724         th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
725                                   &iph->saddr, &iph->daddr, 0);
726 }
727
728 static void bnx2x_gro_csum(struct bnx2x *bp, struct sk_buff *skb,
729                             void (*gro_func)(struct bnx2x*, struct sk_buff*))
730 {
731         skb_set_network_header(skb, 0);
732         gro_func(bp, skb);
733         tcp_gro_complete(skb);
734 }
735 #endif
736
737 static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
738                                struct sk_buff *skb)
739 {
740 panic("Not implemented");
741 #if 0 // AKAROS_PORT
742 #ifdef CONFIG_INET
743         if (skb_shinfo(skb)->gso_size) {
744                 switch (be16_to_cpu(skb->protocol)) {
745                 case ETH_P_IP:
746                         bnx2x_gro_csum(bp, skb, bnx2x_gro_ip_csum);
747                         break;
748                 case ETH_P_IPV6:
749                         bnx2x_gro_csum(bp, skb, bnx2x_gro_ipv6_csum);
750                         break;
751                 default:
752                         BNX2X_ERR("Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
753                                   be16_to_cpu(skb->protocol));
754                 }
755         }
756 #endif
757         skb_record_rx_queue(skb, fp->rx_queue);
758         napi_gro_receive(&fp->napi, skb);
759 #endif
760 }
761
762 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
763                            struct bnx2x_agg_info *tpa_info,
764                            uint16_t pages,
765                            struct eth_end_agg_rx_cqe *cqe,
766                            uint16_t cqe_idx)
767 {
768 panic("Not implemented");
769 #if 0 // AKAROS_PORT
770         struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
771         uint8_t pad = tpa_info->placement_offset;
772         uint16_t len = tpa_info->len_on_bd;
773         struct sk_buff *skb = NULL;
774         uint8_t *new_data, *data = rx_buf->data;
775         uint8_t old_tpa_state = tpa_info->tpa_state;
776
777         tpa_info->tpa_state = BNX2X_TPA_STOP;
778
779         /* If we there was an error during the handling of the TPA_START -
780          * drop this aggregation.
781          */
782         if (old_tpa_state == BNX2X_TPA_ERROR)
783                 goto drop;
784
785         /* Try to allocate the new data */
786         new_data = bnx2x_frag_alloc(fp, 0);
787         /* Unmap skb in the pool anyway, as we are going to change
788            pool entry status to BNX2X_TPA_STOP even if new skb allocation
789            fails. */
790         dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
791                          fp->rx_buf_size, DMA_FROM_DEVICE);
792         if (likely(new_data))
793                 skb = build_skb(data, fp->rx_frag_size);
794
795         if (likely(skb)) {
796 #ifdef BNX2X_STOP_ON_ERROR
797                 if (pad + len > fp->rx_buf_size) {
798                         BNX2X_ERR("skb_put is about to fail...  pad %d  len %d  rx_buf_size %d\n",
799                                   pad, len, fp->rx_buf_size);
800                         bnx2x_panic();
801                         return;
802                 }
803 #endif
804
805                 skb_reserve(skb, pad + NET_SKB_PAD);
806                 skb_put(skb, len);
807                 skb_set_hash(skb, tpa_info->rxhash, tpa_info->rxhash_type);
808
809                 skb->protocol = eth_type_trans(skb, bp->dev);
810                 skb->ip_summed = CHECKSUM_UNNECESSARY;
811
812                 if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages,
813                                          skb, cqe, cqe_idx)) {
814                         if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN)
815                                 __vlan_hwaccel_put_tag(skb,
816                                                        cpu_to_be16(ETH_P_8021Q),
817                                                        tpa_info->vlan_tag);
818                         bnx2x_gro_receive(bp, fp, skb);
819                 } else {
820                         DP(NETIF_MSG_RX_STATUS,
821                            "Failed to allocate new pages - dropping packet!\n");
822                         dev_kfree_skb_any(skb);
823                 }
824
825                 /* put new data in bin */
826                 rx_buf->data = new_data;
827
828                 return;
829         }
830         if (new_data)
831                 bnx2x_frag_free(fp, new_data);
832 drop:
833         /* drop the packet and keep the buffer in the bin */
834         DP(NETIF_MSG_RX_STATUS,
835            "Failed to allocate or map a new skb - dropping packet!\n");
836         bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++;
837 #endif
838 }
839
840 static int bnx2x_alloc_rx_data(struct bnx2x *bp, struct bnx2x_fastpath *fp,
841                                uint16_t index, gfp_t gfp_mask)
842 {
843 panic("Not implemented");
844 #if 0 // AKAROS_PORT
845         uint8_t *data;
846         struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
847         struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
848         dma_addr_t mapping;
849
850         data = bnx2x_frag_alloc(fp, gfp_mask);
851         if (unlikely(data == NULL))
852                 return -ENOMEM;
853
854         mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
855                                  fp->rx_buf_size,
856                                  DMA_FROM_DEVICE);
857         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
858                 bnx2x_frag_free(fp, data);
859                 BNX2X_ERR("Can't map rx data\n");
860                 return -ENOMEM;
861         }
862
863         rx_buf->data = data;
864         dma_unmap_addr_set(rx_buf, mapping, mapping);
865
866         rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
867         rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
868
869         return 0;
870 #endif
871 }
872
873 static
874 void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe,
875                                  struct bnx2x_fastpath *fp,
876                                  struct bnx2x_eth_q_stats *qstats)
877 {
878 panic("Not implemented");
879 #if 0 // AKAROS_PORT
880         /* Do nothing if no L4 csum validation was done.
881          * We do not check whether IP csum was validated. For IPv4 we assume
882          * that if the card got as far as validating the L4 csum, it also
883          * validated the IP csum. IPv6 has no IP csum.
884          */
885         if (cqe->fast_path_cqe.status_flags &
886             ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)
887                 return;
888
889         /* If L4 validation was done, check if an error was found. */
890
891         if (cqe->fast_path_cqe.type_error_flags &
892             (ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG |
893              ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
894                 qstats->hw_csum_err++;
895         else
896                 skb->ip_summed = CHECKSUM_UNNECESSARY;
897 #endif
898 }
899
900 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
901 {
902 panic("Not implemented");
903 #if 0 // AKAROS_PORT
904         struct bnx2x *bp = fp->bp;
905         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
906         uint16_t sw_comp_cons, sw_comp_prod;
907         int rx_pkt = 0;
908         union eth_rx_cqe *cqe;
909         struct eth_fast_path_rx_cqe *cqe_fp;
910
911 #ifdef BNX2X_STOP_ON_ERROR
912         if (unlikely(bp->panic))
913                 return 0;
914 #endif
915         if (budget <= 0)
916                 return rx_pkt;
917
918         bd_cons = fp->rx_bd_cons;
919         bd_prod = fp->rx_bd_prod;
920         bd_prod_fw = bd_prod;
921         sw_comp_cons = fp->rx_comp_cons;
922         sw_comp_prod = fp->rx_comp_prod;
923
924         comp_ring_cons = RCQ_BD(sw_comp_cons);
925         cqe = &fp->rx_comp_ring[comp_ring_cons];
926         cqe_fp = &cqe->fast_path_cqe;
927
928         DP(NETIF_MSG_RX_STATUS,
929            "queue[%d]: sw_comp_cons %u\n", fp->index, sw_comp_cons);
930
931         while (BNX2X_IS_CQE_COMPLETED(cqe_fp)) {
932                 struct sw_rx_bd *rx_buf = NULL;
933                 struct sk_buff *skb;
934                 uint8_t cqe_fp_flags;
935                 enum eth_rx_cqe_type cqe_fp_type;
936                 uint16_t len, pad, queue;
937                 uint8_t *data;
938                 uint32_t rxhash;
939                 enum pkt_hash_types rxhash_type;
940
941 #ifdef BNX2X_STOP_ON_ERROR
942                 if (unlikely(bp->panic))
943                         return 0;
944 #endif
945
946                 bd_prod = RX_BD(bd_prod);
947                 bd_cons = RX_BD(bd_cons);
948
949                 /* A rmb() is required to ensure that the CQE is not read
950                  * before it is written by the adapter DMA.  PCI ordering
951                  * rules will make sure the other fields are written before
952                  * the marker at the end of struct eth_fast_path_rx_cqe
953                  * but without rmb() a weakly ordered processor can process
954                  * stale data.  Without the barrier TPA state-machine might
955                  * enter inconsistent state and kernel stack might be
956                  * provided with incorrect packet description - these lead
957                  * to various kernel crashed.
958                  */
959                 rmb();
960
961                 cqe_fp_flags = cqe_fp->type_error_flags;
962                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
963
964                 DP(NETIF_MSG_RX_STATUS,
965                    "CQE type %x  err %x  status %x  queue %x  vlan %x  len %u\n",
966                    CQE_TYPE(cqe_fp_flags),
967                    cqe_fp_flags, cqe_fp->status_flags,
968                    le32_to_cpu(cqe_fp->rss_hash_result),
969                    le16_to_cpu(cqe_fp->vlan_tag),
970                    le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len));
971
972                 /* is this a slowpath msg? */
973                 if (unlikely(CQE_TYPE_SLOW(cqe_fp_type))) {
974                         bnx2x_sp_event(fp, cqe);
975                         goto next_cqe;
976                 }
977
978                 rx_buf = &fp->rx_buf_ring[bd_cons];
979                 data = rx_buf->data;
980
981                 if (!CQE_TYPE_FAST(cqe_fp_type)) {
982                         struct bnx2x_agg_info *tpa_info;
983                         uint16_t frag_size, pages;
984 #ifdef BNX2X_STOP_ON_ERROR
985                         /* sanity check */
986                         if (fp->disable_tpa &&
987                             (CQE_TYPE_START(cqe_fp_type) ||
988                              CQE_TYPE_STOP(cqe_fp_type)))
989                                 BNX2X_ERR("START/STOP packet while disable_tpa type %x\n",
990                                           CQE_TYPE(cqe_fp_type));
991 #endif
992
993                         if (CQE_TYPE_START(cqe_fp_type)) {
994                                 uint16_t queue = cqe_fp->queue_index;
995                                 DP(NETIF_MSG_RX_STATUS,
996                                    "calling tpa_start on queue %d\n",
997                                    queue);
998
999                                 bnx2x_tpa_start(fp, queue,
1000                                                 bd_cons, bd_prod,
1001                                                 cqe_fp);
1002
1003                                 goto next_rx;
1004                         }
1005                         queue = cqe->end_agg_cqe.queue_index;
1006                         tpa_info = &fp->tpa_info[queue];
1007                         DP(NETIF_MSG_RX_STATUS,
1008                            "calling tpa_stop on queue %d\n",
1009                            queue);
1010
1011                         frag_size = le16_to_cpu(cqe->end_agg_cqe.pkt_len) -
1012                                     tpa_info->len_on_bd;
1013
1014                         if (fp->mode == TPA_MODE_GRO)
1015                                 pages = (frag_size + tpa_info->full_page - 1) /
1016                                          tpa_info->full_page;
1017                         else
1018                                 pages = SGE_PAGE_ALIGN(frag_size) >>
1019                                         SGE_PAGE_SHIFT;
1020
1021                         bnx2x_tpa_stop(bp, fp, tpa_info, pages,
1022                                        &cqe->end_agg_cqe, comp_ring_cons);
1023 #ifdef BNX2X_STOP_ON_ERROR
1024                         if (bp->panic)
1025                                 return 0;
1026 #endif
1027
1028                         bnx2x_update_sge_prod(fp, pages, &cqe->end_agg_cqe);
1029                         goto next_cqe;
1030                 }
1031                 /* non TPA */
1032                 len = le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len);
1033                 pad = cqe_fp->placement_offset;
1034                 dma_sync_single_for_cpu(&bp->pdev->dev,
1035                                         dma_unmap_addr(rx_buf, mapping),
1036                                         pad + RX_COPY_THRESH,
1037                                         DMA_FROM_DEVICE);
1038                 pad += NET_SKB_PAD;
1039                 prefetch(data + pad); /* speedup eth_type_trans() */
1040                 /* is this an error packet? */
1041                 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1042                         DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1043                            "ERROR  flags %x  rx packet %u\n",
1044                            cqe_fp_flags, sw_comp_cons);
1045                         bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++;
1046                         goto reuse_rx;
1047                 }
1048
1049                 /* Since we don't have a jumbo ring
1050                  * copy small packets if mtu > 1500
1051                  */
1052                 if ((bp->dev->maxmtu > ETH_MAX_PACKET_SIZE) &&
1053                     (len <= RX_COPY_THRESH)) {
1054                         skb = napi_alloc_skb(&fp->napi, len);
1055                         if (skb == NULL) {
1056                                 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1057                                    "ERROR  packet dropped because of alloc failure\n");
1058                                 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1059                                 goto reuse_rx;
1060                         }
1061                         memcpy(skb->data, data + pad, len);
1062                         bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1063                 } else {
1064                         if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod,
1065                                                        0) == 0)) {
1066                                 dma_unmap_single(&bp->pdev->dev,
1067                                                  dma_unmap_addr(rx_buf, mapping),
1068                                                  fp->rx_buf_size,
1069                                                  DMA_FROM_DEVICE);
1070                                 skb = build_skb(data, fp->rx_frag_size);
1071                                 if (unlikely(!skb)) {
1072                                         bnx2x_frag_free(fp, data);
1073                                         bnx2x_fp_qstats(bp, fp)->
1074                                                         rx_skb_alloc_failed++;
1075                                         goto next_rx;
1076                                 }
1077                                 skb_reserve(skb, pad);
1078                         } else {
1079                                 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
1080                                    "ERROR  packet dropped because of alloc failure\n");
1081                                 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
1082 reuse_rx:
1083                                 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
1084                                 goto next_rx;
1085                         }
1086                 }
1087
1088                 skb_put(skb, len);
1089                 skb->protocol = eth_type_trans(skb, bp->dev);
1090
1091                 /* Set Toeplitz hash for a none-LRO skb */
1092                 rxhash = bnx2x_get_rxhash(bp, cqe_fp, &rxhash_type);
1093                 skb_set_hash(skb, rxhash, rxhash_type);
1094
1095                 skb_checksum_none_assert(skb);
1096
1097                 if (bp->dev->feat & NETIF_F_RXCSUM)
1098                         bnx2x_csum_validate(skb, cqe, fp,
1099                                             bnx2x_fp_qstats(bp, fp));
1100
1101                 skb_record_rx_queue(skb, fp->rx_queue);
1102
1103                 if (le16_to_cpu(cqe_fp->pars_flags.flags) &
1104                     PARSING_FLAGS_VLAN)
1105                         __vlan_hwaccel_put_tag(skb, cpu_to_be16(ETH_P_8021Q),
1106                                                le16_to_cpu(cqe_fp->vlan_tag));
1107
1108                 skb_mark_napi_id(skb, &fp->napi);
1109
1110                 if (bnx2x_fp_ll_polling(fp))
1111                         netif_receive_skb(skb);
1112                 else
1113                         napi_gro_receive(&fp->napi, skb);
1114 next_rx:
1115                 rx_buf->data = NULL;
1116
1117                 bd_cons = NEXT_RX_IDX(bd_cons);
1118                 bd_prod = NEXT_RX_IDX(bd_prod);
1119                 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1120                 rx_pkt++;
1121 next_cqe:
1122                 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1123                 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1124
1125                 /* mark CQE as free */
1126                 BNX2X_SEED_CQE(cqe_fp);
1127
1128                 if (rx_pkt == budget)
1129                         break;
1130
1131                 comp_ring_cons = RCQ_BD(sw_comp_cons);
1132                 cqe = &fp->rx_comp_ring[comp_ring_cons];
1133                 cqe_fp = &cqe->fast_path_cqe;
1134         } /* while */
1135
1136         fp->rx_bd_cons = bd_cons;
1137         fp->rx_bd_prod = bd_prod_fw;
1138         fp->rx_comp_cons = sw_comp_cons;
1139         fp->rx_comp_prod = sw_comp_prod;
1140
1141         /* Update producers */
1142         bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1143                              fp->rx_sge_prod);
1144
1145         fp->rx_pkt += rx_pkt;
1146         fp->rx_calls++;
1147
1148         return rx_pkt;
1149 #endif
1150 }
1151
1152 static void bnx2x_msix_fp_int(struct hw_trapframe *hw_tf, void *fp_cookie)
1153 {
1154 panic("Not implemented");
1155 #if 0 // AKAROS_PORT
1156         struct bnx2x_fastpath *fp = fp_cookie;
1157         struct bnx2x *bp = fp->bp;
1158         uint8_t cos;
1159
1160         DP(NETIF_MSG_INTR,
1161            "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
1162            fp->index, fp->fw_sb_id, fp->igu_sb_id);
1163
1164         bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1165
1166 #ifdef BNX2X_STOP_ON_ERROR
1167         if (unlikely(bp->panic))
1168                 return;
1169 #endif
1170
1171         /* Handle Rx and Tx according to MSI-X vector */
1172         for_each_cos_in_tx_queue(fp, cos)
1173                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1174
1175         prefetch(&fp->sb_running_index[SM_RX_ID]);
1176         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1177
1178         return;
1179 #endif
1180 }
1181
1182 /* HW Lock for shared dual port PHYs */
1183 void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1184 {
1185         qlock(&bp->port.phy_mutex);
1186
1187         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1188 }
1189
1190 void bnx2x_release_phy_lock(struct bnx2x *bp)
1191 {
1192         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1193
1194         qunlock(&bp->port.phy_mutex);
1195 }
1196
1197 /* calculates MF speed according to current linespeed and MF configuration */
1198 uint16_t bnx2x_get_mf_speed(struct bnx2x *bp)
1199 {
1200         uint16_t line_speed = bp->link_vars.line_speed;
1201         if (IS_MF(bp)) {
1202                 uint16_t maxCfg = bnx2x_extract_max_cfg(bp,
1203                                                    bp->mf_config[BP_VN(bp)]);
1204
1205                 /* Calculate the current MAX line speed limit for the MF
1206                  * devices
1207                  */
1208                 if (IS_MF_SI(bp))
1209                         line_speed = (line_speed * maxCfg) / 100;
1210                 else { /* SD mode */
1211                         uint16_t vn_max_rate = maxCfg * 100;
1212
1213                         if (vn_max_rate < line_speed)
1214                                 line_speed = vn_max_rate;
1215                 }
1216         }
1217
1218         return line_speed;
1219 }
1220
1221 /**
1222  * bnx2x_fill_report_data - fill link report data to report
1223  *
1224  * @bp:         driver handle
1225  * @data:       link state to update
1226  *
1227  * It uses a none-atomic bit operations because is called under the mutex.
1228  */
1229 static void bnx2x_fill_report_data(struct bnx2x *bp,
1230                                    struct bnx2x_link_report_data *data)
1231 {
1232 panic("Not implemented");
1233 #if 0 // AKAROS_PORT
1234         memset(data, 0, sizeof(*data));
1235
1236         if (IS_PF(bp)) {
1237                 /* Fill the report data: effective line speed */
1238                 data->line_speed = bnx2x_get_mf_speed(bp);
1239
1240                 /* Link is down */
1241                 if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS))
1242                         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1243                                   &data->link_report_flags);
1244
1245                 if (!BNX2X_NUM_ETH_QUEUES(bp))
1246                         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1247                                   &data->link_report_flags);
1248
1249                 /* Full DUPLEX */
1250                 if (bp->link_vars.duplex == DUPLEX_FULL)
1251                         __set_bit(BNX2X_LINK_REPORT_FD,
1252                                   &data->link_report_flags);
1253
1254                 /* Rx Flow Control is ON */
1255                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX)
1256                         __set_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1257                                   &data->link_report_flags);
1258
1259                 /* Tx Flow Control is ON */
1260                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1261                         __set_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1262                                   &data->link_report_flags);
1263         } else { /* VF */
1264                 *data = bp->vf_link_vars;
1265         }
1266 #endif
1267 }
1268
1269 /**
1270  * bnx2x_link_report - report link status to OS.
1271  *
1272  * @bp:         driver handle
1273  *
1274  * Calls the __bnx2x_link_report() under the same locking scheme
1275  * as a link/PHY state managing code to ensure a consistent link
1276  * reporting.
1277  */
1278
1279 void bnx2x_link_report(struct bnx2x *bp)
1280 {
1281         bnx2x_acquire_phy_lock(bp);
1282         __bnx2x_link_report(bp);
1283         bnx2x_release_phy_lock(bp);
1284 }
1285
1286 /**
1287  * __bnx2x_link_report - report link status to OS.
1288  *
1289  * @bp:         driver handle
1290  *
1291  * None atomic implementation.
1292  * Should be called under the phy_lock.
1293  */
1294 void __bnx2x_link_report(struct bnx2x *bp)
1295 {
1296 panic("Not implemented");
1297 #if 0 // AKAROS_PORT
1298         struct bnx2x_link_report_data cur_data;
1299
1300         /* reread mf_cfg */
1301         if (IS_PF(bp) && !CHIP_IS_E1(bp))
1302                 bnx2x_read_mf_cfg(bp);
1303
1304         /* Read the current link report info */
1305         bnx2x_fill_report_data(bp, &cur_data);
1306
1307         /* Don't report link down or exactly the same link status twice */
1308         if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) ||
1309             (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1310                       &bp->last_reported_link.link_report_flags) &&
1311              test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1312                       &cur_data.link_report_flags)))
1313                 return;
1314
1315         bp->link_cnt++;
1316
1317         /* We are going to report a new link parameters now -
1318          * remember the current data for the next time.
1319          */
1320         memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data));
1321
1322         /* propagate status to VFs */
1323         if (IS_PF(bp))
1324                 bnx2x_iov_link_update(bp);
1325
1326         if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1327                      &cur_data.link_report_flags)) {
1328                 netif_carrier_off(bp->dev);
1329                 netdev_err(bp->dev, "NIC Link is Down\n");
1330                 return;
1331         } else {
1332                 const char *duplex;
1333                 const char *flow;
1334
1335                 netif_carrier_on(bp->dev);
1336
1337                 if (test_and_clear_bit(BNX2X_LINK_REPORT_FD,
1338                                        &cur_data.link_report_flags))
1339                         duplex = "full";
1340                 else
1341                         duplex = "half";
1342
1343                 /* Handle the FC at the end so that only these flags would be
1344                  * possibly set. This way we may easily check if there is no FC
1345                  * enabled.
1346                  */
1347                 if (cur_data.link_report_flags) {
1348                         if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1349                                      &cur_data.link_report_flags)) {
1350                                 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1351                                      &cur_data.link_report_flags))
1352                                         flow = "ON - receive & transmit";
1353                                 else
1354                                         flow = "ON - receive";
1355                         } else {
1356                                 flow = "ON - transmit";
1357                         }
1358                 } else {
1359                         flow = "none";
1360                 }
1361                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
1362                             cur_data.line_speed, duplex, flow);
1363         }
1364 #endif
1365 }
1366
1367 static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
1368 {
1369         int i;
1370
1371         for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1372                 struct eth_rx_sge *sge;
1373
1374                 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
1375                 sge->addr_hi =
1376                         cpu_to_le32(U64_HI(fp->rx_sge_mapping +
1377                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1378
1379                 sge->addr_lo =
1380                         cpu_to_le32(U64_LO(fp->rx_sge_mapping +
1381                         BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1382         }
1383 }
1384
1385 static void bnx2x_free_tpa_pool(struct bnx2x *bp,
1386                                 struct bnx2x_fastpath *fp, int last)
1387 {
1388         int i;
1389
1390         for (i = 0; i < last; i++) {
1391                 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
1392                 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
1393                 uint8_t *data = first_buf->data;
1394
1395                 if (data == NULL) {
1396                         DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
1397                         continue;
1398                 }
1399                 if (tpa_info->tpa_state == BNX2X_TPA_START)
1400                         dma_unmap_single(&bp->pdev->dev,
1401                                          dma_unmap_addr(first_buf, mapping),
1402                                          fp->rx_buf_size, DMA_FROM_DEVICE);
1403                 bnx2x_frag_free(fp, data);
1404                 first_buf->data = NULL;
1405         }
1406 }
1407
1408 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
1409 {
1410         int j;
1411
1412         for_each_rx_queue_cnic(bp, j) {
1413                 struct bnx2x_fastpath *fp = &bp->fp[j];
1414
1415                 fp->rx_bd_cons = 0;
1416
1417                 /* Activate BD ring */
1418                 /* Warning!
1419                  * this will generate an interrupt (to the TSTORM)
1420                  * must only be done after chip is initialized
1421                  */
1422                 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1423                                      fp->rx_sge_prod);
1424         }
1425 }
1426
1427 void bnx2x_init_rx_rings(struct bnx2x *bp)
1428 {
1429         int func = BP_FUNC(bp);
1430         uint16_t ring_prod;
1431         int i, j;
1432
1433         /* Allocate TPA resources */
1434         for_each_eth_queue(bp, j) {
1435                 struct bnx2x_fastpath *fp = &bp->fp[j];
1436
1437                 DP(NETIF_MSG_IFUP,
1438                    "mtu %d  rx_buf_size %d\n", bp->dev->maxmtu, fp->rx_buf_size);
1439
1440                 if (!fp->disable_tpa) {
1441                         /* Fill the per-aggregation pool */
1442                         for (i = 0; i < MAX_AGG_QS(bp); i++) {
1443                                 struct bnx2x_agg_info *tpa_info =
1444                                         &fp->tpa_info[i];
1445                                 struct sw_rx_bd *first_buf =
1446                                         &tpa_info->first_buf;
1447
1448                                 first_buf->data =
1449                                         bnx2x_frag_alloc(fp, KMALLOC_WAIT);
1450                                 if (!first_buf->data) {
1451                                         BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n",
1452                                                   j);
1453                                         bnx2x_free_tpa_pool(bp, fp, i);
1454                                         fp->disable_tpa = 1;
1455                                         break;
1456                                 }
1457                                 dma_unmap_addr_set(first_buf, mapping, 0);
1458                                 tpa_info->tpa_state = BNX2X_TPA_STOP;
1459                         }
1460
1461                         /* "next page" elements initialization */
1462                         bnx2x_set_next_page_sgl(fp);
1463
1464                         /* set SGEs bit mask */
1465                         bnx2x_init_sge_ring_bit_mask(fp);
1466
1467                         /* Allocate SGEs and initialize the ring elements */
1468                         for (i = 0, ring_prod = 0;
1469                              i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
1470
1471                                 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod,
1472                                                        KMALLOC_WAIT) < 0) {
1473                                         BNX2X_ERR("was only able to allocate %d rx sges\n",
1474                                                   i);
1475                                         BNX2X_ERR("disabling TPA for queue[%d]\n",
1476                                                   j);
1477                                         /* Cleanup already allocated elements */
1478                                         bnx2x_free_rx_sge_range(bp, fp,
1479                                                                 ring_prod);
1480                                         bnx2x_free_tpa_pool(bp, fp,
1481                                                             MAX_AGG_QS(bp));
1482                                         fp->disable_tpa = 1;
1483                                         ring_prod = 0;
1484                                         break;
1485                                 }
1486                                 ring_prod = NEXT_SGE_IDX(ring_prod);
1487                         }
1488
1489                         fp->rx_sge_prod = ring_prod;
1490                 }
1491         }
1492
1493         for_each_eth_queue(bp, j) {
1494                 struct bnx2x_fastpath *fp = &bp->fp[j];
1495
1496                 fp->rx_bd_cons = 0;
1497
1498                 /* Activate BD ring */
1499                 /* Warning!
1500                  * this will generate an interrupt (to the TSTORM)
1501                  * must only be done after chip is initialized
1502                  */
1503                 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1504                                      fp->rx_sge_prod);
1505
1506                 if (j != 0)
1507                         continue;
1508
1509                 if (CHIP_IS_E1(bp)) {
1510                         REG_WR(bp, BAR_USTRORM_INTMEM +
1511                                USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
1512                                U64_LO(fp->rx_comp_mapping));
1513                         REG_WR(bp, BAR_USTRORM_INTMEM +
1514                                USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
1515                                U64_HI(fp->rx_comp_mapping));
1516                 }
1517         }
1518 }
1519
1520 static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp)
1521 {
1522 panic("Not implemented");
1523 #if 0 // AKAROS_PORT
1524         uint8_t cos;
1525         struct bnx2x *bp = fp->bp;
1526
1527         for_each_cos_in_tx_queue(fp, cos) {
1528                 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1529                 unsigned pkts_compl = 0, bytes_compl = 0;
1530
1531                 uint16_t sw_prod = txdata->tx_pkt_prod;
1532                 uint16_t sw_cons = txdata->tx_pkt_cons;
1533
1534                 while (sw_cons != sw_prod) {
1535                         bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
1536                                           &pkts_compl, &bytes_compl);
1537                         sw_cons++;
1538                 }
1539
1540                 netdev_tx_reset_queue(
1541                         netdev_get_tx_queue(bp->dev,
1542                                             txdata->txq_index));
1543         }
1544 #endif
1545 }
1546
1547 static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp)
1548 {
1549         int i;
1550
1551         for_each_tx_queue_cnic(bp, i) {
1552                 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1553         }
1554 }
1555
1556 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
1557 {
1558         int i;
1559
1560         for_each_eth_queue(bp, i) {
1561                 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1562         }
1563 }
1564
1565 static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp)
1566 {
1567         struct bnx2x *bp = fp->bp;
1568         int i;
1569
1570         /* ring wasn't allocated */
1571         if (fp->rx_buf_ring == NULL)
1572                 return;
1573
1574         for (i = 0; i < NUM_RX_BD; i++) {
1575                 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
1576                 uint8_t *data = rx_buf->data;
1577
1578                 if (data == NULL)
1579                         continue;
1580                 dma_unmap_single(&bp->pdev->dev,
1581                                  dma_unmap_addr(rx_buf, mapping),
1582                                  fp->rx_buf_size, DMA_FROM_DEVICE);
1583
1584                 rx_buf->data = NULL;
1585                 bnx2x_frag_free(fp, data);
1586         }
1587 }
1588
1589 static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp)
1590 {
1591         int j;
1592
1593         for_each_rx_queue_cnic(bp, j) {
1594                 bnx2x_free_rx_bds(&bp->fp[j]);
1595         }
1596 }
1597
1598 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
1599 {
1600         int j;
1601
1602         for_each_eth_queue(bp, j) {
1603                 struct bnx2x_fastpath *fp = &bp->fp[j];
1604
1605                 bnx2x_free_rx_bds(fp);
1606
1607                 if (!fp->disable_tpa)
1608                         bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
1609         }
1610 }
1611
1612 static void bnx2x_free_skbs_cnic(struct bnx2x *bp)
1613 {
1614         bnx2x_free_tx_skbs_cnic(bp);
1615         bnx2x_free_rx_skbs_cnic(bp);
1616 }
1617
1618 void bnx2x_free_skbs(struct bnx2x *bp)
1619 {
1620         bnx2x_free_tx_skbs(bp);
1621         bnx2x_free_rx_skbs(bp);
1622 }
1623
1624 void bnx2x_update_max_mf_config(struct bnx2x *bp, uint32_t value)
1625 {
1626         /* load old values */
1627         uint32_t mf_cfg = bp->mf_config[BP_VN(bp)];
1628
1629         if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
1630                 /* leave all but MAX value */
1631                 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
1632
1633                 /* set new MAX value */
1634                 mf_cfg |= (value << FUNC_MF_CFG_MAX_BW_SHIFT)
1635                                 & FUNC_MF_CFG_MAX_BW_MASK;
1636
1637                 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
1638         }
1639 }
1640
1641 /**
1642  * bnx2x_free_msix_irqs - free previously requested MSI-X IRQ vectors
1643  *
1644  * @bp:         driver handle
1645  * @nvecs:      number of vectors to be released
1646  */
1647 static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
1648 {
1649 panic("Not implemented");
1650 #if 0 // AKAROS_PORT
1651         int i, offset = 0;
1652
1653         if (nvecs == offset)
1654                 return;
1655
1656         /* VFs don't have a default SB */
1657         if (IS_PF(bp)) {
1658                 free_irq(bp->msix_table[offset].vector, bp->dev);
1659                 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
1660                    bp->msix_table[offset].vector);
1661                 offset++;
1662         }
1663
1664         if (CNIC_SUPPORT(bp)) {
1665                 if (nvecs == offset)
1666                         return;
1667                 offset++;
1668         }
1669
1670         for_each_eth_queue(bp, i) {
1671                 if (nvecs == offset)
1672                         return;
1673                 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n",
1674                    i, bp->msix_table[offset].vector);
1675
1676                 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
1677         }
1678 #endif
1679 }
1680
1681 void bnx2x_free_irq(struct bnx2x *bp)
1682 {
1683 panic("Not implemented");
1684 #if 0 // AKAROS_PORT
1685         if (bp->flags & USING_MSIX_FLAG &&
1686             !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1687                 int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp);
1688
1689                 /* vfs don't have a default status block */
1690                 if (IS_PF(bp))
1691                         nvecs++;
1692
1693                 bnx2x_free_msix_irqs(bp, nvecs);
1694         } else {
1695                 free_irq(bp->dev->irq, bp->dev);
1696         }
1697 #endif
1698 }
1699
1700 int bnx2x_enable_msix(struct bnx2x *bp)
1701 {
1702         int msix_vec = 0, i, rc;
1703 panic("Not implemented");
1704 #if 0 // AKAROS_PORT
1705         /* VFs don't have a default status block */
1706         if (IS_PF(bp)) {
1707                 bp->msix_table[msix_vec].entry = msix_vec;
1708                 BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n",
1709                                bp->msix_table[0].entry);
1710                 msix_vec++;
1711         }
1712
1713         /* Cnic requires an msix vector for itself */
1714         if (CNIC_SUPPORT(bp)) {
1715                 bp->msix_table[msix_vec].entry = msix_vec;
1716                 BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n",
1717                                msix_vec, bp->msix_table[msix_vec].entry);
1718                 msix_vec++;
1719         }
1720
1721         /* We need separate vectors for ETH queues only (not FCoE) */
1722         for_each_eth_queue(bp, i) {
1723                 bp->msix_table[msix_vec].entry = msix_vec;
1724                 BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n",
1725                                msix_vec, msix_vec, i);
1726                 msix_vec++;
1727         }
1728
1729         DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n",
1730            msix_vec);
1731
1732         rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0],
1733                                    BNX2X_MIN_MSIX_VEC_CNT(bp), msix_vec);
1734         /*
1735          * reconfigure number of tx/rx queues according to available
1736          * MSI-X vectors
1737          */
1738         if (rc == -ENOSPC) {
1739                 /* Get by with single vector */
1740                 rc = pci_enable_msix_range(bp->pdev, &bp->msix_table[0], 1, 1);
1741                 if (rc < 0) {
1742                         BNX2X_DEV_INFO("Single MSI-X is not attainable rc %d\n",
1743                                        rc);
1744                         goto no_msix;
1745                 }
1746
1747                 BNX2X_DEV_INFO("Using single MSI-X vector\n");
1748                 bp->flags |= USING_SINGLE_MSIX_FLAG;
1749
1750                 BNX2X_DEV_INFO("set number of queues to 1\n");
1751                 bp->num_ethernet_queues = 1;
1752                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1753         } else if (rc < 0) {
1754                 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1755                 goto no_msix;
1756         } else if (rc < msix_vec) {
1757                 /* how less vectors we will have? */
1758                 int diff = msix_vec - rc;
1759
1760                 BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc);
1761
1762                 /*
1763                  * decrease number of queues by number of unallocated entries
1764                  */
1765                 bp->num_ethernet_queues -= diff;
1766                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1767
1768                 BNX2X_DEV_INFO("New queue configuration set: %d\n",
1769                                bp->num_queues);
1770         }
1771
1772         bp->flags |= USING_MSIX_FLAG;
1773
1774         return 0;
1775
1776 no_msix:
1777         /* fall to INTx if not enough memory */
1778         if (rc == -ENOMEM)
1779                 bp->flags |= DISABLE_MSI_FLAG;
1780
1781         return rc;
1782 #endif
1783 }
1784
1785 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1786 {
1787 panic("Not implemented");
1788 #if 0 // AKAROS_PORT
1789         int i, rc, offset = 0;
1790
1791         /* no default status block for vf */
1792         if (IS_PF(bp)) {
1793                 rc = register_irq(bp->msix_table[offset++].vector,
1794                                   bnx2x_msix_sp_int, bp->dev,
1795                                   pci_to_tbdf(bp->pdev));
1796                 if (rc) {
1797                         BNX2X_ERR("request sp irq failed\n");
1798                         return -EBUSY;
1799                 }
1800         }
1801
1802         if (CNIC_SUPPORT(bp))
1803                 offset++;
1804
1805         for_each_eth_queue(bp, i) {
1806                 struct bnx2x_fastpath *fp = &bp->fp[i];
1807                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1808                          bp->dev->name, i);
1809
1810                 rc = register_irq(bp->msix_table[offset].vector,
1811                                   bnx2x_msix_fp_int, fp, pci_to_tbdf(bp->pdev));
1812                 if (rc) {
1813                         BNX2X_ERR("request fp #%d irq (%d) failed  rc %d\n", i,
1814                               bp->msix_table[offset].vector, rc);
1815                         bnx2x_free_msix_irqs(bp, offset);
1816                         return -EBUSY;
1817                 }
1818
1819                 offset++;
1820         }
1821
1822         i = BNX2X_NUM_ETH_QUEUES(bp);
1823         if (IS_PF(bp)) {
1824                 offset = 1 + CNIC_SUPPORT(bp);
1825                 netdev_info(bp->dev,
1826                             "using MSI-X  IRQs: sp %d  fp[%d] %d ... fp[%d] %d\n",
1827                             bp->msix_table[0].vector,
1828                             0, bp->msix_table[offset].vector,
1829                             i - 1, bp->msix_table[offset + i - 1].vector);
1830         } else {
1831                 offset = CNIC_SUPPORT(bp);
1832                 netdev_info(bp->dev,
1833                             "using MSI-X  IRQs: fp[%d] %d ... fp[%d] %d\n",
1834                             0, bp->msix_table[offset].vector,
1835                             i - 1, bp->msix_table[offset + i - 1].vector);
1836         }
1837         return 0;
1838 #endif
1839 }
1840
1841 int bnx2x_enable_msi(struct bnx2x *bp)
1842 {
1843 panic("Not implemented");
1844 #if 0 // AKAROS_PORT
1845         int rc;
1846
1847         rc = pci_enable_msi(bp->pdev);
1848         if (rc) {
1849                 BNX2X_DEV_INFO("MSI is not attainable\n");
1850                 return -1;
1851         }
1852         bp->flags |= USING_MSI_FLAG;
1853
1854         return 0;
1855 #endif
1856 }
1857
1858 static int bnx2x_req_irq(struct bnx2x *bp)
1859 {
1860         unsigned long flags;
1861 panic("Not implemented");
1862 #if 0 // AKAROS_PORT
1863         unsigned int irq;
1864
1865         if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG))
1866                 flags = 0;
1867         else
1868                 flags = IRQF_SHARED;
1869
1870         if (bp->flags & USING_MSIX_FLAG)
1871                 irq = bp->msix_table[0].vector;
1872         else
1873                 irq = bp->pdev->irq;
1874
1875         return register_irq(irq, bnx2x_interrupt, bp->dev,
1876                             pci_to_tbdf(bp->pdev));
1877 #endif
1878 }
1879
1880 static int bnx2x_setup_irqs(struct bnx2x *bp)
1881 {
1882         int rc = 0;
1883 panic("Not implemented");
1884 #if 0 // AKAROS_PORT
1885         if (bp->flags & USING_MSIX_FLAG &&
1886             !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1887                 rc = bnx2x_req_msix_irqs(bp);
1888                 if (rc)
1889                         return rc;
1890         } else {
1891                 rc = bnx2x_req_irq(bp);
1892                 if (rc) {
1893                         BNX2X_ERR("IRQ request failed  rc %d, aborting\n", rc);
1894                         return rc;
1895                 }
1896                 if (bp->flags & USING_MSI_FLAG) {
1897                         bp->dev->irq = bp->pdev->irq;
1898                         netdev_info(bp->dev, "using MSI IRQ %d\n",
1899                                     bp->dev->irq);
1900                 }
1901                 if (bp->flags & USING_MSIX_FLAG) {
1902                         bp->dev->irq = bp->msix_table[0].vector;
1903                         netdev_info(bp->dev, "using MSIX IRQ %d\n",
1904                                     bp->dev->irq);
1905                 }
1906         }
1907
1908         return 0;
1909 #endif
1910 }
1911
1912 static void bnx2x_napi_enable_cnic(struct bnx2x *bp)
1913 {
1914 panic("Not implemented");
1915 #if 0 // AKAROS_PORT
1916         int i;
1917
1918         for_each_rx_queue_cnic(bp, i) {
1919                 bnx2x_fp_init_lock(&bp->fp[i]);
1920                 napi_enable(&bnx2x_fp(bp, i, napi));
1921         }
1922 #endif
1923 }
1924
1925 static void bnx2x_napi_enable(struct bnx2x *bp)
1926 {
1927 panic("Not implemented");
1928 #if 0 // AKAROS_PORT
1929         int i;
1930
1931         for_each_eth_queue(bp, i) {
1932                 bnx2x_fp_init_lock(&bp->fp[i]);
1933                 napi_enable(&bnx2x_fp(bp, i, napi));
1934         }
1935 #endif
1936 }
1937
1938 static void bnx2x_napi_disable_cnic(struct bnx2x *bp)
1939 {
1940 panic("Not implemented");
1941 #if 0 // AKAROS_PORT
1942         int i;
1943
1944         for_each_rx_queue_cnic(bp, i) {
1945                 napi_disable(&bnx2x_fp(bp, i, napi));
1946                 while (!bnx2x_fp_ll_disable(&bp->fp[i]))
1947                         kthread_usleep(1000);
1948         }
1949 #endif
1950 }
1951
1952 static void bnx2x_napi_disable(struct bnx2x *bp)
1953 {
1954 panic("Not implemented");
1955 #if 0 // AKAROS_PORT
1956         int i;
1957
1958         for_each_eth_queue(bp, i) {
1959                 napi_disable(&bnx2x_fp(bp, i, napi));
1960                 while (!bnx2x_fp_ll_disable(&bp->fp[i]))
1961                         kthread_usleep(1000);
1962         }
1963 #endif
1964 }
1965
1966 void bnx2x_netif_start(struct bnx2x *bp)
1967 {
1968 panic("Not implemented");
1969 #if 0 // AKAROS_PORT
1970         if (netif_running(bp->dev)) {
1971                 bnx2x_napi_enable(bp);
1972                 if (CNIC_LOADED(bp))
1973                         bnx2x_napi_enable_cnic(bp);
1974                 bnx2x_int_enable(bp);
1975                 if (bp->state == BNX2X_STATE_OPEN)
1976                         netif_tx_wake_all_queues(bp->dev);
1977         }
1978 #endif
1979 }
1980
1981 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
1982 {
1983         bnx2x_int_disable_sync(bp, disable_hw);
1984         bnx2x_napi_disable(bp);
1985         if (CNIC_LOADED(bp))
1986                 bnx2x_napi_disable_cnic(bp);
1987 }
1988
1989 uint16_t bnx2x_select_queue(struct ether *dev, struct sk_buff *skb,
1990                        void *accel_priv, select_queue_fallback_t fallback)
1991 {
1992 panic("Not implemented");
1993 #if 0 // AKAROS_PORT
1994         struct bnx2x *bp = netdev_priv(dev);
1995
1996         if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
1997                 struct ethhdr *hdr = (struct ethhdr *)skb->data;
1998                 uint16_t ether_type = be16_to_cpu(hdr->h_proto);
1999
2000                 /* Skip VLAN tag if present */
2001                 if (ether_type == ETH_P_8021Q) {
2002                         struct vlan_ethhdr *vhdr =
2003                                 (struct vlan_ethhdr *)skb->data;
2004
2005                         ether_type = be16_to_cpu(vhdr->h_vlan_encapsulated_proto);
2006                 }
2007
2008                 /* If ethertype is FCoE or FIP - use FCoE ring */
2009                 if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP))
2010                         return bnx2x_fcoe_tx(bp, txq_index);
2011         }
2012
2013         /* select a non-FCoE queue */
2014         return fallback(dev, skb) % BNX2X_NUM_ETH_QUEUES(bp);
2015 #endif
2016 }
2017
2018 void bnx2x_set_num_queues(struct bnx2x *bp)
2019 {
2020         /* RSS queues */
2021         bp->num_ethernet_queues = bnx2x_calc_num_queues(bp);
2022
2023         /* override in STORAGE SD modes */
2024         if (IS_MF_STORAGE_ONLY(bp))
2025                 bp->num_ethernet_queues = 1;
2026
2027         /* Add special queues */
2028         bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */
2029         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
2030
2031         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
2032 }
2033
2034 /**
2035  * bnx2x_set_real_num_queues - configure netdev->real_num_[tx,rx]_queues
2036  *
2037  * @bp:         Driver handle
2038  *
2039  * We currently support for at most 16 Tx queues for each CoS thus we will
2040  * allocate a multiple of 16 for ETH L2 rings according to the value of the
2041  * bp->max_cos.
2042  *
2043  * If there is an FCoE L2 queue the appropriate Tx queue will have the next
2044  * index after all ETH L2 indices.
2045  *
2046  * If the actual number of Tx queues (for each CoS) is less than 16 then there
2047  * will be the holes at the end of each group of 16 ETh L2 indices (0..15,
2048  * 16..31,...) with indices that are not coupled with any real Tx queue.
2049  *
2050  * The proper configuration of skb->queue_mapping is handled by
2051  * bnx2x_select_queue() and __skb_tx_hash().
2052  *
2053  * bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash()
2054  * will return a proper Tx index if TC is enabled (netdev->num_tc > 0).
2055  */
2056 static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic)
2057 {
2058 panic("Not implemented");
2059 #if 0 // AKAROS_PORT
2060         int rc, tx, rx;
2061
2062         tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos;
2063         rx = BNX2X_NUM_ETH_QUEUES(bp);
2064
2065 /* account for fcoe queue */
2066         if (include_cnic && !NO_FCOE(bp)) {
2067                 rx++;
2068                 tx++;
2069         }
2070
2071         rc = netif_set_real_num_tx_queues(bp->dev, tx);
2072         if (rc) {
2073                 BNX2X_ERR("Failed to set real number of Tx queues: %d\n", rc);
2074                 return rc;
2075         }
2076         rc = netif_set_real_num_rx_queues(bp->dev, rx);
2077         if (rc) {
2078                 BNX2X_ERR("Failed to set real number of Rx queues: %d\n", rc);
2079                 return rc;
2080         }
2081
2082         DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n",
2083                           tx, rx);
2084
2085         return rc;
2086 #endif
2087 }
2088
2089 static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
2090 {
2091 panic("Not implemented");
2092 #if 0 // AKAROS_PORT
2093         int i;
2094
2095         for_each_queue(bp, i) {
2096                 struct bnx2x_fastpath *fp = &bp->fp[i];
2097                 uint32_t mtu;
2098
2099                 /* Always use a mini-jumbo MTU for the FCoE L2 ring */
2100                 if (IS_FCOE_IDX(i))
2101                         /*
2102                          * Although there are no IP frames expected to arrive to
2103                          * this ring we still want to add an
2104                          * IP_HEADER_ALIGNMENT_PADDING to prevent a buffer
2105                          * overrun attack.
2106                          */
2107                         mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2108                 else
2109                         mtu = bp->dev->maxmtu;
2110                 fp->rx_buf_size = BNX2X_FW_RX_ALIGN_START +
2111                                   IP_HEADER_ALIGNMENT_PADDING +
2112                                   ETH_OVREHEAD +
2113                                   mtu +
2114                                   BNX2X_FW_RX_ALIGN_END;
2115                 /* Note : rx_buf_size doesn't take into account NET_SKB_PAD */
2116                 if (fp->rx_buf_size + NET_SKB_PAD <= PAGE_SIZE)
2117                         fp->rx_frag_size = fp->rx_buf_size + NET_SKB_PAD;
2118                 else
2119                         fp->rx_frag_size = 0;
2120         }
2121 #endif
2122 }
2123
2124 static int bnx2x_init_rss(struct bnx2x *bp)
2125 {
2126 panic("Not implemented");
2127 #if 0 // AKAROS_PORT
2128         int i;
2129         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2130
2131         /* Prepare the initial contents for the indirection table if RSS is
2132          * enabled
2133          */
2134         for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++)
2135                 bp->rss_conf_obj.ind_table[i] =
2136                         bp->fp->cl_id +
2137                         ethtool_rxfh_indir_default(i, num_eth_queues);
2138
2139         /*
2140          * For 57710 and 57711 SEARCHER configuration (rss_keys) is
2141          * per-port, so if explicit configuration is needed , do it only
2142          * for a PMF.
2143          *
2144          * For 57712 and newer on the other hand it's a per-function
2145          * configuration.
2146          */
2147         return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp));
2148 #endif
2149 }
2150
2151 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
2152               bool config_hash, bool enable)
2153 {
2154 panic("Not implemented");
2155 #if 0 // AKAROS_PORT
2156         struct bnx2x_config_rss_params params = {NULL};
2157
2158         /* Although RSS is meaningless when there is a single HW queue we
2159          * still need it enabled in order to have HW Rx hash generated.
2160          *
2161          * if (!is_eth_multi(bp))
2162          *      bp->multi_mode = ETH_RSS_MODE_DISABLED;
2163          */
2164
2165         params.rss_obj = rss_obj;
2166
2167         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2168
2169         if (enable) {
2170                 __set_bit(BNX2X_RSS_MODE_REGULAR, &params.rss_flags);
2171
2172                 /* RSS configuration */
2173                 __set_bit(BNX2X_RSS_IPV4, &params.rss_flags);
2174                 __set_bit(BNX2X_RSS_IPV4_TCP, &params.rss_flags);
2175                 __set_bit(BNX2X_RSS_IPV6, &params.rss_flags);
2176                 __set_bit(BNX2X_RSS_IPV6_TCP, &params.rss_flags);
2177                 if (rss_obj->udp_rss_v4)
2178                         __set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags);
2179                 if (rss_obj->udp_rss_v6)
2180                         __set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);
2181
2182                 if (!CHIP_IS_E1x(bp))
2183                         /* valid only for TUNN_MODE_GRE tunnel mode */
2184                         __set_bit(BNX2X_RSS_GRE_INNER_HDRS, &params.rss_flags);
2185         } else {
2186                 __set_bit(BNX2X_RSS_MODE_DISABLED, &params.rss_flags);
2187         }
2188
2189         /* Hash bits */
2190         params.rss_result_mask = MULTI_MASK;
2191
2192         memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
2193
2194         if (config_hash) {
2195                 /* RSS keys */
2196                 netdev_rss_key_fill(params.rss_key, T_ETH_RSS_KEY * 4);
2197                 __set_bit(BNX2X_RSS_SET_SRCH, &params.rss_flags);
2198         }
2199
2200         if (IS_PF(bp))
2201                 return bnx2x_config_rss(bp, &params);
2202         else
2203                 return bnx2x_vfpf_config_rss(bp, &params);
2204 #endif
2205 }
2206
2207 static int bnx2x_init_hw(struct bnx2x *bp, uint32_t load_code)
2208 {
2209         struct bnx2x_func_state_params func_params = {NULL};
2210
2211         /* Prepare parameters for function state transitions */
2212         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
2213
2214         func_params.f_obj = &bp->func_obj;
2215         func_params.cmd = BNX2X_F_CMD_HW_INIT;
2216
2217         func_params.params.hw_init.load_phase = load_code;
2218
2219         return bnx2x_func_state_change(bp, &func_params);
2220 }
2221
2222 /*
2223  * Cleans the object that have internal lists without sending
2224  * ramrods. Should be run when interrupts are disabled.
2225  */
2226 void bnx2x_squeeze_objects(struct bnx2x *bp)
2227 {
2228         int rc;
2229         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
2230         struct bnx2x_mcast_ramrod_params rparam = {NULL};
2231         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
2232
2233         /***************** Cleanup MACs' object first *************************/
2234
2235         /* Wait for completion of requested */
2236         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2237         /* Perform a dry cleanup */
2238         __set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
2239
2240         /* Clean ETH primary MAC */
2241         __set_bit(BNX2X_ETH_MAC, &vlan_mac_flags);
2242         rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags,
2243                                  &ramrod_flags);
2244         if (rc != 0)
2245                 BNX2X_ERR("Failed to clean ETH MACs: %d\n", rc);
2246
2247         /* Cleanup UC list */
2248         vlan_mac_flags = 0;
2249         __set_bit(BNX2X_UC_LIST_MAC, &vlan_mac_flags);
2250         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags,
2251                                  &ramrod_flags);
2252         if (rc != 0)
2253                 BNX2X_ERR("Failed to clean UC list MACs: %d\n", rc);
2254
2255         /***************** Now clean mcast object *****************************/
2256         rparam.mcast_obj = &bp->mcast_obj;
2257         __set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
2258
2259         /* Add a DEL command... - Since we're doing a driver cleanup only,
2260          * we take a lock surrounding both the initial send and the CONTs,
2261          * as we don't want a true completion to disrupt us in the middle.
2262          */
2263         qlock(&bp->dev->qlock);
2264         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
2265         if (rc < 0)
2266                 BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n",
2267                           rc);
2268
2269         /* ...and wait until all pending commands are cleared */
2270         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2271         while (rc != 0) {
2272                 if (rc < 0) {
2273                         BNX2X_ERR("Failed to clean multi-cast object: %d\n",
2274                                   rc);
2275                         qunlock(&bp->dev->qlock);
2276                         return;
2277                 }
2278
2279                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2280         }
2281         qunlock(&bp->dev->qlock);
2282 }
2283
2284 #ifndef BNX2X_STOP_ON_ERROR
2285 #define LOAD_ERROR_EXIT(bp, label) \
2286         do { \
2287                 (bp)->state = BNX2X_STATE_ERROR; \
2288                 goto label; \
2289         } while (0)
2290
2291 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2292         do { \
2293                 bp->cnic_loaded = false; \
2294                 goto label; \
2295         } while (0)
2296 #else /*BNX2X_STOP_ON_ERROR*/
2297 #define LOAD_ERROR_EXIT(bp, label) \
2298         do { \
2299                 (bp)->state = BNX2X_STATE_ERROR; \
2300                 (bp)->panic = 1; \
2301                 return -EBUSY; \
2302         } while (0)
2303 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2304         do { \
2305                 bp->cnic_loaded = false; \
2306                 (bp)->panic = 1; \
2307                 return -EBUSY; \
2308         } while (0)
2309 #endif /*BNX2X_STOP_ON_ERROR*/
2310
2311 static void bnx2x_free_fw_stats_mem(struct bnx2x *bp)
2312 {
2313         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
2314                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2315         return;
2316 }
2317
2318 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
2319 {
2320         int num_groups, vf_headroom = 0;
2321         int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
2322
2323         /* number of queues for statistics is number of eth queues + FCoE */
2324         uint8_t num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
2325
2326         /* Total number of FW statistics requests =
2327          * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper
2328          * and fcoe l2 queue) stats + num of queues (which includes another 1
2329          * for fcoe l2 queue if applicable)
2330          */
2331         bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
2332
2333         /* vf stats appear in the request list, but their data is allocated by
2334          * the VFs themselves. We don't include them in the bp->fw_stats_num as
2335          * it is used to determine where to place the vf stats queries in the
2336          * request struct
2337          */
2338         if (IS_SRIOV(bp))
2339                 vf_headroom = bnx2x_vf_headroom(bp);
2340
2341         /* Request is built from stats_query_header and an array of
2342          * stats_query_cmd_group each of which contains
2343          * STATS_QUERY_CMD_COUNT rules. The real number or requests is
2344          * configured in the stats_query_header.
2345          */
2346         num_groups =
2347                 (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +
2348                  (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?
2349                  1 : 0));
2350
2351         DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n",
2352            bp->fw_stats_num, vf_headroom, num_groups);
2353         bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
2354                 num_groups * sizeof(struct stats_query_cmd_group);
2355
2356         /* Data for statistics requests + stats_counter
2357          * stats_counter holds per-STORM counters that are incremented
2358          * when STORM has finished with the current request.
2359          * memory for FCoE offloaded statistics are counted anyway,
2360          * even if they will not be sent.
2361          * VF stats are not accounted for here as the data of VF stats is stored
2362          * in memory allocated by the VF, not here.
2363          */
2364         bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
2365                 sizeof(struct per_pf_stats) +
2366                 sizeof(struct fcoe_statistics_params) +
2367                 sizeof(struct per_queue_stats) * num_queue_stats +
2368                 sizeof(struct stats_counter);
2369
2370         bp->fw_stats = BNX2X_PCI_ALLOC(&bp->fw_stats_mapping,
2371                                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2372         if (!bp->fw_stats)
2373                 goto alloc_mem_err;
2374
2375         /* Set shortcuts */
2376         bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
2377         bp->fw_stats_req_mapping = bp->fw_stats_mapping;
2378         bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
2379                 ((uint8_t *)bp->fw_stats + bp->fw_stats_req_sz);
2380         bp->fw_stats_data_mapping = bp->fw_stats_mapping +
2381                 bp->fw_stats_req_sz;
2382
2383         DP(BNX2X_MSG_SP, "statistics request base address set to %x %x\n",
2384            U64_HI(bp->fw_stats_req_mapping),
2385            U64_LO(bp->fw_stats_req_mapping));
2386         DP(BNX2X_MSG_SP, "statistics data base address set to %x %x\n",
2387            U64_HI(bp->fw_stats_data_mapping),
2388            U64_LO(bp->fw_stats_data_mapping));
2389         return 0;
2390
2391 alloc_mem_err:
2392         bnx2x_free_fw_stats_mem(bp);
2393         BNX2X_ERR("Can't allocate FW stats memory\n");
2394         return -ENOMEM;
2395 }
2396
2397 /* send load request to mcp and analyze response */
2398 static int bnx2x_nic_load_request(struct bnx2x *bp, uint32_t *load_code)
2399 {
2400 panic("Not implemented");
2401 #if 0 // AKAROS_PORT
2402         uint32_t param;
2403
2404         /* init fw_seq */
2405         bp->fw_seq =
2406                 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
2407                  DRV_MSG_SEQ_NUMBER_MASK);
2408         BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
2409
2410         /* Get current FW pulse sequence */
2411         bp->fw_drv_pulse_wr_seq =
2412                 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) &
2413                  DRV_PULSE_SEQ_MASK);
2414         BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
2415
2416         param = DRV_MSG_CODE_LOAD_REQ_WITH_LFA;
2417
2418         if (IS_MF_SD(bp) && bnx2x_port_after_undi(bp))
2419                 param |= DRV_MSG_CODE_LOAD_REQ_FORCE_LFA;
2420
2421         /* load request */
2422         (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, param);
2423
2424         /* if mcp fails to respond we must abort */
2425         if (!(*load_code)) {
2426                 BNX2X_ERR("MCP response failure, aborting\n");
2427                 return -EBUSY;
2428         }
2429
2430         /* If mcp refused (e.g. other port is in diagnostic mode) we
2431          * must abort
2432          */
2433         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2434                 BNX2X_ERR("MCP refused load request, aborting\n");
2435                 return -EBUSY;
2436         }
2437         return 0;
2438 #endif
2439 }
2440
2441 /* check whether another PF has already loaded FW to chip. In
2442  * virtualized environments a pf from another VM may have already
2443  * initialized the device including loading FW
2444  */
2445 int bnx2x_compare_fw_ver(struct bnx2x *bp, uint32_t load_code,
2446                          bool print_err)
2447 {
2448 panic("Not implemented");
2449 #if 0 // AKAROS_PORT
2450         /* is another pf loaded on this engine? */
2451         if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
2452             load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
2453                 /* build my FW version dword */
2454                 uint32_t my_fw = (BCM_5710_FW_MAJOR_VERSION) +
2455                         (BCM_5710_FW_MINOR_VERSION << 8) +
2456                         (BCM_5710_FW_REVISION_VERSION << 16) +
2457                         (BCM_5710_FW_ENGINEERING_VERSION << 24);
2458
2459                 /* read loaded FW from chip */
2460                 uint32_t loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
2461
2462                 DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n",
2463                    loaded_fw, my_fw);
2464
2465                 /* abort nic load if version mismatch */
2466                 if (my_fw != loaded_fw) {
2467                         if (print_err)
2468                                 BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. Aborting\n",
2469                                           loaded_fw, my_fw);
2470                         else
2471                                 BNX2X_DEV_INFO("bnx2x with FW %x was already loaded which mismatches my %x FW, possibly due to MF UNDI\n",
2472                                                loaded_fw, my_fw);
2473                         return -EBUSY;
2474                 }
2475         }
2476         return 0;
2477 #endif
2478 }
2479
2480 /* returns the "mcp load_code" according to global load_count array */
2481 static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
2482 {
2483         int path = BP_PATH(bp);
2484
2485         DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d]      %d, %d, %d\n",
2486            path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2487            bnx2x_load_count[path][2]);
2488         bnx2x_load_count[path][0]++;
2489         bnx2x_load_count[path][1 + port]++;
2490         DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d]  %d, %d, %d\n",
2491            path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
2492            bnx2x_load_count[path][2]);
2493         if (bnx2x_load_count[path][0] == 1)
2494                 return FW_MSG_CODE_DRV_LOAD_COMMON;
2495         else if (bnx2x_load_count[path][1 + port] == 1)
2496                 return FW_MSG_CODE_DRV_LOAD_PORT;
2497         else
2498                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
2499 }
2500
2501 /* mark PMF if applicable */
2502 static void bnx2x_nic_load_pmf(struct bnx2x *bp, uint32_t load_code)
2503 {
2504         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2505             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2506             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2507                 bp->port.pmf = 1;
2508                 /* We need the barrier to ensure the ordering between the
2509                  * writing to bp->port.pmf here and reading it from the
2510                  * bnx2x_periodic_task().
2511                  */
2512                 mb();
2513         } else {
2514                 bp->port.pmf = 0;
2515         }
2516
2517         DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2518 }
2519
2520 static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code)
2521 {
2522         if (((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2523              (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP)) &&
2524             (bp->common.shmem2_base)) {
2525                 if (SHMEM2_HAS(bp, dcc_support))
2526                         SHMEM2_WR(bp, dcc_support,
2527                                   (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
2528                                    SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
2529                 if (SHMEM2_HAS(bp, afex_driver_support))
2530                         SHMEM2_WR(bp, afex_driver_support,
2531                                   SHMEM_AFEX_SUPPORTED_VERSION_ONE);
2532         }
2533
2534         /* Set AFEX default VLAN tag to an invalid value */
2535         bp->afex_def_vlan_tag = -1;
2536 }
2537
2538 /**
2539  * bnx2x_bz_fp - zero content of the fastpath structure.
2540  *
2541  * @bp:         driver handle
2542  * @index:      fastpath index to be zeroed
2543  *
2544  * Makes sure the contents of the bp->fp[index].napi is kept
2545  * intact.
2546  */
2547 static void bnx2x_bz_fp(struct bnx2x *bp, int index)
2548 {
2549         struct bnx2x_fastpath *fp = &bp->fp[index];
2550         int cos;
2551         struct napi_struct orig_napi = fp->napi;
2552         struct bnx2x_agg_info *orig_tpa_info = fp->tpa_info;
2553
2554         /* bzero bnx2x_fastpath contents */
2555         if (fp->tpa_info)
2556                 memset(fp->tpa_info, 0, ETH_MAX_AGGREGATION_QUEUES_E1H_E2 *
2557                        sizeof(struct bnx2x_agg_info));
2558         memset(fp, 0, sizeof(*fp));
2559
2560         /* Restore the NAPI object as it has been already initialized */
2561         fp->napi = orig_napi;
2562         fp->tpa_info = orig_tpa_info;
2563         fp->bp = bp;
2564         fp->index = index;
2565         if (IS_ETH_FP(fp))
2566                 fp->max_cos = bp->max_cos;
2567         else
2568                 /* Special queues support only one CoS */
2569                 fp->max_cos = 1;
2570
2571         /* Init txdata pointers */
2572         if (IS_FCOE_FP(fp))
2573                 fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)];
2574         if (IS_ETH_FP(fp))
2575                 for_each_cos_in_tx_queue(fp, cos)
2576                         fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos *
2577                                 BNX2X_NUM_ETH_QUEUES(bp) + index];
2578
2579         /* set the tpa flag for each queue. The tpa flag determines the queue
2580          * minimal size so it must be set prior to queue memory allocation
2581          */
2582         fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG ||
2583                                   (bp->flags & GRO_ENABLE_FLAG &&
2584                                    bnx2x_mtu_allows_gro(bp->dev->maxmtu)));
2585         if (bp->flags & TPA_ENABLE_FLAG)
2586                 fp->mode = TPA_MODE_LRO;
2587         else if (bp->flags & GRO_ENABLE_FLAG)
2588                 fp->mode = TPA_MODE_GRO;
2589
2590         /* We don't want TPA on an FCoE L2 ring */
2591         if (IS_FCOE_FP(fp))
2592                 fp->disable_tpa = 1;
2593 }
2594
2595 int bnx2x_load_cnic(struct bnx2x *bp)
2596 {
2597         int i, rc, port = BP_PORT(bp);
2598
2599         DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n");
2600
2601         qlock_init(&bp->cnic_mutex);
2602
2603         if (IS_PF(bp)) {
2604                 rc = bnx2x_alloc_mem_cnic(bp);
2605                 if (rc) {
2606                         BNX2X_ERR("Unable to allocate bp memory for cnic\n");
2607                         LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2608                 }
2609         }
2610
2611         rc = bnx2x_alloc_fp_mem_cnic(bp);
2612         if (rc) {
2613                 BNX2X_ERR("Unable to allocate memory for cnic fps\n");
2614                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2615         }
2616
2617         /* Update the number of queues with the cnic queues */
2618         rc = bnx2x_set_real_num_queues(bp, 1);
2619         if (rc) {
2620                 BNX2X_ERR("Unable to set real_num_queues including cnic\n");
2621                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2622         }
2623
2624         /* Add all CNIC NAPI objects */
2625         bnx2x_add_all_napi_cnic(bp);
2626         DP(NETIF_MSG_IFUP, "cnic napi added\n");
2627         bnx2x_napi_enable_cnic(bp);
2628
2629         rc = bnx2x_init_hw_func_cnic(bp);
2630         if (rc)
2631                 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1);
2632
2633         bnx2x_nic_init_cnic(bp);
2634
2635         if (IS_PF(bp)) {
2636                 /* Enable Timer scan */
2637                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1);
2638
2639                 /* setup cnic queues */
2640                 for_each_cnic_queue(bp, i) {
2641                         rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2642                         if (rc) {
2643                                 BNX2X_ERR("Queue setup failed\n");
2644                                 LOAD_ERROR_EXIT(bp, load_error_cnic2);
2645                         }
2646                 }
2647         }
2648
2649         /* Initialize Rx filter. */
2650         bnx2x_set_rx_mode_inner(bp);
2651
2652         /* re-read iscsi info */
2653         bnx2x_get_iscsi_info(bp);
2654         bnx2x_setup_cnic_irq_info(bp);
2655         bnx2x_setup_cnic_info(bp);
2656         bp->cnic_loaded = true;
2657         if (bp->state == BNX2X_STATE_OPEN)
2658                 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
2659
2660         DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n");
2661
2662         return 0;
2663
2664 #ifndef BNX2X_STOP_ON_ERROR
2665 load_error_cnic2:
2666         /* Disable Timer scan */
2667         REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
2668
2669 load_error_cnic1:
2670         bnx2x_napi_disable_cnic(bp);
2671         /* Update the number of queues without the cnic queues */
2672         if (bnx2x_set_real_num_queues(bp, 0))
2673                 BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
2674 load_error_cnic0:
2675         BNX2X_ERR("CNIC-related load failed\n");
2676         bnx2x_free_fp_mem_cnic(bp);
2677         bnx2x_free_mem_cnic(bp);
2678         return rc;
2679 #endif /* ! BNX2X_STOP_ON_ERROR */
2680 }
2681
2682 /* must be called with rtnl_lock */
2683 int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
2684 {
2685 panic("Not implemented");
2686 #if 0 // AKAROS_PORT
2687         int port = BP_PORT(bp);
2688         int i, rc = 0;
2689         uint32_t load_code = 0;
2690
2691         DP(NETIF_MSG_IFUP, "Starting NIC load\n");
2692         DP(NETIF_MSG_IFUP,
2693            "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled");
2694
2695 #ifdef BNX2X_STOP_ON_ERROR
2696         if (unlikely(bp->panic)) {
2697                 BNX2X_ERR("Can't load NIC when there is panic\n");
2698                 return -EPERM;
2699         }
2700 #endif
2701
2702         bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
2703
2704         /* zero the structure w/o any lock, before SP handler is initialized */
2705         memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link));
2706         __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
2707                 &bp->last_reported_link.link_report_flags);
2708
2709         if (IS_PF(bp))
2710                 /* must be called before memory allocation and HW init */
2711                 bnx2x_ilt_set_info(bp);
2712
2713         /*
2714          * Zero fastpath structures preserving invariants like napi, which are
2715          * allocated only once, fp index, max_cos, bp pointer.
2716          * Also set fp->disable_tpa and txdata_ptr.
2717          */
2718         DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
2719         for_each_queue(bp, i)
2720                 bnx2x_bz_fp(bp, i);
2721         memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS +
2722                                   bp->num_cnic_queues) *
2723                                   sizeof(struct bnx2x_fp_txdata));
2724
2725         bp->fcoe_init = false;
2726
2727         /* Set the receive queues buffer size */
2728         bnx2x_set_rx_buf_size(bp);
2729
2730         if (IS_PF(bp)) {
2731                 rc = bnx2x_alloc_mem(bp);
2732                 if (rc) {
2733                         BNX2X_ERR("Unable to allocate bp memory\n");
2734                         return rc;
2735                 }
2736         }
2737
2738         /* need to be done after alloc mem, since it's self adjusting to amount
2739          * of memory available for RSS queues
2740          */
2741         rc = bnx2x_alloc_fp_mem(bp);
2742         if (rc) {
2743                 BNX2X_ERR("Unable to allocate memory for fps\n");
2744                 LOAD_ERROR_EXIT(bp, load_error0);
2745         }
2746
2747         /* Allocated memory for FW statistics  */
2748         if (bnx2x_alloc_fw_stats_mem(bp))
2749                 LOAD_ERROR_EXIT(bp, load_error0);
2750
2751         /* request pf to initialize status blocks */
2752         if (IS_VF(bp)) {
2753                 rc = bnx2x_vfpf_init(bp);
2754                 if (rc)
2755                         LOAD_ERROR_EXIT(bp, load_error0);
2756         }
2757
2758         /* As long as bnx2x_alloc_mem() may possibly update
2759          * bp->num_queues, bnx2x_set_real_num_queues() should always
2760          * come after it. At this stage cnic queues are not counted.
2761          */
2762         rc = bnx2x_set_real_num_queues(bp, 0);
2763         if (rc) {
2764                 BNX2X_ERR("Unable to set real_num_queues\n");
2765                 LOAD_ERROR_EXIT(bp, load_error0);
2766         }
2767
2768         /* configure multi cos mappings in kernel.
2769          * this configuration may be overridden by a multi class queue
2770          * discipline or by a dcbx negotiation result.
2771          */
2772         bnx2x_setup_tc(bp->dev, bp->max_cos);
2773
2774         /* Add all NAPI objects */
2775         bnx2x_add_all_napi(bp);
2776         DP(NETIF_MSG_IFUP, "napi added\n");
2777         bnx2x_napi_enable(bp);
2778
2779         if (IS_PF(bp)) {
2780                 /* set pf load just before approaching the MCP */
2781                 bnx2x_set_pf_load(bp);
2782
2783                 /* if mcp exists send load request and analyze response */
2784                 if (!BP_NOMCP(bp)) {
2785                         /* attempt to load pf */
2786                         rc = bnx2x_nic_load_request(bp, &load_code);
2787                         if (rc)
2788                                 LOAD_ERROR_EXIT(bp, load_error1);
2789
2790                         /* what did mcp say? */
2791                         rc = bnx2x_compare_fw_ver(bp, load_code, true);
2792                         if (rc) {
2793                                 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2794                                 LOAD_ERROR_EXIT(bp, load_error2);
2795                         }
2796                 } else {
2797                         load_code = bnx2x_nic_load_no_mcp(bp, port);
2798                 }
2799
2800                 /* mark pmf if applicable */
2801                 bnx2x_nic_load_pmf(bp, load_code);
2802
2803                 /* Init Function state controlling object */
2804                 bnx2x__init_func_obj(bp);
2805
2806                 /* Initialize HW */
2807                 rc = bnx2x_init_hw(bp, load_code);
2808                 if (rc) {
2809                         BNX2X_ERR("HW init failed, aborting\n");
2810                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2811                         LOAD_ERROR_EXIT(bp, load_error2);
2812                 }
2813         }
2814
2815         bnx2x_pre_irq_nic_init(bp);
2816
2817         /* Connect to IRQs */
2818         rc = bnx2x_setup_irqs(bp);
2819         if (rc) {
2820                 BNX2X_ERR("setup irqs failed\n");
2821                 if (IS_PF(bp))
2822                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2823                 LOAD_ERROR_EXIT(bp, load_error2);
2824         }
2825
2826         /* Init per-function objects */
2827         if (IS_PF(bp)) {
2828                 /* Setup NIC internals and enable interrupts */
2829                 bnx2x_post_irq_nic_init(bp, load_code);
2830
2831                 bnx2x_init_bp_objs(bp);
2832                 bnx2x_iov_nic_init(bp);
2833
2834                 /* Set AFEX default VLAN tag to an invalid value */
2835                 bp->afex_def_vlan_tag = -1;
2836                 bnx2x_nic_load_afex_dcc(bp, load_code);
2837                 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
2838                 rc = bnx2x_func_start(bp);
2839                 if (rc) {
2840                         BNX2X_ERR("Function start failed!\n");
2841                         bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2842
2843                         LOAD_ERROR_EXIT(bp, load_error3);
2844                 }
2845
2846                 /* Send LOAD_DONE command to MCP */
2847                 if (!BP_NOMCP(bp)) {
2848                         load_code = bnx2x_fw_command(bp,
2849                                                      DRV_MSG_CODE_LOAD_DONE, 0);
2850                         if (!load_code) {
2851                                 BNX2X_ERR("MCP response failure, aborting\n");
2852                                 rc = -EBUSY;
2853                                 LOAD_ERROR_EXIT(bp, load_error3);
2854                         }
2855                 }
2856
2857                 /* initialize FW coalescing state machines in RAM */
2858                 bnx2x_update_coalesce(bp);
2859         }
2860
2861         /* setup the leading queue */
2862         rc = bnx2x_setup_leading(bp);
2863         if (rc) {
2864                 BNX2X_ERR("Setup leading failed!\n");
2865                 LOAD_ERROR_EXIT(bp, load_error3);
2866         }
2867
2868         /* set up the rest of the queues */
2869         for_each_nondefault_eth_queue(bp, i) {
2870                 if (IS_PF(bp))
2871                         rc = bnx2x_setup_queue(bp, &bp->fp[i], false);
2872                 else /* VF */
2873                         rc = bnx2x_vfpf_setup_q(bp, &bp->fp[i], false);
2874                 if (rc) {
2875                         BNX2X_ERR("Queue %d setup failed\n", i);
2876                         LOAD_ERROR_EXIT(bp, load_error3);
2877                 }
2878         }
2879
2880         /* setup rss */
2881         rc = bnx2x_init_rss(bp);
2882         if (rc) {
2883                 BNX2X_ERR("PF RSS init failed\n");
2884                 LOAD_ERROR_EXIT(bp, load_error3);
2885         }
2886
2887         /* Now when Clients are configured we are ready to work */
2888         bp->state = BNX2X_STATE_OPEN;
2889
2890         /* Configure a ucast MAC */
2891 panic("Not implemented");
2892 #if 0 // AKAROS_PORT
2893         if (IS_PF(bp))
2894                 rc = bnx2x_set_eth_mac(bp, true);
2895         else /* vf */
2896                 rc = bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, bp->fp->index,
2897                                            true);
2898 #endif
2899         if (rc) {
2900                 BNX2X_ERR("Setting Ethernet MAC failed\n");
2901                 LOAD_ERROR_EXIT(bp, load_error3);
2902         }
2903
2904         if (IS_PF(bp) && bp->pending_max) {
2905                 bnx2x_update_max_mf_config(bp, bp->pending_max);
2906                 bp->pending_max = 0;
2907         }
2908
2909         if (bp->port.pmf) {
2910                 rc = bnx2x_initial_phy_init(bp, load_mode);
2911                 if (rc)
2912                         LOAD_ERROR_EXIT(bp, load_error3);
2913         }
2914         bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN;
2915
2916         /* Start fast path */
2917
2918         /* Initialize Rx filter. */
2919         bnx2x_set_rx_mode_inner(bp);
2920
2921         /* Start Tx */
2922         switch (load_mode) {
2923         case LOAD_NORMAL:
2924                 /* Tx queue should be only re-enabled */
2925                 netif_tx_wake_all_queues(bp->dev);
2926                 break;
2927
2928         case LOAD_OPEN:
2929                 netif_tx_start_all_queues(bp->dev);
2930                 cmb();
2931                 break;
2932
2933         case LOAD_DIAG:
2934         case LOAD_LOOPBACK_EXT:
2935                 bp->state = BNX2X_STATE_DIAG;
2936                 break;
2937
2938         default:
2939                 break;
2940         }
2941
2942         if (bp->port.pmf)
2943                 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0);
2944         else
2945                 bnx2x__link_status_update(bp);
2946
2947         /* start the timer */
2948         set_awaiter_rel(&bp->timer, bp->current_interval * 1000); // fudge
2949         set_alarm(&per_cpu_info[0].tchain, &bp->timer);
2950
2951         if (CNIC_ENABLED(bp))
2952                 bnx2x_load_cnic(bp);
2953
2954         if (IS_PF(bp))
2955                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
2956
2957         if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2958                 /* mark driver is loaded in shmem2 */
2959                 uint32_t val;
2960                 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2961                 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2962                           val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
2963                           DRV_FLAGS_CAPABILITIES_LOADED_L2);
2964         }
2965
2966         /* Wait for all pending SP commands to complete */
2967         if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) {
2968                 BNX2X_ERR("Timeout waiting for SP elements to complete\n");
2969                 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
2970                 return -EBUSY;
2971         }
2972
2973         /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
2974         if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
2975                 bnx2x_dcbx_init(bp, false);
2976
2977         DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
2978
2979         return 0;
2980
2981 #ifndef BNX2X_STOP_ON_ERROR
2982 load_error3:
2983         if (IS_PF(bp)) {
2984                 bnx2x_int_disable_sync(bp, 1);
2985
2986                 /* Clean queueable objects */
2987                 bnx2x_squeeze_objects(bp);
2988         }
2989
2990         /* Free SKBs, SGEs, TPA pool and driver internals */
2991         bnx2x_free_skbs(bp);
2992         for_each_rx_queue(bp, i)
2993                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2994
2995         /* Release IRQs */
2996         bnx2x_free_irq(bp);
2997 load_error2:
2998         if (IS_PF(bp) && !BP_NOMCP(bp)) {
2999                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
3000                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
3001         }
3002
3003         bp->port.pmf = 0;
3004 load_error1:
3005         bnx2x_napi_disable(bp);
3006         bnx2x_del_all_napi(bp);
3007
3008         /* clear pf_load status, as it was already set */
3009         if (IS_PF(bp))
3010                 bnx2x_clear_pf_load(bp);
3011 load_error0:
3012         bnx2x_free_fw_stats_mem(bp);
3013         bnx2x_free_fp_mem(bp);
3014         bnx2x_free_mem(bp);
3015
3016         return rc;
3017 #endif /* ! BNX2X_STOP_ON_ERROR */
3018 #endif
3019 }
3020
3021 int bnx2x_drain_tx_queues(struct bnx2x *bp)
3022 {
3023         uint8_t rc = 0, cos, i;
3024
3025         /* Wait until tx fastpath tasks complete */
3026         for_each_tx_queue(bp, i) {
3027                 struct bnx2x_fastpath *fp = &bp->fp[i];
3028
3029                 for_each_cos_in_tx_queue(fp, cos)
3030                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
3031                 if (rc)
3032                         return rc;
3033         }
3034         return 0;
3035 }
3036
3037 /* must be called with rtnl_lock */
3038 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
3039 {
3040 panic("Not implemented");
3041 #if 0 // AKAROS_PORT
3042         int i;
3043         bool global = false;
3044
3045         DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
3046
3047         /* mark driver is unloaded in shmem2 */
3048         if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
3049                 uint32_t val;
3050                 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
3051                 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
3052                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
3053         }
3054
3055         if (IS_PF(bp) && bp->recovery_state != BNX2X_RECOVERY_DONE &&
3056             (bp->state == BNX2X_STATE_CLOSED ||
3057              bp->state == BNX2X_STATE_ERROR)) {
3058                 /* We can get here if the driver has been unloaded
3059                  * during parity error recovery and is either waiting for a
3060                  * leader to complete or for other functions to unload and
3061                  * then ifdown has been issued. In this case we want to
3062                  * unload and let other functions to complete a recovery
3063                  * process.
3064                  */
3065                 bp->recovery_state = BNX2X_RECOVERY_DONE;
3066                 bp->is_leader = 0;
3067                 bnx2x_release_leader_lock(bp);
3068                 mb();
3069
3070                 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n");
3071                 BNX2X_ERR("Can't unload in closed or error state\n");
3072                 return -EINVAL;
3073         }
3074
3075         /* Nothing to do during unload if previous bnx2x_nic_load()
3076          * have not completed successfully - all resources are released.
3077          *
3078          * we can get here only after unsuccessful ndo_* callback, during which
3079          * dev->IFF_UP flag is still on.
3080          */
3081         if (bp->state == BNX2X_STATE_CLOSED || bp->state == BNX2X_STATE_ERROR)
3082                 return 0;
3083
3084         /* It's important to set the bp->state to the value different from
3085          * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int()
3086          * may restart the Tx from the NAPI context (see bnx2x_tx_int()).
3087          */
3088         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
3089         mb();
3090
3091         /* indicate to VFs that the PF is going down */
3092         bnx2x_iov_channel_down(bp);
3093
3094         if (CNIC_LOADED(bp))
3095                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
3096
3097         /* Stop Tx */
3098         bnx2x_tx_disable(bp);
3099         netdev_reset_tc(bp->dev);
3100
3101         bp->rx_mode = BNX2X_RX_MODE_NONE;
3102
3103         del_timer_sync(&bp->timer);
3104
3105         if (IS_PF(bp)) {
3106                 /* Set ALWAYS_ALIVE bit in shmem */
3107                 bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
3108                 bnx2x_drv_pulse(bp);
3109                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
3110                 bnx2x_save_statistics(bp);
3111         }
3112
3113         /* wait till consumers catch up with producers in all queues */
3114         bnx2x_drain_tx_queues(bp);
3115
3116         /* if VF indicate to PF this function is going down (PF will delete sp
3117          * elements and clear initializations
3118          */
3119         if (IS_VF(bp))
3120                 bnx2x_vfpf_close_vf(bp);
3121         else if (unload_mode != UNLOAD_RECOVERY)
3122                 /* if this is a normal/close unload need to clean up chip*/
3123                 bnx2x_chip_cleanup(bp, unload_mode, keep_link);
3124         else {
3125                 /* Send the UNLOAD_REQUEST to the MCP */
3126                 bnx2x_send_unload_req(bp, unload_mode);
3127
3128                 /* Prevent transactions to host from the functions on the
3129                  * engine that doesn't reset global blocks in case of global
3130                  * attention once global blocks are reset and gates are opened
3131                  * (the engine which leader will perform the recovery
3132                  * last).
3133                  */
3134                 if (!CHIP_IS_E1x(bp))
3135                         bnx2x_pf_disable(bp);
3136
3137                 /* Disable HW interrupts, NAPI */
3138                 bnx2x_netif_stop(bp, 1);
3139                 /* Delete all NAPI objects */
3140                 bnx2x_del_all_napi(bp);
3141                 if (CNIC_LOADED(bp))
3142                         bnx2x_del_all_napi_cnic(bp);
3143                 /* Release IRQs */
3144                 bnx2x_free_irq(bp);
3145
3146                 /* Report UNLOAD_DONE to MCP */
3147                 bnx2x_send_unload_done(bp, false);
3148         }
3149
3150         /*
3151          * At this stage no more interrupts will arrive so we may safely clean
3152          * the queueable objects here in case they failed to get cleaned so far.
3153          */
3154         if (IS_PF(bp))
3155                 bnx2x_squeeze_objects(bp);
3156
3157         /* There should be no more pending SP commands at this stage */
3158         bp->sp_state = 0;
3159
3160         bp->port.pmf = 0;
3161
3162         /* clear pending work in rtnl task */
3163         bp->sp_rtnl_state = 0;
3164         mb();
3165
3166         /* Free SKBs, SGEs, TPA pool and driver internals */
3167         bnx2x_free_skbs(bp);
3168         if (CNIC_LOADED(bp))
3169                 bnx2x_free_skbs_cnic(bp);
3170         for_each_rx_queue(bp, i)
3171                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
3172
3173         bnx2x_free_fp_mem(bp);
3174         if (CNIC_LOADED(bp))
3175                 bnx2x_free_fp_mem_cnic(bp);
3176
3177         if (IS_PF(bp)) {
3178                 if (CNIC_LOADED(bp))
3179                         bnx2x_free_mem_cnic(bp);
3180         }
3181         bnx2x_free_mem(bp);
3182
3183         bp->state = BNX2X_STATE_CLOSED;
3184         bp->cnic_loaded = false;
3185
3186         /* Clear driver version indication in shmem */
3187         if (IS_PF(bp))
3188                 bnx2x_update_mng_version(bp);
3189
3190         /* Check if there are pending parity attentions. If there are - set
3191          * RECOVERY_IN_PROGRESS.
3192          */
3193         if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) {
3194                 bnx2x_set_reset_in_progress(bp);
3195
3196                 /* Set RESET_IS_GLOBAL if needed */
3197                 if (global)
3198                         bnx2x_set_reset_global(bp);
3199         }
3200
3201         /* The last driver must disable a "close the gate" if there is no
3202          * parity attention or "process kill" pending.
3203          */