This now enables vmx via vmxon and vmclear works too
[akaros.git] / kern / arch / x86 / vmx_mmu.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * MMU support
8  *
9  * Copyright (C) 2006 Qumranet, Inc.
10  *
11  * Authors:
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *   Avi Kivity   <avi@qumranet.com>
14  *
15  */
16 #define DEBUG
17 #include <kmalloc.h>
18 #include <string.h>
19 #include <stdio.h>
20 #include <assert.h>
21 #include <error.h>
22 #include <pmap.h>
23 #include <sys/queue.h>
24 #include <smp.h>
25 #include <kref.h>
26 #include <atomic.h>
27 #include <alarm.h>
28 #include <event.h>
29 #include <umem.h>
30 #include <devalarm.h>
31 #include <arch/types.h>
32 #include <arch/vm.h>
33 #include <arch/emulate.h>
34 #include <arch/vmdebug.h>
35 #include <arch/msr-index.h>
36
37 #define pgprintk(x...) do { } while (0)
38
39 #define ASSERT(x)                                                       \
40         if (!(x)) {                                                     \
41                 printd( "assertion failed %s:%d: %s\n", \
42                        __FILE__, __LINE__, #x);                         \
43         }
44
45 #define PT64_ENT_PER_PAGE 512
46 #define PT32_ENT_PER_PAGE 1024
47
48 #define PT_WRITABLE_SHIFT 1
49
50 #define PT_PRESENT_MASK (1ULL << 0)
51 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
52 #define PT_USER_MASK (1ULL << 2)
53 #define PT_PWT_MASK (1ULL << 3)
54 #define PT_PCD_MASK (1ULL << 4)
55 #define PT_ACCESSED_MASK (1ULL << 5)
56 #define PT_DIRTY_MASK (1ULL << 6)
57 #define PT_PAGE_SIZE_MASK (1ULL << 7)
58 #define PT_PAT_MASK (1ULL << 7)
59 #define PT_GLOBAL_MASK (1ULL << 8)
60 #define PT64_NX_MASK (1ULL << 63)
61
62 #define PT_PAT_SHIFT 7
63 #define PT_DIR_PAT_SHIFT 12
64 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
65
66 #define PT32_DIR_PSE36_SIZE 4
67 #define PT32_DIR_PSE36_SHIFT 13
68 #define PT32_DIR_PSE36_MASK (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
69
70
71 #define PT32_PTE_COPY_MASK \
72         (PT_PRESENT_MASK | PT_PWT_MASK | PT_PCD_MASK | \
73         PT_ACCESSED_MASK | PT_DIRTY_MASK | PT_PAT_MASK | \
74         PT_GLOBAL_MASK )
75
76 #define PT32_NON_PTE_COPY_MASK \
77         (PT_PRESENT_MASK | PT_PWT_MASK | PT_PCD_MASK | \
78         PT_ACCESSED_MASK | PT_DIRTY_MASK)
79
80
81 #define PT64_PTE_COPY_MASK \
82         (PT64_NX_MASK | PT32_PTE_COPY_MASK)
83
84 #define PT64_NON_PTE_COPY_MASK \
85         (PT64_NX_MASK | PT32_NON_PTE_COPY_MASK)
86
87
88
89 #define PT_FIRST_AVAIL_BITS_SHIFT 9
90 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
91
92 #define PT_SHADOW_PS_MARK (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
93 #define PT_SHADOW_IO_MARK (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
94
95 #define PT_SHADOW_WRITABLE_SHIFT (PT_FIRST_AVAIL_BITS_SHIFT + 1)
96 #define PT_SHADOW_WRITABLE_MASK (1ULL << PT_SHADOW_WRITABLE_SHIFT)
97
98 #define PT_SHADOW_USER_SHIFT (PT_SHADOW_WRITABLE_SHIFT + 1)
99 #define PT_SHADOW_USER_MASK (1ULL << (PT_SHADOW_USER_SHIFT))
100
101 #define PT_SHADOW_BITS_OFFSET (PT_SHADOW_WRITABLE_SHIFT - PT_WRITABLE_SHIFT)
102
103 #define VALID_PAGE(x) ((x) != INVALID_PAGE)
104
105 #define PT64_LEVEL_BITS 9
106
107 #define PT64_LEVEL_SHIFT(level) \
108                 ( PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS )
109
110 #define PT64_LEVEL_MASK(level) \
111                 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
112
113 #define PT64_INDEX(address, level)\
114         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
115
116
117 #define PT32_LEVEL_BITS 10
118
119 #define PT32_LEVEL_SHIFT(level) \
120                 ( PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS )
121
122 #define PT32_LEVEL_MASK(level) \
123                 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
124
125 #define PT32_INDEX(address, level)\
126         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
127
128
129 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & PAGE_MASK)
130 #define PT64_DIR_BASE_ADDR_MASK \
131         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
132
133 #define PT32_BASE_ADDR_MASK PAGE_MASK
134 #define PT32_DIR_BASE_ADDR_MASK \
135         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
136
137
138 #define PFERR_PRESENT_MASK (1U << 0)
139 #define PFERR_WRITE_MASK (1U << 1)
140 #define PFERR_USER_MASK (1U << 2)
141
142 #define PT64_ROOT_LEVEL 4
143 #define PT32_ROOT_LEVEL 2
144 #define PT32E_ROOT_LEVEL 3
145
146 #define PT_DIRECTORY_LEVEL 2
147 #define PT_PAGE_TABLE_LEVEL 1
148
149 static int is_write_protection(void)
150 {
151         print_func_entry();
152         print_func_exit();
153         return guest_cr0() & CR0_WP_MASK;
154 }
155
156 static int is_cpuid_PSE36(void)
157 {
158         print_func_entry();
159         print_func_exit();
160         return 1;
161 }
162
163 static int is_present_pte(unsigned long pte)
164 {
165         print_func_entry();
166         print_func_exit();
167         return pte & PT_PRESENT_MASK;
168 }
169
170 static int is_writeble_pte(unsigned long pte)
171 {
172         print_func_entry();
173         print_func_exit();
174         return pte & PT_WRITABLE_MASK;
175 }
176
177 static int is_io_pte(unsigned long pte)
178 {
179         print_func_entry();
180         print_func_exit();
181         return pte & PT_SHADOW_IO_MARK;
182 }
183
184 static void litevm_mmu_free_page(struct litevm_vcpu *vcpu, hpa_t page_hpa)
185 {
186         print_func_entry();
187         struct litevm_mmu_page *page_head = page_header(page_hpa);
188
189         LIST_REMOVE(page_head, link);
190         //list_del(&page_head->link);
191         page_head->page_hpa = page_hpa;
192         //list_add(&page_head->link, &vcpu->free_pages);
193         LIST_INSERT_HEAD(&vcpu->link, page_head, link);
194         print_func_exit();
195 }
196
197 static int is_empty_shadow_page(hpa_t page_hpa)
198 {
199         print_func_entry();
200         uint32_t *pos;
201         uint32_t *end;
202         for (pos = KADDR(page_hpa), end = pos + PAGE_SIZE / sizeof(uint32_t);
203                       pos != end; pos++)
204                 if (*pos != 0) {
205                         print_func_exit();
206                         return 0;
207                 }
208         print_func_exit();
209         return 1;
210 }
211
212 static hpa_t litevm_mmu_alloc_page(struct litevm_vcpu *vcpu,
213                                    uint64_t *parent_pte)
214 {
215         print_func_entry();
216         struct litevm_mmu_page *page;
217
218         if (LIST_EMPTY(&vcpu->link)) {
219                 print_func_exit();
220                 return INVALID_PAGE;
221         }
222
223         page = LIST_FIRST(&vcpu->link);
224         LIST_REMOVE(page, link);
225         LIST_INSERT_HEAD(&vcpu->litevm->link, page, link);
226         ASSERT(is_empty_shadow_page(page->page_hpa));
227         page->slot_bitmap = 0;
228         page->global = 1;
229         page->parent_pte = parent_pte;
230         print_func_exit();
231         return page->page_hpa;
232 }
233
234 static void page_header_update_slot(struct litevm *litevm, void *pte, gpa_t gpa)
235 {
236         print_func_entry();
237         int slot = memslot_id(litevm, gfn_to_memslot(litevm, gpa >> PAGE_SHIFT));
238         struct litevm_mmu_page *page_head = page_header(PADDR(pte));
239
240         SET_BITMASK_BIT_ATOMIC((uint8_t *)&page_head->slot_bitmap, slot);
241         print_func_exit();
242 }
243
244 hpa_t safe_gpa_to_hpa(struct litevm_vcpu *vcpu, gpa_t gpa)
245 {
246         print_func_entry();
247         hpa_t hpa = gpa_to_hpa(vcpu, gpa);
248
249         print_func_exit();
250         return is_error_hpa(hpa) ? bad_page_address | (gpa & ~PAGE_MASK): hpa;
251 }
252
253 hpa_t gpa_to_hpa(struct litevm_vcpu *vcpu, gpa_t gpa)
254 {
255         print_func_entry();
256         struct litevm_memory_slot *slot;
257         struct page *page;
258
259         ASSERT((gpa & HPA_ERR_MASK) == 0);
260         slot = gfn_to_memslot(vcpu->litevm, gpa >> PAGE_SHIFT);
261         if (!slot) {
262                 print_func_exit();
263                 return gpa | HPA_ERR_MASK;
264         }
265         page = gfn_to_page(slot, gpa >> PAGE_SHIFT);
266         print_func_exit();
267         return ((hpa_t)page2ppn(page) << PAGE_SHIFT)
268                 | (gpa & (PAGE_SIZE-1));
269 }
270
271 hpa_t gva_to_hpa(struct litevm_vcpu *vcpu, gva_t gva)
272 {
273         print_func_entry();
274         gpa_t gpa = vcpu->mmu.gva_to_gpa(vcpu, gva);
275
276         if (gpa == UNMAPPED_GVA) {
277                 print_func_exit();
278                 return UNMAPPED_GVA;
279         }
280         print_func_exit();
281         return gpa_to_hpa(vcpu, gpa);
282 }
283
284
285 static void release_pt_page_64(struct litevm_vcpu *vcpu, hpa_t page_hpa,
286                                int level)
287 {
288         print_func_entry();
289         ASSERT(vcpu);
290         ASSERT(VALID_PAGE(page_hpa));
291         ASSERT(level <= PT64_ROOT_LEVEL && level > 0);
292
293         if (level == 1)
294                 memset(KADDR(page_hpa), 0, PAGE_SIZE);
295         else {
296                 uint64_t *pos;
297                 uint64_t *end;
298
299                 for (pos = KADDR(page_hpa), end = pos + PT64_ENT_PER_PAGE;
300                      pos != end; pos++) {
301                         uint64_t current_ent = *pos;
302
303                         *pos = 0;
304                         if (is_present_pte(current_ent))
305                                 release_pt_page_64(vcpu,
306                                                   current_ent &
307                                                   PT64_BASE_ADDR_MASK,
308                                                   level - 1);
309                 }
310         }
311         litevm_mmu_free_page(vcpu, page_hpa);
312         print_func_exit();
313 }
314
315 static void nonpaging_new_cr3(struct litevm_vcpu *vcpu)
316 {
317 print_func_entry();
318 print_func_exit();
319 }
320
321 static int nonpaging_map(struct litevm_vcpu *vcpu, gva_t v, hpa_t p)
322 {
323         print_func_entry();
324         int level = PT32E_ROOT_LEVEL;
325         hpa_t table_addr = vcpu->mmu.root_hpa;
326
327         for (; ; level--) {
328                 uint32_t index = PT64_INDEX(v, level);
329                 uint64_t *table;
330
331                 ASSERT(VALID_PAGE(table_addr));
332                 table = KADDR(table_addr);
333
334                 if (level == 1) {
335                         mark_page_dirty(vcpu->litevm, v >> PAGE_SHIFT);
336                         page_header_update_slot(vcpu->litevm, table, v);
337                         table[index] = p | PT_PRESENT_MASK | PT_WRITABLE_MASK |
338                                                                 PT_USER_MASK;
339                         print_func_exit();
340                         return 0;
341                 }
342
343                 if (table[index] == 0) {
344                         hpa_t new_table = litevm_mmu_alloc_page(vcpu,
345                                                              &table[index]);
346
347                         if (!VALID_PAGE(new_table)) {
348                                 pgprintk("nonpaging_map: ENOMEM\n");
349                                 print_func_exit();
350                                 return -ENOMEM;
351                         }
352
353                         if (level == PT32E_ROOT_LEVEL)
354                                 table[index] = new_table | PT_PRESENT_MASK;
355                         else
356                                 table[index] = new_table | PT_PRESENT_MASK |
357                                                 PT_WRITABLE_MASK | PT_USER_MASK;
358                 }
359                 table_addr = table[index] & PT64_BASE_ADDR_MASK;
360         }
361         print_func_exit();
362 }
363
364 static void nonpaging_flush(struct litevm_vcpu *vcpu)
365 {
366         print_func_entry();
367         hpa_t root = vcpu->mmu.root_hpa;
368
369         ++litevm_stat.tlb_flush;
370         pgprintk("nonpaging_flush\n");
371         ASSERT(VALID_PAGE(root));
372         release_pt_page_64(vcpu, root, vcpu->mmu.shadow_root_level);
373         root = litevm_mmu_alloc_page(vcpu, 0);
374         ASSERT(VALID_PAGE(root));
375         vcpu->mmu.root_hpa = root;
376         if (is_paging())
377                 root |= (vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK));
378         vmcs_writel(GUEST_CR3, root);
379         print_func_exit();
380 }
381
382 static gpa_t nonpaging_gva_to_gpa(struct litevm_vcpu *vcpu, gva_t vaddr)
383 {
384         print_func_entry();
385         print_func_exit();
386         return vaddr;
387 }
388
389 static int nonpaging_page_fault(struct litevm_vcpu *vcpu, gva_t gva,
390                                uint32_t error_code)
391 {
392         print_func_entry();
393         int ret;
394         gpa_t addr = gva;
395
396         ASSERT(vcpu);
397         ASSERT(VALID_PAGE(vcpu->mmu.root_hpa));
398
399         for (;;) {
400              hpa_t paddr;
401
402              paddr = gpa_to_hpa(vcpu , addr & PT64_BASE_ADDR_MASK);
403
404              if (is_error_hpa(paddr)) {
405                 print_func_exit();
406                      return 1;
407              }
408
409              ret = nonpaging_map(vcpu, addr & PAGE_MASK, paddr);
410              if (ret) {
411                      nonpaging_flush(vcpu);
412                      continue;
413              }
414              break;
415         }
416         print_func_exit();
417         return ret;
418 }
419
420 static void nonpaging_inval_page(struct litevm_vcpu *vcpu, gva_t addr)
421 {
422 print_func_entry();
423 print_func_exit();
424 }
425
426 static void nonpaging_free(struct litevm_vcpu *vcpu)
427 {
428         print_func_entry();
429         hpa_t root;
430
431         ASSERT(vcpu);
432         root = vcpu->mmu.root_hpa;
433         if (VALID_PAGE(root))
434                 release_pt_page_64(vcpu, root, vcpu->mmu.shadow_root_level);
435         vcpu->mmu.root_hpa = INVALID_PAGE;
436         print_func_exit();
437 }
438
439 static int nonpaging_init_context(struct litevm_vcpu *vcpu)
440 {
441         print_func_entry();
442         struct litevm_mmu *context = &vcpu->mmu;
443
444         context->new_cr3 = nonpaging_new_cr3;
445         context->page_fault = nonpaging_page_fault;
446         context->inval_page = nonpaging_inval_page;
447         context->gva_to_gpa = nonpaging_gva_to_gpa;
448         context->free = nonpaging_free;
449         context->root_level = PT32E_ROOT_LEVEL;
450         context->shadow_root_level = PT32E_ROOT_LEVEL;
451         context->root_hpa = litevm_mmu_alloc_page(vcpu, 0);
452         ASSERT(VALID_PAGE(context->root_hpa));
453         vmcs_writel(GUEST_CR3, context->root_hpa);
454         print_func_exit();
455         return 0;
456 }
457
458
459 static void litevm_mmu_flush_tlb(struct litevm_vcpu *vcpu)
460 {
461         print_func_entry();
462         struct litevm_mmu_page *page, *npage;
463
464         //list_for_each_entry_safe(page, npage, &vcpu->litevm->active_mmu_pages,
465         LIST_FOREACH_SAFE(page, &vcpu->litevm->link,
466                                  link, npage) {
467                 if (page->global)
468                         continue;
469
470                 if (!page->parent_pte)
471                         continue;
472
473                 *page->parent_pte = 0;
474                 release_pt_page_64(vcpu, page->page_hpa, 1);
475         }
476         ++litevm_stat.tlb_flush;
477         print_func_exit();
478 }
479
480 static void paging_new_cr3(struct litevm_vcpu *vcpu)
481 {
482         print_func_entry();
483         litevm_mmu_flush_tlb(vcpu);
484         print_func_exit();
485 }
486
487 static void mark_pagetable_nonglobal(void *shadow_pte)
488 {
489         print_func_entry();
490         page_header(PADDR(shadow_pte))->global = 0;
491         print_func_exit();
492 }
493
494 static inline void set_pte_common(struct litevm_vcpu *vcpu,
495                              uint64_t *shadow_pte,
496                              gpa_t gaddr,
497                              int dirty,
498                              uint64_t access_bits)
499 {
500         print_func_entry();
501         hpa_t paddr;
502
503         *shadow_pte |= access_bits << PT_SHADOW_BITS_OFFSET;
504         if (!dirty)
505                 access_bits &= ~PT_WRITABLE_MASK;
506
507         if (access_bits & PT_WRITABLE_MASK)
508                 mark_page_dirty(vcpu->litevm, gaddr >> PAGE_SHIFT);
509
510         *shadow_pte |= access_bits;
511
512         paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);
513
514         if (!(*shadow_pte & PT_GLOBAL_MASK))
515                 mark_pagetable_nonglobal(shadow_pte);
516
517         if (is_error_hpa(paddr)) {
518                 *shadow_pte |= gaddr;
519                 *shadow_pte |= PT_SHADOW_IO_MARK;
520                 *shadow_pte &= ~PT_PRESENT_MASK;
521         } else {
522                 *shadow_pte |= paddr;
523                 page_header_update_slot(vcpu->litevm, shadow_pte, gaddr);
524         }
525         print_func_exit();
526 }
527
528 static void inject_page_fault(struct litevm_vcpu *vcpu,
529                               uint64_t addr,
530                               uint32_t err_code)
531 {
532         print_func_entry();
533         uint32_t vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
534
535         pgprintk("inject_page_fault: 0x%llx err 0x%x\n", addr, err_code);
536
537         ++litevm_stat.pf_guest;
538
539         if (is_page_fault(vect_info)) {
540                 printd( "inject_page_fault: "
541                        "double fault 0x%llx @ 0x%lx\n",
542                        addr, vmcs_readl(GUEST_RIP));
543                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
544                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
545                              DF_VECTOR |
546                              INTR_TYPE_EXCEPTION |
547                              INTR_INFO_DELIEVER_CODE_MASK |
548                              INTR_INFO_VALID_MASK);
549                 print_func_exit();
550                 return;
551         }
552         vcpu->cr2 = addr;
553         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
554         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
555                      PF_VECTOR |
556                      INTR_TYPE_EXCEPTION |
557                      INTR_INFO_DELIEVER_CODE_MASK |
558                      INTR_INFO_VALID_MASK);
559
560         print_func_exit();
561 }
562
563 static inline int fix_read_pf(uint64_t *shadow_ent)
564 {
565         print_func_entry();
566         if ((*shadow_ent & PT_SHADOW_USER_MASK) &&
567             !(*shadow_ent & PT_USER_MASK)) {
568                 /*
569                  * If supervisor write protect is disabled, we shadow kernel
570                  * pages as user pages so we can trap the write access.
571                  */
572                 *shadow_ent |= PT_USER_MASK;
573                 *shadow_ent &= ~PT_WRITABLE_MASK;
574
575                 print_func_exit();
576                 return 1;
577
578         }
579         print_func_exit();
580         return 0;
581 }
582
583 static int may_access(uint64_t pte, int write, int user)
584 {
585 print_func_entry();
586
587         if (user && !(pte & PT_USER_MASK)) {
588         print_func_exit();
589         return 0;
590         }
591         if (write && !(pte & PT_WRITABLE_MASK)) {
592         print_func_exit();
593         return 0;
594         }
595         print_func_exit();
596         return 1;
597 }
598
599 /*
600  * Remove a shadow pte.
601  */
602 static void paging_inval_page(struct litevm_vcpu *vcpu, gva_t addr)
603 {
604         print_func_entry();
605         hpa_t page_addr = vcpu->mmu.root_hpa;
606         int level = vcpu->mmu.shadow_root_level;
607
608         ++litevm_stat.invlpg;
609
610         for (; ; level--) {
611                 uint32_t index = PT64_INDEX(addr, level);
612                 uint64_t *table = KADDR(page_addr);
613
614                 if (level == PT_PAGE_TABLE_LEVEL ) {
615                         table[index] = 0;
616                         print_func_exit();
617                         return;
618                 }
619
620                 if (!is_present_pte(table[index])) {
621                         print_func_exit();
622                         return;
623                 }
624
625                 page_addr = table[index] & PT64_BASE_ADDR_MASK;
626
627                 if (level == PT_DIRECTORY_LEVEL &&
628                           (table[index] & PT_SHADOW_PS_MARK)) {
629                         table[index] = 0;
630                         release_pt_page_64(vcpu, page_addr, PT_PAGE_TABLE_LEVEL);
631
632                         //flush tlb
633                         vmcs_writel(GUEST_CR3, vcpu->mmu.root_hpa |
634                                     (vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK)));
635                         print_func_exit();
636                         return;
637                 }
638         }
639         print_func_exit();
640 }
641
642 static void paging_free(struct litevm_vcpu *vcpu)
643 {
644         print_func_entry();
645         nonpaging_free(vcpu);
646         print_func_exit();
647 }
648
649 #define PTTYPE 64
650 #include "paging_tmpl.h"
651 #undef PTTYPE
652
653 #define PTTYPE 32
654 #include "paging_tmpl.h"
655 #undef PTTYPE
656
657 static int paging64_init_context(struct litevm_vcpu *vcpu)
658 {
659         print_func_entry();
660         struct litevm_mmu *context = &vcpu->mmu;
661
662         ASSERT(is_pae());
663         context->new_cr3 = paging_new_cr3;
664         context->page_fault = paging64_page_fault;
665         context->inval_page = paging_inval_page;
666         context->gva_to_gpa = paging64_gva_to_gpa;
667         context->free = paging_free;
668         context->root_level = PT64_ROOT_LEVEL;
669         context->shadow_root_level = PT64_ROOT_LEVEL;
670         context->root_hpa = litevm_mmu_alloc_page(vcpu, 0);
671         ASSERT(VALID_PAGE(context->root_hpa));
672         vmcs_writel(GUEST_CR3, context->root_hpa |
673                     (vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK)));
674         print_func_exit();
675         return 0;
676 }
677
678 static int paging32_init_context(struct litevm_vcpu *vcpu)
679 {
680         print_func_entry();
681         struct litevm_mmu *context = &vcpu->mmu;
682
683         context->new_cr3 = paging_new_cr3;
684         context->page_fault = paging32_page_fault;
685         context->inval_page = paging_inval_page;
686         context->gva_to_gpa = paging32_gva_to_gpa;
687         context->free = paging_free;
688         context->root_level = PT32_ROOT_LEVEL;
689         context->shadow_root_level = PT32E_ROOT_LEVEL;
690         context->root_hpa = litevm_mmu_alloc_page(vcpu, 0);
691         ASSERT(VALID_PAGE(context->root_hpa));
692         vmcs_writel(GUEST_CR3, context->root_hpa |
693                     (vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK)));
694         print_func_exit();
695         return 0;
696 }
697
698 static int paging32E_init_context(struct litevm_vcpu *vcpu)
699 {
700         print_func_entry();
701         int ret;
702
703         if ((ret = paging64_init_context(vcpu))) {
704                 print_func_exit();
705                 return ret;
706         }
707
708         vcpu->mmu.root_level = PT32E_ROOT_LEVEL;
709         vcpu->mmu.shadow_root_level = PT32E_ROOT_LEVEL;
710         print_func_exit();
711         return 0;
712 }
713
714 static int init_litevm_mmu(struct litevm_vcpu *vcpu)
715 {
716         print_func_entry();
717         ASSERT(vcpu);
718         ASSERT(!VALID_PAGE(vcpu->mmu.root_hpa));
719
720         if (!is_paging()) {
721                 print_func_exit();
722                 return nonpaging_init_context(vcpu);
723         }
724         else if (is_long_mode()) {
725                 print_func_exit();
726                 return paging64_init_context(vcpu);
727         }
728         else if (is_pae()) {
729                 print_func_exit();
730                 return paging32E_init_context(vcpu);
731         }
732         else
733                 {
734                         print_func_exit();
735                         return paging32_init_context(vcpu);
736                 }
737 }
738
739 static void destroy_litevm_mmu(struct litevm_vcpu *vcpu)
740 {
741         print_func_entry();
742         ASSERT(vcpu);
743         if (VALID_PAGE(vcpu->mmu.root_hpa)) {
744                 vcpu->mmu.free(vcpu);
745                 vcpu->mmu.root_hpa = INVALID_PAGE;
746         }
747         print_func_exit();
748 }
749
750 int litevm_mmu_reset_context(struct litevm_vcpu *vcpu)
751 {
752         print_func_entry();
753         destroy_litevm_mmu(vcpu);
754         print_func_exit();
755         return init_litevm_mmu(vcpu);
756 }
757
758 static void free_mmu_pages(struct litevm_vcpu *vcpu)
759 {
760         print_func_entry();
761         /* todo: use the right macros */
762         while (!LIST_EMPTY(&vcpu->link)) {
763                 struct litevm_mmu_page *vmpage;
764                 vmpage = LIST_FIRST(&vcpu->link);
765                 LIST_REMOVE(vmpage, link);
766                 uintptr_t ppn = vmpage->page_hpa>>PAGE_SHIFT;
767                 page_decref(ppn2page(ppn));
768                 assert(page_is_free(ppn));
769                 vmpage->page_hpa = INVALID_PAGE;
770         }
771         print_func_exit();
772 }
773
774 static int alloc_mmu_pages(struct litevm_vcpu *vcpu)
775 {
776         print_func_entry();
777         int i;
778
779         ASSERT(vcpu);
780
781         /* we could try to do the contiguous alloc but it's not
782          * necessary for them to be contiguous.
783          */
784         for (i = 0; i < LITEVM_NUM_MMU_PAGES; i++) {
785                 struct page *page;
786                 struct litevm_mmu_page *page_header = &vcpu->page_header_buf[i];
787
788                 if ((page = kpage_alloc_addr()) == NULL)
789                         goto error_1;
790                 page->pg_private = page_header;
791                 page_header->page_hpa = (hpa_t)page2ppn(page) << PAGE_SHIFT;
792                 memset(KADDR(page_header->page_hpa), 0, PAGE_SIZE);
793                 LIST_INSERT_HEAD(&vcpu->link, page_header, link);
794         }
795         print_func_exit();
796         return 0;
797
798 error_1:
799         free_mmu_pages(vcpu);
800         print_func_exit();
801         return -ENOMEM;
802 }
803
804 int litevm_mmu_init(struct litevm_vcpu *vcpu)
805 {
806         print_func_entry();
807         int r;
808
809         ASSERT(vcpu);
810         ASSERT(!VALID_PAGE(vcpu->mmu.root_hpa));
811         ASSERT(LIST_EMPTY(&vcpu->link));
812
813         if ((r = alloc_mmu_pages(vcpu))) {
814                 print_func_exit();
815                 return r;
816         }
817
818         if ((r = init_litevm_mmu(vcpu))) {
819                 free_mmu_pages(vcpu);
820                 print_func_exit();
821                 return r;
822         }
823         print_func_exit();
824         return 0;
825 }
826
827 void litevm_mmu_destroy(struct litevm_vcpu *vcpu)
828 {
829         print_func_entry();
830         ASSERT(vcpu);
831
832         destroy_litevm_mmu(vcpu);
833         free_mmu_pages(vcpu);
834         print_func_exit();
835 }
836
837 void litevm_mmu_slot_remove_write_access(struct litevm *litevm, int slot)
838 {
839         print_func_entry();
840         struct litevm_mmu_page *page, *link;
841
842         LIST_FOREACH(page, &litevm->link, link) {
843                 int i;
844                 uint64_t *pt;
845
846                 if (!GET_BITMASK_BIT((uint8_t*)&page->slot_bitmap, slot))
847                         continue;
848
849                 pt = KADDR(page->page_hpa);
850                 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
851                         /* avoid RMW */
852                         if (pt[i] & PT_WRITABLE_MASK)
853                                 pt[i] &= ~PT_WRITABLE_MASK;
854
855         }
856         print_func_exit();
857 }