651d4cc595f5ed67c4f21bac62d428d932e5af9f
[akaros.git] / kern / arch / x86 / vmx_mmu.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * MMU support
8  *
9  * Copyright (C) 2006 Qumranet, Inc.
10  *
11  * Authors:
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *   Avi Kivity   <avi@qumranet.com>
14  *
15  */
16 #define DEBUG
17 #include <kmalloc.h>
18 #include <string.h>
19 #include <stdio.h>
20 #include <assert.h>
21 #include <error.h>
22 #include <pmap.h>
23 #include <sys/queue.h>
24 #include <smp.h>
25 #include <kref.h>
26 #include <atomic.h>
27 #include <alarm.h>
28 #include <event.h>
29 #include <umem.h>
30 #include <devalarm.h>
31 #include <arch/types.h>
32 #include <arch/vm.h>
33 #include <arch/emulate.h>
34 #include <arch/vmdebug.h>
35 #include <arch/msr-index.h>
36
37 #define pgprintk(x...) do { } while (0)
38
39 #define ASSERT(x)                                                       \
40         if (!(x)) {                                                     \
41                 printd( "assertion failed %s:%d: %s\n", \
42                        __FILE__, __LINE__, #x);                         \
43         }
44
45 #define PT64_ENT_PER_PAGE 512
46 #define PT32_ENT_PER_PAGE 1024
47
48 #define PT_WRITABLE_SHIFT 1
49
50 #define PT_PRESENT_MASK (1ULL << 0)
51 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
52 #define PT_USER_MASK (1ULL << 2)
53 #define PT_PWT_MASK (1ULL << 3)
54 #define PT_PCD_MASK (1ULL << 4)
55 #define PT_ACCESSED_MASK (1ULL << 5)
56 #define PT_DIRTY_MASK (1ULL << 6)
57 #define PT_PAGE_SIZE_MASK (1ULL << 7)
58 #define PT_PAT_MASK (1ULL << 7)
59 #define PT_GLOBAL_MASK (1ULL << 8)
60 #define PT64_NX_MASK (1ULL << 63)
61
62 #define PT_PAT_SHIFT 7
63 #define PT_DIR_PAT_SHIFT 12
64 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
65
66 #define PT32_DIR_PSE36_SIZE 4
67 #define PT32_DIR_PSE36_SHIFT 13
68 #define PT32_DIR_PSE36_MASK (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
69
70 #define PT32_PTE_COPY_MASK \
71         (PT_PRESENT_MASK | PT_PWT_MASK | PT_PCD_MASK | \
72         PT_ACCESSED_MASK | PT_DIRTY_MASK | PT_PAT_MASK | \
73         PT_GLOBAL_MASK )
74
75 #define PT32_NON_PTE_COPY_MASK \
76         (PT_PRESENT_MASK | PT_PWT_MASK | PT_PCD_MASK | \
77         PT_ACCESSED_MASK | PT_DIRTY_MASK)
78
79 #define PT64_PTE_COPY_MASK \
80         (PT64_NX_MASK | PT32_PTE_COPY_MASK)
81
82 #define PT64_NON_PTE_COPY_MASK \
83         (PT64_NX_MASK | PT32_NON_PTE_COPY_MASK)
84
85 #define PT_FIRST_AVAIL_BITS_SHIFT 9
86 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
87
88 #define PT_SHADOW_PS_MARK (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
89 #define PT_SHADOW_IO_MARK (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
90
91 #define PT_SHADOW_WRITABLE_SHIFT (PT_FIRST_AVAIL_BITS_SHIFT + 1)
92 #define PT_SHADOW_WRITABLE_MASK (1ULL << PT_SHADOW_WRITABLE_SHIFT)
93
94 #define PT_SHADOW_USER_SHIFT (PT_SHADOW_WRITABLE_SHIFT + 1)
95 #define PT_SHADOW_USER_MASK (1ULL << (PT_SHADOW_USER_SHIFT))
96
97 #define PT_SHADOW_BITS_OFFSET (PT_SHADOW_WRITABLE_SHIFT - PT_WRITABLE_SHIFT)
98
99 #define VALID_PAGE(x) ((x) != INVALID_PAGE)
100
101 #define PT64_LEVEL_BITS 9
102
103 #define PT64_LEVEL_SHIFT(level) \
104                 ( PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS )
105
106 #define PT64_LEVEL_MASK(level) \
107                 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
108
109 #define PT64_INDEX(address, level)\
110         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
111
112 #define PT32_LEVEL_BITS 10
113
114 #define PT32_LEVEL_SHIFT(level) \
115                 ( PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS )
116
117 #define PT32_LEVEL_MASK(level) \
118                 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
119
120 #define PT32_INDEX(address, level)\
121         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
122
123 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & PAGE_MASK)
124 #define PT64_DIR_BASE_ADDR_MASK \
125         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
126
127 #define PT32_BASE_ADDR_MASK PAGE_MASK
128 #define PT32_DIR_BASE_ADDR_MASK \
129         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
130
131 #define PFERR_PRESENT_MASK (1U << 0)
132 #define PFERR_WRITE_MASK (1U << 1)
133 #define PFERR_USER_MASK (1U << 2)
134
135 #define PT64_ROOT_LEVEL 4
136 #define PT32_ROOT_LEVEL 2
137 #define PT32E_ROOT_LEVEL 3
138
139 #define PT_DIRECTORY_LEVEL 2
140 #define PT_PAGE_TABLE_LEVEL 1
141
142 static int is_write_protection(void)
143 {
144         print_func_entry();
145         print_func_exit();
146         return guest_cr0() & CR0_WP_MASK;
147 }
148
149 static int is_cpuid_PSE36(void)
150 {
151         print_func_entry();
152         print_func_exit();
153         return 1;
154 }
155
156 static int is_present_pte(unsigned long pte)
157 {
158         print_func_entry();
159         print_func_exit();
160         return pte & PT_PRESENT_MASK;
161 }
162
163 static int is_writeble_pte(unsigned long pte)
164 {
165         print_func_entry();
166         print_func_exit();
167         return pte & PT_WRITABLE_MASK;
168 }
169
170 static int is_io_pte(unsigned long pte)
171 {
172         print_func_entry();
173         print_func_exit();
174         return pte & PT_SHADOW_IO_MARK;
175 }
176
177 static void litevm_mmu_free_page(struct litevm_vcpu *vcpu, hpa_t page_hpa)
178 {
179         print_func_entry();
180         struct litevm_mmu_page *page_head = page_header(page_hpa);
181
182         LIST_REMOVE(page_head, link);
183         //list_del(&page_head->link);
184         page_head->page_hpa = page_hpa;
185         //list_add(&page_head->link, &vcpu->free_pages);
186         LIST_INSERT_HEAD(&vcpu->link, page_head, link);
187         print_func_exit();
188 }
189
190 static int is_empty_shadow_page(hpa_t page_hpa)
191 {
192         print_func_entry();
193         uint32_t *pos;
194         uint32_t *end;
195         for (pos = KADDR(page_hpa), end = pos + PAGE_SIZE / sizeof(uint32_t);
196                  pos != end; pos++)
197                 if (*pos != 0) {
198                         print_func_exit();
199                         return 0;
200                 }
201         print_func_exit();
202         return 1;
203 }
204
205 static hpa_t litevm_mmu_alloc_page(struct litevm_vcpu *vcpu,
206                                                                    uint64_t * parent_pte)
207 {
208         print_func_entry();
209         struct litevm_mmu_page *page;
210
211         if (LIST_EMPTY(&vcpu->link)) {
212                 print_func_exit();
213                 return INVALID_PAGE;
214         }
215
216         page = LIST_FIRST(&vcpu->link);
217         LIST_REMOVE(page, link);
218         LIST_INSERT_HEAD(&vcpu->litevm->link, page, link);
219         ASSERT(is_empty_shadow_page(page->page_hpa));
220         page->slot_bitmap = 0;
221         page->global = 1;
222         page->parent_pte = parent_pte;
223         print_func_exit();
224         return page->page_hpa;
225 }
226
227 static void page_header_update_slot(struct litevm *litevm, void *pte, gpa_t gpa)
228 {
229         print_func_entry();
230         int slot = memslot_id(litevm, gfn_to_memslot(litevm, gpa >> PAGE_SHIFT));
231         struct litevm_mmu_page *page_head = page_header(PADDR(pte));
232
233         SET_BITMASK_BIT_ATOMIC((uint8_t *) & page_head->slot_bitmap, slot);
234         print_func_exit();
235 }
236
237 hpa_t safe_gpa_to_hpa(struct litevm_vcpu *vcpu, gpa_t gpa)
238 {
239         print_func_entry();
240         hpa_t hpa = gpa_to_hpa(vcpu, gpa);
241
242         print_func_exit();
243         return is_error_hpa(hpa) ? bad_page_address | (gpa & ~PAGE_MASK) : hpa;
244 }
245
246 hpa_t gpa_to_hpa(struct litevm_vcpu * vcpu, gpa_t gpa)
247 {
248         print_func_entry();
249         struct litevm_memory_slot *slot;
250         struct page *page;
251
252         ASSERT((gpa & HPA_ERR_MASK) == 0);
253         slot = gfn_to_memslot(vcpu->litevm, gpa >> PAGE_SHIFT);
254         if (!slot) {
255                 print_func_exit();
256                 return gpa | HPA_ERR_MASK;
257         }
258         page = gfn_to_page(slot, gpa >> PAGE_SHIFT);
259         print_func_exit();
260         return ((hpa_t) page2ppn(page) << PAGE_SHIFT)
261                 | (gpa & (PAGE_SIZE - 1));
262 }
263
264 hpa_t gva_to_hpa(struct litevm_vcpu * vcpu, gva_t gva)
265 {
266         print_func_entry();
267         gpa_t gpa = vcpu->mmu.gva_to_gpa(vcpu, gva);
268
269         if (gpa == UNMAPPED_GVA) {
270                 print_func_exit();
271                 return UNMAPPED_GVA;
272         }
273         print_func_exit();
274         return gpa_to_hpa(vcpu, gpa);
275 }
276
277 static void release_pt_page_64(struct litevm_vcpu *vcpu, hpa_t page_hpa,
278                                                            int level)
279 {
280         print_func_entry();
281         ASSERT(vcpu);
282         ASSERT(VALID_PAGE(page_hpa));
283         ASSERT(level <= PT64_ROOT_LEVEL && level > 0);
284
285         if (level == 1)
286                 memset(KADDR(page_hpa), 0, PAGE_SIZE);
287         else {
288                 uint64_t *pos;
289                 uint64_t *end;
290
291                 for (pos = KADDR(page_hpa), end = pos + PT64_ENT_PER_PAGE;
292                          pos != end; pos++) {
293                         uint64_t current_ent = *pos;
294
295                         *pos = 0;
296                         if (is_present_pte(current_ent))
297                                 release_pt_page_64(vcpu,
298                                                                    current_ent &
299                                                                    PT64_BASE_ADDR_MASK, level - 1);
300                 }
301         }
302         litevm_mmu_free_page(vcpu, page_hpa);
303         print_func_exit();
304 }
305
306 static void nonpaging_new_cr3(struct litevm_vcpu *vcpu)
307 {
308         print_func_entry();
309         print_func_exit();
310 }
311
312 static int nonpaging_map(struct litevm_vcpu *vcpu, gva_t v, hpa_t p)
313 {
314         print_func_entry();
315         int level = PT32E_ROOT_LEVEL;
316         hpa_t table_addr = vcpu->mmu.root_hpa;
317
318         for (;; level--) {
319                 uint32_t index = PT64_INDEX(v, level);
320                 uint64_t *table;
321
322                 ASSERT(VALID_PAGE(table_addr));
323                 table = KADDR(table_addr);
324
325                 if (level == 1) {
326                         mark_page_dirty(vcpu->litevm, v >> PAGE_SHIFT);
327                         page_header_update_slot(vcpu->litevm, table, v);
328                         table[index] = p | PT_PRESENT_MASK | PT_WRITABLE_MASK |
329                                 PT_USER_MASK;
330                         print_func_exit();
331                         return 0;
332                 }
333
334                 if (table[index] == 0) {
335                         hpa_t new_table = litevm_mmu_alloc_page(vcpu,
336                                                                                                         &table[index]);
337
338                         if (!VALID_PAGE(new_table)) {
339                                 pgprintk("nonpaging_map: ENOMEM\n");
340                                 print_func_exit();
341                                 return -ENOMEM;
342                         }
343
344                         if (level == PT32E_ROOT_LEVEL)
345                                 table[index] = new_table | PT_PRESENT_MASK;
346                         else
347                                 table[index] = new_table | PT_PRESENT_MASK |
348                                         PT_WRITABLE_MASK | PT_USER_MASK;
349                 }
350                 table_addr = table[index] & PT64_BASE_ADDR_MASK;
351         }
352         print_func_exit();
353 }
354
355 static void nonpaging_flush(struct litevm_vcpu *vcpu)
356 {
357         print_func_entry();
358         hpa_t root = vcpu->mmu.root_hpa;
359
360         ++litevm_stat.tlb_flush;
361         pgprintk("nonpaging_flush\n");
362         ASSERT(VALID_PAGE(root));
363         release_pt_page_64(vcpu, root, vcpu->mmu.shadow_root_level);
364         root = litevm_mmu_alloc_page(vcpu, 0);
365         ASSERT(VALID_PAGE(root));
366         vcpu->mmu.root_hpa = root;
367         if (is_paging())
368                 root |= (vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK));
369         vmcs_writel(GUEST_CR3, root);
370         print_func_exit();
371 }
372
373 static gpa_t nonpaging_gva_to_gpa(struct litevm_vcpu *vcpu, gva_t vaddr)
374 {
375         print_func_entry();
376         print_func_exit();
377         return vaddr;
378 }
379
380 static int nonpaging_page_fault(struct litevm_vcpu *vcpu, gva_t gva,
381                                                                 uint32_t error_code)
382 {
383         print_func_entry();
384         int ret;
385         gpa_t addr = gva;
386
387         ASSERT(vcpu);
388         ASSERT(VALID_PAGE(vcpu->mmu.root_hpa));
389
390         for (;;) {
391                 hpa_t paddr;
392
393                 paddr = gpa_to_hpa(vcpu, addr & PT64_BASE_ADDR_MASK);
394
395                 if (is_error_hpa(paddr)) {
396                         print_func_exit();
397                         return 1;
398                 }
399
400                 ret = nonpaging_map(vcpu, addr & PAGE_MASK, paddr);
401                 if (ret) {
402                         nonpaging_flush(vcpu);
403                         continue;
404                 }
405                 break;
406         }
407         print_func_exit();
408         return ret;
409 }
410
411 static void nonpaging_inval_page(struct litevm_vcpu *vcpu, gva_t addr)
412 {
413         print_func_entry();
414         print_func_exit();
415 }
416
417 static void nonpaging_free(struct litevm_vcpu *vcpu)
418 {
419         print_func_entry();
420         hpa_t root;
421
422         ASSERT(vcpu);
423         root = vcpu->mmu.root_hpa;
424         if (VALID_PAGE(root))
425                 release_pt_page_64(vcpu, root, vcpu->mmu.shadow_root_level);
426         vcpu->mmu.root_hpa = INVALID_PAGE;
427         print_func_exit();
428 }
429
430 static int nonpaging_init_context(struct litevm_vcpu *vcpu)
431 {
432         print_func_entry();
433         struct litevm_mmu *context = &vcpu->mmu;
434
435         context->new_cr3 = nonpaging_new_cr3;
436         context->page_fault = nonpaging_page_fault;
437         context->inval_page = nonpaging_inval_page;
438         context->gva_to_gpa = nonpaging_gva_to_gpa;
439         context->free = nonpaging_free;
440         context->root_level = PT32E_ROOT_LEVEL;
441         context->shadow_root_level = PT32E_ROOT_LEVEL;
442         context->root_hpa = litevm_mmu_alloc_page(vcpu, 0);
443         ASSERT(VALID_PAGE(context->root_hpa));
444         vmcs_writel(GUEST_CR3, context->root_hpa);
445         print_func_exit();
446         return 0;
447 }
448
449 static void litevm_mmu_flush_tlb(struct litevm_vcpu *vcpu)
450 {
451         print_func_entry();
452         struct litevm_mmu_page *page, *npage;
453
454         //list_for_each_entry_safe(page, npage, &vcpu->litevm->active_mmu_pages,
455         LIST_FOREACH_SAFE(page, &vcpu->litevm->link, link, npage) {
456                 if (page->global)
457                         continue;
458
459                 if (!page->parent_pte)
460                         continue;
461
462                 *page->parent_pte = 0;
463                 release_pt_page_64(vcpu, page->page_hpa, 1);
464         }
465         ++litevm_stat.tlb_flush;
466         print_func_exit();
467 }
468
469 static void paging_new_cr3(struct litevm_vcpu *vcpu)
470 {
471         print_func_entry();
472         litevm_mmu_flush_tlb(vcpu);
473         print_func_exit();
474 }
475
476 static void mark_pagetable_nonglobal(void *shadow_pte)
477 {
478         print_func_entry();
479         page_header(PADDR(shadow_pte))->global = 0;
480         print_func_exit();
481 }
482
483 static inline void set_pte_common(struct litevm_vcpu *vcpu,
484                                                                   uint64_t * shadow_pte,
485                                                                   gpa_t gaddr, int dirty, uint64_t access_bits)
486 {
487         print_func_entry();
488         hpa_t paddr;
489
490         *shadow_pte |= access_bits << PT_SHADOW_BITS_OFFSET;
491         if (!dirty)
492                 access_bits &= ~PT_WRITABLE_MASK;
493
494         if (access_bits & PT_WRITABLE_MASK)
495                 mark_page_dirty(vcpu->litevm, gaddr >> PAGE_SHIFT);
496
497         *shadow_pte |= access_bits;
498
499         paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK);
500
501         if (!(*shadow_pte & PT_GLOBAL_MASK))
502                 mark_pagetable_nonglobal(shadow_pte);
503
504         if (is_error_hpa(paddr)) {
505                 *shadow_pte |= gaddr;
506                 *shadow_pte |= PT_SHADOW_IO_MARK;
507                 *shadow_pte &= ~PT_PRESENT_MASK;
508         } else {
509                 *shadow_pte |= paddr;
510                 page_header_update_slot(vcpu->litevm, shadow_pte, gaddr);
511         }
512         print_func_exit();
513 }
514
515 static void inject_page_fault(struct litevm_vcpu *vcpu,
516                                                           uint64_t addr, uint32_t err_code)
517 {
518         print_func_entry();
519         uint32_t vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
520
521         pgprintk("inject_page_fault: 0x%llx err 0x%x\n", addr, err_code);
522
523         ++litevm_stat.pf_guest;
524
525         if (is_page_fault(vect_info)) {
526                 printd("inject_page_fault: "
527                            "double fault 0x%llx @ 0x%lx\n", addr, vmcs_readl(GUEST_RIP));
528                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
529                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
530                                          DF_VECTOR |
531                                          INTR_TYPE_EXCEPTION |
532                                          INTR_INFO_DELIEVER_CODE_MASK | INTR_INFO_VALID_MASK);
533                 print_func_exit();
534                 return;
535         }
536         vcpu->cr2 = addr;
537         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
538         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
539                                  PF_VECTOR |
540                                  INTR_TYPE_EXCEPTION |
541                                  INTR_INFO_DELIEVER_CODE_MASK | INTR_INFO_VALID_MASK);
542
543         print_func_exit();
544 }
545
546 static inline int fix_read_pf(uint64_t * shadow_ent)
547 {
548         print_func_entry();
549         if ((*shadow_ent & PT_SHADOW_USER_MASK) && !(*shadow_ent & PT_USER_MASK)) {
550                 /*
551                  * If supervisor write protect is disabled, we shadow kernel
552                  * pages as user pages so we can trap the write access.
553                  */
554                 *shadow_ent |= PT_USER_MASK;
555                 *shadow_ent &= ~PT_WRITABLE_MASK;
556
557                 print_func_exit();
558                 return 1;
559
560         }
561         print_func_exit();
562         return 0;
563 }
564
565 static int may_access(uint64_t pte, int write, int user)
566 {
567         print_func_entry();
568
569         if (user && !(pte & PT_USER_MASK)) {
570                 print_func_exit();
571                 return 0;
572         }
573         if (write && !(pte & PT_WRITABLE_MASK)) {
574                 print_func_exit();
575                 return 0;
576         }
577         print_func_exit();
578         return 1;
579 }
580
581 /*
582  * Remove a shadow pte.
583  */
584 static void paging_inval_page(struct litevm_vcpu *vcpu, gva_t addr)
585 {
586         print_func_entry();
587         hpa_t page_addr = vcpu->mmu.root_hpa;
588         int level = vcpu->mmu.shadow_root_level;
589
590         ++litevm_stat.invlpg;
591
592         for (;; level--) {
593                 uint32_t index = PT64_INDEX(addr, level);
594                 uint64_t *table = KADDR(page_addr);
595
596                 if (level == PT_PAGE_TABLE_LEVEL) {
597                         table[index] = 0;
598                         print_func_exit();
599                         return;
600                 }
601
602                 if (!is_present_pte(table[index])) {
603                         print_func_exit();
604                         return;
605                 }
606
607                 page_addr = table[index] & PT64_BASE_ADDR_MASK;
608
609                 if (level == PT_DIRECTORY_LEVEL && (table[index] & PT_SHADOW_PS_MARK)) {
610                         table[index] = 0;
611                         release_pt_page_64(vcpu, page_addr, PT_PAGE_TABLE_LEVEL);
612
613                         //flush tlb
614                         vmcs_writel(GUEST_CR3, vcpu->mmu.root_hpa |
615                                                 (vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK)));
616                         print_func_exit();
617                         return;
618                 }
619         }
620         print_func_exit();
621 }
622
623 static void paging_free(struct litevm_vcpu *vcpu)
624 {
625         print_func_entry();
626         nonpaging_free(vcpu);
627         print_func_exit();
628 }
629
630 #define PTTYPE 64
631 #include "paging_tmpl.h"
632 #undef PTTYPE
633
634 #define PTTYPE 32
635 #include "paging_tmpl.h"
636 #undef PTTYPE
637
638 static int paging64_init_context(struct litevm_vcpu *vcpu)
639 {
640         print_func_entry();
641         struct litevm_mmu *context = &vcpu->mmu;
642
643         ASSERT(is_pae());
644         context->new_cr3 = paging_new_cr3;
645         context->page_fault = paging64_page_fault;
646         context->inval_page = paging_inval_page;
647         context->gva_to_gpa = paging64_gva_to_gpa;
648         context->free = paging_free;
649         context->root_level = PT64_ROOT_LEVEL;
650         context->shadow_root_level = PT64_ROOT_LEVEL;
651         context->root_hpa = litevm_mmu_alloc_page(vcpu, 0);
652         ASSERT(VALID_PAGE(context->root_hpa));
653         vmcs_writel(GUEST_CR3, context->root_hpa |
654                                 (vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK)));
655         print_func_exit();
656         return 0;
657 }
658
659 static int paging32_init_context(struct litevm_vcpu *vcpu)
660 {
661         print_func_entry();
662         struct litevm_mmu *context = &vcpu->mmu;
663
664         context->new_cr3 = paging_new_cr3;
665         context->page_fault = paging32_page_fault;
666         context->inval_page = paging_inval_page;
667         context->gva_to_gpa = paging32_gva_to_gpa;
668         context->free = paging_free;
669         context->root_level = PT32_ROOT_LEVEL;
670         context->shadow_root_level = PT32E_ROOT_LEVEL;
671         context->root_hpa = litevm_mmu_alloc_page(vcpu, 0);
672         ASSERT(VALID_PAGE(context->root_hpa));
673         vmcs_writel(GUEST_CR3, context->root_hpa |
674                                 (vcpu->cr3 & (CR3_PCD_MASK | CR3_WPT_MASK)));
675         print_func_exit();
676         return 0;
677 }
678
679 static int paging32E_init_context(struct litevm_vcpu *vcpu)
680 {
681         print_func_entry();
682         int ret;
683
684         if ((ret = paging64_init_context(vcpu))) {
685                 print_func_exit();
686                 return ret;
687         }
688
689         vcpu->mmu.root_level = PT32E_ROOT_LEVEL;
690         vcpu->mmu.shadow_root_level = PT32E_ROOT_LEVEL;
691         print_func_exit();
692         return 0;
693 }
694
695 static int init_litevm_mmu(struct litevm_vcpu *vcpu)
696 {
697         print_func_entry();
698         ASSERT(vcpu);
699         ASSERT(!VALID_PAGE(vcpu->mmu.root_hpa));
700
701         if (!is_paging()) {
702                 print_func_exit();
703                 return nonpaging_init_context(vcpu);
704         } else if (is_long_mode()) {
705                 print_func_exit();
706                 return paging64_init_context(vcpu);
707         } else if (is_pae()) {
708                 print_func_exit();
709                 return paging32E_init_context(vcpu);
710         } else {
711                 print_func_exit();
712                 return paging32_init_context(vcpu);
713         }
714 }
715
716 static void destroy_litevm_mmu(struct litevm_vcpu *vcpu)
717 {
718         print_func_entry();
719         ASSERT(vcpu);
720         if (VALID_PAGE(vcpu->mmu.root_hpa)) {
721                 vcpu->mmu.free(vcpu);
722                 vcpu->mmu.root_hpa = INVALID_PAGE;
723         }
724         print_func_exit();
725 }
726
727 int litevm_mmu_reset_context(struct litevm_vcpu *vcpu)
728 {
729         print_func_entry();
730         destroy_litevm_mmu(vcpu);
731         print_func_exit();
732         return init_litevm_mmu(vcpu);
733 }
734
735 static void free_mmu_pages(struct litevm_vcpu *vcpu)
736 {
737         print_func_entry();
738         /* todo: use the right macros */
739         while (!LIST_EMPTY(&vcpu->link)) {
740                 struct litevm_mmu_page *vmpage;
741                 vmpage = LIST_FIRST(&vcpu->link);
742                 LIST_REMOVE(vmpage, link);
743                 uintptr_t ppn = vmpage->page_hpa >> PAGE_SHIFT;
744                 page_decref(ppn2page(ppn));
745                 assert(page_is_free(ppn));
746                 vmpage->page_hpa = INVALID_PAGE;
747         }
748         print_func_exit();
749 }
750
751 static int alloc_mmu_pages(struct litevm_vcpu *vcpu)
752 {
753         print_func_entry();
754         int i;
755
756         ASSERT(vcpu);
757
758         /* we could try to do the contiguous alloc but it's not
759          * necessary for them to be contiguous.
760          */
761         for (i = 0; i < LITEVM_NUM_MMU_PAGES; i++) {
762                 struct page *page;
763                 struct litevm_mmu_page *page_header = &vcpu->page_header_buf[i];
764
765                 if (kpage_alloc(&page) != ESUCCESS)
766                         goto error_1;
767                 page->pg_private = page_header;
768                 page_header->page_hpa = (hpa_t) page2pa(page);
769                 memset(KADDR(page_header->page_hpa), 0, PAGE_SIZE);
770                 LIST_INSERT_HEAD(&vcpu->link, page_header, link);
771         }
772         print_func_exit();
773         return 0;
774
775 error_1:
776         free_mmu_pages(vcpu);
777         print_func_exit();
778         return -ENOMEM;
779 }
780
781 int litevm_mmu_init(struct litevm_vcpu *vcpu)
782 {
783         print_func_entry();
784         int r;
785
786         ASSERT(vcpu);
787         ASSERT(!VALID_PAGE(vcpu->mmu.root_hpa));
788         ASSERT(LIST_EMPTY(&vcpu->link));
789
790         if ((r = alloc_mmu_pages(vcpu))) {
791                 print_func_exit();
792                 return r;
793         }
794
795         if ((r = init_litevm_mmu(vcpu))) {
796                 free_mmu_pages(vcpu);
797                 print_func_exit();
798                 return r;
799         }
800         print_func_exit();
801         return 0;
802 }
803
804 void litevm_mmu_destroy(struct litevm_vcpu *vcpu)
805 {
806         print_func_entry();
807         ASSERT(vcpu);
808
809         destroy_litevm_mmu(vcpu);
810         free_mmu_pages(vcpu);
811         print_func_exit();
812 }
813
814 void litevm_mmu_slot_remove_write_access(struct litevm *litevm, int slot)
815 {
816         print_func_entry();
817         struct litevm_mmu_page *page, *link;
818
819         LIST_FOREACH(page, &litevm->link, link) {
820                 int i;
821                 uint64_t *pt;
822
823                 if (!GET_BITMASK_BIT((uint8_t *) & page->slot_bitmap, slot))
824                         continue;
825
826                 pt = KADDR(page->page_hpa);
827                 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
828                         /* avoid RMW */
829                         if (pt[i] & PT_WRITABLE_MASK)
830                                 pt[i] &= ~PT_WRITABLE_MASK;
831
832         }
833         print_func_exit();
834 }