VMM: Move MSR emulation to vmm.c [4/4]
[akaros.git] / kern / arch / x86 / vmm / vmm.c
1 /* Copyright 2015 Google Inc.
2  * 
3  * See LICENSE for details.
4  */
5
6 /* We're not going to falll into the trap of only compiling support
7  * for AMD OR Intel for an image. It all gets compiled in, and which
8  * one you use depends on on cpuinfo, not a compile-time
9  * switch. That's proven to be the best strategy.  Conditionally
10  * compiling in support is the path to hell.
11  */
12 #include <assert.h>
13 #include <pmap.h>
14 #include <smp.h>
15 #include <kmalloc.h>
16
17 #include <ros/vmm.h>
18 #include "intel/vmx.h"
19 #include "vmm.h"
20 #include <trap.h>
21 #include <umem.h>
22
23 /* TODO: have better cpuid info storage and checks */
24 bool x86_supports_vmx = FALSE;
25
26 static void vmmcp_posted_handler(struct hw_trapframe *hw_tf, void *data);
27
28 /* Figure out what kind of CPU we are on, and if it supports any reasonable
29  * virtualization. For now, if we're not some sort of newer intel, don't
30  * bother. This does all cores. Again, note, we make these decisions at runtime,
31  * to avoid getting into the problems that compile-time decisions can cause. 
32  * At this point, of course, it's still all intel.
33  */
34 void vmm_init(void)
35 {
36         int ret;
37         /* Check first for intel capabilities. This is hence two back-to-back
38          * implementationd-dependent checks. That's ok, it's all msr dependent.
39          */
40         ret = intel_vmm_init();
41         if (! ret) {
42                 printd("intel_vmm_init worked\n");
43
44                 //Register I_VMMCP_POSTED IRQ
45                 //register_irq(I_VMMCP_POSTED, vmmcp_posted_handler, NULL,
46                 //              MKBUS(BusLAPIC, 0, 0, 0));
47                 x86_supports_vmx = TRUE;
48                 return;
49         }
50
51         /* TODO: AMD. Will we ever care? It's not clear. */
52         printk("vmm_init failed, ret %d\n", ret);
53         return;
54 }
55
56 static void vmmcp_posted_handler(struct hw_trapframe *hw_tf, void *data)
57 {
58         printk("%s\n", __func__);
59 }
60
61 void vmm_pcpu_init(void)
62 {
63         struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
64
65         pcpui->guest_pcoreid = -1;
66         if (!x86_supports_vmx)
67                 return;
68         if (! intel_vmm_pcpu_init()) {
69                 printd("vmm_pcpu_init worked\n");
70                 return;
71         }
72         /* TODO: AMD. Will we ever care? It's not clear. */
73         printk("vmm_pcpu_init failed\n");
74 }
75
76 int vm_post_interrupt(struct vmctl *v)
77 {
78         int vmx_interrupt_notify(struct vmctl *v);
79         if (current->vmm.amd) {
80                 return -1;
81         } else {
82                 return vmx_interrupt_notify(v);
83         }
84         return -1;
85 }
86
87 int vm_run(struct vmctl *v)
88 {
89         int vmx_launch(struct vmctl *v);
90         if (current->vmm.amd) {
91                 return -1;
92         } else {
93                 return vmx_launch(v);
94         }
95         return -1;
96 }
97
98 /* Initializes a process to run virtual machine contexts, returning the number
99  * initialized, optionally setting errno */
100 int vmm_struct_init(struct proc *p, unsigned int nr_guest_pcores,
101                     struct vmm_gpcore_init *u_gpcis, int flags)
102 {
103         struct vmm *vmm = &p->vmm;
104         unsigned int i;
105         struct vmm_gpcore_init gpci;
106
107         if (flags & ~VMM_ALL_FLAGS) {
108                 set_errstr("%s: flags is 0x%lx, VMM_ALL_FLAGS is 0x%lx\n", __func__,
109                            flags, VMM_ALL_FLAGS);
110                 set_errno(EINVAL);
111                 return 0;
112         }
113         vmm->flags = flags;
114         if (!x86_supports_vmx) {
115                 set_errno(ENODEV);
116                 return 0;
117         }
118         qlock(&vmm->qlock);
119         if (vmm->vmmcp) {
120                 set_errno(EINVAL);
121                 qunlock(&vmm->qlock);
122                 return 0;
123         }
124         /* Set this early, so cleanup checks the gpc array */
125         vmm->vmmcp = TRUE;
126         nr_guest_pcores = MIN(nr_guest_pcores, num_cores);
127         vmm->amd = 0;
128         vmm->guest_pcores = kzmalloc(sizeof(void*) * nr_guest_pcores, KMALLOC_WAIT);
129         for (i = 0; i < nr_guest_pcores; i++) {
130                 if (copy_from_user(&gpci, &u_gpcis[i],
131                                    sizeof(struct vmm_gpcore_init))) {
132                         set_error(EINVAL, "Bad pointer %p for gps", u_gpcis);
133                         break;
134                 }
135                 vmm->guest_pcores[i] = vmx_create_vcpu(p, &gpci);
136                 /* If we failed, we'll clean it up when the process dies */
137                 if (!vmm->guest_pcores[i]) {
138                         set_errno(ENOMEM);
139                         break;
140                 }
141         }
142         vmm->nr_guest_pcores = i;
143         for (int i = 0; i < VMM_VMEXIT_NR_TYPES; i++)
144                 vmm->vmexits[i] = 0;
145         qunlock(&vmm->qlock);
146         return i;
147 }
148
149 /* Has no concurrency protection - only call this when you know you have the
150  * only ref to vmm.  For instance, from __proc_free, where there is only one ref
151  * to the proc (and thus proc.vmm). */
152 void __vmm_struct_cleanup(struct proc *p)
153 {
154         struct vmm *vmm = &p->vmm;
155         if (!vmm->vmmcp)
156                 return;
157         for (int i = 0; i < vmm->nr_guest_pcores; i++) {
158                 if (vmm->guest_pcores[i])
159                         vmx_destroy_vcpu(vmm->guest_pcores[i]);
160         }
161         kfree(vmm->guest_pcores);
162         ept_flush(p->env_pgdir.eptp);
163         vmm->vmmcp = FALSE;
164 }
165
166 struct vmx_vcpu *lookup_guest_pcore(struct proc *p, int guest_pcoreid)
167 {
168         /* nr_guest_pcores is written once at setup and never changed */
169         if (guest_pcoreid >= p->vmm.nr_guest_pcores)
170                 return 0;
171         return p->vmm.guest_pcores[guest_pcoreid];
172 }
173
174 struct vmx_vcpu *load_guest_pcore(struct proc *p, int guest_pcoreid)
175 {
176         struct vmx_vcpu *gpc;
177         struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
178
179         gpc = lookup_guest_pcore(p, guest_pcoreid);
180         if (!gpc)
181                 return 0;
182         assert(pcpui->guest_pcoreid == -1);
183         spin_lock(&p->vmm.lock);
184         if (gpc->cpu != -1) {
185                 spin_unlock(&p->vmm.lock);
186                 return 0;
187         }
188         gpc->cpu = core_id();
189         spin_unlock(&p->vmm.lock);
190         /* We've got dibs on the gpc; we don't need to hold the lock any longer. */
191         pcpui->guest_pcoreid = guest_pcoreid;
192         ept_sync_context(vcpu_get_eptp(gpc));
193         vmx_load_guest_pcore(gpc);
194         return gpc;
195 }
196
197 void unload_guest_pcore(struct proc *p, int guest_pcoreid)
198 {
199         struct vmx_vcpu *gpc;
200         struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
201
202         gpc = lookup_guest_pcore(p, guest_pcoreid);
203         assert(gpc);
204         spin_lock(&p->vmm.lock);
205         assert(gpc->cpu != -1);
206         ept_sync_context(vcpu_get_eptp(gpc));
207         vmx_unload_guest_pcore(gpc);
208         gpc->cpu = -1;
209         /* As soon as we unlock, this gpc can be started on another core */
210         spin_unlock(&p->vmm.lock);
211         pcpui->guest_pcoreid = -1;
212 }
213
214 /* emulated msr. For now, an msr value and a pointer to a helper that
215  * performs the requested operation.
216  */
217 struct emmsr {
218         uint32_t reg;
219         char *name;
220         bool (*f)(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
221                   uint64_t *rax, uint32_t opcode);
222         bool written;
223         uint32_t edx, eax;
224 };
225
226 static bool emsr_miscenable(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
227                             uint64_t *rax, uint32_t opcode);
228 static bool emsr_mustmatch(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
229                            uint64_t *rax, uint32_t opcode);
230 static bool emsr_readonly(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
231                           uint64_t *rax, uint32_t opcode);
232 static bool emsr_readzero(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
233                           uint64_t *rax, uint32_t opcode);
234 static bool emsr_fakewrite(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
235                            uint64_t *rax, uint32_t opcode);
236 static bool emsr_ok(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
237                     uint64_t *rax, uint32_t opcode);
238 static bool emsr_fake_apicbase(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
239                                uint64_t *rax, uint32_t opcode);
240
241 struct emmsr emmsrs[] = {
242         {MSR_IA32_MISC_ENABLE, "MSR_IA32_MISC_ENABLE", emsr_miscenable},
243         {MSR_IA32_SYSENTER_CS, "MSR_IA32_SYSENTER_CS", emsr_ok},
244         {MSR_IA32_SYSENTER_EIP, "MSR_IA32_SYSENTER_EIP", emsr_ok},
245         {MSR_IA32_SYSENTER_ESP, "MSR_IA32_SYSENTER_ESP", emsr_ok},
246         {MSR_IA32_UCODE_REV, "MSR_IA32_UCODE_REV", emsr_fakewrite},
247         {MSR_CSTAR, "MSR_CSTAR", emsr_fakewrite},
248         {MSR_IA32_VMX_BASIC_MSR, "MSR_IA32_VMX_BASIC_MSR", emsr_fakewrite},
249         {MSR_IA32_VMX_PINBASED_CTLS_MSR, "MSR_IA32_VMX_PINBASED_CTLS_MSR",
250          emsr_fakewrite},
251         {MSR_IA32_VMX_PROCBASED_CTLS_MSR, "MSR_IA32_VMX_PROCBASED_CTLS_MSR",
252          emsr_fakewrite},
253         {MSR_IA32_VMX_PROCBASED_CTLS2, "MSR_IA32_VMX_PROCBASED_CTLS2",
254          emsr_fakewrite},
255         {MSR_IA32_VMX_EXIT_CTLS_MSR, "MSR_IA32_VMX_EXIT_CTLS_MSR",
256          emsr_fakewrite},
257         {MSR_IA32_VMX_ENTRY_CTLS_MSR, "MSR_IA32_VMX_ENTRY_CTLS_MSR",
258          emsr_fakewrite},
259         {MSR_IA32_ENERGY_PERF_BIAS, "MSR_IA32_ENERGY_PERF_BIAS",
260          emsr_fakewrite},
261         {MSR_LBR_SELECT, "MSR_LBR_SELECT", emsr_ok},
262         {MSR_LBR_TOS, "MSR_LBR_TOS", emsr_ok},
263         {MSR_LBR_NHM_FROM, "MSR_LBR_NHM_FROM", emsr_ok},
264         {MSR_LBR_NHM_TO, "MSR_LBR_NHM_TO", emsr_ok},
265         {MSR_LBR_CORE_FROM, "MSR_LBR_CORE_FROM", emsr_ok},
266         {MSR_LBR_CORE_TO, "MSR_LBR_CORE_TO", emsr_ok},
267
268         // grumble.
269         {MSR_OFFCORE_RSP_0, "MSR_OFFCORE_RSP_0", emsr_ok},
270         {MSR_OFFCORE_RSP_1, "MSR_OFFCORE_RSP_1", emsr_ok},
271         // louder.
272         {MSR_PEBS_LD_LAT_THRESHOLD, "MSR_PEBS_LD_LAT_THRESHOLD", emsr_ok},
273         // aaaaaahhhhhhhhhhhhhhhhhhhhh
274         {MSR_ARCH_PERFMON_EVENTSEL0, "MSR_ARCH_PERFMON_EVENTSEL0", emsr_ok},
275         {MSR_ARCH_PERFMON_EVENTSEL1, "MSR_ARCH_PERFMON_EVENTSEL0", emsr_ok},
276         {MSR_IA32_PERF_CAPABILITIES, "MSR_IA32_PERF_CAPABILITIES", emsr_ok},
277         // unsafe.
278         {MSR_IA32_APICBASE, "MSR_IA32_APICBASE", emsr_fake_apicbase},
279
280         // mostly harmless.
281         {MSR_TSC_AUX, "MSR_TSC_AUX", emsr_fakewrite},
282         {MSR_RAPL_POWER_UNIT, "MSR_RAPL_POWER_UNIT", emsr_readzero},
283
284         // TBD
285         {MSR_IA32_TSC_DEADLINE, "MSR_IA32_TSC_DEADLINE", emsr_fakewrite},
286 };
287
288 /* this may be the only register that needs special handling.
289  * If there others then we might want to extend the emmsr struct.
290  */
291 bool emsr_miscenable(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
292                      uint64_t *rax, uint32_t opcode)
293 {
294         uint32_t eax, edx;
295
296         rdmsr(msr->reg, eax, edx);
297         /* we just let them read the misc msr for now. */
298         if (opcode == VMM_MSR_EMU_READ) {
299                 *rax = eax;
300                 *rax |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
301                 *rdx = edx;
302                 return TRUE;
303         } else {
304                 /* if they are writing what is already written, that's ok. */
305                 if (((uint32_t) *rax == eax) && ((uint32_t) *rdx == edx))
306                         return TRUE;
307         }
308         printk
309                 ("%s: Wanted to write 0x%x:0x%x, but could not; value was 0x%x:0x%x\n",
310                  msr->name, (uint32_t) *rdx, (uint32_t) *rax, edx, eax);
311         return FALSE;
312 }
313
314 /* TODO: this looks like a copy-paste for the read side.  What's the purpose of
315  * mustmatch?  No one even uses it. */
316 bool emsr_mustmatch(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
317                     uint64_t *rax, uint32_t opcode)
318 {
319         uint32_t eax, edx;
320
321         rdmsr(msr->reg, eax, edx);
322         /* we just let them read the misc msr for now. */
323         if (opcode == VMM_MSR_EMU_READ) {
324                 *rax = eax;
325                 *rdx = edx;
326                 return TRUE;
327         } else {
328                 /* if they are writing what is already written, that's ok. */
329                 if (((uint32_t) *rax == eax) && ((uint32_t) *rdx == edx))
330                         return TRUE;
331         }
332         printk
333                 ("%s: Wanted to write 0x%x:0x%x, but could not; value was 0x%x:0x%x\n",
334                  msr->name, (uint32_t) *rdx, (uint32_t) *rax, edx, eax);
335         return FALSE;
336 }
337
338 bool emsr_readonly(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
339                    uint64_t *rax, uint32_t opcode)
340 {
341         uint32_t eax, edx;
342
343         rdmsr((uint32_t) *rcx, eax, edx);
344         if (opcode == VMM_MSR_EMU_READ) {
345                 *rax = eax;
346                 *rdx = edx;
347                 return TRUE;
348         }
349
350         printk("%s: Tried to write a readonly register\n", msr->name);
351         return FALSE;
352 }
353
354 bool emsr_readzero(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
355                    uint64_t *rax, uint32_t opcode)
356 {
357         if (opcode == VMM_MSR_EMU_READ) {
358                 *rax = 0;
359                 *rdx = 0;
360                 return TRUE;
361         }
362
363         printk("%s: Tried to write a readonly register\n", msr->name);
364         return FALSE;
365 }
366
367 /* pretend to write it, but don't write it. */
368 bool emsr_fakewrite(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
369                     uint64_t *rax, uint32_t opcode)
370 {
371         uint32_t eax, edx;
372
373         if (!msr->written) {
374                 rdmsr(msr->reg, eax, edx);
375         } else {
376                 edx = msr->edx;
377                 eax = msr->eax;
378         }
379         /* we just let them read the misc msr for now. */
380         if (opcode == VMM_MSR_EMU_READ) {
381                 *rax = eax;
382                 *rdx = edx;
383                 return TRUE;
384         } else {
385                 /* if they are writing what is already written, that's ok. */
386                 if (((uint32_t) *rax == eax) && ((uint32_t) *rdx == edx))
387                         return TRUE;
388                 msr->edx = *rdx;
389                 msr->eax = *rax;
390                 msr->written = TRUE;
391         }
392         return TRUE;
393 }
394
395 bool emsr_ok(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
396              uint64_t *rax, uint32_t opcode)
397 {
398         if (opcode == VMM_MSR_EMU_READ) {
399                 rdmsr(msr->reg, *rdx, *rax);
400         } else {
401                 uint64_t val = (uint64_t) *rdx << 32 | *rax;
402
403                 write_msr(msr->reg, val);
404         }
405         return TRUE;
406 }
407
408 /* pretend to write it, but don't write it. */
409 bool emsr_fake_apicbase(struct emmsr *msr, uint64_t *rcx, uint64_t *rdx,
410                         uint64_t *rax, uint32_t opcode)
411 {
412         uint32_t eax, edx;
413
414         if (!msr->written) {
415                 //rdmsr(msr->reg, eax, edx);
416                 /* TODO: tightly coupled to the addr in vmrunkernel.  We want this func
417                  * to return the val that vmrunkernel put into the VMCS. */
418                 eax = 0xfee00900;
419                 edx = 0;
420         } else {
421                 edx = msr->edx;
422                 eax = msr->eax;
423         }
424         /* we just let them read the misc msr for now. */
425         if (opcode == VMM_MSR_EMU_READ) {
426                 *rax = eax;
427                 *rdx = edx;
428                 return TRUE;
429         } else {
430                 /* if they are writing what is already written, that's ok. */
431                 if (((uint32_t) *rax == eax) && ((uint32_t) *rdx == edx))
432                         return 0;
433                 msr->edx = *rdx;
434                 msr->eax = *rax;
435                 msr->written = TRUE;
436         }
437         return TRUE;
438 }
439
440 bool vmm_emulate_msr(uint64_t *rcx, uint64_t *rdx, uint64_t *rax, int op)
441 {
442         for (int i = 0; i < ARRAY_SIZE(emmsrs); i++) {
443                 if (emmsrs[i].reg != *rcx)
444                         continue;
445                 return emmsrs[i].f(&emmsrs[i], rcx, rdx, rax, op);
446         }
447         return FALSE;
448 }