VMX: change msr emulation to pass in the vm trapframe
[akaros.git] / kern / arch / x86 / vmm / vmm.c
1 /* Copyright 2015 Google Inc.
2  *
3  * See LICENSE for details.
4  */
5
6 /* We're not going to falll into the trap of only compiling support
7  * for AMD OR Intel for an image. It all gets compiled in, and which
8  * one you use depends on on cpuinfo, not a compile-time
9  * switch. That's proven to be the best strategy.  Conditionally
10  * compiling in support is the path to hell.
11  */
12 #include <assert.h>
13 #include <pmap.h>
14 #include <smp.h>
15 #include <kmalloc.h>
16
17 #include <ros/vmm.h>
18 #include "intel/vmx.h"
19 #include "vmm.h"
20 #include <trap.h>
21 #include <umem.h>
22
23 #include <arch/x86.h>
24 #include <ros/procinfo.h>
25
26
27 /* TODO: have better cpuid info storage and checks */
28 bool x86_supports_vmx = FALSE;
29
30 /* Figure out what kind of CPU we are on, and if it supports any reasonable
31  * virtualization. For now, if we're not some sort of newer intel, don't
32  * bother. This does all cores. Again, note, we make these decisions at runtime,
33  * to avoid getting into the problems that compile-time decisions can cause.
34  * At this point, of course, it's still all intel.
35  */
36 void vmm_init(void)
37 {
38         int ret;
39         /* Check first for intel capabilities. This is hence two back-to-back
40          * implementationd-dependent checks. That's ok, it's all msr dependent.
41          */
42         ret = intel_vmm_init();
43         if (! ret) {
44                 x86_supports_vmx = TRUE;
45                 return;
46         }
47
48         /* TODO: AMD. Will we ever care? It's not clear. */
49         printk("vmm_init failed, ret %d\n", ret);
50         return;
51 }
52
53 void vmm_pcpu_init(void)
54 {
55         struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
56
57         pcpui->guest_pcoreid = -1;
58         if (!x86_supports_vmx)
59                 return;
60         if (! intel_vmm_pcpu_init()) {
61                 printd("vmm_pcpu_init worked\n");
62                 return;
63         }
64         /* TODO: AMD. Will we ever care? It's not clear. */
65         printk("vmm_pcpu_init failed\n");
66 }
67
68 /* Initializes a process to run virtual machine contexts, returning the number
69  * initialized, throwing on error. */
70 int vmm_struct_init(struct proc *p, unsigned int nr_guest_pcores,
71                     struct vmm_gpcore_init *u_gpcis, int flags)
72 {
73         ERRSTACK(1);
74         struct vmm *vmm = &p->vmm;
75         struct vmm_gpcore_init gpci;
76
77         if (flags & ~VMM_ALL_FLAGS)
78                 error(EINVAL, "%s: flags is 0x%lx, VMM_ALL_FLAGS is 0x%lx\n", __func__,
79                       flags, VMM_ALL_FLAGS);
80         vmm->flags = flags;
81         if (!x86_supports_vmx)
82                 error(ENODEV, "This CPU does not support VMX");
83         qlock(&vmm->qlock);
84         if (waserror()) {
85                 qunlock(&vmm->qlock);
86                 nexterror();
87         }
88
89         /* TODO: just use an atomic test instead of all this locking stuff? */
90         if (vmm->vmmcp)
91                 error(EAGAIN, "We're already running a vmmcp?");
92         /* Set this early, so cleanup checks the gpc array */
93         vmm->vmmcp = TRUE;
94         nr_guest_pcores = MIN(nr_guest_pcores, num_cores);
95         vmm->amd = 0;
96         vmm->guest_pcores = kzmalloc(sizeof(void *) * nr_guest_pcores, MEM_WAIT);
97         if (!vmm->guest_pcores)
98                 error(ENOMEM, "Allocation of vmm->guest_pcores failed");
99
100         for (int i = 0; i < nr_guest_pcores; i++) {
101                 if (copy_from_user(&gpci, &u_gpcis[i], sizeof(struct vmm_gpcore_init)))
102                         error(EINVAL, "Bad pointer %p for gps", u_gpcis);
103                 vmm->guest_pcores[i] = create_guest_pcore(p, &gpci);
104                 vmm->nr_guest_pcores = i + 1;
105         }
106         for (int i = 0; i < VMM_VMEXIT_NR_TYPES; i++)
107                 vmm->vmexits[i] = 0;
108         qunlock(&vmm->qlock);
109         poperror();
110         return vmm->nr_guest_pcores;
111 }
112
113 /* Has no concurrency protection - only call this when you know you have the
114  * only ref to vmm.  For instance, from __proc_free, where there is only one ref
115  * to the proc (and thus proc.vmm). */
116 void __vmm_struct_cleanup(struct proc *p)
117 {
118         struct vmm *vmm = &p->vmm;
119         if (!vmm->vmmcp)
120                 return;
121         for (int i = 0; i < vmm->nr_guest_pcores; i++) {
122                 if (vmm->guest_pcores[i])
123                         destroy_guest_pcore(vmm->guest_pcores[i]);
124         }
125         kfree(vmm->guest_pcores);
126         ept_flush(p->env_pgdir.eptp);
127         vmm->vmmcp = FALSE;
128 }
129
130 int vmm_poke_guest(struct proc *p, int guest_pcoreid)
131 {
132         struct guest_pcore *gpc;
133         int pcoreid;
134
135         gpc = lookup_guest_pcore(p, guest_pcoreid);
136         if (!gpc) {
137                 set_error(ENOENT, "Bad guest_pcoreid %d", guest_pcoreid);
138                 return -1;
139         }
140         /* We're doing an unlocked peek; it could change immediately.  This is a
141          * best effort service. */
142         pcoreid = ACCESS_ONCE(gpc->cpu);
143         if (pcoreid == -1) {
144                 /* So we know that we'll miss the poke for the posted IRQ.  We could
145                  * return an error.  However, error handling for this case isn't
146                  * particularly helpful (yet).  The absence of the error does not mean
147                  * the IRQ was posted.  We'll still return 0, meaning "the user didn't
148                  * mess up; we tried." */
149                 return 0;
150         }
151         send_ipi(pcoreid, I_POKE_CORE);
152         return 0;
153 }
154
155 struct guest_pcore *lookup_guest_pcore(struct proc *p, int guest_pcoreid)
156 {
157         /* nr_guest_pcores is written once at setup and never changed */
158         if (guest_pcoreid >= p->vmm.nr_guest_pcores)
159                 return 0;
160         return p->vmm.guest_pcores[guest_pcoreid];
161 }
162
163 struct guest_pcore *load_guest_pcore(struct proc *p, int guest_pcoreid,
164                                      bool *should_vmresume)
165 {
166         struct guest_pcore *gpc;
167         struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
168
169         gpc = lookup_guest_pcore(p, guest_pcoreid);
170         if (!gpc)
171                 return 0;
172         assert(pcpui->guest_pcoreid == -1);
173         spin_lock(&p->vmm.lock);
174         if (gpc->cpu != -1) {
175                 spin_unlock(&p->vmm.lock);
176                 return 0;
177         }
178         gpc->cpu = core_id();
179         spin_unlock(&p->vmm.lock);
180         /* We've got dibs on the gpc; we don't need to hold the lock any longer. */
181         pcpui->guest_pcoreid = guest_pcoreid;
182         vmx_load_guest_pcore(gpc, should_vmresume);
183         /* Load guest's xcr0 */
184         lxcr0(gpc->xcr0);
185
186         /* Manual MSR save/restore */
187         write_kern_gsbase(gpc->msr_kern_gs_base);
188         if (gpc->msr_star != AKAROS_MSR_STAR)
189                 write_msr(MSR_STAR, gpc->msr_star);
190         if (gpc->msr_lstar != AKAROS_MSR_LSTAR)
191                 write_msr(MSR_LSTAR, gpc->msr_lstar);
192         if (gpc->msr_sfmask != AKAROS_MSR_SFMASK)
193                 write_msr(MSR_SFMASK, gpc->msr_sfmask);
194
195         return gpc;
196 }
197
198 void unload_guest_pcore(struct proc *p, int guest_pcoreid)
199 {
200         struct guest_pcore *gpc;
201         struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
202
203         gpc = lookup_guest_pcore(p, guest_pcoreid);
204         assert(gpc);
205         spin_lock(&p->vmm.lock);
206         assert(gpc->cpu != -1);
207         vmx_unload_guest_pcore(gpc);
208         gpc->cpu = -1;
209
210         /* Save guest's xcr0 and restore Akaros's default. */
211         gpc->xcr0 = rxcr0();
212         lxcr0(__proc_global_info.x86_default_xcr0);
213
214         /* We manage these MSRs manually. */
215         gpc->msr_kern_gs_base = read_kern_gsbase();
216         gpc->msr_star = read_msr(MSR_STAR);
217         gpc->msr_lstar = read_msr(MSR_LSTAR);
218         gpc->msr_sfmask = read_msr(MSR_SFMASK);
219
220         write_kern_gsbase((uint64_t)pcpui);
221         if (gpc->msr_star != AKAROS_MSR_STAR)
222                 write_msr(MSR_STAR, AKAROS_MSR_STAR);
223         if (gpc->msr_lstar != AKAROS_MSR_LSTAR)
224                 write_msr(MSR_LSTAR, AKAROS_MSR_LSTAR);
225         if (gpc->msr_sfmask, AKAROS_MSR_SFMASK)
226                 write_msr(MSR_SFMASK, AKAROS_MSR_SFMASK);
227
228         /* As soon as we unlock, this gpc can be started on another core */
229         spin_unlock(&p->vmm.lock);
230         pcpui->guest_pcoreid = -1;
231 }
232
233 /* emulated msr. For now, an msr value and a pointer to a helper that
234  * performs the requested operation.
235  */
236 struct emmsr {
237         uint32_t reg;
238         char *name;
239         bool (*f)(struct emmsr *msr, struct vm_trapframe *vm_tf,
240                   uint32_t opcode);
241         bool written;
242         uint32_t edx, eax;
243 };
244
245 static bool emsr_miscenable(struct emmsr *msr, struct vm_trapframe *vm_tf,
246                             uint32_t opcode);
247 static bool emsr_mustmatch(struct emmsr *msr, struct vm_trapframe *vm_tf,
248                            uint32_t opcode);
249 static bool emsr_readonly(struct emmsr *msr, struct vm_trapframe *vm_tf,
250                           uint32_t opcode);
251 static bool emsr_readzero(struct emmsr *msr, struct vm_trapframe *vm_tf,
252                           uint32_t opcode);
253 static bool emsr_fakewrite(struct emmsr *msr, struct vm_trapframe *vm_tf,
254                            uint32_t opcode);
255 static bool emsr_ok(struct emmsr *msr, struct vm_trapframe *vm_tf,
256                     uint32_t opcode);
257 static bool emsr_fake_apicbase(struct emmsr *msr, struct vm_trapframe *vm_tf,
258                                uint32_t opcode);
259
260 struct emmsr emmsrs[] = {
261         {MSR_IA32_MISC_ENABLE, "MSR_IA32_MISC_ENABLE", emsr_miscenable},
262         {MSR_IA32_SYSENTER_CS, "MSR_IA32_SYSENTER_CS", emsr_ok},
263         {MSR_IA32_SYSENTER_EIP, "MSR_IA32_SYSENTER_EIP", emsr_ok},
264         {MSR_IA32_SYSENTER_ESP, "MSR_IA32_SYSENTER_ESP", emsr_ok},
265         {MSR_IA32_UCODE_REV, "MSR_IA32_UCODE_REV", emsr_fakewrite},
266         {MSR_CSTAR, "MSR_CSTAR", emsr_fakewrite},
267         {MSR_IA32_VMX_BASIC_MSR, "MSR_IA32_VMX_BASIC_MSR", emsr_fakewrite},
268         {MSR_IA32_VMX_PINBASED_CTLS_MSR, "MSR_IA32_VMX_PINBASED_CTLS_MSR",
269          emsr_fakewrite},
270         {MSR_IA32_VMX_PROCBASED_CTLS_MSR, "MSR_IA32_VMX_PROCBASED_CTLS_MSR",
271          emsr_fakewrite},
272         {MSR_IA32_VMX_PROCBASED_CTLS2, "MSR_IA32_VMX_PROCBASED_CTLS2",
273          emsr_fakewrite},
274         {MSR_IA32_VMX_EXIT_CTLS_MSR, "MSR_IA32_VMX_EXIT_CTLS_MSR",
275          emsr_fakewrite},
276         {MSR_IA32_VMX_ENTRY_CTLS_MSR, "MSR_IA32_VMX_ENTRY_CTLS_MSR",
277          emsr_fakewrite},
278         {MSR_IA32_ENERGY_PERF_BIAS, "MSR_IA32_ENERGY_PERF_BIAS",
279          emsr_fakewrite},
280         {MSR_LBR_SELECT, "MSR_LBR_SELECT", emsr_ok},
281         {MSR_LBR_TOS, "MSR_LBR_TOS", emsr_ok},
282         {MSR_LBR_NHM_FROM, "MSR_LBR_NHM_FROM", emsr_ok},
283         {MSR_LBR_NHM_TO, "MSR_LBR_NHM_TO", emsr_ok},
284         {MSR_LBR_CORE_FROM, "MSR_LBR_CORE_FROM", emsr_ok},
285         {MSR_LBR_CORE_TO, "MSR_LBR_CORE_TO", emsr_ok},
286
287         // grumble.
288         {MSR_OFFCORE_RSP_0, "MSR_OFFCORE_RSP_0", emsr_ok},
289         {MSR_OFFCORE_RSP_1, "MSR_OFFCORE_RSP_1", emsr_ok},
290         // louder.
291         {MSR_PEBS_LD_LAT_THRESHOLD, "MSR_PEBS_LD_LAT_THRESHOLD", emsr_ok},
292         // aaaaaahhhhhhhhhhhhhhhhhhhhh
293         {MSR_ARCH_PERFMON_EVENTSEL0, "MSR_ARCH_PERFMON_EVENTSEL0", emsr_ok},
294         {MSR_ARCH_PERFMON_EVENTSEL1, "MSR_ARCH_PERFMON_EVENTSEL1", emsr_ok},
295         {MSR_IA32_PERF_CAPABILITIES, "MSR_IA32_PERF_CAPABILITIES", emsr_readzero},
296         // unsafe.
297         {MSR_IA32_APICBASE, "MSR_IA32_APICBASE", emsr_fake_apicbase},
298
299         // mostly harmless.
300         {MSR_TSC_AUX, "MSR_TSC_AUX", emsr_fakewrite},
301         {MSR_RAPL_POWER_UNIT, "MSR_RAPL_POWER_UNIT", emsr_readzero},
302         {MSR_IA32_MCG_CAP, "MSR_IA32_MCG_CAP", emsr_readzero},
303         {MSR_IA32_DEBUGCTLMSR, "MSR_IA32_DEBUGCTLMSR", emsr_fakewrite},
304
305         // TBD
306         {MSR_IA32_TSC_DEADLINE, "MSR_IA32_TSC_DEADLINE", emsr_fakewrite},
307 };
308
309 /* this may be the only register that needs special handling.
310  * If there others then we might want to extend the emmsr struct.
311  */
312 bool emsr_miscenable(struct emmsr *msr, struct vm_trapframe *vm_tf,
313                      uint32_t opcode)
314 {
315         uint32_t eax, edx;
316         uint64_t val;
317
318         if (read_msr_safe(msr->reg, &val))
319                 return FALSE;
320         split_msr_val(val, &edx, &eax);
321         /* we just let them read the misc msr for now. */
322         if (opcode == VMM_MSR_EMU_READ) {
323                 vm_tf->tf_rax = eax;
324                 vm_tf->tf_rax |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
325                 vm_tf->tf_rdx = edx;
326                 return TRUE;
327         } else {
328                 /* if they are writing what is already written, that's ok. */
329                 eax |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
330                 if (((uint32_t) vm_tf->tf_rax == eax)
331                     && ((uint32_t) vm_tf->tf_rdx == edx))
332                         return TRUE;
333         }
334         printk
335                 ("%s: Wanted to write 0x%x:0x%x, but could not; value was 0x%x:0x%x\n",
336                  msr->name, (uint32_t) vm_tf->tf_rdx, (uint32_t) vm_tf->tf_rax, edx,
337                  eax);
338         return FALSE;
339 }
340
341 /* TODO: this looks like a copy-paste for the read side.  What's the purpose of
342  * mustmatch?  No one even uses it. */
343 bool emsr_mustmatch(struct emmsr *msr, struct vm_trapframe *vm_tf,
344                     uint32_t opcode)
345 {
346         uint32_t eax, edx;
347         uint64_t val;
348
349         if (read_msr_safe(msr->reg, &val))
350                 return FALSE;
351         split_msr_val(val, &edx, &eax);
352         /* we just let them read the misc msr for now. */
353         if (opcode == VMM_MSR_EMU_READ) {
354                 vm_tf->tf_rax = eax;
355                 vm_tf->tf_rdx = edx;
356                 return TRUE;
357         } else {
358                 /* if they are writing what is already written, that's ok. */
359                 if (((uint32_t) vm_tf->tf_rax == eax)
360                     && ((uint32_t) vm_tf->tf_rdx == edx))
361                         return TRUE;
362         }
363         printk
364                 ("%s: Wanted to write 0x%x:0x%x, but could not; value was 0x%x:0x%x\n",
365                  msr->name, (uint32_t) vm_tf->tf_rdx, (uint32_t) vm_tf->tf_rax, edx,
366                  eax);
367         return FALSE;
368 }
369
370 bool emsr_readonly(struct emmsr *msr, struct vm_trapframe *vm_tf,
371                    uint32_t opcode)
372 {
373         uint32_t eax, edx;
374         uint64_t val;
375
376         if (read_msr_safe(msr->reg, &val))
377                 return FALSE;
378         split_msr_val(val, &edx, &eax);
379         if (opcode == VMM_MSR_EMU_READ) {
380                 vm_tf->tf_rax = eax;
381                 vm_tf->tf_rdx = edx;
382                 return TRUE;
383         }
384
385         printk("%s: Tried to write a readonly register\n", msr->name);
386         return FALSE;
387 }
388
389 bool emsr_readzero(struct emmsr *msr, struct vm_trapframe *vm_tf,
390                    uint32_t opcode)
391 {
392         if (opcode == VMM_MSR_EMU_READ) {
393                 vm_tf->tf_rax = 0;
394                 vm_tf->tf_rdx = 0;
395                 return TRUE;
396         }
397
398         printk("%s: Tried to write a readonly register\n", msr->name);
399         return FALSE;
400 }
401
402 /* pretend to write it, but don't write it. */
403 bool emsr_fakewrite(struct emmsr *msr, struct vm_trapframe *vm_tf,
404                     uint32_t opcode)
405 {
406         uint32_t eax, edx;
407         uint64_t val;
408
409         if (!msr->written) {
410                 if (read_msr_safe(msr->reg, &val))
411                         return FALSE;
412                 split_msr_val(val, &edx, &eax);
413         } else {
414                 edx = msr->edx;
415                 eax = msr->eax;
416         }
417         /* we just let them read the misc msr for now. */
418         if (opcode == VMM_MSR_EMU_READ) {
419                 vm_tf->tf_rax = eax;
420                 vm_tf->tf_rdx = edx;
421                 return TRUE;
422         } else {
423                 /* if they are writing what is already written, that's ok. */
424                 if (((uint32_t) vm_tf->tf_rax == eax)
425                     && ((uint32_t) vm_tf->tf_rdx == edx))
426                         return TRUE;
427                 msr->edx = vm_tf->tf_rdx;
428                 msr->eax = vm_tf->tf_rax;
429                 msr->written = TRUE;
430         }
431         return TRUE;
432 }
433
434 bool emsr_ok(struct emmsr *msr, struct vm_trapframe *vm_tf,
435              uint32_t opcode)
436 {
437         uint32_t eax, edx;
438         uint64_t val;
439
440         if (opcode == VMM_MSR_EMU_READ) {
441                 if (read_msr_safe(msr->reg, &val))
442                         return FALSE;
443                 split_msr_val(val, &edx, &eax);
444                 vm_tf->tf_rax = eax;
445                 vm_tf->tf_rdx = edx;
446         } else {
447                 val = (vm_tf->tf_rdx << 32) | (vm_tf->tf_rax & 0xffffffff);
448                 if (write_msr_safe(msr->reg, val))
449                         return FALSE;
450         }
451         return TRUE;
452 }
453
454 /* pretend to write it, but don't write it. */
455 bool emsr_fake_apicbase(struct emmsr *msr, struct vm_trapframe *vm_tf,
456                         uint32_t opcode)
457 {
458         uint32_t eax, edx;
459
460         if (!msr->written) {
461                 /* TODO: tightly coupled to the addr in vmrunkernel.  We want this func
462                  * to return the val that vmrunkernel put into the VMCS. */
463                 eax = 0xfee00900;
464                 edx = 0;
465         } else {
466                 edx = msr->edx;
467                 eax = msr->eax;
468         }
469         /* we just let them read the misc msr for now. */
470         if (opcode == VMM_MSR_EMU_READ) {
471                 vm_tf->tf_rax = eax;
472                 vm_tf->tf_rdx = edx;
473                 return TRUE;
474         } else {
475                 /* if they are writing what is already written, that's ok. */
476                 if (((uint32_t) vm_tf->tf_rax == eax)
477                     && ((uint32_t) vm_tf->tf_rdx == edx))
478                         return 0;
479                 msr->edx = vm_tf->tf_rdx;
480                 msr->eax = vm_tf->tf_rax;
481                 msr->written = TRUE;
482         }
483         return TRUE;
484 }
485
486 bool vmm_emulate_msr(struct vm_trapframe *vm_tf, int op)
487 {
488         for (int i = 0; i < ARRAY_SIZE(emmsrs); i++) {
489                 if (emmsrs[i].reg != vm_tf->tf_rcx)
490                         continue;
491                 return emmsrs[i].f(&emmsrs[i], vm_tf, op);
492         }
493         return FALSE;
494 }