x86: Remove split_msr_val()
[akaros.git] / kern / arch / x86 / vmm / vmm.c
1 /* Copyright 2015 Google Inc.
2  *
3  * See LICENSE for details.
4  */
5
6 /* We're not going to falll into the trap of only compiling support
7  * for AMD OR Intel for an image. It all gets compiled in, and which
8  * one you use depends on on cpuinfo, not a compile-time
9  * switch. That's proven to be the best strategy.  Conditionally
10  * compiling in support is the path to hell.
11  */
12 #include <assert.h>
13 #include <pmap.h>
14 #include <smp.h>
15 #include <kmalloc.h>
16
17 #include <ros/vmm.h>
18 #include "intel/vmx.h"
19 #include "vmm.h"
20 #include <trap.h>
21 #include <umem.h>
22
23 #include <arch/x86.h>
24 #include <ros/procinfo.h>
25
26
27 /* TODO: have better cpuid info storage and checks */
28 bool x86_supports_vmx = FALSE;
29
30 /* Figure out what kind of CPU we are on, and if it supports any reasonable
31  * virtualization. For now, if we're not some sort of newer intel, don't
32  * bother. This does all cores. Again, note, we make these decisions at runtime,
33  * to avoid getting into the problems that compile-time decisions can cause.
34  * At this point, of course, it's still all intel.
35  */
36 void vmm_init(void)
37 {
38         int ret;
39         /* Check first for intel capabilities. This is hence two back-to-back
40          * implementationd-dependent checks. That's ok, it's all msr dependent.
41          */
42         ret = intel_vmm_init();
43         if (! ret) {
44                 x86_supports_vmx = TRUE;
45                 return;
46         }
47
48         /* TODO: AMD. Will we ever care? It's not clear. */
49         printk("vmm_init failed, ret %d\n", ret);
50         return;
51 }
52
53 void vmm_pcpu_init(void)
54 {
55         struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
56
57         pcpui->guest_pcoreid = -1;
58         if (!x86_supports_vmx)
59                 return;
60         if (! intel_vmm_pcpu_init()) {
61                 printd("vmm_pcpu_init worked\n");
62                 return;
63         }
64         /* TODO: AMD. Will we ever care? It's not clear. */
65         printk("vmm_pcpu_init failed\n");
66 }
67
68 /* Initializes a process to run virtual machine contexts, returning the number
69  * initialized, throwing on error. */
70 int vmm_struct_init(struct proc *p, unsigned int nr_guest_pcores,
71                     struct vmm_gpcore_init *u_gpcis, int flags)
72 {
73         ERRSTACK(1);
74         struct vmm *vmm = &p->vmm;
75         struct vmm_gpcore_init gpci;
76
77         if (flags & ~VMM_ALL_FLAGS)
78                 error(EINVAL, "%s: flags is 0x%lx, VMM_ALL_FLAGS is 0x%lx\n", __func__,
79                       flags, VMM_ALL_FLAGS);
80         vmm->flags = flags;
81         if (!x86_supports_vmx)
82                 error(ENODEV, "This CPU does not support VMX");
83         qlock(&vmm->qlock);
84         if (waserror()) {
85                 qunlock(&vmm->qlock);
86                 nexterror();
87         }
88
89         /* TODO: just use an atomic test instead of all this locking stuff? */
90         if (vmm->vmmcp)
91                 error(EAGAIN, "We're already running a vmmcp?");
92         /* Set this early, so cleanup checks the gpc array */
93         vmm->vmmcp = TRUE;
94         nr_guest_pcores = MIN(nr_guest_pcores, num_cores);
95         vmm->amd = 0;
96         vmm->guest_pcores = kzmalloc(sizeof(void *) * nr_guest_pcores, MEM_WAIT);
97         if (!vmm->guest_pcores)
98                 error(ENOMEM, "Allocation of vmm->guest_pcores failed");
99
100         for (int i = 0; i < nr_guest_pcores; i++) {
101                 if (copy_from_user(&gpci, &u_gpcis[i], sizeof(struct vmm_gpcore_init)))
102                         error(EINVAL, "Bad pointer %p for gps", u_gpcis);
103                 vmm->guest_pcores[i] = create_guest_pcore(p, &gpci);
104                 vmm->nr_guest_pcores = i + 1;
105         }
106         for (int i = 0; i < VMM_VMEXIT_NR_TYPES; i++)
107                 vmm->vmexits[i] = 0;
108         qunlock(&vmm->qlock);
109         poperror();
110         return vmm->nr_guest_pcores;
111 }
112
113 /* Has no concurrency protection - only call this when you know you have the
114  * only ref to vmm.  For instance, from __proc_free, where there is only one ref
115  * to the proc (and thus proc.vmm). */
116 void __vmm_struct_cleanup(struct proc *p)
117 {
118         struct vmm *vmm = &p->vmm;
119         if (!vmm->vmmcp)
120                 return;
121         for (int i = 0; i < vmm->nr_guest_pcores; i++) {
122                 if (vmm->guest_pcores[i])
123                         destroy_guest_pcore(vmm->guest_pcores[i]);
124         }
125         kfree(vmm->guest_pcores);
126         ept_flush(p->env_pgdir.eptp);
127         vmm->vmmcp = FALSE;
128 }
129
130 int vmm_poke_guest(struct proc *p, int guest_pcoreid)
131 {
132         struct guest_pcore *gpc;
133         int pcoreid;
134
135         gpc = lookup_guest_pcore(p, guest_pcoreid);
136         if (!gpc) {
137                 set_error(ENOENT, "Bad guest_pcoreid %d", guest_pcoreid);
138                 return -1;
139         }
140         /* We're doing an unlocked peek; it could change immediately.  This is a
141          * best effort service. */
142         pcoreid = ACCESS_ONCE(gpc->cpu);
143         if (pcoreid == -1) {
144                 /* So we know that we'll miss the poke for the posted IRQ.  We could
145                  * return an error.  However, error handling for this case isn't
146                  * particularly helpful (yet).  The absence of the error does not mean
147                  * the IRQ was posted.  We'll still return 0, meaning "the user didn't
148                  * mess up; we tried." */
149                 return 0;
150         }
151         send_ipi(pcoreid, I_POKE_GUEST);
152         return 0;
153 }
154
155 struct guest_pcore *lookup_guest_pcore(struct proc *p, int guest_pcoreid)
156 {
157         /* nr_guest_pcores is written once at setup and never changed */
158         if (guest_pcoreid >= p->vmm.nr_guest_pcores)
159                 return 0;
160         return p->vmm.guest_pcores[guest_pcoreid];
161 }
162
163 struct guest_pcore *load_guest_pcore(struct proc *p, int guest_pcoreid)
164 {
165         struct guest_pcore *gpc;
166         struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
167
168         gpc = lookup_guest_pcore(p, guest_pcoreid);
169         if (!gpc)
170                 return 0;
171         assert(pcpui->guest_pcoreid == -1);
172         spin_lock(&p->vmm.lock);
173         if (gpc->cpu != -1) {
174                 spin_unlock(&p->vmm.lock);
175                 return 0;
176         }
177         gpc->cpu = core_id();
178         spin_unlock(&p->vmm.lock);
179         /* We've got dibs on the gpc; we don't need to hold the lock any longer. */
180         pcpui->guest_pcoreid = guest_pcoreid;
181         vmx_load_guest_pcore(gpc);
182         /* Load guest's xcr0 */
183         lxcr0(gpc->xcr0);
184
185         /* Manual MSR save/restore */
186         write_kern_gsbase(gpc->msr_kern_gs_base);
187         if (gpc->msr_star != AKAROS_MSR_STAR)
188                 write_msr(MSR_STAR, gpc->msr_star);
189         if (gpc->msr_lstar != AKAROS_MSR_LSTAR)
190                 write_msr(MSR_LSTAR, gpc->msr_lstar);
191         if (gpc->msr_sfmask != AKAROS_MSR_SFMASK)
192                 write_msr(MSR_SFMASK, gpc->msr_sfmask);
193
194         return gpc;
195 }
196
197 void unload_guest_pcore(struct proc *p, int guest_pcoreid)
198 {
199         struct guest_pcore *gpc;
200         struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
201
202         gpc = lookup_guest_pcore(p, guest_pcoreid);
203         assert(gpc);
204         spin_lock(&p->vmm.lock);
205         assert(gpc->cpu != -1);
206         vmx_unload_guest_pcore(gpc);
207         gpc->cpu = -1;
208
209         /* Save guest's xcr0 and restore Akaros's default. */
210         gpc->xcr0 = rxcr0();
211         lxcr0(__proc_global_info.x86_default_xcr0);
212
213         /* We manage these MSRs manually. */
214         gpc->msr_kern_gs_base = read_kern_gsbase();
215         gpc->msr_star = read_msr(MSR_STAR);
216         gpc->msr_lstar = read_msr(MSR_LSTAR);
217         gpc->msr_sfmask = read_msr(MSR_SFMASK);
218
219         write_kern_gsbase((uint64_t)pcpui);
220         if (gpc->msr_star != AKAROS_MSR_STAR)
221                 write_msr(MSR_STAR, AKAROS_MSR_STAR);
222         if (gpc->msr_lstar != AKAROS_MSR_LSTAR)
223                 write_msr(MSR_LSTAR, AKAROS_MSR_LSTAR);
224         if (gpc->msr_sfmask, AKAROS_MSR_SFMASK)
225                 write_msr(MSR_SFMASK, AKAROS_MSR_SFMASK);
226
227         /* As soon as we unlock, this gpc can be started on another core */
228         spin_unlock(&p->vmm.lock);
229         pcpui->guest_pcoreid = -1;
230 }
231
232 /* emulated msr. For now, an msr value and a pointer to a helper that
233  * performs the requested operation.
234  */
235 struct emmsr {
236         uint32_t reg;
237         char *name;
238         bool (*f)(struct emmsr *msr, struct vm_trapframe *vm_tf,
239                   uint32_t opcode);
240         bool written;
241         uint32_t edx, eax;
242 };
243
244 static bool emsr_miscenable(struct emmsr *msr, struct vm_trapframe *vm_tf,
245                             uint32_t opcode);
246 static bool emsr_readonly(struct emmsr *msr, struct vm_trapframe *vm_tf,
247                           uint32_t opcode);
248 static bool emsr_readzero(struct emmsr *msr, struct vm_trapframe *vm_tf,
249                           uint32_t opcode);
250 static bool emsr_fakewrite(struct emmsr *msr, struct vm_trapframe *vm_tf,
251                            uint32_t opcode);
252 static bool emsr_ok(struct emmsr *msr, struct vm_trapframe *vm_tf,
253                     uint32_t opcode);
254 static bool emsr_fake_apicbase(struct emmsr *msr, struct vm_trapframe *vm_tf,
255                                uint32_t opcode);
256
257 struct emmsr emmsrs[] = {
258         {MSR_IA32_MISC_ENABLE, "MSR_IA32_MISC_ENABLE", emsr_miscenable},
259         {MSR_IA32_SYSENTER_CS, "MSR_IA32_SYSENTER_CS", emsr_ok},
260         {MSR_IA32_SYSENTER_EIP, "MSR_IA32_SYSENTER_EIP", emsr_ok},
261         {MSR_IA32_SYSENTER_ESP, "MSR_IA32_SYSENTER_ESP", emsr_ok},
262         {MSR_IA32_UCODE_REV, "MSR_IA32_UCODE_REV", emsr_fakewrite},
263         {MSR_CSTAR, "MSR_CSTAR", emsr_fakewrite},
264         {MSR_IA32_VMX_BASIC_MSR, "MSR_IA32_VMX_BASIC_MSR", emsr_fakewrite},
265         {MSR_IA32_VMX_PINBASED_CTLS_MSR, "MSR_IA32_VMX_PINBASED_CTLS_MSR",
266          emsr_fakewrite},
267         {MSR_IA32_VMX_PROCBASED_CTLS_MSR, "MSR_IA32_VMX_PROCBASED_CTLS_MSR",
268          emsr_fakewrite},
269         {MSR_IA32_VMX_PROCBASED_CTLS2, "MSR_IA32_VMX_PROCBASED_CTLS2",
270          emsr_fakewrite},
271         {MSR_IA32_VMX_EXIT_CTLS_MSR, "MSR_IA32_VMX_EXIT_CTLS_MSR",
272          emsr_fakewrite},
273         {MSR_IA32_VMX_ENTRY_CTLS_MSR, "MSR_IA32_VMX_ENTRY_CTLS_MSR",
274          emsr_fakewrite},
275         {MSR_IA32_ENERGY_PERF_BIAS, "MSR_IA32_ENERGY_PERF_BIAS",
276          emsr_fakewrite},
277         {MSR_LBR_SELECT, "MSR_LBR_SELECT", emsr_ok},
278         {MSR_LBR_TOS, "MSR_LBR_TOS", emsr_ok},
279         {MSR_LBR_NHM_FROM, "MSR_LBR_NHM_FROM", emsr_ok},
280         {MSR_LBR_NHM_TO, "MSR_LBR_NHM_TO", emsr_ok},
281         {MSR_LBR_CORE_FROM, "MSR_LBR_CORE_FROM", emsr_ok},
282         {MSR_LBR_CORE_TO, "MSR_LBR_CORE_TO", emsr_ok},
283
284         // grumble.
285         {MSR_OFFCORE_RSP_0, "MSR_OFFCORE_RSP_0", emsr_ok},
286         {MSR_OFFCORE_RSP_1, "MSR_OFFCORE_RSP_1", emsr_ok},
287         // louder.
288         {MSR_PEBS_LD_LAT_THRESHOLD, "MSR_PEBS_LD_LAT_THRESHOLD", emsr_ok},
289         // aaaaaahhhhhhhhhhhhhhhhhhhhh
290         {MSR_ARCH_PERFMON_EVENTSEL0, "MSR_ARCH_PERFMON_EVENTSEL0", emsr_ok},
291         {MSR_ARCH_PERFMON_EVENTSEL1, "MSR_ARCH_PERFMON_EVENTSEL1", emsr_ok},
292         {MSR_IA32_PERF_CAPABILITIES, "MSR_IA32_PERF_CAPABILITIES", emsr_readzero},
293         // unsafe.
294         {MSR_IA32_APICBASE, "MSR_IA32_APICBASE", emsr_fake_apicbase},
295
296         // mostly harmless.
297         {MSR_TSC_AUX, "MSR_TSC_AUX", emsr_fakewrite},
298         {MSR_RAPL_POWER_UNIT, "MSR_RAPL_POWER_UNIT", emsr_readzero},
299         {MSR_IA32_MCG_CAP, "MSR_IA32_MCG_CAP", emsr_readzero},
300         {MSR_IA32_DEBUGCTLMSR, "MSR_IA32_DEBUGCTLMSR", emsr_fakewrite},
301
302         // TBD
303         {MSR_IA32_TSC_DEADLINE, "MSR_IA32_TSC_DEADLINE", emsr_fakewrite},
304 };
305
306 /* this may be the only register that needs special handling.
307  * If there others then we might want to extend the emmsr struct.
308  */
309 bool emsr_miscenable(struct emmsr *msr, struct vm_trapframe *vm_tf,
310                      uint32_t opcode)
311 {
312         uint64_t val;
313         uint32_t eax, edx;
314
315         if (read_msr_safe(msr->reg, &val))
316                 return FALSE;
317         eax = low32(val);
318         eax |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
319         edx = high32(val);
320         /* we just let them read the misc msr for now. */
321         if (opcode == VMM_MSR_EMU_READ) {
322                 vm_tf->tf_rax = eax;
323                 vm_tf->tf_rdx = edx;
324                 return TRUE;
325         } else {
326                 /* if they are writing what is already written, that's ok. */
327                 if (((uint32_t) vm_tf->tf_rax == eax)
328                     && ((uint32_t) vm_tf->tf_rdx == edx))
329                         return TRUE;
330         }
331         printk("%s: Wanted to write 0x%x%x, but could not; value was 0x%x%x\n",
332                msr->name, (uint32_t) vm_tf->tf_rdx, (uint32_t) vm_tf->tf_rax,
333                edx, eax);
334         return FALSE;
335 }
336
337 bool emsr_readonly(struct emmsr *msr, struct vm_trapframe *vm_tf,
338                    uint32_t opcode)
339 {
340         uint64_t val;
341
342         if (read_msr_safe(msr->reg, &val))
343                 return FALSE;
344         if (opcode == VMM_MSR_EMU_READ) {
345                 vm_tf->tf_rax = low32(val);
346                 vm_tf->tf_rdx = high32(val);
347                 return TRUE;
348         }
349
350         printk("%s: Tried to write a readonly register\n", msr->name);
351         return FALSE;
352 }
353
354 bool emsr_readzero(struct emmsr *msr, struct vm_trapframe *vm_tf,
355                    uint32_t opcode)
356 {
357         if (opcode == VMM_MSR_EMU_READ) {
358                 vm_tf->tf_rax = 0;
359                 vm_tf->tf_rdx = 0;
360                 return TRUE;
361         }
362
363         printk("%s: Tried to write a readonly register\n", msr->name);
364         return FALSE;
365 }
366
367 /* pretend to write it, but don't write it. */
368 bool emsr_fakewrite(struct emmsr *msr, struct vm_trapframe *vm_tf,
369                     uint32_t opcode)
370 {
371         uint32_t eax, edx;
372         uint64_t val;
373
374         if (!msr->written) {
375                 if (read_msr_safe(msr->reg, &val))
376                         return FALSE;
377                 eax = low32(val);
378                 edx = high32(val);
379         } else {
380                 eax = msr->eax;
381                 edx = msr->edx;
382         }
383         /* we just let them read the misc msr for now. */
384         if (opcode == VMM_MSR_EMU_READ) {
385                 vm_tf->tf_rax = eax;
386                 vm_tf->tf_rdx = edx;
387                 return TRUE;
388         } else {
389                 msr->edx = vm_tf->tf_rdx;
390                 msr->eax = vm_tf->tf_rax;
391                 msr->written = TRUE;
392         }
393         return TRUE;
394 }
395
396 bool emsr_ok(struct emmsr *msr, struct vm_trapframe *vm_tf,
397              uint32_t opcode)
398 {
399         uint64_t val;
400
401         if (opcode == VMM_MSR_EMU_READ) {
402                 if (read_msr_safe(msr->reg, &val))
403                         return FALSE;
404                 vm_tf->tf_rax = low32(val);
405                 vm_tf->tf_rdx = high32(val);
406         } else {
407                 val = (vm_tf->tf_rdx << 32) | (vm_tf->tf_rax & 0xffffffff);
408                 if (write_msr_safe(msr->reg, val))
409                         return FALSE;
410         }
411         return TRUE;
412 }
413
414 /* pretend to write it, but don't write it. */
415 bool emsr_fake_apicbase(struct emmsr *msr, struct vm_trapframe *vm_tf,
416                         uint32_t opcode)
417 {
418         uint32_t eax, edx;
419
420         if (!msr->written) {
421                 /* TODO: tightly coupled to the addr in vmrunkernel.  We want this func
422                  * to return the val that vmrunkernel put into the VMCS. */
423                 eax = 0xfee00d00;
424                 if (vm_tf->tf_guest_pcoreid != 0) {
425                         // Remove BSP bit if not core 0
426                         eax = 0xfee00c00;
427                 }
428                 edx = 0;
429         } else {
430                 edx = msr->edx;
431                 eax = msr->eax;
432         }
433         /* we just let them read the misc msr for now. */
434         if (opcode == VMM_MSR_EMU_READ) {
435                 vm_tf->tf_rax = eax;
436                 vm_tf->tf_rdx = edx;
437                 return TRUE;
438         } else {
439                 /* if they are writing what is already written, that's ok. */
440                 if (((uint32_t) vm_tf->tf_rax == eax)
441                     && ((uint32_t) vm_tf->tf_rdx == edx))
442                         return 0;
443                 msr->edx = vm_tf->tf_rdx;
444                 msr->eax = vm_tf->tf_rax;
445                 msr->written = TRUE;
446         }
447         return TRUE;
448 }
449
450 bool vmm_emulate_msr(struct vm_trapframe *vm_tf, int op)
451 {
452         for (int i = 0; i < ARRAY_SIZE(emmsrs); i++) {
453                 if (emmsrs[i].reg != vm_tf->tf_rcx)
454                         continue;
455                 return emmsrs[i].f(&emmsrs[i], vm_tf, op);
456         }
457         return FALSE;
458 }