VMM: EPT checks, init, and basic usage
[akaros.git] / kern / arch / x86 / vmm / intel / vmx.h
1 #ifndef VMX_H
2 #define VMX_H
3
4 /*
5  * vmx.h: VMX Architecture related definitions
6  * Copyright (c) 2004, Intel Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19  * Place - Suite 330, Boston, MA 02111-1307 USA.
20  *
21  * A few random additions are:
22  * Copyright (C) 2006 Qumranet
23  *    Avi Kivity <avi@qumranet.com>
24  *    Yaniv Kamay <yaniv@qumranet.com>
25  *
26  */
27
28 #define CPU_BASED_VIRTUAL_INTR_PENDING  0x00000004
29 #define CPU_BASED_USE_TSC_OFFSETING     0x00000008
30 #define CPU_BASED_HLT_EXITING           0x00000080
31 #define CPU_BASED_INVDPG_EXITING        0x00000200
32 #define CPU_BASED_MWAIT_EXITING         0x00000400
33 #define CPU_BASED_RDPMC_EXITING         0x00000800
34 #define CPU_BASED_RDTSC_EXITING         0x00001000
35 #define CPU_BASED_CR8_LOAD_EXITING      0x00080000
36 #define CPU_BASED_CR8_STORE_EXITING     0x00100000
37 #define CPU_BASED_TPR_SHADOW            0x00200000
38 #define CPU_BASED_MOV_DR_EXITING        0x00800000
39 #define CPU_BASED_UNCOND_IO_EXITING     0x01000000
40 #define CPU_BASED_ACTIVATE_IO_BITMAP    0x02000000
41 #define CPU_BASED_MSR_BITMAPS           0x10000000
42 #define CPU_BASED_MONITOR_EXITING       0x20000000
43 #define CPU_BASED_PAUSE_EXITING         0x40000000
44
45 /*
46  * Definitions of Primary Processor-Based VM-Execution Controls.
47  */
48 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
49 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
50 #define CPU_BASED_HLT_EXITING                   0x00000080
51 #define CPU_BASED_INVLPG_EXITING                0x00000200
52 #define CPU_BASED_MWAIT_EXITING                 0x00000400
53 #define CPU_BASED_RDPMC_EXITING                 0x00000800
54 #define CPU_BASED_RDTSC_EXITING                 0x00001000
55 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
56 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
57 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
58 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
59 #define CPU_BASED_TPR_SHADOW                    0x00200000
60 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
61 #define CPU_BASED_MOV_DR_EXITING                0x00800000
62 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
63 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
64 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
65 #define CPU_BASED_MONITOR_EXITING               0x20000000
66 #define CPU_BASED_PAUSE_EXITING                 0x40000000
67 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
68 /*
69  * Definitions of Secondary Processor-Based VM-Execution Controls.
70  */
71 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
72 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
73 #define SECONDARY_EXEC_RDTSCP                   0x00000008
74 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
75 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
76 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
77 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
78 #define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
79
80
81 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
82 #define PIN_BASED_NMI_EXITING                   0x00000008
83 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
84
85 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000002
86 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
87 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
88 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
89 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
90 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
91 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
92 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
93 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
94
95 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000002
96 #define VM_ENTRY_IA32E_MODE                     0x00000200
97 #define VM_ENTRY_SMM                            0x00000400
98 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
99 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
100 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
101 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
102
103 /* VMCS Encodings */
104 enum vmcs_field {
105         VIRTUAL_PROCESSOR_ID            = 0x00000000,
106         GUEST_ES_SELECTOR               = 0x00000800,
107         GUEST_CS_SELECTOR               = 0x00000802,
108         GUEST_SS_SELECTOR               = 0x00000804,
109         GUEST_DS_SELECTOR               = 0x00000806,
110         GUEST_FS_SELECTOR               = 0x00000808,
111         GUEST_GS_SELECTOR               = 0x0000080a,
112         GUEST_LDTR_SELECTOR             = 0x0000080c,
113         GUEST_TR_SELECTOR               = 0x0000080e,
114         HOST_ES_SELECTOR                = 0x00000c00,
115         HOST_CS_SELECTOR                = 0x00000c02,
116         HOST_SS_SELECTOR                = 0x00000c04,
117         HOST_DS_SELECTOR                = 0x00000c06,
118         HOST_FS_SELECTOR                = 0x00000c08,
119         HOST_GS_SELECTOR                = 0x00000c0a,
120         HOST_TR_SELECTOR                = 0x00000c0c,
121         IO_BITMAP_A                     = 0x00002000,
122         IO_BITMAP_A_HIGH                = 0x00002001,
123         IO_BITMAP_B                     = 0x00002002,
124         IO_BITMAP_B_HIGH                = 0x00002003,
125         MSR_BITMAP                      = 0x00002004,
126         MSR_BITMAP_HIGH                 = 0x00002005,
127         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
128         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
129         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
130         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
131         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
132         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
133         TSC_OFFSET                      = 0x00002010,
134         TSC_OFFSET_HIGH                 = 0x00002011,
135         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
136         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
137         APIC_ACCESS_ADDR                = 0x00002014,
138         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
139         EPT_POINTER                     = 0x0000201a,
140         EPT_POINTER_HIGH                = 0x0000201b,
141         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
142         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
143         VMCS_LINK_POINTER               = 0x00002800,
144         VMCS_LINK_POINTER_HIGH          = 0x00002801,
145         GUEST_IA32_DEBUGCTL             = 0x00002802,
146         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
147         GUEST_IA32_PAT                  = 0x00002804,
148         GUEST_IA32_PAT_HIGH             = 0x00002805,
149         GUEST_IA32_EFER                 = 0x00002806,
150         GUEST_IA32_EFER_HIGH            = 0x00002807,
151         GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
152         GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
153         GUEST_PDPTR0                    = 0x0000280a,
154         GUEST_PDPTR0_HIGH               = 0x0000280b,
155         GUEST_PDPTR1                    = 0x0000280c,
156         GUEST_PDPTR1_HIGH               = 0x0000280d,
157         GUEST_PDPTR2                    = 0x0000280e,
158         GUEST_PDPTR2_HIGH               = 0x0000280f,
159         GUEST_PDPTR3                    = 0x00002810,
160         GUEST_PDPTR3_HIGH               = 0x00002811,
161         HOST_IA32_PAT                   = 0x00002c00,
162         HOST_IA32_PAT_HIGH              = 0x00002c01,
163         HOST_IA32_EFER                  = 0x00002c02,
164         HOST_IA32_EFER_HIGH             = 0x00002c03,
165         HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
166         HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
167         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
168         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
169         EXCEPTION_BITMAP                = 0x00004004,
170         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
171         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
172         CR3_TARGET_COUNT                = 0x0000400a,
173         VM_EXIT_CONTROLS                = 0x0000400c,
174         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
175         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
176         VM_ENTRY_CONTROLS               = 0x00004012,
177         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
178         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
179         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
180         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
181         TPR_THRESHOLD                   = 0x0000401c,
182         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
183         PLE_GAP                         = 0x00004020,
184         PLE_WINDOW                      = 0x00004022,
185         VM_INSTRUCTION_ERROR            = 0x00004400,
186         VM_EXIT_REASON                  = 0x00004402,
187         VM_EXIT_INTR_INFO               = 0x00004404,
188         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
189         IDT_VECTORING_INFO_FIELD        = 0x00004408,
190         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
191         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
192         VMX_INSTRUCTION_INFO            = 0x0000440e,
193         GUEST_ES_LIMIT                  = 0x00004800,
194         GUEST_CS_LIMIT                  = 0x00004802,
195         GUEST_SS_LIMIT                  = 0x00004804,
196         GUEST_DS_LIMIT                  = 0x00004806,
197         GUEST_FS_LIMIT                  = 0x00004808,
198         GUEST_GS_LIMIT                  = 0x0000480a,
199         GUEST_LDTR_LIMIT                = 0x0000480c,
200         GUEST_TR_LIMIT                  = 0x0000480e,
201         GUEST_GDTR_LIMIT                = 0x00004810,
202         GUEST_IDTR_LIMIT                = 0x00004812,
203         GUEST_ES_AR_BYTES               = 0x00004814,
204         GUEST_CS_AR_BYTES               = 0x00004816,
205         GUEST_SS_AR_BYTES               = 0x00004818,
206         GUEST_DS_AR_BYTES               = 0x0000481a,
207         GUEST_FS_AR_BYTES               = 0x0000481c,
208         GUEST_GS_AR_BYTES               = 0x0000481e,
209         GUEST_LDTR_AR_BYTES             = 0x00004820,
210         GUEST_TR_AR_BYTES               = 0x00004822,
211         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
212         GUEST_ACTIVITY_STATE            = 0X00004826,
213         GUEST_SYSENTER_CS               = 0x0000482A,
214         HOST_IA32_SYSENTER_CS           = 0x00004c00,
215         CR0_GUEST_HOST_MASK             = 0x00006000,
216         CR4_GUEST_HOST_MASK             = 0x00006002,
217         CR0_READ_SHADOW                 = 0x00006004,
218         CR4_READ_SHADOW                 = 0x00006006,
219         CR3_TARGET_VALUE0               = 0x00006008,
220         CR3_TARGET_VALUE1               = 0x0000600a,
221         CR3_TARGET_VALUE2               = 0x0000600c,
222         CR3_TARGET_VALUE3               = 0x0000600e,
223         EXIT_QUALIFICATION              = 0x00006400,
224         GUEST_LINEAR_ADDRESS            = 0x0000640a,
225         GUEST_CR0                       = 0x00006800,
226         GUEST_CR3                       = 0x00006802,
227         GUEST_CR4                       = 0x00006804,
228         GUEST_ES_BASE                   = 0x00006806,
229         GUEST_CS_BASE                   = 0x00006808,
230         GUEST_SS_BASE                   = 0x0000680a,
231         GUEST_DS_BASE                   = 0x0000680c,
232         GUEST_FS_BASE                   = 0x0000680e,
233         GUEST_GS_BASE                   = 0x00006810,
234         GUEST_LDTR_BASE                 = 0x00006812,
235         GUEST_TR_BASE                   = 0x00006814,
236         GUEST_GDTR_BASE                 = 0x00006816,
237         GUEST_IDTR_BASE                 = 0x00006818,
238         GUEST_DR7                       = 0x0000681a,
239         GUEST_RSP                       = 0x0000681c,
240         GUEST_RIP                       = 0x0000681e,
241         GUEST_RFLAGS                    = 0x00006820,
242         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
243         GUEST_SYSENTER_ESP              = 0x00006824,
244         GUEST_SYSENTER_EIP              = 0x00006826,
245         HOST_CR0                        = 0x00006c00,
246         HOST_CR3                        = 0x00006c02,
247         HOST_CR4                        = 0x00006c04,
248         HOST_FS_BASE                    = 0x00006c06,
249         HOST_GS_BASE                    = 0x00006c08,
250         HOST_TR_BASE                    = 0x00006c0a,
251         HOST_GDTR_BASE                  = 0x00006c0c,
252         HOST_IDTR_BASE                  = 0x00006c0e,
253         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
254         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
255         HOST_RSP                        = 0x00006c14,
256         HOST_RIP                        = 0x00006c16,
257 };
258
259 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
260
261 #define EXIT_REASON_EXCEPTION_NMI       0
262 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
263 #define EXIT_REASON_TRIPLE_FAULT        2
264
265 #define EXIT_REASON_PENDING_INTERRUPT   7
266 #define EXIT_REASON_NMI_WINDOW          8
267 #define EXIT_REASON_TASK_SWITCH         9
268 #define EXIT_REASON_CPUID               10
269 #define EXIT_REASON_HLT                 12
270 #define EXIT_REASON_INVD                13
271 #define EXIT_REASON_INVLPG              14
272 #define EXIT_REASON_RDPMC               15
273 #define EXIT_REASON_RDTSC               16
274 #define EXIT_REASON_VMCALL              18
275 #define EXIT_REASON_VMCLEAR             19
276 #define EXIT_REASON_VMLAUNCH            20
277 #define EXIT_REASON_VMPTRLD             21
278 #define EXIT_REASON_VMPTRST             22
279 #define EXIT_REASON_VMREAD              23
280 #define EXIT_REASON_VMRESUME            24
281 #define EXIT_REASON_VMWRITE             25
282 #define EXIT_REASON_VMOFF               26
283 #define EXIT_REASON_VMON                27
284 #define EXIT_REASON_CR_ACCESS           28
285 #define EXIT_REASON_DR_ACCESS           29
286 #define EXIT_REASON_IO_INSTRUCTION      30
287 #define EXIT_REASON_MSR_READ            31
288 #define EXIT_REASON_MSR_WRITE           32
289 #define EXIT_REASON_INVALID_STATE       33
290 #define EXIT_REASON_MWAIT_INSTRUCTION   36
291 #define EXIT_REASON_MONITOR_INSTRUCTION 39
292 #define EXIT_REASON_PAUSE_INSTRUCTION   40
293 #define EXIT_REASON_MCE_DURING_VMENTRY  41
294 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
295 #define EXIT_REASON_APIC_ACCESS         44
296 #define EXIT_REASON_EPT_VIOLATION       48
297 #define EXIT_REASON_EPT_MISCONFIG       49
298 #define EXIT_REASON_WBINVD              54
299 #define EXIT_REASON_XSETBV              55
300 #define EXIT_REASON_INVPCID             58
301
302 #define VMX_EXIT_REASONS \
303         { EXIT_REASON_EXCEPTION_NMI,         "EXCEPTION_NMI" }, \
304         { EXIT_REASON_EXTERNAL_INTERRUPT,    "EXTERNAL_INTERRUPT" }, \
305         { EXIT_REASON_TRIPLE_FAULT,          "TRIPLE_FAULT" }, \
306         { EXIT_REASON_PENDING_INTERRUPT,     "PENDING_INTERRUPT" }, \
307         { EXIT_REASON_NMI_WINDOW,            "NMI_WINDOW" }, \
308         { EXIT_REASON_TASK_SWITCH,           "TASK_SWITCH" }, \
309         { EXIT_REASON_CPUID,                 "CPUID" }, \
310         { EXIT_REASON_HLT,                   "HLT" }, \
311         { EXIT_REASON_INVLPG,                "INVLPG" }, \
312         { EXIT_REASON_RDPMC,                 "RDPMC" }, \
313         { EXIT_REASON_RDTSC,                 "RDTSC" }, \
314         { EXIT_REASON_VMCALL,                "VMCALL" }, \
315         { EXIT_REASON_VMCLEAR,               "VMCLEAR" }, \
316         { EXIT_REASON_VMLAUNCH,              "VMLAUNCH" }, \
317         { EXIT_REASON_VMPTRLD,               "VMPTRLD" }, \
318         { EXIT_REASON_VMPTRST,               "VMPTRST" }, \
319         { EXIT_REASON_VMREAD,                "VMREAD" }, \
320         { EXIT_REASON_VMRESUME,              "VMRESUME" }, \
321         { EXIT_REASON_VMWRITE,               "VMWRITE" }, \
322         { EXIT_REASON_VMOFF,                 "VMOFF" }, \
323         { EXIT_REASON_VMON,                  "VMON" }, \
324         { EXIT_REASON_CR_ACCESS,             "CR_ACCESS" }, \
325         { EXIT_REASON_DR_ACCESS,             "DR_ACCESS" }, \
326         { EXIT_REASON_IO_INSTRUCTION,        "IO_INSTRUCTION" }, \
327         { EXIT_REASON_MSR_READ,              "MSR_READ" }, \
328         { EXIT_REASON_MSR_WRITE,             "MSR_WRITE" }, \
329         { EXIT_REASON_MWAIT_INSTRUCTION,     "MWAIT_INSTRUCTION" }, \
330         { EXIT_REASON_MONITOR_INSTRUCTION,   "MONITOR_INSTRUCTION" }, \
331         { EXIT_REASON_PAUSE_INSTRUCTION,     "PAUSE_INSTRUCTION" }, \
332         { EXIT_REASON_MCE_DURING_VMENTRY,    "MCE_DURING_VMENTRY" }, \
333         { EXIT_REASON_TPR_BELOW_THRESHOLD,   "TPR_BELOW_THRESHOLD" }, \
334         { EXIT_REASON_APIC_ACCESS,           "APIC_ACCESS" }, \
335         { EXIT_REASON_EPT_VIOLATION,         "EPT_VIOLATION" }, \
336         { EXIT_REASON_EPT_MISCONFIG,         "EPT_MISCONFIG" }, \
337         { EXIT_REASON_WBINVD,                "WBINVD" }
338
339 /*
340  * Interruption-information format
341  */
342 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
343 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
344 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
345 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
346 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
347 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
348
349 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
350 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
351 #define VECTORING_INFO_DELIEVER_CODE_MASK       INTR_INFO_DELIEVER_CODE_MASK
352 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
353
354 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
355 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
356 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
357 #define INTR_TYPE_EXCEPTION             (3 << 8)       /* processor exception */  
358 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
359 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
360
361 /* GUEST_INTERRUPTIBILITY_INFO flags. */
362 #define GUEST_INTR_STATE_STI            0x00000001
363 #define GUEST_INTR_STATE_MOV_SS         0x00000002
364 #define GUEST_INTR_STATE_SMI            0x00000004
365 #define GUEST_INTR_STATE_NMI            0x00000008
366
367 /* GUEST_ACTIVITY_STATE flags */
368 #define GUEST_ACTIVITY_ACTIVE           0
369 #define GUEST_ACTIVITY_HLT              1
370 #define GUEST_ACTIVITY_SHUTDOWN         2
371 #define GUEST_ACTIVITY_WAIT_SIPI        3
372
373 /*
374  * Exit Qualifications for MOV for Control Register Access
375  */
376 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control register */
377 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
378 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose register */
379 #define LMSW_SOURCE_DATA_SHIFT 16
380 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT)    /* 16:31 lmsw source */
381 #define REG_EAX                         (0 << 8)
382 #define REG_ECX                         (1 << 8)
383 #define REG_EDX                         (2 << 8)
384 #define REG_EBX                         (3 << 8)
385 #define REG_ESP                         (4 << 8)
386 #define REG_EBP                         (5 << 8)
387 #define REG_ESI                         (6 << 8)
388 #define REG_EDI                         (7 << 8)
389 #define REG_R8                         (8 << 8)
390 #define REG_R9                         (9 << 8)
391 #define REG_R10                        (10 << 8)
392 #define REG_R11                        (11 << 8)
393 #define REG_R12                        (12 << 8)
394 #define REG_R13                        (13 << 8)
395 #define REG_R14                        (14 << 8)
396 #define REG_R15                        (15 << 8)
397
398 /*
399  * Exit Qualifications for MOV for Debug Register Access
400  */
401 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug register */
402 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
403 #define TYPE_MOV_TO_DR                  (0 << 4)
404 #define TYPE_MOV_FROM_DR                (1 << 4)
405 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
406
407
408 /*
409  * Exit Qualifications for APIC-Access
410  */
411 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
412 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
413 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
414 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
415 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
416 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
417 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
418 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
419
420 /* segment AR */
421 #define SEGMENT_AR_L_MASK (1 << 13)
422
423 /* entry controls */
424 #define VM_ENTRY_CONTROLS_IA32E_MASK (1 << 9)
425
426 #define AR_TYPE_ACCESSES_MASK 1
427 #define AR_TYPE_READABLE_MASK (1 << 1)
428 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
429 #define AR_TYPE_CODE_MASK (1 << 3)
430 #define AR_TYPE_MASK 0x0f
431 #define AR_TYPE_BUSY_64_TSS 11
432 #define AR_TYPE_BUSY_32_TSS 11
433 #define AR_TYPE_BUSY_16_TSS 3
434 #define AR_TYPE_LDT 2
435
436 #define AR_UNUSABLE_MASK (1 << 16)
437 #define AR_S_MASK (1 << 4)
438 #define AR_P_MASK (1 << 7)
439 #define AR_L_MASK (1 << 13)
440 #define AR_DB_MASK (1 << 14)
441 #define AR_G_MASK (1 << 15)
442 #define AR_DPL_SHIFT 5
443 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
444
445 #define AR_RESERVD_MASK 0xfffe0f00
446
447 #define TSS_PRIVATE_MEMSLOT                     (KVM_MEMORY_SLOTS + 0)
448 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_MEMORY_SLOTS + 1)
449 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_MEMORY_SLOTS + 2)
450
451 #define VMX_NR_VPIDS                            (1 << 16)
452 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
453 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
454
455 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
456 #define VMX_EPT_EXTENT_CONTEXT                  1
457 #define VMX_EPT_EXTENT_GLOBAL                   2
458
459 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
460 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
461 #define VMX_EPTP_UC_BIT                         (1ull << 8)
462 #define VMX_EPTP_WB_BIT                         (1ull << 14)
463 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
464 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
465 #define VMX_EPT_INVEPT_BIT                              (1ull << 20)
466 #define VMX_EPT_AD_BIT                              (1ull << 21)
467 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
468 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
469
470 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
471 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
472
473 #define VMX_EPT_GAW_4_LVL                               3       /* LVL - 1 */
474 #define VMX_EPT_MAX_GAW                                 0x4
475 #define VMX_EPT_MT_EPTE_SHIFT                   3
476 #define VMX_EPT_GAW_EPTP_SHIFT                  3
477 #define VMX_EPT_AD_ENABLE_BIT                   (1ull << 6)
478 #define VMX_EPT_MEM_TYPE_WB                             0x6ull
479 #define VMX_EPT_READABLE_MASK                   0x1ull
480 #define VMX_EPT_WRITABLE_MASK                   0x2ull
481 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
482 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
483 #define VMX_EPT_ACCESS_BIT                              (1ull << 8)
484 #define VMX_EPT_DIRTY_BIT                               (1ull << 9)
485
486 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
487
488
489 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
490 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
491 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
492 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
493 #define ASM_VMX_VMPTRST_RAX       ".byte 0x0f, 0xc7, 0x38"
494 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
495 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
496 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
497 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
498 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
499 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
500 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
501
502 struct vmx_msr_entry {
503         uint32_t index;
504         uint32_t reserved;
505         uint64_t value;
506 } __attribute__((aligned(16))) ;
507
508 /*
509  * Exit Qualifications for entry failure during or after loading guest state
510  */
511 #define ENTRY_FAIL_DEFAULT              0
512 #define ENTRY_FAIL_PDPTE                2
513 #define ENTRY_FAIL_NMI                  3
514 #define ENTRY_FAIL_VMCS_LINK_PTR        4
515
516 /*
517  * VM-instruction error numbers
518  */
519 enum vm_instruction_error_number {
520         VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
521         VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
522         VMXERR_VMCLEAR_VMXON_POINTER = 3,
523         VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
524         VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
525         VMXERR_VMRESUME_AFTER_VMXOFF = 6,
526         VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
527         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
528         VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
529         VMXERR_VMPTRLD_VMXON_POINTER = 10,
530         VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
531         VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
532         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
533         VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
534         VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
535         VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
536         VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
537         VMXERR_VMCALL_NONCLEAR_VMCS = 19,
538         VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
539         VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
540         VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
541         VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
542         VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
543         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
544         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
545 };
546
547 #define MSR_IA32_VMX_BASIC_MSR                  0x480
548 #define MSR_IA32_VMX_PINBASED_CTLS_MSR          0x481
549 #define MSR_IA32_VMX_PROCBASED_CTLS_MSR         0x482
550 #define MSR_IA32_VMX_EXIT_CTLS_MSR              0x483
551 #define MSR_IA32_VMX_ENTRY_CTLS_MSR             0x484
552
553 int intel_vmm_init(void);
554 int intel_vmm_pcpu_init(void);
555
556 /* Additional bits for VMMCPs, originally from the Dune version of kvm. */
557 /*
558  * vmx.h - header file for USM VMX driver.
559  */
560
561 /* This is per-guest per-core, and the implementation specific area
562  * should be assumed to have hidden fields.
563  */
564 struct vmcs {
565         uint32_t revision_id;
566         uint32_t abort_code;
567         char _impl_specific[PAGE_SIZE - sizeof(uint32_t) * 2];
568 };
569
570 typedef uint64_t gpa_t;
571 typedef uint64_t gva_t;
572 #define rdmsrl(msr, val) (val) = read_msr((msr))
573 #define rdmsr(msr, low, high) do {uint64_t m = read_msr(msr); low = m; high = m>>32;} while (0)
574
575 struct vmx_capability {
576         uint32_t ept;
577         uint32_t vpid;
578         int has_load_efer:1;
579 };
580
581 extern struct vmx_capability vmx_capability;
582
583 #define NR_AUTOLOAD_MSRS 8
584
585 /* the horror. */
586 struct desc_struct {
587         union {
588                 struct {
589                         unsigned int a;
590                         unsigned int b;
591                 };
592                 struct {
593                         uint16_t limit0;
594                         uint16_t base0;
595                         unsigned base1: 8, type: 4, s: 1, dpl: 2, p: 1;
596                         unsigned limit: 4, avl: 1, l: 1, d: 1, g: 1, base2: 8;
597                 };
598         };
599 } __attribute__((packed));
600
601 /* LDT or TSS descriptor in the GDT. 16 bytes. */
602 struct ldttss_desc64 {
603         uint16_t limit0;
604         uint16_t base0;
605         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
606         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
607         uint32_t base3;
608         uint32_t zero1;
609 } __attribute__((packed));
610
611 struct dune_struct {
612         struct vmx_vcpu *vcpu;
613 };
614
615 struct vmx_vcpu {
616
617         int cpu;
618         int vpid;
619         int launched;
620         struct hw_trapframe regs;
621         uint8_t  fail;
622         uint64_t exit_reason;
623         uint64_t host_rsp;
624
625         uint64_t cr2;
626
627         int shutdown;
628         int ret_code;
629         struct proc *proc;
630
631         struct msr_autoload {
632                 unsigned nr;
633                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
634                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
635         } msr_autoload;
636
637         struct vmcs *vmcs;
638 };
639
640 extern int vmx_init(void);
641 extern void vmx_exit(void);
642 int ept_fault_pages(void *dir, uint32_t start, uint32_t end);
643 int ept_check_page(void *dir, unsigned long addr);
644 int vmx_do_ept_fault(void *dir, unsigned long gpa, unsigned long gva, int fault_flags);
645 /* no way to get around some of this stuff. */
646 /* we will do the bare minimum required. */
647 static inline void native_store_idt(pseudodesc_t *dtr)
648 {
649         asm volatile("sidt %0":"=m" (*dtr));
650 }
651
652 static inline unsigned long get_desc_base(const struct desc_struct *desc)
653 {
654         return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
655 }
656
657 #define store_gdt(dtr)                          native_store_gdt(dtr)
658 static inline void native_store_gdt(pseudodesc_t *dtr)
659 {
660         asm volatile("sgdt %0":"=m" (*dtr));
661 }
662
663 #endif