kern/arch/x86/ros/vmx.h

   1 /*
   2  * vmx.h: VMX Architecture related definitions
   3  * Copyright (c) 2004, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16  * Place - Suite 330, Boston, MA 02111-1307 USA.
  17  *
  18  * A few random additions are:
  19  * Copyright (C) 2006 Qumranet
  20  *    Avi Kivity <avi@qumranet.com>
  21  *    Yaniv Kamay <yaniv@qumranet.com>
  22  *
  23  */
  24 #pragma once
  25
  26 #define CPU_BASED_VIRTUAL_INTR_PENDING  0x00000004
  27 #define CPU_BASED_USE_TSC_OFFSETING     0x00000008
  28 #define CPU_BASED_HLT_EXITING           0x00000080
  29 #define CPU_BASED_INVDPG_EXITING        0x00000200
  30 #define CPU_BASED_MWAIT_EXITING         0x00000400
  31 #define CPU_BASED_RDPMC_EXITING         0x00000800
  32 #define CPU_BASED_RDTSC_EXITING         0x00001000
  33 #define CPU_BASED_CR8_LOAD_EXITING      0x00080000
  34 #define CPU_BASED_CR8_STORE_EXITING     0x00100000
  35 #define CPU_BASED_TPR_SHADOW            0x00200000
  36 #define CPU_BASED_MOV_DR_EXITING        0x00800000
  37 #define CPU_BASED_UNCOND_IO_EXITING     0x01000000
  38 #define CPU_BASED_ACTIVATE_IO_BITMAP    0x02000000
  39 #define CPU_BASED_MSR_BITMAPS           0x10000000
  40 #define CPU_BASED_MONITOR_EXITING       0x20000000
  41 #define CPU_BASED_PAUSE_EXITING         0x40000000
  42
  43 /*
  44  * Definitions of Primary Processor-Based VM-Execution Controls.
  45  */
  46 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
  47 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
  48 #define CPU_BASED_HLT_EXITING                   0x00000080
  49 #define CPU_BASED_INVLPG_EXITING                0x00000200
  50 #define CPU_BASED_MWAIT_EXITING                 0x00000400
  51 #define CPU_BASED_RDPMC_EXITING                 0x00000800
  52 #define CPU_BASED_RDTSC_EXITING                 0x00001000
  53 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
  54 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
  55 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
  56 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
  57 #define CPU_BASED_TPR_SHADOW                    0x00200000
  58 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
  59 #define CPU_BASED_MOV_DR_EXITING                0x00800000
  60 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
  61 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
  62 #define CPU_BASED_MONITOR_TRAP                  0x08000000
  63 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
  64 #define CPU_BASED_MONITOR_EXITING               0x20000000
  65 #define CPU_BASED_PAUSE_EXITING                 0x40000000
  66 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
  67 /*
  68  * Definitions of Secondary Processor-Based VM-Execution Controls.
  69  */
  70 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
  71 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
  72 #define SECONDARY_EXEC_DESCRIPTOR_EXITING       0x00000004
  73 #define SECONDARY_EXEC_RDTSCP                   0x00000008
  74 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
  75 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
  76 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
  77 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
  78 #define SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
  79 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
  80 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
  81 #define SECONDARY_EXEC_RDRAND_EXITING           0x00000800
  82 #define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
  83 #define SECONDARY_EXEC_ENABLE_VMFUNC            0x00002000
  84 #define SECONDARY_EXEC_SHADOW_VMCS              0x00004000
  85 #define SECONDARY_EXEC_RDSEED_EXITING           0x00010000
  86 #define SECONDARY_EPT_VE                        0x00040000
  87 #define SECONDARY_ENABLE_XSAV_RESTORE           0x00100000
  88
  89 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
  90 #define PIN_BASED_NMI_EXITING                   0x00000008
  91 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
  92 #define PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
  93 #define PIN_BASED_POSTED_INTR                   0x00000080
  94
  95 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
  96 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
  97 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
  98 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
  99 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
 100 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
 101 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
 102 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
 103 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
 104
 105 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
 106 #define VM_ENTRY_IA32E_MODE                     0x00000200
 107 #define VM_ENTRY_SMM                            0x00000400
 108 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
 109 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
 110 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
 111 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
 112
 113 /* VMCS Encodings */
 114 enum vmcs_field {
 115         VIRTUAL_PROCESSOR_ID            = 0x00000000,
 116         POSTED_NOTIFICATION_VEC         = 0x00000002,
 117         GUEST_ES_SELECTOR               = 0x00000800,
 118         GUEST_CS_SELECTOR               = 0x00000802,
 119         GUEST_SS_SELECTOR               = 0x00000804,
 120         GUEST_DS_SELECTOR               = 0x00000806,
 121         GUEST_FS_SELECTOR               = 0x00000808,
 122         GUEST_GS_SELECTOR               = 0x0000080a,
 123         GUEST_LDTR_SELECTOR             = 0x0000080c,
 124         GUEST_TR_SELECTOR               = 0x0000080e,
 125         GUEST_INTR_STATUS               = 0x00000810,
 126         GUEST_PML_INDEX                 = 0x00000812,
 127         HOST_ES_SELECTOR                = 0x00000c00,
 128         HOST_CS_SELECTOR                = 0x00000c02,
 129         HOST_SS_SELECTOR                = 0x00000c04,
 130         HOST_DS_SELECTOR                = 0x00000c06,
 131         HOST_FS_SELECTOR                = 0x00000c08,
 132         HOST_GS_SELECTOR                = 0x00000c0a,
 133         HOST_TR_SELECTOR                = 0x00000c0c,
 134         IO_BITMAP_A                     = 0x00002000,
 135         IO_BITMAP_A_HIGH                = 0x00002001,
 136         IO_BITMAP_B                     = 0x00002002,
 137         IO_BITMAP_B_HIGH                = 0x00002003,
 138         MSR_BITMAP                      = 0x00002004,
 139         MSR_BITMAP_HIGH                 = 0x00002005,
 140         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
 141         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
 142         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
 143         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
 144         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
 145         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
 146         TSC_OFFSET                      = 0x00002010,
 147         TSC_OFFSET_HIGH                 = 0x00002011,
 148         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
 149         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
 150         APIC_ACCESS_ADDR                = 0x00002014,
 151         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
 152         POSTED_INTR_DESC_ADDR           = 0x00002016,
 153         POSTED_INTR_DESC_ADDR_HIGH      = 0x00002017,
 154         EPT_POINTER                     = 0x0000201a,
 155         EPT_POINTER_HIGH                = 0x0000201b,
 156         EOI_EXIT_BITMAP0                = 0x0000201c,
 157         EOI_EXIT_BITMAP0_HIGH           = 0x0000201d,
 158         EOI_EXIT_BITMAP1                = 0x0000201e,
 159         EOI_EXIT_BITMAP1_HIGH           = 0x0000201f,
 160         EOI_EXIT_BITMAP2                = 0x00002020,
 161         EOI_EXIT_BITMAP2_HIGH           = 0x00002021,
 162         EOI_EXIT_BITMAP3                = 0x00002022,
 163         EOI_EXIT_BITMAP3_HIGH           = 0x00002023,
 164         VMREAD_BITMAP                   = 0x00002026,
 165         VMWRITE_BITMAP                  = 0x00002028,
 166         XSS_EXIT_BITMAP                 = 0x0000202C,
 167         XSS_EXIT_BITMAP_HIGH            = 0x0000202D,
 168         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
 169         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
 170         VMCS_LINK_POINTER               = 0x00002800,
 171         VMCS_LINK_POINTER_HIGH          = 0x00002801,
 172         GUEST_IA32_DEBUGCTL             = 0x00002802,
 173         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
 174         GUEST_IA32_PAT                  = 0x00002804,
 175         GUEST_IA32_PAT_HIGH             = 0x00002805,
 176         GUEST_IA32_EFER                 = 0x00002806,
 177         GUEST_IA32_EFER_HIGH            = 0x00002807,
 178         GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
 179         GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
 180         GUEST_PDPTR0                    = 0x0000280a,
 181         GUEST_PDPTR0_HIGH               = 0x0000280b,
 182         GUEST_PDPTR1                    = 0x0000280c,
 183         GUEST_PDPTR1_HIGH               = 0x0000280d,
 184         GUEST_PDPTR2                    = 0x0000280e,
 185         GUEST_PDPTR2_HIGH               = 0x0000280f,
 186         GUEST_PDPTR3                    = 0x00002810,
 187         GUEST_PDPTR3_HIGH               = 0x00002811,
 188         HOST_IA32_PAT                   = 0x00002c00,
 189         HOST_IA32_PAT_HIGH              = 0x00002c01,
 190         HOST_IA32_EFER                  = 0x00002c02,
 191         HOST_IA32_EFER_HIGH             = 0x00002c03,
 192         HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
 193         HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
 194         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
 195         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
 196         EXCEPTION_BITMAP                = 0x00004004,
 197         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
 198         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
 199         CR3_TARGET_COUNT                = 0x0000400a,
 200         VM_EXIT_CONTROLS                = 0x0000400c,
 201         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
 202         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
 203         VM_ENTRY_CONTROLS               = 0x00004012,
 204         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
 205         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
 206         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
 207         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
 208         TPR_THRESHOLD                   = 0x0000401c,
 209         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
 210         PLE_GAP                         = 0x00004020,
 211         PLE_WINDOW                      = 0x00004022,
 212         VM_INSTRUCTION_ERROR            = 0x00004400,
 213         VM_EXIT_REASON                  = 0x00004402,
 214         VM_EXIT_INTR_INFO               = 0x00004404,
 215         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
 216         IDT_VECTORING_INFO_FIELD        = 0x00004408,
 217         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
 218         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
 219         VMX_INSTRUCTION_INFO            = 0x0000440e,
 220         GUEST_ES_LIMIT                  = 0x00004800,
 221         GUEST_CS_LIMIT                  = 0x00004802,
 222         GUEST_SS_LIMIT                  = 0x00004804,
 223         GUEST_DS_LIMIT                  = 0x00004806,
 224         GUEST_FS_LIMIT                  = 0x00004808,
 225         GUEST_GS_LIMIT                  = 0x0000480a,
 226         GUEST_LDTR_LIMIT                = 0x0000480c,
 227         GUEST_TR_LIMIT                  = 0x0000480e,
 228         GUEST_GDTR_LIMIT                = 0x00004810,
 229         GUEST_IDTR_LIMIT                = 0x00004812,
 230         GUEST_ES_AR_BYTES               = 0x00004814,
 231         GUEST_CS_AR_BYTES               = 0x00004816,
 232         GUEST_SS_AR_BYTES               = 0x00004818,
 233         GUEST_DS_AR_BYTES               = 0x0000481a,
 234         GUEST_FS_AR_BYTES               = 0x0000481c,
 235         GUEST_GS_AR_BYTES               = 0x0000481e,
 236         GUEST_LDTR_AR_BYTES             = 0x00004820,
 237         GUEST_TR_AR_BYTES               = 0x00004822,
 238         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
 239         GUEST_ACTIVITY_STATE            = 0X00004826,
 240         GUEST_SYSENTER_CS               = 0x0000482A,
 241         HOST_IA32_SYSENTER_CS           = 0x00004c00,
 242         CR0_GUEST_HOST_MASK             = 0x00006000,
 243         CR4_GUEST_HOST_MASK             = 0x00006002,
 244         CR0_READ_SHADOW                 = 0x00006004,
 245         CR4_READ_SHADOW                 = 0x00006006,
 246         CR3_TARGET_VALUE0               = 0x00006008,
 247         CR3_TARGET_VALUE1               = 0x0000600a,
 248         CR3_TARGET_VALUE2               = 0x0000600c,
 249         CR3_TARGET_VALUE3               = 0x0000600e,
 250         EXIT_QUALIFICATION              = 0x00006400,
 251         GUEST_LINEAR_ADDRESS            = 0x0000640a,
 252         GUEST_CR0                       = 0x00006800,
 253         GUEST_CR3                       = 0x00006802,
 254         GUEST_CR4                       = 0x00006804,
 255         GUEST_ES_BASE                   = 0x00006806,
 256         GUEST_CS_BASE                   = 0x00006808,
 257         GUEST_SS_BASE                   = 0x0000680a,
 258         GUEST_DS_BASE                   = 0x0000680c,
 259         GUEST_FS_BASE                   = 0x0000680e,
 260         GUEST_GS_BASE                   = 0x00006810,
 261         GUEST_LDTR_BASE                 = 0x00006812,
 262         GUEST_TR_BASE                   = 0x00006814,
 263         GUEST_GDTR_BASE                 = 0x00006816,
 264         GUEST_IDTR_BASE                 = 0x00006818,
 265         GUEST_DR7                       = 0x0000681a,
 266         GUEST_RSP                       = 0x0000681c,
 267         GUEST_RIP                       = 0x0000681e,
 268         GUEST_RFLAGS                    = 0x00006820,
 269         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
 270         GUEST_SYSENTER_ESP              = 0x00006824,
 271         GUEST_SYSENTER_EIP              = 0x00006826,
 272         HOST_CR0                        = 0x00006c00,
 273         HOST_CR3                        = 0x00006c02,
 274         HOST_CR4                        = 0x00006c04,
 275         HOST_FS_BASE                    = 0x00006c06,
 276         HOST_GS_BASE                    = 0x00006c08,
 277         HOST_TR_BASE                    = 0x00006c0a,
 278         HOST_GDTR_BASE                  = 0x00006c0c,
 279         HOST_IDTR_BASE                  = 0x00006c0e,
 280         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
 281         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
 282         HOST_RSP                        = 0x00006c14,
 283         HOST_RIP                        = 0x00006c16,
 284 };
 285
 286 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
 287
 288 #define EXIT_REASON_EXCEPTION_NMI       0
 289 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
 290 #define EXIT_REASON_TRIPLE_FAULT        2
 291 #define EXIT_REASON_INIT_SIGNAL         3
 292 #define EXIT_REASON_START_UP_IPI        4
 293 #define EXIT_REASON_IO_SM_INTERRUPT     5
 294 #define EXIT_REASON_OTHER_SMI           6
 295 #define EXIT_REASON_PENDING_INTERRUPT   7
 296 #define EXIT_REASON_INTERRUPT_WINDOW    7
 297 #define EXIT_REASON_NMI_WINDOW          8
 298 #define EXIT_REASON_TASK_SWITCH         9
 299 #define EXIT_REASON_CPUID               10
 300 #define EXIT_REASON_GETSEC              11
 301 #define EXIT_REASON_HLT                 12
 302 #define EXIT_REASON_INVD                13
 303 #define EXIT_REASON_INVLPG              14
 304 #define EXIT_REASON_RDPMC               15
 305 #define EXIT_REASON_RDTSC               16
 306 #define EXIT_REASON_RSM                 17
 307 #define EXIT_REASON_VMCALL              18
 308 #define EXIT_REASON_VMCLEAR             19
 309 #define EXIT_REASON_VMLAUNCH            20
 310 #define EXIT_REASON_VMPTRLD             21
 311 #define EXIT_REASON_VMPTRST             22
 312 #define EXIT_REASON_VMREAD              23
 313 #define EXIT_REASON_VMRESUME            24
 314 #define EXIT_REASON_VMWRITE             25
 315 #define EXIT_REASON_VMOFF               26
 316 #define EXIT_REASON_VMON                27
 317 #define EXIT_REASON_CR_ACCESS           28
 318 #define EXIT_REASON_DR_ACCESS           29
 319 #define EXIT_REASON_IO_INSTRUCTION      30
 320 #define EXIT_REASON_MSR_READ            31
 321 #define EXIT_REASON_MSR_WRITE           32
 322 #define EXIT_REASON_INVALID_STATE       33
 323 #define EXIT_REASON_ENTRY_MSR_LOADING   34
 324 #define EXIT_REASON_MWAIT_INSTRUCTION   36
 325 #define EXIT_REASON_MONITOR_TRAP_FLAG   37
 326 #define EXIT_REASON_MONITOR_INSTRUCTION 39
 327 #define EXIT_REASON_PAUSE_INSTRUCTION   40
 328 #define EXIT_REASON_MCE_DURING_VMENTRY  41
 329 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
 330 #define EXIT_REASON_APIC_ACCESS         44
 331 #define EXIT_REASON_VIRTUALIZED_EOI     45
 332 #define EXIT_REASON_GDTR_IDTR_ACCESS    46
 333 #define EXIT_REASON_LDTR_TR_ACCESS      47
 334 #define EXIT_REASON_EPT_VIOLATION       48
 335 #define EXIT_REASON_EPT_MISCONFIG       49
 336 #define EXIT_REASON_INVEPT              50
 337 #define EXIT_REASON_RDTSCP              51
 338 #define EXIT_REASON_VMX_TIMER_EXPIRED   52
 339 #define EXIT_REASON_INVVPID             53
 340 #define EXIT_REASON_WBINVD              54
 341 #define EXIT_REASON_XSETBV              55
 342 #define EXIT_REASON_APIC_WRITE          56
 343 #define EXIT_REASON_RDRAND              57
 344 #define EXIT_REASON_INVPCID             58
 345 #define EXIT_REASON_VMFUNC              59
 346 #define EXIT_REASON_RDSEED              61
 347 #define EXIT_REASON_XSAVES              63
 348 #define EXIT_REASON_XRSTORS             64
 349 /* Non-standard exit reasons */
 350 #define EXIT_REASON_GUEST_IN_USE        257
 351 #define EXIT_REASON_VMENTER_FAILED      258
 352
 353 #define VMX_EXIT_REASONS \
 354         [EXIT_REASON_EXCEPTION_NMI]         "EXCEPTION_NMI", \
 355         [EXIT_REASON_EXTERNAL_INTERRUPT]    "EXTERNAL_INTERRUPT", \
 356         [EXIT_REASON_TRIPLE_FAULT]          "TRIPLE_FAULT", \
 357         [EXIT_REASON_PENDING_INTERRUPT]     "PENDING_INTERRUPT", \
 358         [EXIT_REASON_NMI_WINDOW]            "NMI_WINDOW", \
 359         [EXIT_REASON_TASK_SWITCH]           "TASK_SWITCH", \
 360         [EXIT_REASON_CPUID]                 "CPUID", \
 361         [EXIT_REASON_HLT]                   "HLT", \
 362         [EXIT_REASON_INVLPG]                "INVLPG", \
 363         [EXIT_REASON_RDPMC]                 "RDPMC", \
 364         [EXIT_REASON_RDTSC]                 "RDTSC", \
 365         [EXIT_REASON_VMCALL]                "VMCALL", \
 366         [EXIT_REASON_VMCLEAR]               "VMCLEAR", \
 367         [EXIT_REASON_VMLAUNCH]              "VMLAUNCH", \
 368         [EXIT_REASON_VMPTRLD]               "VMPTRLD", \
 369         [EXIT_REASON_VMPTRST]               "VMPTRST", \
 370         [EXIT_REASON_VMREAD]                "VMREAD", \
 371         [EXIT_REASON_VMRESUME]              "VMRESUME", \
 372         [EXIT_REASON_VMWRITE]               "VMWRITE", \
 373         [EXIT_REASON_VMOFF]                 "VMOFF", \
 374         [EXIT_REASON_VMON]                  "VMON", \
 375         [EXIT_REASON_CR_ACCESS]             "CR_ACCESS", \
 376         [EXIT_REASON_DR_ACCESS]             "DR_ACCESS", \
 377         [EXIT_REASON_IO_INSTRUCTION]        "IO_INSTRUCTION", \
 378         [EXIT_REASON_MSR_READ]              "MSR_READ", \
 379         [EXIT_REASON_MSR_WRITE]             "MSR_WRITE", \
 380         [EXIT_REASON_MWAIT_INSTRUCTION]     "MWAIT_INSTRUCTION", \
 381         [EXIT_REASON_MONITOR_INSTRUCTION]   "MONITOR_INSTRUCTION", \
 382         [EXIT_REASON_PAUSE_INSTRUCTION]     "PAUSE_INSTRUCTION", \
 383         [EXIT_REASON_MCE_DURING_VMENTRY]    "MCE_DURING_VMENTRY", \
 384         [EXIT_REASON_TPR_BELOW_THRESHOLD]   "TPR_BELOW_THRESHOLD", \
 385         [EXIT_REASON_APIC_ACCESS]           "APIC_ACCESS", \
 386         [EXIT_REASON_EPT_VIOLATION]         "EPT_VIOLATION", \
 387         [EXIT_REASON_EPT_MISCONFIG]         "EPT_MISCONFIG", \
 388         [EXIT_REASON_WBINVD]                "WBINVD", \
 389         [EXIT_REASON_GUEST_IN_USE]          "GUEST_IN_USE", \
 390         [EXIT_REASON_VMENTER_FAILED]        "VMENTER_FAILED"
 391
 392 /*
 393  * Interruption-information format
 394  */
 395 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
 396 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
 397 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
 398 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
 399 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
 400 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
 401
 402 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
 403 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
 404 #define VECTORING_INFO_DELIEVER_CODE_MASK       INTR_INFO_DELIEVER_CODE_MASK
 405 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
 406
 407 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
 408 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
 409 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
 410 #define INTR_TYPE_EXCEPTION             (3 << 8)       /* processor exception */
 411 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
 412 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
 413
 414 #define VMX_POSTED_OUTSTANDING_NOTIF            256
 415
 416 /* GUEST_INTERRUPTIBILITY_INFO flags. */
 417 #define GUEST_INTR_STATE_STI            0x00000001
 418 #define GUEST_INTR_STATE_MOV_SS         0x00000002
 419 #define GUEST_INTR_STATE_SMI            0x00000004
 420 #define GUEST_INTR_STATE_NMI            0x00000008
 421
 422 /* GUEST_ACTIVITY_STATE flags */
 423 #define GUEST_ACTIVITY_ACTIVE           0
 424 #define GUEST_ACTIVITY_HLT              1
 425 #define GUEST_ACTIVITY_SHUTDOWN         2
 426 #define GUEST_ACTIVITY_WAIT_SIPI        3
 427
 428 /*
 429  * Exit Qualifications for MOV for Control Register Access
 430  */
 431 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control register */
 432 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
 433 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose register */
 434 #define LMSW_SOURCE_DATA_SHIFT 16
 435 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT)    /* 16:31 lmsw source */
 436 #define REG_EAX                         (0 << 8)
 437 #define REG_ECX                         (1 << 8)
 438 #define REG_EDX                         (2 << 8)
 439 #define REG_EBX                         (3 << 8)
 440 #define REG_ESP                         (4 << 8)
 441 #define REG_EBP                         (5 << 8)
 442 #define REG_ESI                         (6 << 8)
 443 #define REG_EDI                         (7 << 8)
 444 #define REG_R8                         (8 << 8)
 445 #define REG_R9                         (9 << 8)
 446 #define REG_R10                        (10 << 8)
 447 #define REG_R11                        (11 << 8)
 448 #define REG_R12                        (12 << 8)
 449 #define REG_R13                        (13 << 8)
 450 #define REG_R14                        (14 << 8)
 451 #define REG_R15                        (15 << 8)
 452
 453 /*
 454  * Exit Qualifications for MOV for Debug Register Access
 455  */
 456 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug register */
 457 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
 458 #define TYPE_MOV_TO_DR                  (0 << 4)
 459 #define TYPE_MOV_FROM_DR                (1 << 4)
 460 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
 461
 462
 463 /*
 464  * Exit Qualifications for APIC-Access
 465  */
 466 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
 467 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
 468 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
 469 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
 470 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
 471 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
 472 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
 473 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
 474
 475 /* segment AR */
 476 #define SEGMENT_AR_L_MASK (1 << 13)
 477
 478 /* entry controls */
 479 #define VM_ENTRY_CONTROLS_IA32E_MASK (1 << 9)
 480
 481 #define AR_TYPE_ACCESSES_MASK 1
 482 #define AR_TYPE_READABLE_MASK (1 << 1)
 483 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
 484 #define AR_TYPE_CODE_MASK (1 << 3)
 485 #define AR_TYPE_MASK 0x0f
 486 #define AR_TYPE_BUSY_64_TSS 11
 487 #define AR_TYPE_BUSY_32_TSS 11
 488 #define AR_TYPE_BUSY_16_TSS 3
 489 #define AR_TYPE_LDT 2
 490
 491 #define AR_UNUSABLE_MASK (1 << 16)
 492 #define AR_S_MASK (1 << 4)
 493 #define AR_P_MASK (1 << 7)
 494 #define AR_L_MASK (1 << 13)
 495 #define AR_DB_MASK (1 << 14)
 496 #define AR_G_MASK (1 << 15)
 497 #define AR_DPL_SHIFT 5
 498 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
 499
 500 #define AR_RESERVD_MASK 0xfffe0f00
 501
 502 #define TSS_PRIVATE_MEMSLOT                     (KVM_MEMORY_SLOTS + 0)
 503 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_MEMORY_SLOTS + 1)
 504 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_MEMORY_SLOTS + 2)
 505
 506 #define VMX_NR_VPIDS                            (1 << 16)
 507 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
 508 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
 509
 510 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
 511 #define VMX_EPT_EXTENT_CONTEXT                  1
 512 #define VMX_EPT_EXTENT_GLOBAL                   2
 513
 514 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
 515 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
 516 #define VMX_EPTP_UC_BIT                         (1ull << 8)
 517 #define VMX_EPTP_WB_BIT                         (1ull << 14)
 518 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
 519 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
 520 #define VMX_EPT_INVEPT_BIT                              (1ull << 20)
 521 #define VMX_EPT_AD_BIT                              (1ull << 21)
 522 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
 523 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
 524 #define VMX_EPT_EXTENT_INDIVIDUAL_BIT           (1ull << 24)
 525
 526 #define SHUTDOWN_REASON(r)      ((r) >> 16)
 527 #define SHUTDOWN_STATUS(r)      ((r) & 0xffff)
 528
 529 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
 530 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
 531
 532 #define VMX_EPT_GAW_4_LVL                               3       /* LVL - 1 */
 533 #define VMX_EPT_MAX_GAW                                 0x4
 534 #define VMX_EPT_MT_EPTE_SHIFT                   3
 535 #define VMX_EPT_GAW_EPTP_SHIFT                  3
 536 #define VMX_EPT_AD_ENABLE_BIT                   (1ull << 6)
 537 #define VMX_EPT_MEM_TYPE_WB                             0x6ull
 538 #define VMX_EPT_READABLE_MASK                   0x1ull
 539 #define VMX_EPT_WRITABLE_MASK                   0x2ull
 540 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
 541 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
 542 #define VMX_EPT_ACCESS_BIT                              (1ull << 8)
 543 #define VMX_EPT_DIRTY_BIT                               (1ull << 9)
 544
 545 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
 546
 547 #define VMX_EPT_FAULT_READ      0x01
 548 #define VMX_EPT_FAULT_WRITE     0x02
 549 #define VMX_EPT_FAULT_INS       0x04
 550
 551 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
 552 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
 553 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
 554 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
 555 #define ASM_VMX_VMPTRST_RAX       ".byte 0x0f, 0xc7, 0x38"
 556 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
 557 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
 558 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
 559 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
 560 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
 561 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
 562 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
 563
 564 struct vmx_msr_entry {
 565         uint32_t index;
 566         uint32_t reserved;
 567         uint64_t value;
 568 } __attribute__((aligned(16))) ;
 569
 570 /*
 571  * Exit Qualifications for entry failure during or after loading guest state
 572  */
 573 #define ENTRY_FAIL_DEFAULT              0
 574 #define ENTRY_FAIL_PDPTE                2
 575 #define ENTRY_FAIL_NMI                  3
 576 #define ENTRY_FAIL_VMCS_LINK_PTR        4
 577
 578 /*
 579  * VM-instruction error numbers
 580  */
 581 enum vm_instruction_error_number {
 582         VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
 583         VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
 584         VMXERR_VMCLEAR_VMXON_POINTER = 3,
 585         VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
 586         VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
 587         VMXERR_VMRESUME_AFTER_VMXOFF = 6,
 588         VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
 589         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
 590         VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
 591         VMXERR_VMPTRLD_VMXON_POINTER = 10,
 592         VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
 593         VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
 594         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
 595         VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
 596         VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
 597         VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
 598         VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
 599         VMXERR_VMCALL_NONCLEAR_VMCS = 19,
 600         VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
 601         VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
 602         VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
 603         VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
 604         VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
 605         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
 606         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
 607 };
 608
 609 #define MSR_IA32_VMX_BASIC_MSR                  0x480
 610 #define MSR_IA32_VMX_PINBASED_CTLS_MSR          0x481
 611 #define MSR_IA32_VMX_PROCBASED_CTLS_MSR         0x482
 612 #define MSR_IA32_VMX_EXIT_CTLS_MSR              0x483
 613 #define MSR_IA32_VMX_ENTRY_CTLS_MSR             0x484
 614
 615 /*
 616  * shutdown reasons
 617  */
 618 enum shutdown_reason {
 619         SHUTDOWN_SYS_EXIT = 1,
 620         SHUTDOWN_SYS_EXIT_GROUP,
 621         SHUTDOWN_SYS_EXECVE,
 622         SHUTDOWN_FATAL_SIGNAL,
 623         SHUTDOWN_EPT_VIOLATION,
 624         SHUTDOWN_NMI_EXCEPTION,
 625         SHUTDOWN_UNHANDLED_EXIT_REASON,
 626 };
 627
 628 /* Additional bits for VMMCPs, originally from the Dune version of kvm. */
 629 /*
 630  * vmx.h - header file for USM VMX driver.
 631  */
 632
 633 /* This is per-guest per-core, and the implementation specific area
 634  * should be assumed to have hidden fields.
 635  */
 636 struct vmcs {
 637         uint32_t revision_id;
 638         uint32_t abort_code;
 639         char _impl_specific[PGSIZE - sizeof(uint32_t) * 2];
 640 };
 641
 642 typedef uint64_t gpa_t;
 643 typedef uint64_t gva_t;
 644 /* TODO: remove these nasty macros */
 645 #define rdmsrl(msr, val) (val) = read_msr((msr))
 646 #define rdmsr(msr, low, high)                                                  \
 647 do {                                                                           \
 648         uint64_t m = read_msr(msr);                                                \
 649                                                                                    \
 650         low = m & 0xffffffff;                                                      \
 651         high = m >> 32;                                                            \
 652 } while (0)
 653
 654 struct vmx_capability {
 655         uint32_t ept;
 656         uint32_t vpid;
 657 };
 658
 659 extern struct vmx_capability vmx_capability;
 660
 661 struct vmcs_config {
 662         int size;
 663         int order;
 664         uint32_t revision_id;
 665         uint32_t pin_based_exec_ctrl;
 666         uint32_t cpu_based_exec_ctrl;
 667         uint32_t cpu_based_2nd_exec_ctrl;
 668         uint32_t vmexit_ctrl;
 669         uint32_t vmentry_ctrl;
 670 };
 671
 672 extern struct vmcs_config vmcs_config;
 673
 674 #define NR_AUTOLOAD_MSRS 8
 675
 676 /* the horror. */
 677 struct desc_struct {
 678         union {
 679                 struct {
 680                         unsigned int a;
 681                         unsigned int b;
 682                 };
 683                 struct {
 684                         uint16_t limit0;
 685                         uint16_t base0;
 686                         unsigned base1: 8, type: 4, s: 1, dpl: 2, p: 1;
 687                         unsigned limit: 4, avl: 1, l: 1, d: 1, g: 1, base2: 8;
 688                 };
 689         };
 690 } __attribute__((packed));
 691
 692 /* LDT or TSS descriptor in the GDT. 16 bytes. */
 693 struct ldttss_desc64 {
 694         uint16_t limit0;
 695         uint16_t base0;
 696         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 697         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 698         uint32_t base3;
 699         uint32_t zero1;
 700 } __attribute__((packed));
 701
 702 static char * const VMX_EXIT_REASON_NAMES[] = {
 703         VMX_EXIT_REASONS
 704 };