Added whitelisting to MSR read/write code
[akaros.git] / kern / arch / x86 / ros / trapframe.h
1 #pragma once
2
3 #define ROS_INC_ARCH_TRAPFRAME_H
4
5 #ifndef ROS_INC_TRAPFRAME_H
6 #error "Do not include include ros/arch/trapframe.h directly"
7 #endif
8
9 #include <ros/common.h>
10
11 #define ROS_ARCH_REFL_ID 0x1234
12
13 /* Page faults return the nature of the fault in the bits of the error code: */
14 #define PF_ERROR_PRESENT                0x01
15 #define PF_ERROR_WRITE                  0x02
16 #define PF_ERROR_USER                   0x04
17 #define PF_VMR_BACKED                   (1 << 31)
18
19 #include <ros/arch/trapframe64.h>
20
21 /* FP state and whatever else the kernel won't muck with automatically.  For
22  * now, it's the Non-64-bit-mode layout of FP and XMM registers, as used by
23  * FXSAVE and FXRSTOR.  Other modes will require a union on a couple entries.
24  * See SDM 2a 3-451. */
25 /* Header for the non-64-bit mode FXSAVE map */
26 struct fp_header_non_64bit {
27         uint16_t                fcw;
28         uint16_t                fsw;
29         uint8_t                 ftw;
30         uint8_t                 padding0;
31         uint16_t                fop;
32         uint32_t                fpu_ip;
33         uint16_t                cs;
34         uint16_t                padding1;
35         uint32_t                fpu_dp;
36         uint16_t                ds;
37         uint16_t                padding2;
38         uint32_t                mxcsr;
39         uint32_t                mxcsr_mask;
40 };
41
42 /* Header for the 64-bit mode FXSAVE map with promoted operand size */
43 struct fp_header_64bit_promoted {
44         uint16_t                fcw;
45         uint16_t                fsw;
46         uint8_t                 ftw;
47         uint8_t                 padding0;
48         uint16_t                fop;
49         uint64_t                fpu_ip;
50         uint64_t                fpu_dp;
51         uint32_t                mxcsr;
52         uint32_t                mxcsr_mask;
53 };
54
55 /* Header for the 64-bit mode FXSAVE map with default operand size */
56 struct fp_header_64bit_default {
57         uint16_t                fcw;
58         uint16_t                fsw;
59         uint8_t                 ftw;
60         uint8_t                 padding0;
61         uint16_t                fop;
62         uint32_t                fpu_ip;
63         uint16_t                cs;
64         uint16_t                padding1;
65         uint32_t                fpu_dp;
66         uint16_t                ds;
67         uint16_t                padding2;
68         uint32_t                mxcsr;
69         uint32_t                mxcsr_mask;
70 };
71
72 /* Just for storage space, not for real use     */
73 typedef struct {
74         unsigned int stor[4];
75 } __128bits;
76
77 typedef struct ancillary_state {
78         union { /* whichever header used depends on the mode */
79                 struct fp_header_non_64bit                      fp_head_n64;
80                 struct fp_header_64bit_promoted         fp_head_64p;
81                 struct fp_header_64bit_default          fp_head_64d;
82         };
83         __128bits               st0_mm0;        /* 128 bits: 80 for the st0, 48 rsv */
84         __128bits               st1_mm1;
85         __128bits               st2_mm2;
86         __128bits               st3_mm3;
87         __128bits               st4_mm4;
88         __128bits               st5_mm5;
89         __128bits               st6_mm6;
90         __128bits               st7_mm7;
91         __128bits               xmm0;
92         __128bits               xmm1;
93         __128bits               xmm2;
94         __128bits               xmm3;
95         __128bits               xmm4;
96         __128bits               xmm5;
97         __128bits               xmm6;
98         __128bits               xmm7;
99         __128bits               xmm8;           /* xmm8 and below only for 64-bit-mode */
100         __128bits               xmm9;
101         __128bits               xmm10;
102         __128bits               xmm11;
103         __128bits               xmm12;
104         __128bits               xmm13;
105         __128bits               xmm14;
106         __128bits               xmm15;
107         __128bits               reserv0;
108         __128bits               reserv1;
109         __128bits               reserv2;
110         __128bits               reserv3;
111         __128bits               reserv4;
112         __128bits               reserv5;
113 } __attribute__((aligned(16))) ancillary_state_t;