PCI device locking and synchronization
[akaros.git] / kern / arch / x86 / ros / trapframe.h
1 #ifndef ROS_INC_ARCH_TRAPFRAME_H
2 #define ROS_INC_ARCH_TRAPFRAME_H
3
4 #ifndef ROS_INC_TRAPFRAME_H
5 #error "Do not include include ros/arch/trapframe.h directly"
6 #endif
7
8 #include <ros/common.h>
9
10 #define ROS_ARCH_REFL_ID 0x1234
11
12 /* Page faults return the nature of the fault in the bits of the error code: */
13 #define PF_ERROR_PRESENT                0x01
14 #define PF_ERROR_WRITE                  0x02
15 #define PF_ERROR_USER                   0x04
16 #define PF_VMR_BACKED                   (1 << 31)
17
18 #ifdef __x86_64__
19 #include <ros/arch/trapframe64.h>
20 #else
21 #include <ros/arch/trapframe32.h>
22 #endif
23
24 /* FP state and whatever else the kernel won't muck with automatically.  For
25  * now, it's the Non-64-bit-mode layout of FP and XMM registers, as used by
26  * FXSAVE and FXRSTOR.  Other modes will require a union on a couple entries.
27  * See SDM 2a 3-451. */
28 /* Header for the non-64-bit mode FXSAVE map */
29 struct fp_header_non_64bit {
30         uint16_t                fcw;
31         uint16_t                fsw;
32         uint8_t                 ftw;
33         uint8_t                 padding0;
34         uint16_t                fop;
35         uint32_t                fpu_ip;
36         uint16_t                cs;
37         uint16_t                padding1;
38         uint32_t                fpu_dp;
39         uint16_t                ds;
40         uint16_t                padding2;
41         uint32_t                mxcsr;
42         uint32_t                mxcsr_mask;
43 };
44
45 /* Header for the 64-bit mode FXSAVE map with promoted operand size */
46 struct fp_header_64bit_promoted {
47         uint16_t                fcw;
48         uint16_t                fsw;
49         uint8_t                 ftw;
50         uint8_t                 padding0;
51         uint16_t                fop;
52         uint64_t                fpu_ip;
53         uint64_t                fpu_dp;
54         uint32_t                mxcsr;
55         uint32_t                mxcsr_mask;
56 };
57
58 /* Header for the 64-bit mode FXSAVE map with default operand size */
59 struct fp_header_64bit_default {
60         uint16_t                fcw;
61         uint16_t                fsw;
62         uint8_t                 ftw;
63         uint8_t                 padding0;
64         uint16_t                fop;
65         uint32_t                fpu_ip;
66         uint16_t                cs;
67         uint16_t                padding1;
68         uint32_t                fpu_dp;
69         uint16_t                ds;
70         uint16_t                padding2;
71         uint32_t                mxcsr;
72         uint32_t                mxcsr_mask;
73 };
74
75 /* Just for storage space, not for real use     */
76 typedef struct {
77         unsigned int stor[4];
78 } __128bits;
79
80 typedef struct ancillary_state {
81         union { /* whichever header used depends on the mode */
82                 struct fp_header_non_64bit                      fp_head_n64;
83                 struct fp_header_64bit_promoted         fp_head_64p;
84                 struct fp_header_64bit_default          fp_head_64d;
85         };
86         __128bits               st0_mm0;        /* 128 bits: 80 for the st0, 48 rsv */
87         __128bits               st1_mm1;
88         __128bits               st2_mm2;
89         __128bits               st3_mm3;
90         __128bits               st4_mm4;
91         __128bits               st5_mm5;
92         __128bits               st6_mm6;
93         __128bits               st7_mm7;
94         __128bits               xmm0;
95         __128bits               xmm1;
96         __128bits               xmm2;
97         __128bits               xmm3;
98         __128bits               xmm4;
99         __128bits               xmm5;
100         __128bits               xmm6;
101         __128bits               xmm7;
102         __128bits               xmm8;           /* xmm8 and below only for 64-bit-mode */
103         __128bits               xmm9;
104         __128bits               xmm10;
105         __128bits               xmm11;
106         __128bits               xmm12;
107         __128bits               xmm13;
108         __128bits               xmm14;
109         __128bits               xmm15;
110         __128bits               reserv0;
111         __128bits               reserv1;
112         __128bits               reserv2;
113         __128bits               reserv3;
114         __128bits               reserv4;
115         __128bits               reserv5;
116 } __attribute__((aligned(16))) ancillary_state_t;
117
118 #endif /* ROS_INC_ARCH_TRAPFRAME_H */