More debugging for VMs.
[akaros.git] / kern / arch / x86 / ros / trapframe.h
1 #ifndef ROS_INC_ARCH_TRAPFRAME_H
2 #define ROS_INC_ARCH_TRAPFRAME_H
3
4 #ifndef ROS_INC_TRAPFRAME_H
5 #error "Do not include include ros/arch/trapframe.h directly"
6 #endif
7
8 #include <ros/common.h>
9
10 #ifdef __x86_64__
11 #include <ros/arch/trapframe64.h>
12 #else
13 #include <ros/arch/trapframe32.h>
14 #endif
15
16 /* FP state and whatever else the kernel won't muck with automatically.  For
17  * now, it's the Non-64-bit-mode layout of FP and XMM registers, as used by
18  * FXSAVE and FXRSTOR.  Other modes will require a union on a couple entries.
19  * See SDM 2a 3-451. */
20 /* Header for the non-64-bit mode FXSAVE map */
21 struct fp_header_non_64bit {
22         uint16_t                fcw;
23         uint16_t                fsw;
24         uint8_t                 ftw;
25         uint8_t                 padding0;
26         uint16_t                fop;
27         uint32_t                fpu_ip;
28         uint16_t                cs;
29         uint16_t                padding1;
30         uint32_t                fpu_dp;
31         uint16_t                ds;
32         uint16_t                padding2;
33         uint32_t                mxcsr;
34         uint32_t                mxcsr_mask;
35 };
36
37 /* Header for the 64-bit mode FXSAVE map with promoted operand size */
38 struct fp_header_64bit_promoted {
39         uint16_t                fcw;
40         uint16_t                fsw;
41         uint8_t                 ftw;
42         uint8_t                 padding0;
43         uint16_t                fop;
44         uint64_t                fpu_ip;
45         uint64_t                fpu_dp;
46         uint32_t                mxcsr;
47         uint32_t                mxcsr_mask;
48 };
49
50 /* Header for the 64-bit mode FXSAVE map with default operand size */
51 struct fp_header_64bit_default {
52         uint16_t                fcw;
53         uint16_t                fsw;
54         uint8_t                 ftw;
55         uint8_t                 padding0;
56         uint16_t                fop;
57         uint32_t                fpu_ip;
58         uint16_t                cs;
59         uint16_t                padding1;
60         uint32_t                fpu_dp;
61         uint16_t                ds;
62         uint16_t                padding2;
63         uint32_t                mxcsr;
64         uint32_t                mxcsr_mask;
65 };
66
67 /* Just for storage space, not for real use     */
68 typedef struct {
69         unsigned int stor[4];
70 } __128bits;
71
72 typedef struct ancillary_state {
73         union { /* whichever header used depends on the mode */
74                 struct fp_header_non_64bit                      fp_head_n64;
75                 struct fp_header_64bit_promoted         fp_head_64p;
76                 struct fp_header_64bit_default          fp_head_64d;
77         };
78         __128bits               st0_mm0;        /* 128 bits: 80 for the st0, 48 rsv */
79         __128bits               st1_mm1;
80         __128bits               st2_mm2;
81         __128bits               st3_mm3;
82         __128bits               st4_mm4;
83         __128bits               st5_mm5;
84         __128bits               st6_mm6;
85         __128bits               st7_mm7;
86         __128bits               xmm0;
87         __128bits               xmm1;
88         __128bits               xmm2;
89         __128bits               xmm3;
90         __128bits               xmm4;
91         __128bits               xmm5;
92         __128bits               xmm6;
93         __128bits               xmm7;
94         __128bits               xmm8;           /* xmm8 and below only for 64-bit-mode */
95         __128bits               xmm9;
96         __128bits               xmm10;
97         __128bits               xmm11;
98         __128bits               xmm12;
99         __128bits               xmm13;
100         __128bits               xmm14;
101         __128bits               xmm15;
102         __128bits               reserv0;
103         __128bits               reserv1;
104         __128bits               reserv2;
105         __128bits               reserv3;
106         __128bits               reserv4;
107         __128bits               reserv5;
108 } __attribute__((aligned(16))) ancillary_state_t;
109
110 #endif /* ROS_INC_ARCH_TRAPFRAME_H */