6 /* See COPYRIGHT for copyright information. */
10 #include <arch/apic.h>
12 #include <ros/error.h>
13 #include <sys/queue.h>
23 #include <page_alloc.h>
25 // These variables are set in i386_vm_init()
26 pde_t* boot_pgdir; // Virtual address of boot time page directory
27 physaddr_t RO boot_cr3; // Physical address of boot time page directory
30 page_t *RO pages = NULL; // Virtual address of physical page array
32 // Global descriptor table.
34 // The kernel and user segments are identical (except for the DPL).
35 // To load the SS register, the CPL must equal the DPL. Thus,
36 // we must duplicate the segments for the user and the kernel.
40 // 0x0 - unused (always faults -- for trapping NULL far pointers)
43 // 0x8 - kernel code segment
44 [GD_KT >> 3] = SEG(STA_X | STA_R, 0x0, 0xffffffff, 0),
46 // 0x10 - kernel data segment
47 [GD_KD >> 3] = SEG(STA_W, 0x0, 0xffffffff, 0),
49 // 0x18 - user code segment
50 [GD_UT >> 3] = SEG(STA_X | STA_R, 0x0, 0xffffffff, 3),
52 // 0x20 - user data segment
53 [GD_UD >> 3] = SEG(STA_W, 0x0, 0xffffffff, 3),
55 // 0x28 - tss, initialized in idt_init()
56 [GD_TSS >> 3] = SEG_NULL,
58 // 0x30 - LDT, set per-process in proc_startcore()
59 [GD_LDT >> 3] = SEG_NULL
62 pseudodesc_t gdt_pd = {
63 sizeof(gdt) - 1, (unsigned long) gdt
69 return mc146818_read(r) | (mc146818_read(r + 1) << 8);
75 cpuid(1, 0, 0, 0, &edx);
76 if (edx & CPUID_PSE_SUPPORT) {
85 // --------------------------------------------------------------
86 // Set up initial memory mappings and turn on MMU.
87 // --------------------------------------------------------------
89 static void check_boot_pgdir(bool pse);
92 // Given pgdir, a pointer to a page directory,
93 // walk the 2-level page table structure to find
94 // the page table entry (PTE) for linear address la.
95 // Return a pointer to this PTE.
97 // If the relevant page table doesn't exist in the page directory:
98 // - If create == 0, return 0.
99 // - Otherwise allocate a new page table, install it into pgdir,
100 // and return a pointer into it.
101 // (Questions: What data should the new page table contain?
102 // And what permissions should the new pgdir entry have?
103 // Note that we use the 486-only "WP" feature of %cr0, which
104 // affects the way supervisor-mode writes are checked.)
106 // This function abstracts away the 2-level nature of
107 // the page directory by allocating new page tables
110 // boot_pgdir_walk may ONLY be used during initialization,
111 // before the page_free_list has been set up.
112 // It should panic on failure. (Note that boot_alloc already panics
115 // Supports returning jumbo (4MB PSE) PTEs. To create with a jumbo, pass in 2.
117 // Maps non-PSE PDEs as U/W. W so the kernel can, U so the user can read via
118 // UVPT. UVPT security comes from the UVPT mapping (U/R). All other kernel pages
119 // protected at the second layer
121 boot_pgdir_walk(pde_t *COUNT(NPDENTRIES) pgdir, uintptr_t la, int create)
123 pde_t* the_pde = &pgdir[PDX(la)];
126 if (*the_pde & PTE_P) {
127 if (*the_pde & PTE_PS)
128 return (pte_t*)the_pde;
129 return &((pde_t*COUNT(NPTENTRIES))KADDR(PTE_ADDR(*the_pde)))[PTX(la)];
135 panic("Attempting to find a Jumbo PTE at an unaligned VA!");
136 *the_pde = PTE_PS | PTE_P;
137 return (pte_t*)the_pde;
139 new_table = boot_alloc(PGSIZE, PGSIZE);
140 memset(new_table, 0, PGSIZE);
141 *the_pde = (pde_t)PADDR(new_table) | PTE_P | PTE_W | PTE_U | PTE_G;
142 return &((pde_t*COUNT(NPTENTRIES))KADDR(PTE_ADDR(*the_pde)))[PTX(la)];
146 // Map [la, la+size) of linear address space to physical [pa, pa+size)
147 // in the page table rooted at pgdir. Size is a multiple of PGSIZE.
148 // Use permission bits perm|PTE_P for the entries.
150 // This function may ONLY be used during initialization,
151 // before the page_free_list has been set up.
153 // To map with Jumbos, set PTE_PS in perm
155 boot_map_segment(pde_t *COUNT(NPDENTRIES) pgdir, uintptr_t la, size_t size, physaddr_t pa, int perm)
159 // la can be page unaligned, but weird things will happen
160 // unless pa has the same offset. pa always truncates any
161 // possible offset. will warn. size can be weird too.
163 warn("la not page aligned in boot_map_segment!");
167 if (JPGOFF(la) || JPGOFF(pa))
168 panic("Tried to map a Jumbo page at an unaligned address!");
169 // need to index with i instead of la + size, in case of wrap-around
170 for (i = 0; i < size; i += JPGSIZE, la += JPGSIZE, pa += JPGSIZE) {
171 pte = boot_pgdir_walk(pgdir, la, 2);
172 *pte = PTE_ADDR(pa) | PTE_P | perm;
175 for (i = 0; i < size; i += PGSIZE, la += PGSIZE, pa += PGSIZE) {
176 pte = boot_pgdir_walk(pgdir, la, 1);
178 // if we start using the extra flag for PAT, which we aren't,
179 // this will warn, since PTE_PS and PTE_PAT are the same....
180 warn("Possibly attempting to map a regular page into a Jumbo PDE");
181 *pte = PTE_ADDR(pa) | PTE_P | perm;
186 // could consider having an API to allow these to dynamically change
187 // MTRRs are for physical, static ranges. PAT are linear, more granular, and
189 void setup_default_mtrrs(barrier_t* smp_barrier)
191 // disable interrupts
193 disable_irqsave(&state);
194 // barrier - if we're meant to do this for all cores, we'll be
195 // passed a pointer to an initialized barrier
197 waiton_barrier(smp_barrier);
199 // disable caching cr0: set CD and clear NW
200 lcr0((rcr0() | CR0_CD) & ~CR0_NW);
205 // disable MTRRs, and sets default type to WB (06)
206 write_msr(IA32_MTRR_DEF_TYPE, 0x00000006);
208 // Now we can actually safely adjust the MTRRs
209 // MTRR for IO Holes (note these are 64 bit values we are writing)
210 // 0x000a0000 - 0x000c0000 : VGA - WC 0x01
211 write_msr(IA32_MTRR_PHYSBASE0, PTE_ADDR(VGAPHYSMEM) | 0x01);
212 // if we need to have a full 64bit val, use the UINT64 macro
213 write_msr(IA32_MTRR_PHYSMASK0, 0x0000000ffffe0800);
214 // 0x000c0000 - 0x00100000 : IO devices (and ROM BIOS) - UC 0x00
215 write_msr(IA32_MTRR_PHYSBASE1, PTE_ADDR(DEVPHYSMEM) | 0x00);
216 write_msr(IA32_MTRR_PHYSMASK1, 0x0000000ffffc0800);
218 /* Going to skip them, since we set their mode using PAT when we
221 // make sure all other MTRR ranges are disabled (should be unnecessary)
222 write_msr(IA32_MTRR_PHYSMASK2, 0);
223 write_msr(IA32_MTRR_PHYSMASK3, 0);
224 write_msr(IA32_MTRR_PHYSMASK4, 0);
225 write_msr(IA32_MTRR_PHYSMASK5, 0);
226 write_msr(IA32_MTRR_PHYSMASK6, 0);
227 write_msr(IA32_MTRR_PHYSMASK7, 0);
229 // keeps default type to WB (06), turns MTRRs on, and turns off fixed ranges
230 write_msr(IA32_MTRR_DEF_TYPE, 0x00000806);
231 // reflush caches and TLB
235 lcr0(rcr0() & ~(CR0_CD | CR0_NW));
238 waiton_barrier(smp_barrier);
240 enable_irqsave(&state);
244 // Set up a two-level page table:
245 // boot_pgdir is its linear (virtual) address of the root
246 // boot_cr3 is the physical adresss of the root
247 // Then turn on paging. Then effectively turn off segmentation.
248 // (i.e., the segment base addrs are set to zero).
250 // This function only sets up the kernel part of the address space
251 // (ie. addresses >= UTOP). The user part of the address space
252 // will be setup later.
254 // From UTOP to ULIM, the user is allowed to read but not write.
255 // Above ULIM the user cannot read (or write).
266 cprintf("PSE capability detected.\n");
268 // we paniced earlier if we don't support PGE. turn it on now.
269 // it's used in boot_map_segment, which covers all of the mappings that are
270 // the same for all address spaces. and also for the VPT mapping below.
271 lcr4(rcr4() | CR4_PGE);
273 // set up mtrr's for core0. other cores will do the same later
274 setup_default_mtrrs(0);
278 * - can walk and set up boot_map_segments with jumbos but can't
279 * insert yet. need to look at the page_dir and friends.
280 * - anything related to a single struct Page still can't handle
281 * jumbos. will need to think about and adjust Page functions
282 * - do we want to store info like this in the struct Page? or just check
284 * - when we alloc a page, and we want it to be 4MB, we'll need
285 * to have contiguous memory, etc
286 * - there's a difference between having 4MB page table entries
287 * and having 4MB Page tracking structs. changing the latter will
288 * break a lot of things
289 * - showmapping and friends work on a 4KB granularity, but map to the
291 * - need to not insert / boot_map a single page into an area that is
292 * already holding a jumbo page. will need to break the jumbo up so that
293 * we can then insert the lone page. currently warns.
294 * - some inherent issues with the pgdir_walks returning a PTE, and we
295 * don't know whether it is a jumbo (PDE) or a regular PTE.
298 //////////////////////////////////////////////////////////////////////
299 // create initial page directory.
300 pgdir = boot_alloc(PGSIZE, PGSIZE);
301 memset(pgdir, 0, PGSIZE);
303 boot_cr3 = PADDR(pgdir);
304 // helpful if you want to manually walk with kvm / bochs
305 //printk("pgdir va = %08p, pgdir pa = %08p\n\n", pgdir, PADDR(pgdir));
307 //////////////////////////////////////////////////////////////////////
308 // Recursively insert PD in itself as a page table, to form
309 // a virtual page table at virtual address VPT.
310 // (For now, you don't have understand the greater purpose of the
311 // following two lines. Unless you are eagle-eyed, in which case you
312 // should already know.)
314 // Permissions: kernel RW, user NONE, Global Page
315 pgdir[PDX(VPT)] = PADDR(pgdir) | PTE_W | PTE_P | PTE_G;
318 // Permissions: kernel R, user R, Global Page
319 pgdir[PDX(UVPT)] = PADDR(pgdir) | PTE_U | PTE_P | PTE_G;
321 //////////////////////////////////////////////////////////////////////
322 // Map the kernel stack (symbol name "bootstack"). The complete VA
323 // range of the stack, [KSTACKTOP-PTSIZE, KSTACKTOP), breaks into two
325 // * [KSTACKTOP-KSTKSIZE, KSTACKTOP) -- backed by physical memory
326 // * [KSTACKTOP-PTSIZE, KSTACKTOP-KSTKSIZE) -- not backed => faults
327 // Permissions: kernel RW, user NONE
328 // Your code goes here:
330 // remember that the space for the kernel stack is allocated in the binary.
331 // bootstack and bootstacktop point to symbols in the data section, which
332 // at this point are like 0xc010b000. KSTACKTOP is the desired loc in VM
333 boot_map_segment(pgdir, (uintptr_t)KSTACKTOP - KSTKSIZE,
334 KSTKSIZE, PADDR(bootstack), PTE_W | PTE_G);
336 //////////////////////////////////////////////////////////////////////
337 // Map all of physical memory at KERNBASE.
338 // Ie. the VA range [KERNBASE, 2^32) should map to
339 // the PA range [0, 2^32 - KERNBASE)
340 // We might not have 2^32 - KERNBASE bytes of physical memory, but
341 // we just set up the mapping anyway.
342 // Permissions: kernel RW, user NONE
343 // Your code goes here:
345 // this maps all of the possible phys memory
346 // note the use of unsigned underflow to get size = 0x40000000
347 //boot_map_segment(pgdir, KERNBASE, -KERNBASE, 0, PTE_W);
348 // but this only maps what is available, and saves memory. every 4MB of
349 // mapped memory requires a 2nd level page: 2^10 entries, each covering 2^12
350 // need to modify tests below to account for this
352 // map the first 4MB as regular entries, to support different MTRRs
353 boot_map_segment(pgdir, KERNBASE, JPGSIZE, 0, PTE_W | PTE_G);
354 boot_map_segment(pgdir, KERNBASE + JPGSIZE, maxaddrpa - JPGSIZE, JPGSIZE,
355 PTE_W | PTE_G | PTE_PS);
357 boot_map_segment(pgdir, KERNBASE, maxaddrpa, 0, PTE_W | PTE_G);
359 // APIC mapping: using PAT (but not *the* PAT flag) to make these type UC
361 boot_map_segment(pgdir, (uintptr_t)IOAPIC_BASE, PGSIZE, IOAPIC_BASE,
362 PTE_PCD | PTE_PWT | PTE_W | PTE_G);
364 boot_map_segment(pgdir, (uintptr_t)LAPIC_BASE, PGSIZE, LAPIC_BASE,
365 PTE_PCD | PTE_PWT | PTE_W | PTE_G);
367 // Check that the initial page directory has been set up correctly.
368 check_boot_pgdir(pse);
370 //////////////////////////////////////////////////////////////////////
371 // On x86, segmentation maps a VA to a LA (linear addr) and
372 // paging maps the LA to a PA. I.e. VA => LA => PA. If paging is
373 // turned off the LA is used as the PA. Note: there is no way to
374 // turn off segmentation. The closest thing is to set the base
375 // address to 0, so the VA => LA mapping is the identity.
377 // Current mapping: VA KERNBASE+x => PA x.
378 // (segmentation base=-KERNBASE and paging is off)
380 // From here on down we must maintain this VA KERNBASE + x => PA x
381 // mapping, even though we are turning on paging and reconfiguring
384 // Map VA 0:4MB same as VA KERNBASE, i.e. to PA 0:4MB.
385 // (Limits our kernel to <4MB)
386 /* They mean linear address 0:4MB, and the kernel < 4MB is only until
387 * segmentation is turned off.
388 * once we turn on paging, segmentation is still on, so references to
389 * KERNBASE+x will get mapped to linear address x, which we need to make
390 * sure can map to phys addr x, until we can turn off segmentation and
391 * KERNBASE+x maps to LA KERNBASE+x, which maps to PA x, via paging
393 pgdir[0] = pgdir[PDX(KERNBASE)];
395 // Install page table.
400 // CD and NW should already be on, but just in case these turn on caching
401 cr0 |= CR0_PE|CR0_PG|CR0_AM|CR0_WP|CR0_NE|CR0_MP;
402 cr0 &= ~(CR0_TS|CR0_EM|CR0_CD|CR0_NW);
405 // Current mapping: KERNBASE+x => x => x.
406 // (x < 4MB so uses paging pgdir[0])
408 // Reload all segment registers.
409 asm volatile("lgdt gdt_pd");
410 asm volatile("movw %%ax,%%gs" :: "a" (GD_UD|3));
411 asm volatile("movw %%ax,%%fs" :: "a" (GD_UD|3));
412 asm volatile("movw %%ax,%%es" :: "a" (GD_KD));
413 asm volatile("movw %%ax,%%ds" :: "a" (GD_KD));
414 asm volatile("movw %%ax,%%ss" :: "a" (GD_KD));
415 asm volatile("ljmp %0,$1f\n 1:\n" :: "i" (GD_KT)); // reload cs
416 asm volatile("lldt %%ax" :: "a" (0));
418 // Final mapping: KERNBASE+x => KERNBASE+x => x.
420 // This mapping was only used after paging was turned on but
421 // before the segment registers were reloaded.
424 // Flush the TLB for good measure, to kill the pgdir[0] mapping.
429 // Checks that the kernel part of virtual address space
430 // has been setup roughly correctly(by i386_vm_init()).
432 // This function doesn't test every corner case,
433 // in fact it doesn't test the permission bits at all,
434 // but it is a pretty good sanity check.
436 static physaddr_t check_va2pa(pde_t *COUNT(NPDENTRIES) pgdir, uintptr_t va);
439 check_boot_pgdir(bool pse)
447 //for (i = 0; KERNBASE + i != 0; i += PGSIZE)
448 // adjusted check to account for only mapping avail mem
450 for (i = 0; i < maxaddrpa; i += JPGSIZE)
451 assert(check_va2pa(pgdir, KERNBASE + i) == i);
453 for (i = 0; i < maxaddrpa; i += PGSIZE)
454 assert(check_va2pa(pgdir, KERNBASE + i) == i);
456 // check kernel stack
457 for (i = 0; i < KSTKSIZE; i += PGSIZE)
458 assert(check_va2pa(pgdir, KSTACKTOP - KSTKSIZE + i) == PADDR(bootstack) + i);
460 // check for zero/non-zero in PDEs
461 for (i = 0; i < NPDENTRIES; i++) {
465 case PDX(KSTACKTOP-1):
466 case PDX(LAPIC_BASE): // LAPIC mapping. TODO: remove when MTRRs are up
470 //if (i >= PDX(KERNBASE))
471 // adjusted check to account for only mapping avail mem
472 // and you can't KADDR maxpa (just above legal range)
473 // maxaddrpa can be up to maxpa, so assume the worst
474 if (i >= PDX(KERNBASE) && i <= PDX(KADDR(maxaddrpa-1)))
477 assert(pgdir[i] == 0);
483 * user read-only. check for user and write, should be only user
484 * eagle-eyed viewers should be able to explain the extra cases.
485 * for the mongoose-eyed, remember that weird shit happens when you loop
486 * through UVPT. Specifically, you can't loop once, then look at a jumbo
487 * page that is kernel only. That's the end of the page table for you, so
488 * having a U on the entry doesn't make sense. Thus we check for a jumbo
489 * page, and special case it. This will happen at 0xbf701000. Why is this
490 * magical? Get your eagle glasses and figure it out. */
491 for (i = UTOP; i < ULIM; i+=PGSIZE) {
492 pte = get_va_perms(pgdir, (void*SAFE)TC(i));
494 if (i == UVPT+(VPT >> 10))
496 if (*pgdir_walk(pgdir, (void*SAFE)TC(i), 0) & PTE_PS) {
497 assert((pte & PTE_U) != PTE_U);
498 assert((pte & PTE_W) != PTE_W);
500 assert((pte & PTE_U) == PTE_U);
501 assert((pte & PTE_W) != PTE_W);
505 // kernel read-write.
506 for (i = ULIM; i <= KERNBASE + maxaddrpa - PGSIZE; i+=PGSIZE) {
507 pte = get_va_perms(pgdir, (void*SAFE)TC(i));
508 if ((pte & PTE_P) && (i != VPT+(UVPT>>10))) {
509 assert((pte & PTE_U) != PTE_U);
510 assert((pte & PTE_W) == PTE_W);
514 pte = get_va_perms(pgdir, (void*SAFE)TC(UVPT+(VPT>>10)));
515 assert((pte & PTE_U) != PTE_U);
516 assert((pte & PTE_W) != PTE_W);
518 // note this means the kernel cannot directly manipulate this virtual address
519 // convince yourself this isn't a big deal, eagle-eyes!
520 pte = get_va_perms(pgdir, (void*SAFE)TC(VPT+(UVPT>>10)));
521 assert((pte & PTE_U) != PTE_U);
522 assert((pte & PTE_W) != PTE_W);
524 cprintf("check_boot_pgdir() succeeded!\n");
527 // This function returns the physical address of the page containing 'va',
528 // defined by the page directory 'pgdir'. The hardware normally performs
529 // this functionality for us! We define our own version to help check
530 // the check_boot_pgdir() function; it shouldn't be used elsewhere.
533 check_va2pa(pde_t *COUNT(NPDENTRIES) _pgdir, uintptr_t va)
535 pte_t *COUNT(NPTENTRIES) p;
536 pde_t *COUNT(1) pgdir;
538 pgdir = &_pgdir[PDX(va)];
539 if (!(*pgdir & PTE_P))
542 return PTE_ADDR(*pgdir);
543 p = (pte_t*COUNT(NPTENTRIES)) KADDR(PTE_ADDR(*pgdir));
544 if (!(p[PTX(va)] & PTE_P))
546 return PTE_ADDR(p[PTX(va)]);
550 * Remove the second level page table associated with virtual address va.
551 * Will 0 out the PDE for that page table.
552 * Panics if the page table has any present entries.
553 * This should be called rarely and with good cause.
554 * Currently errors if the PDE is jumbo or not present.
556 error_t pagetable_remove(pde_t *pgdir, void *va)
558 pde_t* the_pde = &pgdir[PDX(va)];
560 if (!(*the_pde & PTE_P) || (*the_pde & PTE_PS))
562 pte_t* page_table = (pde_t*COUNT(NPTENTRIES))KADDR(PTE_ADDR(*the_pde));
563 for (int i = 0; i < NPTENTRIES; i++)
564 if (page_table[i] & PTE_P)
565 panic("Page table not empty during attempted removal!");
567 page_decref(pa2page(PADDR(page_table)));
571 // Given 'pgdir', a pointer to a page directory, pgdir_walk returns
572 // a pointer to the page table entry (PTE) for linear address 'va'.
573 // This requires walking the two-level page table structure.
575 // If the relevant page table doesn't exist in the page directory, then:
576 // - If create == 0, pgdir_walk returns NULL.
577 // - Otherwise, pgdir_walk tries to allocate a new page table
578 // with page_alloc. If this fails, pgdir_walk returns NULL.
579 // - Otherwise, pgdir_walk returns a pointer into the new page table.
581 // This is boot_pgdir_walk, but using page_alloc() instead of boot_alloc().
582 // Unlike boot_pgdir_walk, pgdir_walk can fail.
584 // Hint: you can turn a Page * into the physical address of the
585 // page it refers to with page2pa() from kern/pmap.h.
587 // Supports returning jumbo (4MB PSE) PTEs. To create with a jumbo, pass in 2.
589 pgdir_walk(pde_t *pgdir, const void *SNT va, int create)
591 pde_t* the_pde = &pgdir[PDX(va)];
594 if (*the_pde & PTE_P) {
595 if (*the_pde & PTE_PS)
596 return (pte_t*)the_pde;
597 return &((pde_t*COUNT(NPTENTRIES))KADDR(PTE_ADDR(*the_pde)))[PTX(va)];
603 panic("Attempting to find a Jumbo PTE at an unaligned VA!");
604 *the_pde = PTE_PS | PTE_P;
605 return (pte_t*)the_pde;
607 if (kpage_alloc(&new_table))
609 page_setref(new_table,1);
610 memset(page2kva(new_table), 0, PGSIZE);
611 *the_pde = (pde_t)page2pa(new_table) | PTE_P | PTE_W | PTE_U;
612 return &((pde_t*COUNT(NPTENTRIES))KADDR(PTE_ADDR(*the_pde)))[PTX(va)];
615 /* Returns the effective permissions for PTE_U, PTE_W, and PTE_P on a given
616 * virtual address. Note we need to consider the composition of every PTE in
617 * the page table walk. */
618 int get_va_perms(pde_t *pgdir, const void *SNT va)
620 pde_t the_pde = pgdir[PDX(va)];
623 if (!(the_pde & PTE_P))
625 if (the_pde & PTE_PS)
626 return the_pde & (PTE_U | PTE_W | PTE_P);
627 the_pte = ((pde_t*COUNT(NPTENTRIES))KADDR(PTE_ADDR(the_pde)))[PTX(va)];
628 if (!(the_pte & PTE_P))
630 return the_pte & the_pde & (PTE_U | PTE_W | PTE_P);
633 void *get_free_va_range(pde_t *pgdir, uintptr_t addr, size_t len)
635 addr = ROUNDUP(MAX(addr,UMMAP_START),PGSIZE);
636 len = ROUNDUP(len,PGSIZE);
638 for(char* a = (char*)addr; a < (char*)USTACKBOT; a += PGSIZE)
640 for(char* b = a; b < a+len; b += PGSIZE)
642 pte_t* pte = pgdir_walk(pgdir,b,0);
643 if(pte && !PAGE_UNMAPPED(*pte))
648 if(b+PGSIZE == a+len)
655 /* Flushes a TLB, including global pages. We should always have the CR4_PGE
656 * flag set, but just in case, we'll check. Toggling this bit flushes the TLB.
658 void tlb_flush_global(void)
660 uint32_t cr4 = rcr4();
662 lcr4(cr4 & ~CR4_PGE);
671 page_t *pp, *pp0, *pp1, *pp2;
672 page_list_t fl[1024];
675 // should be able to allocate three pages
677 assert(kpage_alloc(&pp0) == 0);
678 assert(kpage_alloc(&pp1) == 0);
679 assert(kpage_alloc(&pp2) == 0);
685 assert(pp1 && pp1 != pp0);
686 assert(pp2 && pp2 != pp1 && pp2 != pp0);
688 // temporarily steal the rest of the free pages
689 for(int i=0; i<llc_cache->num_colors; i++) {
690 fl[i] = colored_page_free_list[i];
691 LIST_INIT(&colored_page_free_list[i]);
694 // should be no free memory
695 assert(kpage_alloc(&pp) == -ENOMEM);
697 // Fill pp1 with bogus data and check for invalid tlb entries
698 memset(page2kva(pp1), 0xFFFFFFFF, PGSIZE);
700 // there is no page allocated at address 0
701 assert(page_lookup(boot_pgdir, (void *) 0x0, &ptep) == NULL);
703 // there is no free memory, so we can't allocate a page table
704 assert(page_insert(boot_pgdir, pp1, 0x0, 0) < 0);
706 // free pp0 and try again: pp0 should be used for page table
708 assert(page_insert(boot_pgdir, pp1, 0x0, 0) == 0);
709 tlb_invalidate(boot_pgdir, 0x0);
710 // DEP Should have shot down invalid TLB entry - let's check
713 assert(*x == 0xFFFFFFFF);
715 assert(PTE_ADDR(boot_pgdir[0]) == page2pa(pp0));
716 assert(check_va2pa(boot_pgdir, 0x0) == page2pa(pp1));
717 assert(pp1->page_ref == 1);
718 assert(pp0->page_ref == 1);
720 // should be able to map pp2 at PGSIZE because pp0 is already allocated for page table
721 assert(page_insert(boot_pgdir, pp2, (void*SNT) PGSIZE, 0) == 0);
722 assert(check_va2pa(boot_pgdir, PGSIZE) == page2pa(pp2));
723 assert(pp2->page_ref == 1);
725 // Make sure that pgdir_walk returns a pointer to the pte and
726 // not the table or some other garbage
728 pte_t *p = (pte_t*COUNT(NPTENTRIES))KADDR(PTE_ADDR(boot_pgdir[PDX(PGSIZE)]));
729 assert(pgdir_walk(boot_pgdir, (void *SNT)PGSIZE, 0) == &p[PTX(PGSIZE)]);
732 // should be no free memory
733 assert(kpage_alloc(&pp) == -ENOMEM);
735 // should be able to map pp2 at PGSIZE because it's already there
736 assert(page_insert(boot_pgdir, pp2, (void*SNT) PGSIZE, PTE_U) == 0);
737 assert(check_va2pa(boot_pgdir, PGSIZE) == page2pa(pp2));
738 assert(pp2->page_ref == 1);
740 // Make sure that we actually changed the permission on pp2 when we re-mapped it
742 pte_t *p = pgdir_walk(boot_pgdir, (void*SNT)PGSIZE, 0);
743 assert(((*p) & PTE_U) == PTE_U);
746 // pp2 should NOT be on the free list
747 // could happen in ref counts are handled sloppily in page_insert
748 assert(kpage_alloc(&pp) == -ENOMEM);
750 // should not be able to map at PTSIZE because need free page for page table
751 assert(page_insert(boot_pgdir, pp0, (void*SNT) PTSIZE, 0) < 0);
753 // insert pp1 at PGSIZE (replacing pp2)
754 assert(page_insert(boot_pgdir, pp1, (void*SNT) PGSIZE, 0) == 0);
756 // should have pp1 at both 0 and PGSIZE, pp2 nowhere, ...
757 assert(check_va2pa(boot_pgdir, 0) == page2pa(pp1));
758 assert(check_va2pa(boot_pgdir, PGSIZE) == page2pa(pp1));
759 // ... and ref counts should reflect this
760 assert(pp1->page_ref == 2);
761 assert(pp2->page_ref == 0);
763 // pp2 should be returned by page_alloc
764 assert(kpage_alloc(&pp) == 0 && pp == pp2);
767 // unmapping pp1 at 0 should keep pp1 at PGSIZE
768 page_remove(boot_pgdir, 0x0);
769 assert(check_va2pa(boot_pgdir, 0x0) == ~0);
770 assert(check_va2pa(boot_pgdir, PGSIZE) == page2pa(pp1));
771 assert(pp1->page_ref == 1);
772 assert(pp2->page_ref == 0);
774 // unmapping pp1 at PGSIZE should free it
775 page_remove(boot_pgdir, (void*SNT) PGSIZE);
776 assert(check_va2pa(boot_pgdir, 0x0) == ~0);
777 assert(check_va2pa(boot_pgdir, PGSIZE) == ~0);
778 assert(pp1->page_ref == 0);
779 assert(pp2->page_ref == 0);
781 // so it should be returned by page_alloc
782 assert(kpage_alloc(&pp) == 0 && pp == pp1);
785 // should be no free memory
786 assert(kpage_alloc(&pp) == -ENOMEM);
788 // forcibly take pp0 back
789 assert(PTE_ADDR(boot_pgdir[0]) == page2pa(pp0));
791 assert(pp0->page_ref == 1);
794 // Catch invalid pointer addition in pgdir_walk - i.e. pgdir + PDX(va)
796 // Give back pp0 for a bit
799 void *SNT va = (void *SNT)((PGSIZE * NPDENTRIES) + PGSIZE);
800 pte_t *p2 = pgdir_walk(boot_pgdir, va, 1);
801 pte_t *p = (pte_t*COUNT(NPTENTRIES))KADDR(PTE_ADDR(boot_pgdir[PDX(va)]));
802 assert(p2 == &p[PTX(va)]);
805 boot_pgdir[PDX(va)] = 0;
809 // give free list back
810 for(int i=0; i<llc_cache->num_colors; i++)
811 colored_page_free_list[i] = fl[i];
813 // free the pages we took
818 cprintf("page_check() succeeded!\n");
823 // testing code for boot_pgdir_walk
825 temp = boot_pgdir_walk(pgdir, VPT + (VPT >> 10), 1);
826 cprintf("pgdir = %p\n", pgdir);
827 cprintf("test recursive walking pte_t* = %p\n", temp);
828 cprintf("test recursive walking entry = %p\n", PTE_ADDR(temp));
829 temp = boot_pgdir_walk(pgdir, 0xc0400000, 1);
830 cprintf("LA = 0xc0400000 = %p\n", temp);
831 temp = boot_pgdir_walk(pgdir, 0xc0400070, 1);
832 cprintf("LA = 0xc0400070 = %p\n", temp);
833 temp = boot_pgdir_walk(pgdir, 0xc0800000, 0);
834 cprintf("LA = 0xc0800000, no create = %p\n", temp);
835 temp = boot_pgdir_walk(pgdir, 0xc0600070, 1);
836 cprintf("LA = 0xc0600070 = %p\n", temp);
837 temp = boot_pgdir_walk(pgdir, 0xc0600090, 0);
838 cprintf("LA = 0xc0600090, nc = %p\n", temp);
839 temp = boot_pgdir_walk(pgdir, 0xc0608070, 0);
840 cprintf("LA = 0xc0608070, nc = %p\n", temp);
841 temp = boot_pgdir_walk(pgdir, 0xc0800070, 1);
842 cprintf("LA = 0xc0800070 = %p\n", temp);
843 temp = boot_pgdir_walk(pgdir, 0xc0b00070, 0);
844 cprintf("LA = 0xc0b00070, nc = %p\n", temp);
845 temp = boot_pgdir_walk(pgdir, 0xc0c00000, 0);
846 cprintf("LA = 0xc0c00000, nc = %p\n", temp);
848 // testing for boot_map_seg
850 cprintf("before mapping 1 page to 0x00350000\n");
851 cprintf("0xc4000000's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xc4000000, 1));
852 cprintf("0xc4000000's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xc4000000, 1)));
853 boot_map_segment(pgdir, 0xc4000000, 4096, 0x00350000, PTE_W);
854 cprintf("after mapping\n");
855 cprintf("0xc4000000's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xc4000000, 1));
856 cprintf("0xc4000000's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xc4000000, 1)));
859 cprintf("before mapping 3 pages to 0x00700000\n");
860 cprintf("0xd0000000's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xd0000000, 1));
861 cprintf("0xd0000000's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xd0000000, 1)));
862 cprintf("0xd0001000's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xd0001000, 1));
863 cprintf("0xd0001000's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xd0001000, 1)));
864 cprintf("0xd0002000's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xd0002000, 1));
865 cprintf("0xd0002000's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xd0002000, 1)));
866 boot_map_segment(pgdir, 0xd0000000, 4096*3, 0x00700000, 0);
867 cprintf("after mapping\n");
868 cprintf("0xd0000000's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xd0000000, 1));
869 cprintf("0xd0000000's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xd0000000, 1)));
870 cprintf("0xd0001000's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xd0001000, 1));
871 cprintf("0xd0001000's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xd0001000, 1)));
872 cprintf("0xd0002000's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xd0002000, 1));
873 cprintf("0xd0002000's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xd0002000, 1)));
876 cprintf("before mapping 1 unaligned to 0x00500010\n");
877 cprintf("0xc8000010's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xc8000010, 1));
878 cprintf("0xc8000010's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xc8000010, 1)));
879 cprintf("0xc8001010's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xc8001010, 1));
880 cprintf("0xc8001010's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xc8001010, 1)));
881 boot_map_segment(pgdir, 0xc8000010, 4096, 0x00500010, PTE_W);
882 cprintf("after mapping\n");
883 cprintf("0xc8000010's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xc8000010, 1));
884 cprintf("0xc8000010's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xc8000010, 1)));
885 cprintf("0xc8001010's &pte: %08x\n",boot_pgdir_walk(pgdir, 0xc8001010, 1));
886 cprintf("0xc8001010's pte: %08x\n",*(boot_pgdir_walk(pgdir, 0xc8001010, 1)));
889 boot_map_segment(pgdir, 0xe0000000, 4096, 0x10000000, PTE_W);