Fixes x86 LAPIC_ISR/IRR reading
[akaros.git] / kern / arch / i686 / apic.h
1 /*
2  * Copyright (c) 2009 The Regents of the University of California
3  * Barret Rhoden <brho@cs.berkeley.edu>
4  * See LICENSE for details.
5  */
6
7 #ifndef ROS_KERN_APIC_H
8 #define ROS_KERN_APIC_H
9
10 /* 
11  * Functions and definitions for dealing with the APIC and PIC, specific to
12  * Intel.  Does not handle an x2APIC.
13  */
14
15 #include <arch/mmu.h>
16 #include <arch/x86.h>
17 #include <arch/ioapic.h>
18
19 /* PIC (8259A)
20  * When looking at the specs, A0 is our CMD line, and A1 is the DATA line.  This
21  * means that blindly writing to PIC1_DATA is an OCW1 (interrupt masks).  When
22  * writing to CMD (A0), the chip can determine betweeb OCW2 and OCW3 by the
23  * setting of a few specific bits (OCW2 has bit 3 unset, OCW3 has it set). */
24 #define PIC1_CMD                                        0x20
25 #define PIC1_DATA                                       0x21
26 #define PIC2_CMD                                        0xA0
27 #define PIC2_DATA                                       0xA1
28 // These are also hardcoded into the IRQ_HANDLERs of kern/trapentry.S
29 #define PIC1_OFFSET                                     0x20
30 #define PIC2_OFFSET                                     0x28
31 #define PIC1_SPURIOUS                           (7 + PIC1_OFFSET)
32 #define PIC2_SPURIOUS                           (7 + PIC2_OFFSET)
33 #define PIC_EOI                                         0x20    /* OCW2 EOI */
34 /* These set the next CMD read to return specific values.  Note that the chip
35  * remembers what setting we had before (IRR or ISR), if you do other reads of
36  * CMD. (not tested, written in the spec sheet) */
37 #define PIC_READ_IRR                            0x0a    /* OCW3 irq ready next CMD read */
38 #define PIC_READ_ISR                            0x0b    /* OCW3 irq service next CMD read */
39
40 // Local APIC
41 /* PBASE is the physical address.  It is mapped in at the VADDR LAPIC_BASE */
42 #define LAPIC_PBASE                                     0xfee00000 /* default *physical* address */
43 #define LAPIC_EOI                                       (LAPIC_BASE + 0x0b0)
44 #define LAPIC_SPURIOUS                          (LAPIC_BASE + 0x0f0)
45 #define LAPIC_VERSION                           (LAPIC_BASE + 0x030)
46 #define LAPIC_ERROR                                     (LAPIC_BASE + 0x280)
47 #define LAPIC_ID                                        (LAPIC_BASE + 0x020)
48 #define LAPIC_LOGICAL_ID                        (LAPIC_BASE + 0x0d0)
49 // LAPIC Local Vector Table
50 #define LAPIC_LVT_TIMER                         (LAPIC_BASE + 0x320)
51 #define LAPIC_LVT_LINT0                         (LAPIC_BASE + 0x350)
52 #define LAPIC_LVT_LINT1                         (LAPIC_BASE + 0x360)
53 #define LAPIC_LVT_ERROR                         (LAPIC_BASE + 0x370)
54 #define LAPIC_LVT_PERFMON                       (LAPIC_BASE + 0x340)
55 #define LAPIC_LVT_THERMAL                       (LAPIC_BASE + 0x330)
56 #define LAPIC_LVT_MASK                          0x00010000
57 // LAPIC Timer
58 #define LAPIC_TIMER_INIT                        (LAPIC_BASE + 0x380)
59 #define LAPIC_TIMER_CURRENT                     (LAPIC_BASE + 0x390)
60 #define LAPIC_TIMER_DIVIDE                      (LAPIC_BASE + 0x3e0)
61 #define LAPIC_TIMER_DEFAULT_VECTOR      0xeb            /* Aka 235, IRQ203 */
62 #define LAPIC_TIMER_DEFAULT_DIVISOR     0xa // This is 128.  Ref SDM 3.a 9.6.4
63 // IPI Interrupt Command Register
64 #define LAPIC_IPI_ICR_LOWER                     (LAPIC_BASE + 0x300)
65 #define LAPIC_IPI_ICR_UPPER                     (LAPIC_BASE + 0x310)
66 /* Interrupts being serviced (in-service) and pending (interrupt request reg).
67  * Note these registers are not normal bitmaps, but instead are 8 separate
68  * 32-bit registers, spaced/aligned on 16 byte boundaries in the LAPIC address
69  * space. */
70 #define LAPIC_ISR                                       (LAPIC_BASE + 0x100)
71 #define LAPIC_IRR                                       (LAPIC_BASE + 0x200)
72
73 // PIT (Programmable Interval Timer)
74 #define TIMER_REG_CNTR0 0       /* timer 0 counter port */
75 #define TIMER_REG_CNTR1 1       /* timer 1 counter port */
76 #define TIMER_REG_CNTR2 2       /* timer 2 counter port */
77 #define TIMER_REG_MODE  3       /* timer mode port */
78 #define TIMER_SEL0      0x00    /* select counter 0 */
79 #define TIMER_SEL1      0x40    /* select counter 1 */
80 #define TIMER_SEL2      0x80    /* select counter 2 */
81 #define TIMER_INTTC     0x00    /* mode 0, intr on terminal cnt */
82 #define TIMER_ONESHOT   0x02    /* mode 1, one shot */
83 #define TIMER_RATEGEN   0x04    /* mode 2, rate generator */
84 #define TIMER_SQWAVE    0x06    /* mode 3, square wave */
85 #define TIMER_SWSTROBE  0x08    /* mode 4, s/w triggered strobe */
86 #define TIMER_HWSTROBE  0x0a    /* mode 5, h/w triggered strobe */
87 #define TIMER_LATCH     0x00    /* latch counter for reading */
88 #define TIMER_LSB       0x10    /* r/w counter LSB */
89 #define TIMER_MSB       0x20    /* r/w counter MSB */
90 #define TIMER_16BIT     0x30    /* r/w counter 16 bits, LSB first */
91 #define TIMER_BCD       0x01    /* count in BCD */
92
93 #define PIT_FREQ                                        1193182
94
95 #define IO_TIMER1   0x40        /* 8253 Timer #1 */
96 #define TIMER_CNTR0 (IO_TIMER1 + TIMER_REG_CNTR0)
97 #define TIMER_CNTR1 (IO_TIMER1 + TIMER_REG_CNTR1)
98 #define TIMER_CNTR2 (IO_TIMER1 + TIMER_REG_CNTR2)
99 #define TIMER_MODE  (IO_TIMER1 + TIMER_REG_MODE)
100
101 typedef struct system_timing {
102         uint64_t tsc_freq;
103         uint64_t bus_freq;
104         uint16_t pit_divisor;
105         uint8_t pit_mode;
106 } system_timing_t;
107
108 extern system_timing_t system_timing;
109
110 void pic_remap(void);
111 void pic_mask_irq(uint8_t irq);
112 void pic_unmask_irq(uint8_t irq);
113 uint16_t pic_get_mask(void);
114 uint16_t pic_get_irr(void);
115 uint16_t pic_get_isr(void);
116 bool lapic_get_isr_bit(uint8_t vector);
117 bool lapic_get_irr_bit(uint8_t vector);
118 void lapic_print_isr(void);
119 bool ipi_is_pending(uint8_t vector);
120 void __lapic_set_timer(uint32_t ticks, uint8_t vec, bool periodic, uint8_t div);
121 void lapic_set_timer(uint32_t usec, bool periodic);
122 uint32_t lapic_get_default_id(void);
123 // PIT related
124 void pit_set_timer(uint32_t freq, uint32_t mode);
125 void timer_init(void);
126 void udelay_pit(uint64_t usec);
127 // TODO: right now timer defaults to TSC
128 uint64_t gettimer(void);
129 uint64_t getfreq(void);
130
131 static inline void pic_send_eoi(uint32_t irq);
132 static inline void lapic_send_eoi(void);
133 static inline uint32_t lapic_get_version(void);
134 static inline uint32_t lapic_get_error(void);
135 static inline uint32_t lapic_get_id(void);
136 static inline void lapic_set_id(uint8_t id); // Careful, may not actually work
137 static inline uint8_t lapic_get_logid(void);
138 static inline void lapic_set_logid(uint8_t id);
139 static inline void lapic_disable_timer(void);
140 static inline void lapic_disable(void);
141 static inline void lapic_enable(void);
142 static inline void lapic_wait_to_send(void);
143 static inline void send_init_ipi(void);
144 static inline void send_startup_ipi(uint8_t vector);
145 static inline void send_self_ipi(uint8_t vector);
146 static inline void send_broadcast_ipi(uint8_t vector);
147 static inline void send_all_others_ipi(uint8_t vector);
148 static inline void send_ipi(uint8_t hw_coreid, uint8_t vector);
149 static inline void send_group_ipi(uint8_t hw_groupid, uint8_t vector);
150 static inline void __send_nmi(uint8_t os_coreid);
151
152 #define mask_lapic_lvt(entry) \
153         write_mmreg32(entry, read_mmreg32(entry) | LAPIC_LVT_MASK)
154 #define unmask_lapic_lvt(entry) \
155         write_mmreg32(entry, read_mmreg32(entry) & ~LAPIC_LVT_MASK)
156
157 static inline void pic_send_eoi(uint32_t irq)
158 {
159         // all irqs beyond the first seven need to be chained to the slave
160         if (irq > 7)
161                 outb(PIC2_CMD, PIC_EOI);
162         outb(PIC1_CMD, PIC_EOI);
163 }
164
165 static inline void lapic_send_eoi(void)
166 {
167         write_mmreg32(LAPIC_EOI, 0);
168 }
169
170 static inline uint32_t lapic_get_version(void)
171 {
172         return read_mmreg32(LAPIC_VERSION);     
173 }
174
175 static inline uint32_t lapic_get_error(void)
176 {
177         write_mmreg32(LAPIC_ERROR, 0xdeadbeef);
178         return read_mmreg32(LAPIC_ERROR);
179 }
180
181 static inline uint32_t lapic_get_id(void)
182 {
183         return read_mmreg32(LAPIC_ID) >> 24;
184 }
185
186 static inline void lapic_set_id(uint8_t id)
187 {
188         write_mmreg32(LAPIC_ID, id << 24);
189 }
190
191 static inline uint8_t lapic_get_logid(void)
192 {
193         return read_mmreg32(LAPIC_LOGICAL_ID) >> 24;
194 }
195
196 static inline void lapic_set_logid(uint8_t id)
197 {
198         write_mmreg32(LAPIC_LOGICAL_ID, id << 24);
199 }
200
201 static inline void lapic_disable_timer(void)
202 {
203         write_mmreg32(LAPIC_LVT_TIMER, 0);
204 }
205
206 /* There are a couple ways to do it.  The MSR route doesn't seem to work
207  * in KVM.  It's also a somewhat permanent thing
208  */
209 static inline void lapic_disable(void)
210 {
211         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) & 0xffffefff);
212         //write_msr(IA32_APIC_BASE, read_msr(IA32_APIC_BASE) & ~MSR_APIC_ENABLE);
213 }
214
215 /* Spins until previous IPIs are delivered.  Not sure if we want it inlined
216  * Also not sure when we really need to do this. 
217  */
218 static inline void lapic_wait_to_send(void)
219 {
220         while(read_mmreg32(LAPIC_IPI_ICR_LOWER) & 0x1000)
221                 __cpu_relax();
222 }
223
224 static inline void lapic_enable(void)
225 {
226         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) | 0x00000100);
227 }
228
229 static inline void send_init_ipi(void)
230 {
231         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4500);
232         lapic_wait_to_send();
233 }
234
235 static inline void send_startup_ipi(uint8_t vector)
236 {
237         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4600 | vector);
238         lapic_wait_to_send();
239 }
240
241 static inline void send_self_ipi(uint8_t vector)
242 {
243         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00044000 | vector);
244         lapic_wait_to_send();
245 }
246
247 static inline void send_broadcast_ipi(uint8_t vector)
248 {
249         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00084000 | vector);
250         lapic_wait_to_send();
251 }
252
253 static inline void send_all_others_ipi(uint8_t vector)
254 {
255         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4000 | vector);
256         lapic_wait_to_send();
257 }
258
259 static inline void __send_ipi(uint8_t hw_coreid, uint8_t vector)
260 {
261         write_mmreg32(LAPIC_IPI_ICR_UPPER, hw_coreid << 24);
262         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004000 | vector);
263         lapic_wait_to_send();
264 }
265
266 static inline void send_ipi(uint8_t hw_coreid, uint8_t vector)
267 {
268         /* 255 is a broadcast, which should use send_broadcast_ipi, and it is also
269          * what would come in if you tried sending an IPI to an os_coreid that
270          * doesn't exist (since they are initialized to -1). */
271         if (hw_coreid == 255)
272                 return;
273         __send_ipi(hw_coreid, vector);
274 }
275
276 static inline void send_group_ipi(uint8_t hw_groupid, uint8_t vector)
277 {
278         write_mmreg32(LAPIC_IPI_ICR_UPPER, hw_groupid << 24);
279         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004800 | vector);
280         lapic_wait_to_send();
281 }
282
283 static inline void __send_nmi(uint8_t hw_coreid)
284 {
285         if (hw_coreid == 255)
286                 return;
287         write_mmreg32(LAPIC_IPI_ICR_UPPER, hw_coreid << 24);
288         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004400);
289         lapic_wait_to_send();
290 }
291
292 /* To change the LAPIC Base (not recommended):
293         msr_val = read_msr(IA32_APIC_BASE);
294         msr_val = msr_val & ~MSR_APIC_BASE_ADDRESS | 0xfaa00000;
295         write_msr(IA32_APIC_BASE, msr_val);
296 */
297 #endif /* ROS_KERN_APIC_H */