1d439856ebece9eba9f3be9daad0cf0b821dd444
[akaros.git] / kern / arch / i686 / apic.h
1 /*
2  * Copyright (c) 2009 The Regents of the University of California
3  * Barret Rhoden <brho@cs.berkeley.edu>
4  * See LICENSE for details.
5  */
6
7 #ifndef ROS_KERN_APIC_H
8 #define ROS_KERN_APIC_H
9
10 /* 
11  * Functions and definitions for dealing with the APIC and PIC, specific to
12  * Intel.  Does not handle an x2APIC.
13  */
14
15 #include <arch/mmu.h>
16 #include <arch/x86.h>
17 #include <arch/ioapic.h>
18
19 /* PIC (8259A)
20  * When looking at the specs, A0 is our CMD line, and A1 is the DATA line.  This
21  * means that blindly writing to PIC1_DATA is an OCW1 (interrupt masks).  When
22  * writing to CMD (A0), the chip can determine betweeb OCW2 and OCW3 by the
23  * setting of a few specific bits (OCW2 has bit 3 unset, OCW3 has it set). */
24 #define PIC1_CMD                                        0x20
25 #define PIC1_DATA                                       0x21
26 #define PIC2_CMD                                        0xA0
27 #define PIC2_DATA                                       0xA1
28 // These are also hardcoded into the IRQ_HANDLERs of kern/trapentry.S
29 #define PIC1_OFFSET                                     0x20
30 #define PIC2_OFFSET                                     0x28
31 #define PIC_EOI                                         0x20    /* OCW2 EOI */
32 /* These set the next CMD read to return specific values.  Note that the chip
33  * remembers what setting we had before (IRR or ISR), if you do other reads of
34  * CMD. (not tested, written in the spec sheet) */
35 #define PIC_READ_IRR                            0x0a    /* OCW3 irq ready next CMD read */
36 #define PIC_READ_ISR                            0x0b    /* OCW3 irq service next CMD read */
37
38 // Local APIC
39 /* PBASE is the physical address.  It is mapped in at the VADDR LAPIC_BASE */
40 #define LAPIC_PBASE                                     0xfee00000 /* default *physical* address */
41 #define LAPIC_EOI                                       (LAPIC_BASE + 0x0b0)
42 #define LAPIC_SPURIOUS                          (LAPIC_BASE + 0x0f0)
43 #define LAPIC_VERSION                           (LAPIC_BASE + 0x030)
44 #define LAPIC_ERROR                                     (LAPIC_BASE + 0x280)
45 #define LAPIC_ID                                        (LAPIC_BASE + 0x020)
46 #define LAPIC_LOGICAL_ID                        (LAPIC_BASE + 0x0d0)
47 // LAPIC Local Vector Table
48 #define LAPIC_LVT_TIMER                         (LAPIC_BASE + 0x320)
49 #define LAPIC_LVT_LINT0                         (LAPIC_BASE + 0x350)
50 #define LAPIC_LVT_LINT1                         (LAPIC_BASE + 0x360)
51 #define LAPIC_LVT_ERROR                         (LAPIC_BASE + 0x370)
52 #define LAPIC_LVT_PERFMON                       (LAPIC_BASE + 0x340)
53 #define LAPIC_LVT_THERMAL                       (LAPIC_BASE + 0x330)
54 #define LAPIC_LVT_MASK                          0x00010000
55 // LAPIC Timer
56 #define LAPIC_TIMER_INIT                        (LAPIC_BASE + 0x380)
57 #define LAPIC_TIMER_CURRENT                     (LAPIC_BASE + 0x390)
58 #define LAPIC_TIMER_DIVIDE                      (LAPIC_BASE + 0x3e0)
59 #define LAPIC_TIMER_DEFAULT_VECTOR      0xeb            /* Aka 235, IRQ203 */
60 #define LAPIC_TIMER_DEFAULT_DIVISOR     0xa // This is 128.  Ref SDM 3.a 9.6.4
61 // IPI Interrupt Command Register
62 #define LAPIC_IPI_ICR_LOWER                     (LAPIC_BASE + 0x300)
63 #define LAPIC_IPI_ICR_UPPER                     (LAPIC_BASE + 0x310)
64 // Interrupts being serviced (in-service) and pending (interrupt request reg)
65 #define LAPIC_ISR                                       (LAPIC_BASE + 0x170)
66 #define LAPIC_IRR                                       (LAPIC_BASE + 0x310)
67
68 // PIT (Programmable Interval Timer)
69 #define TIMER_REG_CNTR0 0       /* timer 0 counter port */
70 #define TIMER_REG_CNTR1 1       /* timer 1 counter port */
71 #define TIMER_REG_CNTR2 2       /* timer 2 counter port */
72 #define TIMER_REG_MODE  3       /* timer mode port */
73 #define TIMER_SEL0      0x00    /* select counter 0 */
74 #define TIMER_SEL1      0x40    /* select counter 1 */
75 #define TIMER_SEL2      0x80    /* select counter 2 */
76 #define TIMER_INTTC     0x00    /* mode 0, intr on terminal cnt */
77 #define TIMER_ONESHOT   0x02    /* mode 1, one shot */
78 #define TIMER_RATEGEN   0x04    /* mode 2, rate generator */
79 #define TIMER_SQWAVE    0x06    /* mode 3, square wave */
80 #define TIMER_SWSTROBE  0x08    /* mode 4, s/w triggered strobe */
81 #define TIMER_HWSTROBE  0x0a    /* mode 5, h/w triggered strobe */
82 #define TIMER_LATCH     0x00    /* latch counter for reading */
83 #define TIMER_LSB       0x10    /* r/w counter LSB */
84 #define TIMER_MSB       0x20    /* r/w counter MSB */
85 #define TIMER_16BIT     0x30    /* r/w counter 16 bits, LSB first */
86 #define TIMER_BCD       0x01    /* count in BCD */
87
88 #define PIT_FREQ                                        1193182
89
90 #define IO_TIMER1   0x40        /* 8253 Timer #1 */
91 #define TIMER_CNTR0 (IO_TIMER1 + TIMER_REG_CNTR0)
92 #define TIMER_CNTR1 (IO_TIMER1 + TIMER_REG_CNTR1)
93 #define TIMER_CNTR2 (IO_TIMER1 + TIMER_REG_CNTR2)
94 #define TIMER_MODE  (IO_TIMER1 + TIMER_REG_MODE)
95
96 typedef struct system_timing {
97         uint64_t tsc_freq;
98         uint64_t bus_freq;
99         uint16_t pit_divisor;
100         uint8_t pit_mode;
101 } system_timing_t;
102
103 extern system_timing_t system_timing;
104
105 void pic_remap(void);
106 void pic_mask_irq(uint8_t irq);
107 void pic_unmask_irq(uint8_t irq);
108 uint16_t pic_get_mask(void);
109 uint16_t pic_get_irr(void);
110 uint16_t pic_get_isr(void);
111 void __lapic_set_timer(uint32_t ticks, uint8_t vec, bool periodic, uint8_t div);
112 void lapic_set_timer(uint32_t usec, bool periodic);
113 uint32_t lapic_get_default_id(void);
114 // PIT related
115 void pit_set_timer(uint32_t freq, uint32_t mode);
116 void timer_init(void);
117 void udelay_pit(uint64_t usec);
118 // TODO: right now timer defaults to TSC
119 uint64_t gettimer(void);
120 uint64_t getfreq(void);
121
122 static inline void pic_send_eoi(uint32_t irq);
123 static inline void lapic_send_eoi(void);
124 static inline uint32_t lapic_get_version(void);
125 static inline uint32_t lapic_get_error(void);
126 static inline uint32_t lapic_get_id(void);
127 static inline void lapic_set_id(uint8_t id); // Careful, may not actually work
128 static inline uint8_t lapic_get_logid(void);
129 static inline void lapic_set_logid(uint8_t id);
130 static inline void lapic_disable_timer(void);
131 static inline void lapic_disable(void);
132 static inline void lapic_enable(void);
133 static inline void lapic_wait_to_send(void);
134 static inline void send_init_ipi(void);
135 static inline void send_startup_ipi(uint8_t vector);
136 static inline void send_self_ipi(uint8_t vector);
137 static inline void send_broadcast_ipi(uint8_t vector);
138 static inline void send_all_others_ipi(uint8_t vector);
139 static inline void send_ipi(uint8_t hw_coreid, uint8_t vector);
140 static inline void send_group_ipi(uint8_t hw_groupid, uint8_t vector);
141 static inline void __send_nmi(uint8_t os_coreid);
142 static inline bool ipi_is_pending(uint8_t vector);
143
144 #define mask_lapic_lvt(entry) \
145         write_mmreg32(entry, read_mmreg32(entry) | LAPIC_LVT_MASK)
146 #define unmask_lapic_lvt(entry) \
147         write_mmreg32(entry, read_mmreg32(entry) & ~LAPIC_LVT_MASK)
148
149 static inline void pic_send_eoi(uint32_t irq)
150 {
151         // all irqs beyond the first seven need to be chained to the slave
152         if (irq > 7)
153                 outb(PIC2_CMD, PIC_EOI);
154         outb(PIC1_CMD, PIC_EOI);
155 }
156
157 static inline void lapic_send_eoi(void)
158 {
159         write_mmreg32(LAPIC_EOI, 0);
160 }
161
162 static inline uint32_t lapic_get_version(void)
163 {
164         return read_mmreg32(LAPIC_VERSION);     
165 }
166
167 static inline uint32_t lapic_get_error(void)
168 {
169         write_mmreg32(LAPIC_ERROR, 0xdeadbeef);
170         return read_mmreg32(LAPIC_ERROR);
171 }
172
173 static inline uint32_t lapic_get_id(void)
174 {
175         return read_mmreg32(LAPIC_ID) >> 24;
176 }
177
178 static inline void lapic_set_id(uint8_t id)
179 {
180         write_mmreg32(LAPIC_ID, id << 24);
181 }
182
183 static inline uint8_t lapic_get_logid(void)
184 {
185         return read_mmreg32(LAPIC_LOGICAL_ID) >> 24;
186 }
187
188 static inline void lapic_set_logid(uint8_t id)
189 {
190         write_mmreg32(LAPIC_LOGICAL_ID, id << 24);
191 }
192
193 static inline void lapic_disable_timer(void)
194 {
195         write_mmreg32(LAPIC_LVT_TIMER, 0);
196 }
197
198 /* There are a couple ways to do it.  The MSR route doesn't seem to work
199  * in KVM.  It's also a somewhat permanent thing
200  */
201 static inline void lapic_disable(void)
202 {
203         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) & 0xffffefff);
204         //write_msr(IA32_APIC_BASE, read_msr(IA32_APIC_BASE) & ~MSR_APIC_ENABLE);
205 }
206
207 /* Spins until previous IPIs are delivered.  Not sure if we want it inlined
208  * Also not sure when we really need to do this. 
209  */
210 static inline void lapic_wait_to_send(void)
211 {
212         while(read_mmreg32(LAPIC_IPI_ICR_LOWER) & 0x1000)
213                 __cpu_relax();
214 }
215
216 static inline void lapic_enable(void)
217 {
218         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) | 0x00000100);
219 }
220
221 static inline void send_init_ipi(void)
222 {
223         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4500);
224         lapic_wait_to_send();
225 }
226
227 static inline void send_startup_ipi(uint8_t vector)
228 {
229         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4600 | vector);
230         lapic_wait_to_send();
231 }
232
233 static inline void send_self_ipi(uint8_t vector)
234 {
235         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00044000 | vector);
236         lapic_wait_to_send();
237 }
238
239 static inline void send_broadcast_ipi(uint8_t vector)
240 {
241         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00084000 | vector);
242         lapic_wait_to_send();
243 }
244
245 static inline void send_all_others_ipi(uint8_t vector)
246 {
247         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4000 | vector);
248         lapic_wait_to_send();
249 }
250
251 static inline void __send_ipi(uint8_t hw_coreid, uint8_t vector)
252 {
253         write_mmreg32(LAPIC_IPI_ICR_UPPER, hw_coreid << 24);
254         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004000 | vector);
255         lapic_wait_to_send();
256 }
257
258 static inline void send_ipi(uint8_t hw_coreid, uint8_t vector)
259 {
260         /* 255 is a broadcast, which should use send_broadcast_ipi, and it is also
261          * what would come in if you tried sending an IPI to an os_coreid that
262          * doesn't exist (since they are initialized to -1). */
263         if (hw_coreid == 255)
264                 return;
265         __send_ipi(hw_coreid, vector);
266 }
267
268 static inline void send_group_ipi(uint8_t hw_groupid, uint8_t vector)
269 {
270         write_mmreg32(LAPIC_IPI_ICR_UPPER, hw_groupid << 24);
271         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004800 | vector);
272         lapic_wait_to_send();
273 }
274
275 static inline void __send_nmi(uint8_t hw_coreid)
276 {
277         if (hw_coreid == 255)
278                 return;
279         write_mmreg32(LAPIC_IPI_ICR_UPPER, hw_coreid << 24);
280         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004400);
281         lapic_wait_to_send();
282 }
283
284 /* This works for any interrupt that goes through the LAPIC, but not things like
285  * ExtInts.  To prevent abuse, we'll use it just for IPIs for now. */
286 static inline bool ipi_is_pending(uint8_t vector)
287 {
288         /* TODO: look at this, it's so fucked up.  also, there's a bit that needs to
289          * be set to allow us to read from the IRR. */
290         return (LAPIC_ISR & vector) || (LAPIC_IRR & vector);
291 }
292
293 /* To change the LAPIC Base (not recommended):
294         msr_val = read_msr(IA32_APIC_BASE);
295         msr_val = msr_val & ~MSR_APIC_BASE_ADDRESS | 0xfaa00000;
296         write_msr(IA32_APIC_BASE, msr_val);
297 */
298 #endif /* ROS_KERN_APIC_H */