Merge branch 'net-dev'. See body of commit for details.
[akaros.git] / kern / arch / i386 / apic.h
1 /*
2  * Copyright (c) 2009 The Regents of the University of California
3  * Barret Rhoden <brho@cs.berkeley.edu>
4  * See LICENSE for details.
5  */
6
7 #ifndef ROS_KERN_APIC_H
8 #define ROS_KERN_APIC_H
9
10 /* 
11  * Functions and definitions for dealing with the APIC and PIC, specific to
12  * Intel.  Does not handle an x2APIC.
13  */
14
15 #include <arch/mmu.h>
16 #include <arch/x86.h>
17 #include <arch/ioapic.h>
18
19 // PIC
20 #define PIC1_CMD                                        0x20
21 #define PIC1_DATA                                       0x21
22 #define PIC2_CMD                                        0xA0
23 #define PIC2_DATA                                       0xA1
24 // These are also hardcoded into the IRQ_HANDLERs of kern/trapentry.S
25 #define PIC1_OFFSET                                     0x20
26 #define PIC2_OFFSET                                     0x28
27 #define PIC_EOI                                         0x20
28
29 // Local APIC
30 #define LAPIC_BASE                                      0xfee00000 // this is the default, can be changed
31 #define LAPIC_EOI                                       (LAPIC_BASE + 0x0b0)
32 #define LAPIC_SPURIOUS                          (LAPIC_BASE + 0x0f0)
33 #define LAPIC_VERSION                           (LAPIC_BASE + 0x030)
34 #define LAPIC_ERROR                                     (LAPIC_BASE + 0x280)
35 #define LAPIC_ID                                        (LAPIC_BASE + 0x020)
36 #define LAPIC_LOGICAL_ID                        (LAPIC_BASE + 0x0d0)
37 // LAPIC Local Vector Table
38 #define LAPIC_LVT_TIMER                         (LAPIC_BASE + 0x320)
39 #define LAPIC_LVT_LINT0                         (LAPIC_BASE + 0x350)
40 #define LAPIC_LVT_LINT1                         (LAPIC_BASE + 0x360)
41 #define LAPIC_LVT_ERROR                         (LAPIC_BASE + 0x370)
42 #define LAPIC_LVT_PERFMON                       (LAPIC_BASE + 0x340)
43 #define LAPIC_LVT_THERMAL                       (LAPIC_BASE + 0x330)
44 #define LAPIC_LVT_MASK                          0x00010000
45 // LAPIC Timer
46 #define LAPIC_TIMER_INIT                        (LAPIC_BASE + 0x380)
47 #define LAPIC_TIMER_CURRENT                     (LAPIC_BASE + 0x390)
48 #define LAPIC_TIMER_DIVIDE                      (LAPIC_BASE + 0x3e0)
49 #define LAPIC_TIMER_DEFAULT_VECTOR      0xeb
50 #define LAPIC_TIMER_DEFAULT_DIVISOR     0xa // This is 128.  Ref SDM 3.a 9.6.4
51 // IPI Interrupt Command Register
52 #define LAPIC_IPI_ICR_LOWER                     (LAPIC_BASE + 0x300)
53 #define LAPIC_IPI_ICR_UPPER                     (LAPIC_BASE + 0x310)
54
55 // PIT (Programmable Interval Timer)
56 #define TIMER_REG_CNTR0 0       /* timer 0 counter port */
57 #define TIMER_REG_CNTR1 1       /* timer 1 counter port */
58 #define TIMER_REG_CNTR2 2       /* timer 2 counter port */
59 #define TIMER_REG_MODE  3       /* timer mode port */
60 #define TIMER_SEL0      0x00    /* select counter 0 */
61 #define TIMER_SEL1      0x40    /* select counter 1 */
62 #define TIMER_SEL2      0x80    /* select counter 2 */
63 #define TIMER_INTTC     0x00    /* mode 0, intr on terminal cnt */
64 #define TIMER_ONESHOT   0x02    /* mode 1, one shot */
65 #define TIMER_RATEGEN   0x04    /* mode 2, rate generator */
66 #define TIMER_SQWAVE    0x06    /* mode 3, square wave */
67 #define TIMER_SWSTROBE  0x08    /* mode 4, s/w triggered strobe */
68 #define TIMER_HWSTROBE  0x0a    /* mode 5, h/w triggered strobe */
69 #define TIMER_LATCH     0x00    /* latch counter for reading */
70 #define TIMER_LSB       0x10    /* r/w counter LSB */
71 #define TIMER_MSB       0x20    /* r/w counter MSB */
72 #define TIMER_16BIT     0x30    /* r/w counter 16 bits, LSB first */
73 #define TIMER_BCD       0x01    /* count in BCD */
74
75 #define PIT_FREQ                                        1193182
76
77 #define IO_TIMER1   0x40        /* 8253 Timer #1 */
78 #define TIMER_CNTR0 (IO_TIMER1 + TIMER_REG_CNTR0)
79 #define TIMER_CNTR1 (IO_TIMER1 + TIMER_REG_CNTR1)
80 #define TIMER_CNTR2 (IO_TIMER1 + TIMER_REG_CNTR2)
81 #define TIMER_MODE  (IO_TIMER1 + TIMER_REG_MODE)
82
83 typedef struct system_timing {
84         uint64_t tsc_freq;
85         uint64_t bus_freq;
86         uint16_t pit_divisor;
87         uint8_t pit_mode;
88 } system_timing_t;
89
90 extern system_timing_t system_timing;
91
92 void pic_remap(void);
93 void pic_mask_irq(uint8_t irq);
94 void pic_unmask_irq(uint8_t irq);
95 void __lapic_set_timer(uint32_t ticks, uint8_t vec, bool periodic, uint8_t div);
96 void lapic_set_timer(uint32_t usec, bool periodic);
97 uint32_t lapic_get_default_id(void);
98 // PIT related
99 void pit_set_timer(uint32_t freq, uint32_t mode);
100 void timer_init(void);
101 void udelay_pit(uint64_t usec);
102 // TODO: right now timer defaults to TSC
103 uint64_t gettimer(void);
104 uint64_t getfreq(void);
105
106 static inline void pic_send_eoi(uint32_t irq);
107 static inline void lapic_send_eoi(void);
108 static inline uint32_t lapic_get_version(void);
109 static inline uint32_t lapic_get_error(void);
110 static inline uint32_t lapic_get_id(void);
111 static inline void lapic_set_id(uint8_t id); // Careful, may not actually work
112 static inline uint8_t lapic_get_logid(void);
113 static inline void lapic_set_logid(uint8_t id);
114 static inline void lapic_disable(void);
115 static inline void lapic_enable(void);
116 static inline void lapic_wait_to_send(void);
117 static inline void send_init_ipi(void);
118 static inline void send_startup_ipi(uint8_t vector);
119 static inline void send_self_ipi(uint8_t vector);
120 static inline void send_broadcast_ipi(uint8_t vector);
121 static inline void send_all_others_ipi(uint8_t vector);
122 static inline void send_ipi(uint8_t dest, bool logical_mode, uint8_t vector);
123
124 #define mask_lapic_lvt(entry) \
125         write_mmreg32(entry, read_mmreg32(entry) | LAPIC_LVT_MASK)
126 #define unmask_lapic_lvt(entry) \
127         write_mmreg32(entry, read_mmreg32(entry) & ~LAPIC_LVT_MASK)
128
129 static inline void pic_send_eoi(uint32_t irq)
130 {
131         // all irqs beyond the first seven need to be chained to the slave
132         if (irq > 7)
133                 outb(PIC2_CMD, PIC_EOI);
134         outb(PIC1_CMD, PIC_EOI);
135 }
136
137 static inline void lapic_send_eoi(void)
138 {
139         write_mmreg32(LAPIC_EOI, 0);
140 }
141
142 static inline uint32_t lapic_get_version(void)
143 {
144         return read_mmreg32(LAPIC_VERSION);     
145 }
146
147 static inline uint32_t lapic_get_error(void)
148 {
149         write_mmreg32(LAPIC_ERROR, 0xdeadbeef);
150         return read_mmreg32(LAPIC_ERROR);
151 }
152
153 static inline uint32_t lapic_get_id(void)
154 {
155         return read_mmreg32(LAPIC_ID) >> 24;
156 }
157
158 static inline void lapic_set_id(uint8_t id)
159 {
160         write_mmreg32(LAPIC_ID, id << 24);
161 }
162
163 static inline uint8_t lapic_get_logid(void)
164 {
165         return read_mmreg32(LAPIC_LOGICAL_ID) >> 24;
166 }
167
168 static inline void lapic_set_logid(uint8_t id)
169 {
170         write_mmreg32(LAPIC_LOGICAL_ID, id << 24);
171 }
172
173 /* There are a couple ways to do it.  The MSR route doesn't seem to work
174  * in KVM.  It's also a somewhat permanent thing
175  */
176 static inline void lapic_disable(void)
177 {
178         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) & 0xffffefff);
179         //write_msr(IA32_APIC_BASE, read_msr(IA32_APIC_BASE) & ~MSR_APIC_ENABLE);
180 }
181
182 /* Spins until previous IPIs are delivered.  Not sure if we want it inlined
183  * Also not sure when we really need to do this. 
184  */
185 static inline void lapic_wait_to_send(void)
186 {
187         while(read_mmreg32(LAPIC_IPI_ICR_LOWER) & 0x1000)
188                 __cpu_relax();
189 }
190
191 static inline void lapic_enable(void)
192 {
193         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) | 0x00000100);
194 }
195
196 static inline void send_init_ipi(void)
197 {
198         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4500);
199 }
200
201 static inline void send_startup_ipi(uint8_t vector)
202 {
203         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4600 | vector);
204 }
205
206 static inline void send_self_ipi(uint8_t vector)
207 {
208         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00044000 | vector);
209 }
210
211 static inline void send_broadcast_ipi(uint8_t vector)
212 {
213         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00084000 | vector);
214 }
215
216 static inline void send_all_others_ipi(uint8_t vector)
217 {
218         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4000 | vector);
219 }
220
221 static inline void send_ipi(uint8_t dest, bool logical_mode, uint8_t vector)
222 {
223         write_mmreg32(LAPIC_IPI_ICR_UPPER, dest << 24);
224         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004000 | (logical_mode << 11) | vector);
225 }
226
227 /* To change the LAPIC Base (not recommended):
228         msr_val = read_msr(IA32_APIC_BASE);
229         msr_val = msr_val & ~MSR_APIC_BASE_ADDRESS | 0xfaa00000;
230         write_msr(IA32_APIC_BASE, msr_val);
231 */
232 #endif /* ROS_KERN_APIC_H */