2a5863fbfbf1aef2723b10220c3343440d61fc75
[akaros.git] / kern / arch / i386 / apic.h
1 /*
2  * Copyright (c) 2009 The Regents of the University of California
3  * Barret Rhoden <brho@cs.berkeley.edu>
4  * See LICENSE for details.
5  */
6
7 #ifndef ROS_KERN_APIC_H
8 #define ROS_KERN_APIC_H
9
10 /* 
11  * Functions and definitions for dealing with the APIC and PIC, specific to
12  * Intel.  Does not handle an x2APIC.
13  */
14
15 #include <arch/mmu.h>
16 #include <arch/x86.h>
17
18 // PIC
19 #define PIC1_CMD                                        0x20
20 #define PIC1_DATA                                       0x21
21 #define PIC2_CMD                                        0xA0
22 #define PIC2_DATA                                       0xA1
23 // These are also hardcoded into the IRQ_HANDLERs of kern/trapentry.S
24 #define PIC1_OFFSET                                     0x20
25 #define PIC2_OFFSET                                     0x28
26 #define PIC_EOI                                         0x20
27
28 // Local APIC
29 #define LAPIC_BASE                                      0xfee00000 // this is the default, can be changed
30 #define LAPIC_EOI                                       (LAPIC_BASE + 0x0b0)
31 #define LAPIC_SPURIOUS                          (LAPIC_BASE + 0x0f0)
32 #define LAPIC_VERSION                           (LAPIC_BASE + 0x030)
33 #define LAPIC_ERROR                                     (LAPIC_BASE + 0x280)
34 #define LAPIC_ID                                        (LAPIC_BASE + 0x020)
35 #define LAPIC_LOGICAL_ID                        (LAPIC_BASE + 0x0d0)
36 // LAPIC Local Vector Table
37 #define LAPIC_LVT_TIMER                         (LAPIC_BASE + 0x320)
38 #define LAPIC_LVT_LINT0                         (LAPIC_BASE + 0x350)
39 #define LAPIC_LVT_LINT1                         (LAPIC_BASE + 0x360)
40 #define LAPIC_LVT_ERROR                         (LAPIC_BASE + 0x370)
41 #define LAPIC_LVT_PERFMON                       (LAPIC_BASE + 0x340)
42 #define LAPIC_LVT_THERMAL                       (LAPIC_BASE + 0x330)
43 #define LAPIC_LVT_MASK                          0x00010000
44 // LAPIC Timer
45 #define LAPIC_TIMER_INIT                        (LAPIC_BASE + 0x380)
46 #define LAPIC_TIMER_CURRENT                     (LAPIC_BASE + 0x390)
47 #define LAPIC_TIMER_DIVIDE                      (LAPIC_BASE + 0x3e0)
48 #define LAPIC_TIMER_DEFAULT_VECTOR      0xeb
49 #define LAPIC_TIMER_DEFAULT_DIVISOR     0xa // This is 128.  Ref SDM 3.a 9.6.4
50 // IPI Interrupt Command Register
51 #define LAPIC_IPI_ICR_LOWER                     (LAPIC_BASE + 0x300)
52 #define LAPIC_IPI_ICR_UPPER                     (LAPIC_BASE + 0x310)
53
54 // IOAPIC
55 #define IOAPIC_BASE                                     0xfec00000 // this is the default, can be changed
56
57 // PIT (Programmable Interval Timer)
58 #define TIMER_REG_CNTR0 0       /* timer 0 counter port */
59 #define TIMER_REG_CNTR1 1       /* timer 1 counter port */
60 #define TIMER_REG_CNTR2 2       /* timer 2 counter port */
61 #define TIMER_REG_MODE  3       /* timer mode port */
62 #define TIMER_SEL0      0x00    /* select counter 0 */
63 #define TIMER_SEL1      0x40    /* select counter 1 */
64 #define TIMER_SEL2      0x80    /* select counter 2 */
65 #define TIMER_INTTC     0x00    /* mode 0, intr on terminal cnt */
66 #define TIMER_ONESHOT   0x02    /* mode 1, one shot */
67 #define TIMER_RATEGEN   0x04    /* mode 2, rate generator */
68 #define TIMER_SQWAVE    0x06    /* mode 3, square wave */
69 #define TIMER_SWSTROBE  0x08    /* mode 4, s/w triggered strobe */
70 #define TIMER_HWSTROBE  0x0a    /* mode 5, h/w triggered strobe */
71 #define TIMER_LATCH     0x00    /* latch counter for reading */
72 #define TIMER_LSB       0x10    /* r/w counter LSB */
73 #define TIMER_MSB       0x20    /* r/w counter MSB */
74 #define TIMER_16BIT     0x30    /* r/w counter 16 bits, LSB first */
75 #define TIMER_BCD       0x01    /* count in BCD */
76
77 #define PIT_FREQ                                        1193182
78
79 #define IO_TIMER1   0x40        /* 8253 Timer #1 */
80 #define TIMER_CNTR0 (IO_TIMER1 + TIMER_REG_CNTR0)
81 #define TIMER_CNTR1 (IO_TIMER1 + TIMER_REG_CNTR1)
82 #define TIMER_CNTR2 (IO_TIMER1 + TIMER_REG_CNTR2)
83 #define TIMER_MODE  (IO_TIMER1 + TIMER_REG_MODE)
84
85 typedef struct system_timing {
86         uint64_t tsc_freq;
87         uint64_t bus_freq;
88         uint16_t pit_divisor;
89         uint8_t pit_mode;
90 } system_timing_t;
91
92 extern system_timing_t system_timing;
93
94 void pic_remap(void);
95 void pic_mask_irq(uint8_t irq);
96 void pic_unmask_irq(uint8_t irq);
97 void __lapic_set_timer(uint32_t ticks, uint8_t vec, bool periodic, uint8_t div);
98 void lapic_set_timer(uint32_t usec, bool periodic);
99 uint32_t lapic_get_default_id(void);
100 // PIT related
101 void pit_set_timer(uint32_t freq, uint32_t mode);
102 void timer_init(void);
103 void udelay(uint64_t usec);
104 void udelay_pit(uint64_t usec);
105 // TODO: right now timer defaults to TSC
106 uint64_t gettimer(void);
107 uint64_t inline getfreq(void);
108
109 static inline void pic_send_eoi(uint32_t irq);
110 static inline void lapic_send_eoi(void);
111 static inline uint32_t lapic_get_version(void);
112 static inline uint32_t lapic_get_error(void);
113 static inline uint32_t lapic_get_id(void);
114 static inline void lapic_set_id(uint8_t id); // Careful, may not actually work
115 static inline uint8_t lapic_get_logid(void);
116 static inline void lapic_set_logid(uint8_t id);
117 static inline void lapic_disable(void);
118 static inline void lapic_enable(void);
119 static inline void lapic_wait_to_send(void);
120 static inline void send_init_ipi(void);
121 static inline void send_startup_ipi(uint8_t vector);
122 static inline void send_self_ipi(uint8_t vector);
123 static inline void send_broadcast_ipi(uint8_t vector);
124 static inline void send_all_others_ipi(uint8_t vector);
125 static inline void send_ipi(uint8_t dest, bool logical_mode, uint8_t vector);
126
127 #define mask_lapic_lvt(entry) \
128         write_mmreg32(entry, read_mmreg32(entry) | LAPIC_LVT_MASK)
129 #define unmask_lapic_lvt(entry) \
130         write_mmreg32(entry, read_mmreg32(entry) & ~LAPIC_LVT_MASK)
131
132 static inline void pic_send_eoi(uint32_t irq)
133 {
134         // all irqs beyond the first seven need to be chained to the slave
135         if (irq > 7)
136                 outb(PIC2_CMD, PIC_EOI);
137         outb(PIC1_CMD, PIC_EOI);
138 }
139
140 static inline void lapic_send_eoi(void)
141 {
142         write_mmreg32(LAPIC_EOI, 0);
143 }
144
145 static inline uint32_t lapic_get_version(void)
146 {
147         return read_mmreg32(LAPIC_VERSION);     
148 }
149
150 static inline uint32_t lapic_get_error(void)
151 {
152         write_mmreg32(LAPIC_ERROR, 0xdeadbeef);
153         return read_mmreg32(LAPIC_ERROR);
154 }
155
156 static inline uint32_t lapic_get_id(void)
157 {
158         return read_mmreg32(LAPIC_ID) >> 24;
159 }
160
161 static inline void lapic_set_id(uint8_t id)
162 {
163         write_mmreg32(LAPIC_ID, id << 24);
164 }
165
166 static inline uint8_t lapic_get_logid(void)
167 {
168         return read_mmreg32(LAPIC_LOGICAL_ID) >> 24;
169 }
170
171 static inline void lapic_set_logid(uint8_t id)
172 {
173         write_mmreg32(LAPIC_LOGICAL_ID, id << 24);
174 }
175
176 /* There are a couple ways to do it.  The MSR route doesn't seem to work
177  * in KVM.  It's also a somewhat permanent thing
178  */
179 static inline void lapic_disable(void)
180 {
181         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) & 0xffffefff);
182         //write_msr(IA32_APIC_BASE, read_msr(IA32_APIC_BASE) & ~MSR_APIC_ENABLE);
183 }
184
185 /* Spins until previous IPIs are delivered.  Not sure if we want it inlined
186  * Also not sure when we really need to do this. 
187  */
188 static inline void lapic_wait_to_send(void)
189 {
190         static inline void cpu_relax(void);
191         while(read_mmreg32(LAPIC_IPI_ICR_LOWER) & 0x1000)
192                 cpu_relax();
193 }
194
195 static inline void lapic_enable(void)
196 {
197         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) | 0x00000100);
198 }
199
200 static inline void send_init_ipi(void)
201 {
202         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4500);
203 }
204
205 static inline void send_startup_ipi(uint8_t vector)
206 {
207         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4600 | vector);
208 }
209
210 static inline void send_self_ipi(uint8_t vector)
211 {
212         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00044000 | vector);
213 }
214
215 static inline void send_broadcast_ipi(uint8_t vector)
216 {
217         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00084000 | vector);
218 }
219
220 static inline void send_all_others_ipi(uint8_t vector)
221 {
222         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4000 | vector);
223 }
224
225 static inline void send_ipi(uint8_t dest, bool logical_mode, uint8_t vector)
226 {
227         write_mmreg32(LAPIC_IPI_ICR_UPPER, dest << 24);
228         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004000 | (logical_mode << 11) | vector);
229 }
230
231 /* To change the LAPIC Base (not recommended):
232         msr_val = read_msr(IA32_APIC_BASE);
233         msr_val = msr_val & ~MSR_APIC_BASE_ADDRESS | 0xfaa00000;
234         write_msr(IA32_APIC_BASE, msr_val);
235 */
236 #endif /* ROS_KERN_APIC_H */