LAPIC logical ID support for IPIs
[akaros.git] / kern / apic.h
1 /*
2  * Copyright (c) 2009 The Regents of the University of California
3  * See LICENSE for details.
4  */
5
6 #ifndef ROS_KERN_APIC_H
7 #define ROS_KERN_APIC_H
8
9 /* 
10  * Functions and definitions for dealing with the APIC and PIC, specific to
11  * Intel.  Does not handle an x2APIC.
12  */
13
14 #include <inc/mmu.h>
15 #include <inc/x86.h>
16
17 // PIC
18 #define PIC1_CMD                                        0x20
19 #define PIC1_DATA                                       0x21
20 #define PIC2_CMD                                        0xA0
21 #define PIC2_DATA                                       0xA1
22 // These are also hardcoded into the IRQ_HANDLERs of kern/trapentry.S
23 #define PIC1_OFFSET                                     0x20
24 #define PIC2_OFFSET                                     0x28
25 #define PIC_EOI                                         0x20
26
27 // Local APIC
28 #define LAPIC_BASE                                      0xfee00000 // this is the default, can be changed
29 #define LAPIC_EOI                                       (LAPIC_BASE + 0x0b0)
30 #define LAPIC_SPURIOUS                          (LAPIC_BASE + 0x0f0)
31 #define LAPIC_VERSION                           (LAPIC_BASE + 0x030)
32 #define LAPIC_ERROR                                     (LAPIC_BASE + 0x280)
33 #define LAPIC_ID                                        (LAPIC_BASE + 0x020)
34 #define LAPIC_LOGICAL_ID                        (LAPIC_BASE + 0x0d0)
35 // LAPIC Local Vector Table
36 #define LAPIC_LVT_TIMER                         (LAPIC_BASE + 0x320)
37 #define LAPIC_LVT_LINT0                         (LAPIC_BASE + 0x350)
38 #define LAPIC_LVT_LINT1                         (LAPIC_BASE + 0x360)
39 #define LAPIC_LVT_ERROR                         (LAPIC_BASE + 0x370)
40 #define LAPIC_LVT_PERFMON                       (LAPIC_BASE + 0x340)
41 #define LAPIC_LVT_THERMAL                       (LAPIC_BASE + 0x330)
42 #define LAPIC_LVT_MASK                          0x00010000
43 // LAPIC Timer
44 #define LAPIC_TIMER_INIT                        (LAPIC_BASE + 0x380)
45 #define LAPIC_TIMER_CURRENT                     (LAPIC_BASE + 0x390)
46 #define LAPIC_TIMER_DIVIDE                      (LAPIC_BASE + 0x3e0)
47 // IPI Interrupt Command Register
48 #define LAPIC_IPI_ICR_LOWER                     (LAPIC_BASE + 0x300)
49 #define LAPIC_IPI_ICR_UPPER                     (LAPIC_BASE + 0x310)
50
51 // IOAPIC
52 #define IOAPIC_BASE                                     0xfec00000 // this is the default, can be changed
53
54 // PIT (Programmable Interrupt Timer)
55 #define PIT_FREQ                                        1193180
56
57 void pic_remap(void);
58 void pic_mask_irq(uint8_t irq);
59 void pic_unmask_irq(uint8_t irq);
60 void lapic_set_timer(uint32_t ticks, uint8_t vector, bool periodic);
61 uint32_t lapic_get_default_id(void);
62 void pit_set_timer(uint32_t freq, bool periodic); // consider adding callback func
63
64 static inline void pic_send_eoi(uint32_t irq);
65 static inline void lapic_send_eoi(void);
66 static inline uint32_t lapic_get_version(void);
67 static inline uint32_t lapic_get_error(void);
68 static inline uint32_t lapic_get_id(void);
69 static inline uint8_t lapic_get_logid(void);
70 static inline void lapic_set_logid(uint8_t id);
71 static inline void lapic_disable(void);
72 static inline void lapic_enable(void);
73 static inline void lapic_wait_to_send(void);
74 static inline void send_init_ipi(void);
75 static inline void send_startup_ipi(uint8_t vector);
76 static inline void send_self_ipi(uint8_t vector);
77 static inline void send_broadcast_ipi(uint8_t vector);
78 static inline void send_all_others_ipi(uint8_t vector);
79 static inline void send_ipi(uint8_t dest, bool logical_mode, uint8_t vector);
80
81 #define mask_lapic_lvt(entry) \
82         write_mmreg32(entry, read_mmreg32(entry) | LAPIC_LVT_MASK)
83 #define unmask_lapic_lvt(entry) \
84         write_mmreg32(entry, read_mmreg32(entry) & ~LAPIC_LVT_MASK)
85
86 static inline void pic_send_eoi(uint32_t irq)
87 {
88         // all irqs beyond the first seven need to be chained to the slave
89         if (irq > 7)
90                 outb(PIC2_CMD, PIC_EOI);
91         outb(PIC1_CMD, PIC_EOI);
92 }
93
94 static inline void lapic_send_eoi(void)
95 {
96         write_mmreg32(LAPIC_EOI, 0);
97 }
98
99 static inline uint32_t lapic_get_version(void)
100 {
101         return read_mmreg32(LAPIC_VERSION);     
102 }
103
104 static inline uint32_t lapic_get_error(void)
105 {
106         write_mmreg32(LAPIC_ERROR, 0xdeadbeef);
107         return read_mmreg32(LAPIC_ERROR);
108 }
109
110 static inline uint32_t lapic_get_id(void)
111 {
112         return read_mmreg32(LAPIC_ID) >> 24;
113 }
114
115 static inline uint8_t lapic_get_logid(void)
116 {
117         return read_mmreg32(LAPIC_LOGICAL_ID) >> 24;
118 }
119
120 static inline void lapic_set_logid(uint8_t id)
121 {
122         write_mmreg32(LAPIC_LOGICAL_ID, id << 24);
123 }
124
125 /* There are a couple ways to do it.  The MSR route doesn't seem to work
126  * in KVM.  It's also a somewhat permanent thing
127  */
128 static inline void lapic_disable(void)
129 {
130         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) & 0xffffefff);
131         //write_msr(IA32_APIC_BASE, read_msr(IA32_APIC_BASE) & ~MSR_APIC_ENABLE);
132 }
133
134 /* Spins until previous IPIs are delivered.  Not sure if we want it inlined
135  * Also not sure when we really need to do this. 
136  */
137 static inline void lapic_wait_to_send(void)
138 {
139         while(read_mmreg32(LAPIC_IPI_ICR_LOWER) & 0x1000)
140                 asm volatile("pause");
141 }
142
143 static inline void lapic_enable(void)
144 {
145         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) | 0x00000100);
146 }
147
148 static inline void send_init_ipi(void)
149 {
150         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4500);
151 }
152
153 static inline void send_startup_ipi(uint8_t vector)
154 {
155         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4600 | vector);
156 }
157
158 static inline void send_self_ipi(uint8_t vector)
159 {
160         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00044000 | vector);
161 }
162
163 static inline void send_broadcast_ipi(uint8_t vector)
164 {
165         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00084000 | vector);
166 }
167
168 static inline void send_all_others_ipi(uint8_t vector)
169 {
170         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4000 | vector);
171 }
172
173 static inline void send_ipi(uint8_t dest, bool logical_mode, uint8_t vector)
174 {
175         write_mmreg32(LAPIC_IPI_ICR_UPPER, dest << 24);
176         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004000 | (logical_mode << 11) | vector);
177 }
178
179 /* To change the LAPIC Base (not recommended):
180         msr_val = read_msr(IA32_APIC_BASE);
181         msr_val = msr_val & ~MSR_APIC_BASE_ADDRESS | 0xfaa00000;
182         write_msr(IA32_APIC_BASE, msr_val);
183 */
184 #endif /* ROS_KERN_APIC_H */