fa66cd39494cffa045d5524b69a7ef55485fd2a4
[akaros.git] / kern / apic.h
1 /*
2  * Copyright (c) 2009 The Regents of the University of California
3  * See LICENSE for details.
4  */
5
6 #ifndef ROS_KERN_APIC_H
7 #define ROS_KERN_APIC_H
8
9 /* 
10  * Functions and definitions for dealing with the APIC and PIC, specific to
11  * Intel.  Does not handle an x2APIC.
12  */
13
14 #include <inc/mmu.h>
15 #include <inc/x86.h>
16
17 // PIC
18 #define PIC1_CMD                                        0x20
19 #define PIC1_DATA                                       0x21
20 #define PIC2_CMD                                        0xA0
21 #define PIC2_DATA                                       0xA1
22 // These are also hardcoded into the IRQ_HANDLERs of kern/trapentry.S
23 #define PIC1_OFFSET                                     0x20
24 #define PIC2_OFFSET                                     0x28
25 #define PIC_EOI                                         0x20
26
27 // Local APIC
28 #define LAPIC_BASE                                      0xfee00000 // this is the default, can be changed
29 #define LAPIC_EOI                                       (LAPIC_BASE + 0x0b0)
30 #define LAPIC_SPURIOUS                          (LAPIC_BASE + 0x0f0)
31 #define LAPIC_VERSION                           (LAPIC_BASE + 0x030)
32 #define LAPIC_ERROR                                     (LAPIC_BASE + 0x280)
33 #define LAPIC_ID                                        (LAPIC_BASE + 0x020)
34 #define LAPIC_LOGICAL_ID                        (LAPIC_BASE + 0x0d0)
35 // LAPIC Local Vector Table
36 #define LAPIC_LVT_TIMER                         (LAPIC_BASE + 0x320)
37 #define LAPIC_LVT_LINT0                         (LAPIC_BASE + 0x350)
38 #define LAPIC_LVT_LINT1                         (LAPIC_BASE + 0x360)
39 #define LAPIC_LVT_ERROR                         (LAPIC_BASE + 0x370)
40 #define LAPIC_LVT_PERFMON                       (LAPIC_BASE + 0x340)
41 #define LAPIC_LVT_THERMAL                       (LAPIC_BASE + 0x330)
42 #define LAPIC_LVT_MASK                          0x00010000
43 // LAPIC Timer
44 #define LAPIC_TIMER_INIT                        (LAPIC_BASE + 0x380)
45 #define LAPIC_TIMER_CURRENT                     (LAPIC_BASE + 0x390)
46 #define LAPIC_TIMER_DIVIDE                      (LAPIC_BASE + 0x3e0)
47 #define LAPIC_TIMER_DEFAULT_VECTOR      0xeb
48 #define LAPIC_TIMER_DEFAULT_DIVISOR     0xa // This is 128.  Ref SDM 3.a 9.6.4
49 // IPI Interrupt Command Register
50 #define LAPIC_IPI_ICR_LOWER                     (LAPIC_BASE + 0x300)
51 #define LAPIC_IPI_ICR_UPPER                     (LAPIC_BASE + 0x310)
52
53 // IOAPIC
54 #define IOAPIC_BASE                                     0xfec00000 // this is the default, can be changed
55
56 // PIT (Programmable Interval Timer)
57 #define TIMER_REG_CNTR0 0       /* timer 0 counter port */
58 #define TIMER_REG_CNTR1 1       /* timer 1 counter port */
59 #define TIMER_REG_CNTR2 2       /* timer 2 counter port */
60 #define TIMER_REG_MODE  3       /* timer mode port */
61 #define TIMER_SEL0      0x00    /* select counter 0 */
62 #define TIMER_SEL1      0x40    /* select counter 1 */
63 #define TIMER_SEL2      0x80    /* select counter 2 */
64 #define TIMER_INTTC     0x00    /* mode 0, intr on terminal cnt */
65 #define TIMER_ONESHOT   0x02    /* mode 1, one shot */
66 #define TIMER_RATEGEN   0x04    /* mode 2, rate generator */
67 #define TIMER_SQWAVE    0x06    /* mode 3, square wave */
68 #define TIMER_SWSTROBE  0x08    /* mode 4, s/w triggered strobe */
69 #define TIMER_HWSTROBE  0x0a    /* mode 5, h/w triggered strobe */
70 #define TIMER_LATCH     0x00    /* latch counter for reading */
71 #define TIMER_LSB       0x10    /* r/w counter LSB */
72 #define TIMER_MSB       0x20    /* r/w counter MSB */
73 #define TIMER_16BIT     0x30    /* r/w counter 16 bits, LSB first */
74 #define TIMER_BCD       0x01    /* count in BCD */
75
76 #define PIT_FREQ                                        1193182
77
78 #define IO_TIMER1   0x40        /* 8253 Timer #1 */
79 #define TIMER_CNTR0 (IO_TIMER1 + TIMER_REG_CNTR0)
80 #define TIMER_CNTR1 (IO_TIMER1 + TIMER_REG_CNTR1)
81 #define TIMER_CNTR2 (IO_TIMER1 + TIMER_REG_CNTR2)
82 #define TIMER_MODE  (IO_TIMER1 + TIMER_REG_MODE)
83
84 typedef struct system_timing {
85         uint64_t tsc_freq;
86         uint64_t bus_freq;
87         uint16_t pit_divisor;
88         uint8_t pit_mode;
89 } system_timing_t;
90
91 extern system_timing_t system_timing;
92
93 void pic_remap(void);
94 void pic_mask_irq(uint8_t irq);
95 void pic_unmask_irq(uint8_t irq);
96 void __lapic_set_timer(uint32_t ticks, uint8_t vec, bool periodic, uint8_t div);
97 void lapic_set_timer(uint32_t usec, bool periodic);
98 uint32_t lapic_get_default_id(void);
99 // PIT related
100 void pit_set_timer(uint32_t freq, uint32_t mode);
101 void timer_init(void);
102 void udelay(uint64_t usec);
103 void udelay_pit(uint64_t usec);
104 // TODO: right now timer defaults to TSC
105 uint64_t gettimer(void);
106 uint64_t inline getfreq(void);
107
108 static inline void pic_send_eoi(uint32_t irq);
109 static inline void lapic_send_eoi(void);
110 static inline uint32_t lapic_get_version(void);
111 static inline uint32_t lapic_get_error(void);
112 static inline uint32_t lapic_get_id(void);
113 static inline uint8_t lapic_get_logid(void);
114 static inline void lapic_set_logid(uint8_t id);
115 static inline void lapic_disable(void);
116 static inline void lapic_enable(void);
117 static inline void lapic_wait_to_send(void);
118 static inline void send_init_ipi(void);
119 static inline void send_startup_ipi(uint8_t vector);
120 static inline void send_self_ipi(uint8_t vector);
121 static inline void send_broadcast_ipi(uint8_t vector);
122 static inline void send_all_others_ipi(uint8_t vector);
123 static inline void send_ipi(uint8_t dest, bool logical_mode, uint8_t vector);
124
125 #define mask_lapic_lvt(entry) \
126         write_mmreg32(entry, read_mmreg32(entry) | LAPIC_LVT_MASK)
127 #define unmask_lapic_lvt(entry) \
128         write_mmreg32(entry, read_mmreg32(entry) & ~LAPIC_LVT_MASK)
129
130 static inline void pic_send_eoi(uint32_t irq)
131 {
132         // all irqs beyond the first seven need to be chained to the slave
133         if (irq > 7)
134                 outb(PIC2_CMD, PIC_EOI);
135         outb(PIC1_CMD, PIC_EOI);
136 }
137
138 static inline void lapic_send_eoi(void)
139 {
140         write_mmreg32(LAPIC_EOI, 0);
141 }
142
143 static inline uint32_t lapic_get_version(void)
144 {
145         return read_mmreg32(LAPIC_VERSION);     
146 }
147
148 static inline uint32_t lapic_get_error(void)
149 {
150         write_mmreg32(LAPIC_ERROR, 0xdeadbeef);
151         return read_mmreg32(LAPIC_ERROR);
152 }
153
154 static inline uint32_t lapic_get_id(void)
155 {
156         return read_mmreg32(LAPIC_ID) >> 24;
157 }
158
159 static inline uint8_t lapic_get_logid(void)
160 {
161         return read_mmreg32(LAPIC_LOGICAL_ID) >> 24;
162 }
163
164 static inline void lapic_set_logid(uint8_t id)
165 {
166         write_mmreg32(LAPIC_LOGICAL_ID, id << 24);
167 }
168
169 /* There are a couple ways to do it.  The MSR route doesn't seem to work
170  * in KVM.  It's also a somewhat permanent thing
171  */
172 static inline void lapic_disable(void)
173 {
174         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) & 0xffffefff);
175         //write_msr(IA32_APIC_BASE, read_msr(IA32_APIC_BASE) & ~MSR_APIC_ENABLE);
176 }
177
178 /* Spins until previous IPIs are delivered.  Not sure if we want it inlined
179  * Also not sure when we really need to do this. 
180  */
181 static inline void lapic_wait_to_send(void)
182 {
183         while(read_mmreg32(LAPIC_IPI_ICR_LOWER) & 0x1000)
184                 cpu_relax();
185 }
186
187 static inline void lapic_enable(void)
188 {
189         write_mmreg32(LAPIC_SPURIOUS, read_mmreg32(LAPIC_SPURIOUS) | 0x00000100);
190 }
191
192 static inline void send_init_ipi(void)
193 {
194         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4500);
195 }
196
197 static inline void send_startup_ipi(uint8_t vector)
198 {
199         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4600 | vector);
200 }
201
202 static inline void send_self_ipi(uint8_t vector)
203 {
204         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00044000 | vector);
205 }
206
207 static inline void send_broadcast_ipi(uint8_t vector)
208 {
209         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00084000 | vector);
210 }
211
212 static inline void send_all_others_ipi(uint8_t vector)
213 {
214         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x000c4000 | vector);
215 }
216
217 static inline void send_ipi(uint8_t dest, bool logical_mode, uint8_t vector)
218 {
219         write_mmreg32(LAPIC_IPI_ICR_UPPER, dest << 24);
220         write_mmreg32(LAPIC_IPI_ICR_LOWER, 0x00004000 | (logical_mode << 11) | vector);
221 }
222
223 /* To change the LAPIC Base (not recommended):
224         msr_val = read_msr(IA32_APIC_BASE);
225         msr_val = msr_val & ~MSR_APIC_BASE_ADDRESS | 0xfaa00000;
226         write_msr(IA32_APIC_BASE, msr_val);
227 */
228 #endif /* ROS_KERN_APIC_H */